opcodes/xc16x-desc.c

   1 /* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
   2 /* CPU data for xc16x.
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5
   6 Copyright (C) 1996-2022 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   9
  10    This file is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 3, or (at your option)
  13    any later version.
  14
  15    It is distributed in the hope that it will be useful, but WITHOUT
  16    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  17    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  18    License for more details.
  19
  20    You should have received a copy of the GNU General Public License along
  21    with this program; if not, write to the Free Software Foundation, Inc.,
  22    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include "sysdep.h"
  27 #include <stdio.h>
  28 #include <stdarg.h>
  29 #include <stdlib.h>
  30 #include "ansidecl.h"
  31 #include "bfd.h"
  32 #include "symcat.h"
  33 #include "xc16x-desc.h"
  34 #include "xc16x-opc.h"
  35 #include "opintl.h"
  36 #include "libiberty.h"
  37 #include "xregex.h"
  38
  39 /* Attributes.  */
  40
  41 static const CGEN_ATTR_ENTRY bool_attr[] =
  42 {
  43   { "#f", 0 },
  44   { "#t", 1 },
  45   { 0, 0 }
  46 };
  47
  48 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
  49 {
  50   { "base", MACH_BASE },
  51   { "xc16x", MACH_XC16X },
  52   { "max", MACH_MAX },
  53   { 0, 0 }
  54 };
  55
  56 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
  57 {
  58   { "xc16x", ISA_XC16X },
  59   { "max", ISA_MAX },
  60   { 0, 0 }
  61 };
  62
  63 static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED =
  64 {
  65   { "NONE", PIPE_NONE },
  66   { "OS", PIPE_OS },
  67   { 0, 0 }
  68 };
  69
  70 const CGEN_ATTR_TABLE xc16x_cgen_ifield_attr_table[] =
  71 {
  72   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  73   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  74   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  75   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  76   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  77   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  78   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  79   { "RELOC", &bool_attr[0], &bool_attr[0] },
  80   { 0, 0, 0 }
  81 };
  82
  83 const CGEN_ATTR_TABLE xc16x_cgen_hardware_attr_table[] =
  84 {
  85   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  86   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  87   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  88   { "PC", &bool_attr[0], &bool_attr[0] },
  89   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  90   { 0, 0, 0 }
  91 };
  92
  93 const CGEN_ATTR_TABLE xc16x_cgen_operand_attr_table[] =
  94 {
  95   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  96   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  97   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  98   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  99   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 100   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 101   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 102   { "RELAX", &bool_attr[0], &bool_attr[0] },
 103   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 104   { "RELOC", &bool_attr[0], &bool_attr[0] },
 105   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
 106   { "DOT-PREFIX", &bool_attr[0], &bool_attr[0] },
 107   { "POF-PREFIX", &bool_attr[0], &bool_attr[0] },
 108   { "PAG-PREFIX", &bool_attr[0], &bool_attr[0] },
 109   { "SOF-PREFIX", &bool_attr[0], &bool_attr[0] },
 110   { "SEG-PREFIX", &bool_attr[0], &bool_attr[0] },
 111   { 0, 0, 0 }
 112 };
 113
 114 const CGEN_ATTR_TABLE xc16x_cgen_insn_attr_table[] =
 115 {
 116   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 117   { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
 118   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 119   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 120   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 121   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 122   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 123   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 124   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 125   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 126   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 127   { "PBB", &bool_attr[0], &bool_attr[0] },
 128   { 0, 0, 0 }
 129 };
 130
 131 /* Instruction set variants.  */
 132
 133 static const CGEN_ISA xc16x_cgen_isa_table[] = {
 134   { "xc16x", 16, 32, 16, 32 },
 135   { 0, 0, 0, 0, 0 }
 136 };
 137
 138 /* Machine variants.  */
 139
 140 static const CGEN_MACH xc16x_cgen_mach_table[] = {
 141   { "xc16x", "xc16x", MACH_XC16X, 32 },
 142   { 0, 0, 0, 0 }
 143 };
 144
 145 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_gr_names_entries[] =
 146 {
 147   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
 148   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
 149   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
 150   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
 151   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
 152   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
 153   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
 154   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
 155   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
 156   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
 157   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
 158   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
 159   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
 160   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
 161   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
 162   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }
 163 };
 164
 165 CGEN_KEYWORD xc16x_cgen_opval_gr_names =
 166 {
 167   & xc16x_cgen_opval_gr_names_entries[0],
 168   16,
 169   0, 0, 0, 0, ""
 170 };
 171
 172 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_ext_names_entries[] =
 173 {
 174   { "0x1", 0, {0, {{{0, 0}}}}, 0, 0 },
 175   { "0x2", 1, {0, {{{0, 0}}}}, 0, 0 },
 176   { "0x3", 2, {0, {{{0, 0}}}}, 0, 0 },
 177   { "0x4", 3, {0, {{{0, 0}}}}, 0, 0 },
 178   { "1", 0, {0, {{{0, 0}}}}, 0, 0 },
 179   { "2", 1, {0, {{{0, 0}}}}, 0, 0 },
 180   { "3", 2, {0, {{{0, 0}}}}, 0, 0 },
 181   { "4", 3, {0, {{{0, 0}}}}, 0, 0 }
 182 };
 183
 184 CGEN_KEYWORD xc16x_cgen_opval_ext_names =
 185 {
 186   & xc16x_cgen_opval_ext_names_entries[0],
 187   8,
 188   0, 0, 0, 0, ""
 189 };
 190
 191 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_psw_names_entries[] =
 192 {
 193   { "IEN", 136, {0, {{{0, 0}}}}, 0, 0 },
 194   { "r0.11", 240, {0, {{{0, 0}}}}, 0, 0 },
 195   { "r1.11", 241, {0, {{{0, 0}}}}, 0, 0 },
 196   { "r2.11", 242, {0, {{{0, 0}}}}, 0, 0 },
 197   { "r3.11", 243, {0, {{{0, 0}}}}, 0, 0 },
 198   { "r4.11", 244, {0, {{{0, 0}}}}, 0, 0 },
 199   { "r5.11", 245, {0, {{{0, 0}}}}, 0, 0 },
 200   { "r6.11", 246, {0, {{{0, 0}}}}, 0, 0 },
 201   { "r7.11", 247, {0, {{{0, 0}}}}, 0, 0 },
 202   { "r8.11", 248, {0, {{{0, 0}}}}, 0, 0 },
 203   { "r9.11", 249, {0, {{{0, 0}}}}, 0, 0 },
 204   { "r10.11", 250, {0, {{{0, 0}}}}, 0, 0 },
 205   { "r11.11", 251, {0, {{{0, 0}}}}, 0, 0 },
 206   { "r12.11", 252, {0, {{{0, 0}}}}, 0, 0 },
 207   { "r13.11", 253, {0, {{{0, 0}}}}, 0, 0 },
 208   { "r14.11", 254, {0, {{{0, 0}}}}, 0, 0 },
 209   { "r15.11", 255, {0, {{{0, 0}}}}, 0, 0 }
 210 };
 211
 212 CGEN_KEYWORD xc16x_cgen_opval_psw_names =
 213 {
 214   & xc16x_cgen_opval_psw_names_entries[0],
 215   17,
 216   0, 0, 0, 0, ""
 217 };
 218
 219 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb_names_entries[] =
 220 {
 221   { "rl0", 0, {0, {{{0, 0}}}}, 0, 0 },
 222   { "rh0", 1, {0, {{{0, 0}}}}, 0, 0 },
 223   { "rl1", 2, {0, {{{0, 0}}}}, 0, 0 },
 224   { "rh1", 3, {0, {{{0, 0}}}}, 0, 0 },
 225   { "rl2", 4, {0, {{{0, 0}}}}, 0, 0 },
 226   { "rh2", 5, {0, {{{0, 0}}}}, 0, 0 },
 227   { "rl3", 6, {0, {{{0, 0}}}}, 0, 0 },
 228   { "rh3", 7, {0, {{{0, 0}}}}, 0, 0 },
 229   { "rl4", 8, {0, {{{0, 0}}}}, 0, 0 },
 230   { "rh4", 9, {0, {{{0, 0}}}}, 0, 0 },
 231   { "rl5", 10, {0, {{{0, 0}}}}, 0, 0 },
 232   { "rh5", 11, {0, {{{0, 0}}}}, 0, 0 },
 233   { "rl6", 12, {0, {{{0, 0}}}}, 0, 0 },
 234   { "rh6", 13, {0, {{{0, 0}}}}, 0, 0 },
 235   { "rl7", 14, {0, {{{0, 0}}}}, 0, 0 },
 236   { "rh7", 15, {0, {{{0, 0}}}}, 0, 0 }
 237 };
 238
 239 CGEN_KEYWORD xc16x_cgen_opval_grb_names =
 240 {
 241   & xc16x_cgen_opval_grb_names_entries[0],
 242   16,
 243   0, 0, 0, 0, ""
 244 };
 245
 246 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_conditioncode_names_entries[] =
 247 {
 248   { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
 249   { "cc_NET", 1, {0, {{{0, 0}}}}, 0, 0 },
 250   { "cc_Z", 2, {0, {{{0, 0}}}}, 0, 0 },
 251   { "cc_EQ", 2, {0, {{{0, 0}}}}, 0, 0 },
 252   { "cc_NZ", 3, {0, {{{0, 0}}}}, 0, 0 },
 253   { "cc_NE", 3, {0, {{{0, 0}}}}, 0, 0 },
 254   { "cc_V", 4, {0, {{{0, 0}}}}, 0, 0 },
 255   { "cc_NV", 5, {0, {{{0, 0}}}}, 0, 0 },
 256   { "cc_N", 6, {0, {{{0, 0}}}}, 0, 0 },
 257   { "cc_NN", 7, {0, {{{0, 0}}}}, 0, 0 },
 258   { "cc_ULT", 8, {0, {{{0, 0}}}}, 0, 0 },
 259   { "cc_UGE", 9, {0, {{{0, 0}}}}, 0, 0 },
 260   { "cc_C", 8, {0, {{{0, 0}}}}, 0, 0 },
 261   { "cc_NC", 9, {0, {{{0, 0}}}}, 0, 0 },
 262   { "cc_SGT", 10, {0, {{{0, 0}}}}, 0, 0 },
 263   { "cc_SLE", 11, {0, {{{0, 0}}}}, 0, 0 },
 264   { "cc_SLT", 12, {0, {{{0, 0}}}}, 0, 0 },
 265   { "cc_SGE", 13, {0, {{{0, 0}}}}, 0, 0 },
 266   { "cc_UGT", 14, {0, {{{0, 0}}}}, 0, 0 },
 267   { "cc_ULE", 15, {0, {{{0, 0}}}}, 0, 0 }
 268 };
 269
 270 CGEN_KEYWORD xc16x_cgen_opval_conditioncode_names =
 271 {
 272   & xc16x_cgen_opval_conditioncode_names_entries[0],
 273   20,
 274   0, 0, 0, 0, ""
 275 };
 276
 277 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_extconditioncode_names_entries[] =
 278 {
 279   { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
 280   { "cc_NET", 2, {0, {{{0, 0}}}}, 0, 0 },
 281   { "cc_Z", 4, {0, {{{0, 0}}}}, 0, 0 },
 282   { "cc_EQ", 4, {0, {{{0, 0}}}}, 0, 0 },
 283   { "cc_NZ", 6, {0, {{{0, 0}}}}, 0, 0 },
 284   { "cc_NE", 6, {0, {{{0, 0}}}}, 0, 0 },
 285   { "cc_V", 8, {0, {{{0, 0}}}}, 0, 0 },
 286   { "cc_NV", 10, {0, {{{0, 0}}}}, 0, 0 },
 287   { "cc_N", 12, {0, {{{0, 0}}}}, 0, 0 },
 288   { "cc_NN", 14, {0, {{{0, 0}}}}, 0, 0 },
 289   { "cc_ULT", 16, {0, {{{0, 0}}}}, 0, 0 },
 290   { "cc_UGE", 18, {0, {{{0, 0}}}}, 0, 0 },
 291   { "cc_C", 16, {0, {{{0, 0}}}}, 0, 0 },
 292   { "cc_NC", 18, {0, {{{0, 0}}}}, 0, 0 },
 293   { "cc_SGT", 20, {0, {{{0, 0}}}}, 0, 0 },
 294   { "cc_SLE", 22, {0, {{{0, 0}}}}, 0, 0 },
 295   { "cc_SLT", 24, {0, {{{0, 0}}}}, 0, 0 },
 296   { "cc_SGE", 26, {0, {{{0, 0}}}}, 0, 0 },
 297   { "cc_UGT", 28, {0, {{{0, 0}}}}, 0, 0 },
 298   { "cc_ULE", 30, {0, {{{0, 0}}}}, 0, 0 },
 299   { "cc_nusr0", 1, {0, {{{0, 0}}}}, 0, 0 },
 300   { "cc_nusr1", 3, {0, {{{0, 0}}}}, 0, 0 },
 301   { "cc_usr0", 5, {0, {{{0, 0}}}}, 0, 0 },
 302   { "cc_usr1", 7, {0, {{{0, 0}}}}, 0, 0 }
 303 };
 304
 305 CGEN_KEYWORD xc16x_cgen_opval_extconditioncode_names =
 306 {
 307   & xc16x_cgen_opval_extconditioncode_names_entries[0],
 308   24,
 309   0, 0, 0, 0, ""
 310 };
 311
 312 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb8_names_entries[] =
 313 {
 314   { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
 315   { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
 316   { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
 317   { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
 318   { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
 319   { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
 320   { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
 321   { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
 322   { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
 323   { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
 324   { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
 325   { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
 326   { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
 327   { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
 328   { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
 329   { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
 330   { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
 331   { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
 332   { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
 333   { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
 334   { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
 335   { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
 336   { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 },
 337   { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 },
 338   { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 },
 339   { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 },
 340   { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 },
 341   { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 },
 342   { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 },
 343   { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 },
 344   { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 },
 345   { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 },
 346   { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
 347   { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
 348   { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
 349   { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
 350 };
 351
 352 CGEN_KEYWORD xc16x_cgen_opval_grb8_names =
 353 {
 354   & xc16x_cgen_opval_grb8_names_entries[0],
 355   36,
 356   0, 0, 0, 0, ""
 357 };
 358
 359 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_r8_names_entries[] =
 360 {
 361   { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
 362   { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
 363   { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
 364   { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
 365   { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
 366   { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
 367   { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
 368   { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
 369   { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
 370   { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
 371   { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
 372   { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
 373   { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
 374   { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
 375   { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
 376   { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
 377   { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
 378   { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
 379   { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
 380   { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
 381   { "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
 382   { "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
 383   { "r2", 242, {0, {{{0, 0}}}}, 0, 0 },
 384   { "r3", 243, {0, {{{0, 0}}}}, 0, 0 },
 385   { "r4", 244, {0, {{{0, 0}}}}, 0, 0 },
 386   { "r5", 245, {0, {{{0, 0}}}}, 0, 0 },
 387   { "r6", 246, {0, {{{0, 0}}}}, 0, 0 },
 388   { "r7", 247, {0, {{{0, 0}}}}, 0, 0 },
 389   { "r8", 248, {0, {{{0, 0}}}}, 0, 0 },
 390   { "r9", 249, {0, {{{0, 0}}}}, 0, 0 },
 391   { "r10", 250, {0, {{{0, 0}}}}, 0, 0 },
 392   { "r11", 251, {0, {{{0, 0}}}}, 0, 0 },
 393   { "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
 394   { "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
 395   { "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
 396   { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
 397 };
 398
 399 CGEN_KEYWORD xc16x_cgen_opval_r8_names =
 400 {
 401   & xc16x_cgen_opval_r8_names_entries[0],
 402   36,
 403   0, 0, 0, 0, ""
 404 };
 405
 406 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regmem8_names_entries[] =
 407 {
 408   { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
 409   { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
 410   { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
 411   { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
 412   { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
 413   { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
 414   { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
 415   { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
 416   { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
 417   { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
 418   { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
 419   { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
 420   { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
 421   { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
 422   { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
 423   { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
 424   { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
 425   { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
 426   { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
 427   { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
 428   { "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
 429   { "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
 430   { "r2", 242, {0, {{{0, 0}}}}, 0, 0 },
 431   { "r3", 243, {0, {{{0, 0}}}}, 0, 0 },
 432   { "r4", 244, {0, {{{0, 0}}}}, 0, 0 },
 433   { "r5", 245, {0, {{{0, 0}}}}, 0, 0 },
 434   { "r6", 246, {0, {{{0, 0}}}}, 0, 0 },
 435   { "r7", 247, {0, {{{0, 0}}}}, 0, 0 },
 436   { "r8", 248, {0, {{{0, 0}}}}, 0, 0 },
 437   { "r9", 249, {0, {{{0, 0}}}}, 0, 0 },
 438   { "r10", 250, {0, {{{0, 0}}}}, 0, 0 },
 439   { "r11", 251, {0, {{{0, 0}}}}, 0, 0 },
 440   { "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
 441   { "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
 442   { "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
 443   { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
 444 };
 445
 446 CGEN_KEYWORD xc16x_cgen_opval_regmem8_names =
 447 {
 448   & xc16x_cgen_opval_regmem8_names_entries[0],
 449   36,
 450   0, 0, 0, 0, ""
 451 };
 452
 453 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regdiv8_names_entries[] =
 454 {
 455   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
 456   { "r1", 17, {0, {{{0, 0}}}}, 0, 0 },
 457   { "r2", 34, {0, {{{0, 0}}}}, 0, 0 },
 458   { "r3", 51, {0, {{{0, 0}}}}, 0, 0 },
 459   { "r4", 68, {0, {{{0, 0}}}}, 0, 0 },
 460   { "r5", 85, {0, {{{0, 0}}}}, 0, 0 },
 461   { "r6", 102, {0, {{{0, 0}}}}, 0, 0 },
 462   { "r7", 119, {0, {{{0, 0}}}}, 0, 0 },
 463   { "r8", 136, {0, {{{0, 0}}}}, 0, 0 },
 464   { "r9", 153, {0, {{{0, 0}}}}, 0, 0 },
 465   { "r10", 170, {0, {{{0, 0}}}}, 0, 0 },
 466   { "r11", 187, {0, {{{0, 0}}}}, 0, 0 },
 467   { "r12", 204, {0, {{{0, 0}}}}, 0, 0 },
 468   { "r13", 221, {0, {{{0, 0}}}}, 0, 0 },
 469   { "r14", 238, {0, {{{0, 0}}}}, 0, 0 },
 470   { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
 471 };
 472
 473 CGEN_KEYWORD xc16x_cgen_opval_regdiv8_names =
 474 {
 475   & xc16x_cgen_opval_regdiv8_names_entries[0],
 476   16,
 477   0, 0, 0, 0, ""
 478 };
 479
 480 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name_entries[] =
 481 {
 482   { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 },
 483   { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 },
 484   { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 },
 485   { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 },
 486   { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 },
 487   { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 },
 488   { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 },
 489   { "0x8", 8, {0, {{{0, 0}}}}, 0, 0 },
 490   { "0x9", 9, {0, {{{0, 0}}}}, 0, 0 },
 491   { "0xa", 10, {0, {{{0, 0}}}}, 0, 0 },
 492   { "0xb", 11, {0, {{{0, 0}}}}, 0, 0 },
 493   { "0xc", 12, {0, {{{0, 0}}}}, 0, 0 },
 494   { "0xd", 13, {0, {{{0, 0}}}}, 0, 0 },
 495   { "0xe", 14, {0, {{{0, 0}}}}, 0, 0 },
 496   { "0xf", 15, {0, {{{0, 0}}}}, 0, 0 },
 497   { "1", 1, {0, {{{0, 0}}}}, 0, 0 },
 498   { "2", 2, {0, {{{0, 0}}}}, 0, 0 },
 499   { "3", 3, {0, {{{0, 0}}}}, 0, 0 },
 500   { "4", 4, {0, {{{0, 0}}}}, 0, 0 },
 501   { "5", 5, {0, {{{0, 0}}}}, 0, 0 },
 502   { "6", 6, {0, {{{0, 0}}}}, 0, 0 },
 503   { "7", 7, {0, {{{0, 0}}}}, 0, 0 },
 504   { "8", 8, {0, {{{0, 0}}}}, 0, 0 },
 505   { "9", 9, {0, {{{0, 0}}}}, 0, 0 },
 506   { "10", 10, {0, {{{0, 0}}}}, 0, 0 },
 507   { "11", 11, {0, {{{0, 0}}}}, 0, 0 },
 508   { "12", 12, {0, {{{0, 0}}}}, 0, 0 },
 509   { "13", 13, {0, {{{0, 0}}}}, 0, 0 },
 510   { "14", 14, {0, {{{0, 0}}}}, 0, 0 },
 511   { "15", 15, {0, {{{0, 0}}}}, 0, 0 }
 512 };
 513
 514 CGEN_KEYWORD xc16x_cgen_opval_reg0_name =
 515 {
 516   & xc16x_cgen_opval_reg0_name_entries[0],
 517   30,
 518   0, 0, 0, 0, ""
 519 };
 520
 521 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name1_entries[] =
 522 {
 523   { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 },
 524   { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 },
 525   { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 },
 526   { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 },
 527   { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 },
 528   { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 },
 529   { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 },
 530   { "1", 1, {0, {{{0, 0}}}}, 0, 0 },
 531   { "2", 2, {0, {{{0, 0}}}}, 0, 0 },
 532   { "3", 3, {0, {{{0, 0}}}}, 0, 0 },
 533   { "4", 4, {0, {{{0, 0}}}}, 0, 0 },
 534   { "5", 5, {0, {{{0, 0}}}}, 0, 0 },
 535   { "6", 6, {0, {{{0, 0}}}}, 0, 0 },
 536   { "7", 7, {0, {{{0, 0}}}}, 0, 0 }
 537 };
 538
 539 CGEN_KEYWORD xc16x_cgen_opval_reg0_name1 =
 540 {
 541   & xc16x_cgen_opval_reg0_name1_entries[0],
 542   14,
 543   0, 0, 0, 0, ""
 544 };
 545
 546 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regbmem8_names_entries[] =
 547 {
 548   { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
 549   { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
 550   { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
 551   { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
 552   { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
 553   { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
 554   { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
 555   { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
 556   { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
 557   { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
 558   { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
 559   { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
 560   { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
 561   { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
 562   { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
 563   { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
 564   { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
 565   { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
 566   { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
 567   { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
 568   { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
 569   { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
 570   { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 },
 571   { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 },
 572   { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 },
 573   { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 },
 574   { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 },
 575   { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 },
 576   { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 },
 577   { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 },
 578   { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 },
 579   { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 },
 580   { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
 581   { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
 582   { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
 583   { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
 584 };
 585
 586 CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names =
 587 {
 588   & xc16x_cgen_opval_regbmem8_names_entries[0],
 589   36,
 590   0, 0, 0, 0, ""
 591 };
 592
 593 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_memgr8_names_entries[] =
 594 {
 595   { "dpp0", 65024, {0, {{{0, 0}}}}, 0, 0 },
 596   { "dpp1", 65026, {0, {{{0, 0}}}}, 0, 0 },
 597   { "dpp2", 65028, {0, {{{0, 0}}}}, 0, 0 },
 598   { "dpp3", 65030, {0, {{{0, 0}}}}, 0, 0 },
 599   { "psw", 65296, {0, {{{0, 0}}}}, 0, 0 },
 600   { "cp", 65040, {0, {{{0, 0}}}}, 0, 0 },
 601   { "mdl", 65038, {0, {{{0, 0}}}}, 0, 0 },
 602   { "mdh", 65036, {0, {{{0, 0}}}}, 0, 0 },
 603   { "mdc", 65294, {0, {{{0, 0}}}}, 0, 0 },
 604   { "sp", 65042, {0, {{{0, 0}}}}, 0, 0 },
 605   { "csp", 65032, {0, {{{0, 0}}}}, 0, 0 },
 606   { "vecseg", 65298, {0, {{{0, 0}}}}, 0, 0 },
 607   { "stkov", 65044, {0, {{{0, 0}}}}, 0, 0 },
 608   { "stkun", 65046, {0, {{{0, 0}}}}, 0, 0 },
 609   { "cpucon1", 65048, {0, {{{0, 0}}}}, 0, 0 },
 610   { "cpucon2", 65050, {0, {{{0, 0}}}}, 0, 0 },
 611   { "zeros", 65308, {0, {{{0, 0}}}}, 0, 0 },
 612   { "ones", 65310, {0, {{{0, 0}}}}, 0, 0 },
 613   { "spseg", 65292, {0, {{{0, 0}}}}, 0, 0 },
 614   { "tfr", 65452, {0, {{{0, 0}}}}, 0, 0 }
 615 };
 616
 617 CGEN_KEYWORD xc16x_cgen_opval_memgr8_names =
 618 {
 619   & xc16x_cgen_opval_memgr8_names_entries[0],
 620   20,
 621   0, 0, 0, 0, ""
 622 };
 623
 624
 625 /* The hardware table.  */
 626
 627 #define A(a) (1 << CGEN_HW_##a)
 628
 629 const CGEN_HW_ENTRY xc16x_cgen_hw_table[] =
 630 {
 631   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 632   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 633   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 634   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 635   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 636   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
 637   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 638   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 639   { "h-ext", HW_H_EXT, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_ext_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 640   { "h-psw", HW_H_PSW, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_psw_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 641   { "h-grb", HW_H_GRB, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 642   { "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_conditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 643   { "h-ecc", HW_H_ECC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_extconditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 644   { "h-grb8", HW_H_GRB8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 645   { "h-r8", HW_H_R8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_r8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 646   { "h-regmem8", HW_H_REGMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regmem8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 647   { "h-regdiv8", HW_H_REGDIV8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regdiv8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 648   { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 649   { "h-r01", HW_H_R01, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name1, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 650   { "h-regbmem8", HW_H_REGBMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regbmem8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 651   { "h-memgr8", HW_H_MEMGR8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_memgr8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 652   { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 653   { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 654   { "h-sgtdis", HW_H_SGTDIS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 655   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 656 };
 657
 658 #undef A
 659
 660
 661 /* The instruction field table.  */
 662
 663 #define A(a) (1 << CGEN_IFLD_##a)
 664
 665 const CGEN_IFLD xc16x_cgen_ifld_table[] =
 666 {
 667   { XC16X_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 668   { XC16X_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 669   { XC16X_F_OP1, "f-op1", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 670   { XC16X_F_OP2, "f-op2", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 671   { XC16X_F_CONDCODE, "f-condcode", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 672   { XC16X_F_ICONDCODE, "f-icondcode", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 673   { XC16X_F_RCOND, "f-rcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 674   { XC16X_F_QCOND, "f-qcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 675   { XC16X_F_EXTCCODE, "f-extccode", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 676   { XC16X_F_R0, "f-r0", 0, 32, 9, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 677   { XC16X_F_R1, "f-r1", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 678   { XC16X_F_R2, "f-r2", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 679   { XC16X_F_R3, "f-r3", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 680   { XC16X_F_R4, "f-r4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 681   { XC16X_F_UIMM2, "f-uimm2", 0, 32, 13, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 682   { XC16X_F_UIMM3, "f-uimm3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 683   { XC16X_F_UIMM4, "f-uimm4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 684   { XC16X_F_UIMM7, "f-uimm7", 0, 32, 15, 7, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 685   { XC16X_F_UIMM8, "f-uimm8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 686   { XC16X_F_UIMM16, "f-uimm16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 687   { XC16X_F_MEMORY, "f-memory", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 688   { XC16X_F_MEMGR8, "f-memgr8", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 689   { XC16X_F_REL8, "f-rel8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 690   { XC16X_F_RELHI8, "f-relhi8", 0, 32, 23, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 691   { XC16X_F_REG8, "f-reg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 692   { XC16X_F_REGMEM8, "f-regmem8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 693   { XC16X_F_REGOFF8, "f-regoff8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 694   { XC16X_F_REGHI8, "f-reghi8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 695   { XC16X_F_REGB8, "f-regb8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 696   { XC16X_F_SEG8, "f-seg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 697   { XC16X_F_SEGNUM8, "f-segnum8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 698   { XC16X_F_MASK8, "f-mask8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 699   { XC16X_F_PAGENUM, "f-pagenum", 0, 32, 25, 10, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 700   { XC16X_F_DATAHI8, "f-datahi8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 701   { XC16X_F_DATA8, "f-data8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 702   { XC16X_F_OFFSET16, "f-offset16", 0, 32, 31, 16, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 703   { XC16X_F_OP_BIT1, "f-op-bit1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 704   { XC16X_F_OP_BIT2, "f-op-bit2", 0, 32, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 705   { XC16X_F_OP_BIT4, "f-op-bit4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 706   { XC16X_F_OP_BIT3, "f-op-bit3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 707   { XC16X_F_OP_2BIT, "f-op-2bit", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 708   { XC16X_F_OP_BITONE, "f-op-bitone", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 709   { XC16X_F_OP_ONEBIT, "f-op-onebit", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 710   { XC16X_F_OP_1BIT, "f-op-1bit", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 711   { XC16X_F_OP_LBIT4, "f-op-lbit4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 712   { XC16X_F_OP_LBIT2, "f-op-lbit2", 0, 32, 15, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 713   { XC16X_F_OP_BIT8, "f-op-bit8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 714   { XC16X_F_OP_BIT16, "f-op-bit16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 715   { XC16X_F_QBIT, "f-qbit", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 716   { XC16X_F_QLOBIT, "f-qlobit", 0, 32, 31, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 717   { XC16X_F_QHIBIT, "f-qhibit", 0, 32, 27, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 718   { XC16X_F_QLOBIT2, "f-qlobit2", 0, 32, 27, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 719   { XC16X_F_POF, "f-pof", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 720   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 721 };
 722
 723 #undef A
 724
 725
 726
 727 /* multi ifield declarations */
 728
 729
 730
 731 /* multi ifield definitions */
 732
 733
 734 /* The operand table.  */
 735
 736 #define A(a) (1 << CGEN_OPERAND_##a)
 737 #define OPERAND(op) XC16X_OPERAND_##op
 738
 739 const CGEN_OPERAND xc16x_cgen_operand_table[] =
 740 {
 741 /* pc: program counter */
 742   { "pc", XC16X_OPERAND_PC, HW_H_PC, 0, 0,
 743     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_NIL] } },
 744     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 745 /* sr: source register */
 746   { "sr", XC16X_OPERAND_SR, HW_H_GR, 11, 4,
 747     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
 748     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 749 /* dr: destination register */
 750   { "dr", XC16X_OPERAND_DR, HW_H_GR, 15, 4,
 751     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
 752     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 753 /* dri: destination register */
 754   { "dri", XC16X_OPERAND_DRI, HW_H_GR, 11, 4,
 755     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R4] } },
 756     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 757 /* srb: source register */
 758   { "srb", XC16X_OPERAND_SRB, HW_H_GRB, 11, 4,
 759     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
 760     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 761 /* drb: destination register */
 762   { "drb", XC16X_OPERAND_DRB, HW_H_GRB, 15, 4,
 763     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
 764     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 765 /* sr2: 2 bit source register */
 766   { "sr2", XC16X_OPERAND_SR2, HW_H_GR, 9, 2,
 767     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R0] } },
 768     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 769 /* src1: source register 1 */
 770   { "src1", XC16X_OPERAND_SRC1, HW_H_GR, 15, 4,
 771     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
 772     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 773 /* src2: source register 2 */
 774   { "src2", XC16X_OPERAND_SRC2, HW_H_GR, 11, 4,
 775     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
 776     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 777 /* srdiv: source register 2 */
 778   { "srdiv", XC16X_OPERAND_SRDIV, HW_H_REGDIV8, 15, 8,
 779     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
 780     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 781 /* RegNam: PSW bits */
 782   { "RegNam", XC16X_OPERAND_REGNAM, HW_H_PSW, 15, 8,
 783     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
 784     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 785 /* uimm2: 2 bit unsigned number */
 786   { "uimm2", XC16X_OPERAND_UIMM2, HW_H_EXT, 13, 2,
 787     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM2] } },
 788     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 789 /* uimm3: 3 bit unsigned number */
 790   { "uimm3", XC16X_OPERAND_UIMM3, HW_H_R01, 10, 3,
 791     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM3] } },
 792     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 793 /* uimm4: 4 bit unsigned number */
 794   { "uimm4", XC16X_OPERAND_UIMM4, HW_H_UINT, 15, 4,
 795     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
 796     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 797 /* uimm7: 7 bit trap number */
 798   { "uimm7", XC16X_OPERAND_UIMM7, HW_H_UINT, 15, 7,
 799     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM7] } },
 800     { 0|A(HASH_PREFIX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 801 /* uimm8: 8 bit unsigned immediate */
 802   { "uimm8", XC16X_OPERAND_UIMM8, HW_H_UINT, 23, 8,
 803     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM8] } },
 804     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 805 /* uimm16: 16 bit unsigned immediate */
 806   { "uimm16", XC16X_OPERAND_UIMM16, HW_H_UINT, 31, 16,
 807     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
 808     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 809 /* upof16: 16 bit unsigned immediate */
 810   { "upof16", XC16X_OPERAND_UPOF16, HW_H_ADDR, 31, 16,
 811     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
 812     { 0|A(POF_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 813 /* reg8: 8 bit word register number */
 814   { "reg8", XC16X_OPERAND_REG8, HW_H_R8, 15, 8,
 815     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
 816     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 817 /* regmem8: 8 bit word register number */
 818   { "regmem8", XC16X_OPERAND_REGMEM8, HW_H_REGMEM8, 15, 8,
 819     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
 820     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 821 /* regbmem8: 8 bit byte register number */
 822   { "regbmem8", XC16X_OPERAND_REGBMEM8, HW_H_REGBMEM8, 15, 8,
 823     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
 824     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 825 /* regoff8: 8 bit word register number */
 826   { "regoff8", XC16X_OPERAND_REGOFF8, HW_H_R8, 15, 8,
 827     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGOFF8] } },
 828     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 829 /* reghi8: 8 bit word register number */
 830   { "reghi8", XC16X_OPERAND_REGHI8, HW_H_R8, 23, 8,
 831     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGHI8] } },
 832     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 833 /* regb8: 8 bit byte register number */
 834   { "regb8", XC16X_OPERAND_REGB8, HW_H_GRB8, 15, 8,
 835     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
 836     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 837 /* genreg: 8 bit word register number */
 838   { "genreg", XC16X_OPERAND_GENREG, HW_H_R8, 15, 8,
 839     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
 840     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 841 /* seg: 8 bit segment number */
 842   { "seg", XC16X_OPERAND_SEG, HW_H_UINT, 15, 8,
 843     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
 844     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 845 /* seghi8: 8 bit hi segment number */
 846   { "seghi8", XC16X_OPERAND_SEGHI8, HW_H_UINT, 23, 8,
 847     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEGNUM8] } },
 848     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 849 /* caddr: 16 bit address offset */
 850   { "caddr", XC16X_OPERAND_CADDR, HW_H_ADDR, 31, 16,
 851     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
 852     { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 853 /* rel: 8 bit signed relative offset */
 854   { "rel", XC16X_OPERAND_REL, HW_H_SINT, 15, 8,
 855     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REL8] } },
 856     { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 857 /* relhi: hi 8 bit signed relative offset */
 858   { "relhi", XC16X_OPERAND_RELHI, HW_H_SINT, 23, 8,
 859     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_RELHI8] } },
 860     { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 861 /* condbit: condition bit */
 862   { "condbit", XC16X_OPERAND_CONDBIT, HW_H_COND, 0, 0,
 863     { 0, { (const PTR) 0 } },
 864     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 865 /* bit1: gap of 1 bit */
 866   { "bit1", XC16X_OPERAND_BIT1, HW_H_UINT, 11, 1,
 867     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT1] } },
 868     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 869 /* bit2: gap of 2 bits */
 870   { "bit2", XC16X_OPERAND_BIT2, HW_H_UINT, 11, 2,
 871     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT2] } },
 872     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 873 /* bit4: gap of 4 bits */
 874   { "bit4", XC16X_OPERAND_BIT4, HW_H_UINT, 11, 4,
 875     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT4] } },
 876     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 877 /* lbit4: gap of 4 bits */
 878   { "lbit4", XC16X_OPERAND_LBIT4, HW_H_UINT, 15, 4,
 879     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT4] } },
 880     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 881 /* lbit2: gap of 2 bits */
 882   { "lbit2", XC16X_OPERAND_LBIT2, HW_H_UINT, 15, 2,
 883     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT2] } },
 884     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 885 /* bit8: gap of 8 bits */
 886   { "bit8", XC16X_OPERAND_BIT8, HW_H_UINT, 31, 8,
 887     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT8] } },
 888     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 889 /* u4: gap of 4 bits */
 890   { "u4", XC16X_OPERAND_U4, HW_H_R0, 15, 4,
 891     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
 892     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 893 /* bitone: field of 1 bit */
 894   { "bitone", XC16X_OPERAND_BITONE, HW_H_UINT, 9, 1,
 895     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_ONEBIT] } },
 896     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 897 /* bit01: field of 1 bit */
 898   { "bit01", XC16X_OPERAND_BIT01, HW_H_UINT, 8, 1,
 899     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_1BIT] } },
 900     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 901 /* cond: condition code */
 902   { "cond", XC16X_OPERAND_COND, HW_H_CC, 7, 4,
 903     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_CONDCODE] } },
 904     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 905 /* icond: indirect condition code */
 906   { "icond", XC16X_OPERAND_ICOND, HW_H_CC, 15, 4,
 907     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_ICONDCODE] } },
 908     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 909 /* extcond: extended condition code */
 910   { "extcond", XC16X_OPERAND_EXTCOND, HW_H_ECC, 15, 5,
 911     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_EXTCCODE] } },
 912     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 913 /* memory: 16 bit memory */
 914   { "memory", XC16X_OPERAND_MEMORY, HW_H_ADDR, 31, 16,
 915     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
 916     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 917 /* memgr8: 16 bit memory */
 918   { "memgr8", XC16X_OPERAND_MEMGR8, HW_H_MEMGR8, 31, 16,
 919     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMGR8] } },
 920     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 921 /* cbit: carry bit */
 922   { "cbit", XC16X_OPERAND_CBIT, HW_H_CBIT, 0, 0,
 923     { 0, { (const PTR) 0 } },
 924     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 925 /* qbit: bit addr */
 926   { "qbit", XC16X_OPERAND_QBIT, HW_H_UINT, 7, 4,
 927     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QBIT] } },
 928     { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 929 /* qlobit: bit addr */
 930   { "qlobit", XC16X_OPERAND_QLOBIT, HW_H_UINT, 31, 4,
 931     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QLOBIT] } },
 932     { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 933 /* qhibit: bit addr */
 934   { "qhibit", XC16X_OPERAND_QHIBIT, HW_H_UINT, 27, 4,
 935     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QHIBIT] } },
 936     { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 937 /* mask8: 8 bit mask */
 938   { "mask8", XC16X_OPERAND_MASK8, HW_H_UINT, 23, 8,
 939     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MASK8] } },
 940     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 941 /* masklo8: 8 bit mask */
 942   { "masklo8", XC16X_OPERAND_MASKLO8, HW_H_UINT, 31, 8,
 943     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
 944     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 945 /* pagenum: 10 bit page number */
 946   { "pagenum", XC16X_OPERAND_PAGENUM, HW_H_UINT, 25, 10,
 947     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_PAGENUM] } },
 948     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 949 /* data8: 8 bit data */
 950   { "data8", XC16X_OPERAND_DATA8, HW_H_UINT, 23, 8,
 951     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATA8] } },
 952     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 953 /* datahi8: 8 bit data */
 954   { "datahi8", XC16X_OPERAND_DATAHI8, HW_H_UINT, 31, 8,
 955     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
 956     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 957 /* sgtdisbit: segmentation enable bit */
 958   { "sgtdisbit", XC16X_OPERAND_SGTDISBIT, HW_H_SGTDIS, 0, 0,
 959     { 0, { (const PTR) 0 } },
 960     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 961 /* upag16: 16 bit unsigned immediate */
 962   { "upag16", XC16X_OPERAND_UPAG16, HW_H_UINT, 31, 16,
 963     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
 964     { 0|A(PAG_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 965 /* useg8: 8 bit segment  */
 966   { "useg8", XC16X_OPERAND_USEG8, HW_H_UINT, 15, 8,
 967     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
 968     { 0|A(SEG_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 969 /* useg16: 16 bit address offset */
 970   { "useg16", XC16X_OPERAND_USEG16, HW_H_UINT, 31, 16,
 971     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
 972     { 0|A(SEG_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 973 /* usof16: 16 bit address offset */
 974   { "usof16", XC16X_OPERAND_USOF16, HW_H_UINT, 31, 16,
 975     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
 976     { 0|A(SOF_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 977 /* hash: # prefix */
 978   { "hash", XC16X_OPERAND_HASH, HW_H_SINT, 0, 0,
 979     { 0, { (const PTR) 0 } },
 980     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 981 /* dot: . prefix */
 982   { "dot", XC16X_OPERAND_DOT, HW_H_SINT, 0, 0,
 983     { 0, { (const PTR) 0 } },
 984     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 985 /* pof: pof: prefix */
 986   { "pof", XC16X_OPERAND_POF, HW_H_SINT, 0, 0,
 987     { 0, { (const PTR) 0 } },
 988     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 989 /* pag: pag: prefix */
 990   { "pag", XC16X_OPERAND_PAG, HW_H_SINT, 0, 0,
 991     { 0, { (const PTR) 0 } },
 992     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 993 /* sof: sof: prefix */
 994   { "sof", XC16X_OPERAND_SOF, HW_H_SINT, 0, 0,
 995     { 0, { (const PTR) 0 } },
 996     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 997 /* segm: seg: prefix */
 998   { "segm", XC16X_OPERAND_SEGM, HW_H_SINT, 0, 0,
 999     { 0, { (const PTR) 0 } },
1000     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
1001 /* sentinel */
1002   { 0, 0, 0, 0, 0,
1003     { 0, { (const PTR) 0 } },
1004     { 0, { { { (1<<MACH_BASE), 0 } } } } }
1005 };
1006
1007 #undef A
1008
1009
1010 /* The instruction table.  */
1011
1012 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1013 #define A(a) (1 << CGEN_INSN_##a)
1014
1015 static const CGEN_IBASE xc16x_cgen_insn_table[MAX_INSNS] =
1016 {
1017   /* Special null first entry.
1018      A `num' value of zero is thus invalid.
1019      Also, the special `invalid' insn resides here.  */
1020   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } },
1021 /* add $reg8,$pof$upof16 */
1022   {
1023     XC16X_INSN_ADDRPOF, "addrpof", "add", 32,
1024     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1025   },
1026 /* sub $reg8,$pof$upof16 */
1027   {
1028     XC16X_INSN_SUBRPOF, "subrpof", "sub", 32,
1029     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1030   },
1031 /* addb $regb8,$pof$upof16 */
1032   {
1033     XC16X_INSN_ADDBRPOF, "addbrpof", "addb", 32,
1034     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1035   },
1036 /* subb $regb8,$pof$upof16 */
1037   {
1038     XC16X_INSN_SUBBRPOF, "subbrpof", "subb", 32,
1039     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1040   },
1041 /* add $reg8,$pag$upag16 */
1042   {
1043     XC16X_INSN_ADDRPAG, "addrpag", "add", 32,
1044     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1045   },
1046 /* sub $reg8,$pag$upag16 */
1047   {
1048     XC16X_INSN_SUBRPAG, "subrpag", "sub", 32,
1049     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1050   },
1051 /* addb $regb8,$pag$upag16 */
1052   {
1053     XC16X_INSN_ADDBRPAG, "addbrpag", "addb", 32,
1054     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1055   },
1056 /* subb $regb8,$pag$upag16 */
1057   {
1058     XC16X_INSN_SUBBRPAG, "subbrpag", "subb", 32,
1059     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1060   },
1061 /* addc $reg8,$pof$upof16 */
1062   {
1063     XC16X_INSN_ADDCRPOF, "addcrpof", "addc", 32,
1064     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1065   },
1066 /* subc $reg8,$pof$upof16 */
1067   {
1068     XC16X_INSN_SUBCRPOF, "subcrpof", "subc", 32,
1069     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1070   },
1071 /* addcb $regb8,$pof$upof16 */
1072   {
1073     XC16X_INSN_ADDCBRPOF, "addcbrpof", "addcb", 32,
1074     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1075   },
1076 /* subcb $regb8,$pof$upof16 */
1077   {
1078     XC16X_INSN_SUBCBRPOF, "subcbrpof", "subcb", 32,
1079     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1080   },
1081 /* addc $reg8,$pag$upag16 */
1082   {
1083     XC16X_INSN_ADDCRPAG, "addcrpag", "addc", 32,
1084     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1085   },
1086 /* subc $reg8,$pag$upag16 */
1087   {
1088     XC16X_INSN_SUBCRPAG, "subcrpag", "subc", 32,
1089     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1090   },
1091 /* addcb $regb8,$pag$upag16 */
1092   {
1093     XC16X_INSN_ADDCBRPAG, "addcbrpag", "addcb", 32,
1094     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1095   },
1096 /* subcb $regb8,$pag$upag16 */
1097   {
1098     XC16X_INSN_SUBCBRPAG, "subcbrpag", "subcb", 32,
1099     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1100   },
1101 /* add $pof$upof16,$reg8 */
1102   {
1103     XC16X_INSN_ADDRPOFR, "addrpofr", "add", 32,
1104     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1105   },
1106 /* sub $pof$upof16,$reg8 */
1107   {
1108     XC16X_INSN_SUBRPOFR, "subrpofr", "sub", 32,
1109     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1110   },
1111 /* addb $pof$upof16,$regb8 */
1112   {
1113     XC16X_INSN_ADDBRPOFR, "addbrpofr", "addb", 32,
1114     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1115   },
1116 /* subb $pof$upof16,$regb8 */
1117   {
1118     XC16X_INSN_SUBBRPOFR, "subbrpofr", "subb", 32,
1119     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1120   },
1121 /* addc $pof$upof16,$reg8 */
1122   {
1123     XC16X_INSN_ADDCRPOFR, "addcrpofr", "addc", 32,
1124     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1125   },
1126 /* subc $pof$upof16,$reg8 */
1127   {
1128     XC16X_INSN_SUBCRPOFR, "subcrpofr", "subc", 32,
1129     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1130   },
1131 /* addcb $pof$upof16,$regb8 */
1132   {
1133     XC16X_INSN_ADDCBRPOFR, "addcbrpofr", "addcb", 32,
1134     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1135   },
1136 /* subcb $pof$upof16,$regb8 */
1137   {
1138     XC16X_INSN_SUBCBRPOFR, "subcbrpofr", "subcb", 32,
1139     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1140   },
1141 /* add $reg8,$hash$pof$uimm16 */
1142   {
1143     XC16X_INSN_ADDRHPOF, "addrhpof", "add", 32,
1144     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1145   },
1146 /* sub $reg8,$hash$pof$uimm16 */
1147   {
1148     XC16X_INSN_SUBRHPOF, "subrhpof", "sub", 32,
1149     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1150   },
1151 /* add $reg8,$hash$pag$uimm16 */
1152   {
1153     XC16X_INSN_ADDBRHPOF, "addbrhpof", "add", 32,
1154     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1155   },
1156 /* sub $reg8,$hash$pag$uimm16 */
1157   {
1158     XC16X_INSN_SUBBRHPOF, "subbrhpof", "sub", 32,
1159     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1160   },
1161 /* add $dr,$hash$pof$uimm3 */
1162   {
1163     XC16X_INSN_ADDRHPOF3, "addrhpof3", "add", 16,
1164     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1165   },
1166 /* sub $dr,$hash$pof$uimm3 */
1167   {
1168     XC16X_INSN_SUBRHPOF3, "subrhpof3", "sub", 16,
1169     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1170   },
1171 /* addb $drb,$hash$pag$uimm3 */
1172   {
1173     XC16X_INSN_ADDBRHPAG3, "addbrhpag3", "addb", 16,
1174     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1175   },
1176 /* subb $drb,$hash$pag$uimm3 */
1177   {
1178     XC16X_INSN_SUBBRHPAG3, "subbrhpag3", "subb", 16,
1179     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1180   },
1181 /* add $dr,$hash$pag$uimm3 */
1182   {
1183     XC16X_INSN_ADDRHPAG3, "addrhpag3", "add", 16,
1184     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1185   },
1186 /* sub $dr,$hash$pag$uimm3 */
1187   {
1188     XC16X_INSN_SUBRHPAG3, "subrhpag3", "sub", 16,
1189     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1190   },
1191 /* addb $drb,$hash$pof$uimm3 */
1192   {
1193     XC16X_INSN_ADDBRHPOF3, "addbrhpof3", "addb", 16,
1194     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1195   },
1196 /* subb $drb,$hash$pof$uimm3 */
1197   {
1198     XC16X_INSN_SUBBRHPOF3, "subbrhpof3", "subb", 16,
1199     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1200   },
1201 /* addb $regb8,$hash$pof$uimm8 */
1202   {
1203     XC16X_INSN_ADDRBHPOF, "addrbhpof", "addb", 32,
1204     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1205   },
1206 /* subb $regb8,$hash$pof$uimm8 */
1207   {
1208     XC16X_INSN_SUBRBHPOF, "subrbhpof", "subb", 32,
1209     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1210   },
1211 /* addb $regb8,$hash$pag$uimm8 */
1212   {
1213     XC16X_INSN_ADDBRHPAG, "addbrhpag", "addb", 32,
1214     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1215   },
1216 /* subb $regb8,$hash$pag$uimm8 */
1217   {
1218     XC16X_INSN_SUBBRHPAG, "subbrhpag", "subb", 32,
1219     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1220   },
1221 /* addc $reg8,$hash$pof$uimm16 */
1222   {
1223     XC16X_INSN_ADDCRHPOF, "addcrhpof", "addc", 32,
1224     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1225   },
1226 /* subc $reg8,$hash$pof$uimm16 */
1227   {
1228     XC16X_INSN_SUBCRHPOF, "subcrhpof", "subc", 32,
1229     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1230   },
1231 /* addc $reg8,$hash$pag$uimm16 */
1232   {
1233     XC16X_INSN_ADDCBRHPOF, "addcbrhpof", "addc", 32,
1234     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1235   },
1236 /* subc $reg8,$hash$pag$uimm16 */
1237   {
1238     XC16X_INSN_SUBCBRHPOF, "subcbrhpof", "subc", 32,
1239     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1240   },
1241 /* addc $dr,$hash$pof$uimm3 */
1242   {
1243     XC16X_INSN_ADDCRHPOF3, "addcrhpof3", "addc", 16,
1244     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1245   },
1246 /* subc $dr,$hash$pof$uimm3 */
1247   {
1248     XC16X_INSN_SUBCRHPOF3, "subcrhpof3", "subc", 16,
1249     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1250   },
1251 /* addcb $drb,$hash$pag$uimm3 */
1252   {
1253     XC16X_INSN_ADDCBRHPAG3, "addcbrhpag3", "addcb", 16,
1254     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1255   },
1256 /* subcb $drb,$hash$pag$uimm3 */
1257   {
1258     XC16X_INSN_SUBCBRHPAG3, "subcbrhpag3", "subcb", 16,
1259     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1260   },
1261 /* addc $dr,$hash$pag$uimm3 */
1262   {
1263     XC16X_INSN_ADDCRHPAG3, "addcrhpag3", "addc", 16,
1264     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1265   },
1266 /* subc $dr,$hash$pag$uimm3 */
1267   {
1268     XC16X_INSN_SUBCRHPAG3, "subcrhpag3", "subc", 16,
1269     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1270   },
1271 /* addcb $drb,$hash$pof$uimm3 */
1272   {
1273     XC16X_INSN_ADDCBRHPOF3, "addcbrhpof3", "addcb", 16,
1274     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1275   },
1276 /* subcb $drb,$hash$pof$uimm3 */
1277   {
1278     XC16X_INSN_SUBCBRHPOF3, "subcbrhpof3", "subcb", 16,
1279     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1280   },
1281 /* addcb $regb8,$hash$pof$uimm8 */
1282   {
1283     XC16X_INSN_ADDCRBHPOF, "addcrbhpof", "addcb", 32,
1284     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1285   },
1286 /* subcb $regb8,$hash$pof$uimm8 */
1287   {
1288     XC16X_INSN_SUBCRBHPOF, "subcrbhpof", "subcb", 32,
1289     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1290   },
1291 /* addcb $regb8,$hash$pag$uimm8 */
1292   {
1293     XC16X_INSN_ADDCBRHPAG, "addcbrhpag", "addcb", 32,
1294     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1295   },
1296 /* subcb $regb8,$hash$pag$uimm8 */
1297   {
1298     XC16X_INSN_SUBCBRHPAG, "subcbrhpag", "subcb", 32,
1299     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1300   },
1301 /* add $dr,$hash$uimm3 */
1302   {
1303     XC16X_INSN_ADDRI, "addri", "add", 16,
1304     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1305   },
1306 /* sub $dr,$hash$uimm3 */
1307   {
1308     XC16X_INSN_SUBRI, "subri", "sub", 16,
1309     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1310   },
1311 /* addb $drb,$hash$uimm3 */
1312   {
1313     XC16X_INSN_ADDBRI, "addbri", "addb", 16,
1314     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1315   },
1316 /* subb $drb,$hash$uimm3 */
1317   {
1318     XC16X_INSN_SUBBRI, "subbri", "subb", 16,
1319     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1320   },
1321 /* add $reg8,$hash$uimm16 */
1322   {
1323     XC16X_INSN_ADDRIM, "addrim", "add", 32,
1324     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1325   },
1326 /* sub $reg8,$hash$uimm16 */
1327   {
1328     XC16X_INSN_SUBRIM, "subrim", "sub", 32,
1329     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1330   },
1331 /* addb $regb8,$hash$uimm8 */
1332   {
1333     XC16X_INSN_ADDBRIM, "addbrim", "addb", 32,
1334     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1335   },
1336 /* subb $regb8,$hash$uimm8 */
1337   {
1338     XC16X_INSN_SUBBRIM, "subbrim", "subb", 32,
1339     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1340   },
1341 /* addc $dr,$hash$uimm3 */
1342   {
1343     XC16X_INSN_ADDCRI, "addcri", "addc", 16,
1344     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1345   },
1346 /* subc $dr,$hash$uimm3 */
1347   {
1348     XC16X_INSN_SUBCRI, "subcri", "subc", 16,
1349     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1350   },
1351 /* addcb $drb,$hash$uimm3 */
1352   {
1353     XC16X_INSN_ADDCBRI, "addcbri", "addcb", 16,
1354     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1355   },
1356 /* subcb $drb,$hash$uimm3 */
1357   {
1358     XC16X_INSN_SUBCBRI, "subcbri", "subcb", 16,
1359     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1360   },
1361 /* addc $reg8,$hash$uimm16 */
1362   {
1363     XC16X_INSN_ADDCRIM, "addcrim", "addc", 32,
1364     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1365   },
1366 /* subc $reg8,$hash$uimm16 */
1367   {
1368     XC16X_INSN_SUBCRIM, "subcrim", "subc", 32,
1369     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1370   },
1371 /* addcb $regb8,$hash$uimm8 */
1372   {
1373     XC16X_INSN_ADDCBRIM, "addcbrim", "addcb", 32,
1374     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1375   },
1376 /* subcb $regb8,$hash$uimm8 */
1377   {
1378     XC16X_INSN_SUBCBRIM, "subcbrim", "subcb", 32,
1379     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1380   },
1381 /* add $dr,$sr */
1382   {
1383     XC16X_INSN_ADDR, "addr", "add", 16,
1384     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1385   },
1386 /* sub $dr,$sr */
1387   {
1388     XC16X_INSN_SUBR, "subr", "sub", 16,
1389     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1390   },
1391 /* addb $drb,$srb */
1392   {
1393     XC16X_INSN_ADDBR, "addbr", "addb", 16,
1394     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1395   },
1396 /* subb $drb,$srb */
1397   {
1398     XC16X_INSN_SUBBR, "subbr", "subb", 16,
1399     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1400   },
1401 /* add $dr,[$sr2] */
1402   {
1403     XC16X_INSN_ADD2, "add2", "add", 16,
1404     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1405   },
1406 /* sub $dr,[$sr2] */
1407   {
1408     XC16X_INSN_SUB2, "sub2", "sub", 16,
1409     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1410   },
1411 /* addb $drb,[$sr2] */
1412   {
1413     XC16X_INSN_ADDB2, "addb2", "addb", 16,
1414     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1415   },
1416 /* subb $drb,[$sr2] */
1417   {
1418     XC16X_INSN_SUBB2, "subb2", "subb", 16,
1419     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1420   },
1421 /* add $dr,[$sr2+] */
1422   {
1423     XC16X_INSN_ADD2I, "add2i", "add", 16,
1424     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1425   },
1426 /* sub $dr,[$sr2+] */
1427   {
1428     XC16X_INSN_SUB2I, "sub2i", "sub", 16,
1429     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1430   },
1431 /* addb $drb,[$sr2+] */
1432   {
1433     XC16X_INSN_ADDB2I, "addb2i", "addb", 16,
1434     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1435   },
1436 /* subb $drb,[$sr2+] */
1437   {
1438     XC16X_INSN_SUBB2I, "subb2i", "subb", 16,
1439     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1440   },
1441 /* addc $dr,$sr */
1442   {
1443     XC16X_INSN_ADDCR, "addcr", "addc", 16,
1444     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1445   },
1446 /* subc $dr,$sr */
1447   {
1448     XC16X_INSN_SUBCR, "subcr", "subc", 16,
1449     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1450   },
1451 /* addcb $drb,$srb */
1452   {
1453     XC16X_INSN_ADDBCR, "addbcr", "addcb", 16,
1454     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1455   },
1456 /* subcb $drb,$srb */
1457   {
1458     XC16X_INSN_SUBBCR, "subbcr", "subcb", 16,
1459     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1460   },
1461 /* addc $dr,[$sr2] */
1462   {
1463     XC16X_INSN_ADDCR2, "addcr2", "addc", 16,
1464     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1465   },
1466 /* subc $dr,[$sr2] */
1467   {
1468     XC16X_INSN_SUBCR2, "subcr2", "subc", 16,
1469     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1470   },
1471 /* addcb $drb,[$sr2] */
1472   {
1473     XC16X_INSN_ADDBCR2, "addbcr2", "addcb", 16,
1474     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1475   },
1476 /* subcb $drb,[$sr2] */
1477   {
1478     XC16X_INSN_SUBBCR2, "subbcr2", "subcb", 16,
1479     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1480   },
1481 /* addc $dr,[$sr2+] */
1482   {
1483     XC16X_INSN_ADDCR2I, "addcr2i", "addc", 16,
1484     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1485   },
1486 /* subc $dr,[$sr2+] */
1487   {
1488     XC16X_INSN_SUBCR2I, "subcr2i", "subc", 16,
1489     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1490   },
1491 /* addcb $drb,[$sr2+] */
1492   {
1493     XC16X_INSN_ADDBCR2I, "addbcr2i", "addcb", 16,
1494     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1495   },
1496 /* subcb $drb,[$sr2+] */
1497   {
1498     XC16X_INSN_SUBBCR2I, "subbcr2i", "subcb", 16,
1499     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1500   },
1501 /* add $regmem8,$memgr8 */
1502   {
1503     XC16X_INSN_ADDRM2, "addrm2", "add", 32,
1504     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1505   },
1506 /* add $memgr8,$regmem8 */
1507   {
1508     XC16X_INSN_ADDRM3, "addrm3", "add", 32,
1509     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1510   },
1511 /* add $reg8,$memory */
1512   {
1513     XC16X_INSN_ADDRM, "addrm", "add", 32,
1514     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1515   },
1516 /* add $memory,$reg8 */
1517   {
1518     XC16X_INSN_ADDRM1, "addrm1", "add", 32,
1519     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1520   },
1521 /* sub $regmem8,$memgr8 */
1522   {
1523     XC16X_INSN_SUBRM3, "subrm3", "sub", 32,
1524     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1525   },
1526 /* sub $memgr8,$regmem8 */
1527   {
1528     XC16X_INSN_SUBRM2, "subrm2", "sub", 32,
1529     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1530   },
1531 /* sub $reg8,$memory */
1532   {
1533     XC16X_INSN_SUBRM1, "subrm1", "sub", 32,
1534     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1535   },
1536 /* sub $memory,$reg8 */
1537   {
1538     XC16X_INSN_SUBRM, "subrm", "sub", 32,
1539     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1540   },
1541 /* addb $regbmem8,$memgr8 */
1542   {
1543     XC16X_INSN_ADDBRM2, "addbrm2", "addb", 32,
1544     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1545   },
1546 /* addb $memgr8,$regbmem8 */
1547   {
1548     XC16X_INSN_ADDBRM3, "addbrm3", "addb", 32,
1549     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1550   },
1551 /* addb $regb8,$memory */
1552   {
1553     XC16X_INSN_ADDBRM, "addbrm", "addb", 32,
1554     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1555   },
1556 /* addb $memory,$regb8 */
1557   {
1558     XC16X_INSN_ADDBRM1, "addbrm1", "addb", 32,
1559     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1560   },
1561 /* subb $regbmem8,$memgr8 */
1562   {
1563     XC16X_INSN_SUBBRM3, "subbrm3", "subb", 32,
1564     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1565   },
1566 /* subb $memgr8,$regbmem8 */
1567   {
1568     XC16X_INSN_SUBBRM2, "subbrm2", "subb", 32,
1569     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1570   },
1571 /* subb $regb8,$memory */
1572   {
1573     XC16X_INSN_SUBBRM1, "subbrm1", "subb", 32,
1574     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1575   },
1576 /* subb $memory,$regb8 */
1577   {
1578     XC16X_INSN_SUBBRM, "subbrm", "subb", 32,
1579     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1580   },
1581 /* addc $regmem8,$memgr8 */
1582   {
1583     XC16X_INSN_ADDCRM2, "addcrm2", "addc", 32,
1584     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1585   },
1586 /* addc $memgr8,$regmem8 */
1587   {
1588     XC16X_INSN_ADDCRM3, "addcrm3", "addc", 32,
1589     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1590   },
1591 /* addc $reg8,$memory */
1592   {
1593     XC16X_INSN_ADDCRM, "addcrm", "addc", 32,
1594     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1595   },
1596 /* addc $memory,$reg8 */
1597   {
1598     XC16X_INSN_ADDCRM1, "addcrm1", "addc", 32,
1599     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1600   },
1601 /* subc $regmem8,$memgr8 */
1602   {
1603     XC16X_INSN_SUBCRM3, "subcrm3", "subc", 32,
1604     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1605   },
1606 /* subc $memgr8,$regmem8 */
1607   {
1608     XC16X_INSN_SUBCRM2, "subcrm2", "subc", 32,
1609     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1610   },
1611 /* subc $reg8,$memory */
1612   {
1613     XC16X_INSN_SUBCRM1, "subcrm1", "subc", 32,
1614     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1615   },
1616 /* subc $memory,$reg8 */
1617   {
1618     XC16X_INSN_SUBCRM, "subcrm", "subc", 32,
1619     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1620   },
1621 /* addcb $regbmem8,$memgr8 */
1622   {
1623     XC16X_INSN_ADDCBRM2, "addcbrm2", "addcb", 32,
1624     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1625   },
1626 /* addcb $memgr8,$regbmem8 */
1627   {
1628     XC16X_INSN_ADDCBRM3, "addcbrm3", "addcb", 32,
1629     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1630   },
1631 /* addcb $regb8,$memory */
1632   {
1633     XC16X_INSN_ADDCBRM, "addcbrm", "addcb", 32,
1634     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1635   },
1636 /* addcb $memory,$regb8 */
1637   {
1638     XC16X_INSN_ADDCBRM1, "addcbrm1", "addcb", 32,
1639     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1640   },
1641 /* subcb $regbmem8,$memgr8 */
1642   {
1643     XC16X_INSN_SUBCBRM3, "subcbrm3", "subcb", 32,
1644     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1645   },
1646 /* subcb $memgr8,$regbmem8 */
1647   {
1648     XC16X_INSN_SUBCBRM2, "subcbrm2", "subcb", 32,
1649     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1650   },
1651 /* subcb $regb8,$memory */
1652   {
1653     XC16X_INSN_SUBCBRM1, "subcbrm1", "subcb", 32,
1654     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1655   },
1656 /* subcb $memory,$regb8 */
1657   {
1658     XC16X_INSN_SUBCBRM, "subcbrm", "subcb", 32,
1659     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1660   },
1661 /* mul $src1,$src2 */
1662   {
1663     XC16X_INSN_MULS, "muls", "mul", 16,
1664     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1665   },
1666 /* mulu $src1,$src2 */
1667   {
1668     XC16X_INSN_MULU, "mulu", "mulu", 16,
1669     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1670   },
1671 /* div $srdiv */
1672   {
1673     XC16X_INSN_DIV, "div", "div", 16,
1674     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1675   },
1676 /* divl $srdiv */
1677   {
1678     XC16X_INSN_DIVL, "divl", "divl", 16,
1679     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1680   },
1681 /* divlu $srdiv */
1682   {
1683     XC16X_INSN_DIVLU, "divlu", "divlu", 16,
1684     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1685   },
1686 /* divu $srdiv */
1687   {
1688     XC16X_INSN_DIVU, "divu", "divu", 16,
1689     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1690   },
1691 /* cpl $dr */
1692   {
1693     XC16X_INSN_CPL, "cpl", "cpl", 16,
1694     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1695   },
1696 /* cplb $drb */
1697   {
1698     XC16X_INSN_CPLB, "cplb", "cplb", 16,
1699     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1700   },
1701 /* neg $dr */
1702   {
1703     XC16X_INSN_NEG, "neg", "neg", 16,
1704     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1705   },
1706 /* negb $drb */
1707   {
1708     XC16X_INSN_NEGB, "negb", "negb", 16,
1709     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1710   },
1711 /* and $dr,$sr */
1712   {
1713     XC16X_INSN_ANDR, "andr", "and", 16,
1714     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1715   },
1716 /* or $dr,$sr */
1717   {
1718     XC16X_INSN_ORR, "orr", "or", 16,
1719     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1720   },
1721 /* xor $dr,$sr */
1722   {
1723     XC16X_INSN_XORR, "xorr", "xor", 16,
1724     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1725   },
1726 /* andb $drb,$srb */
1727   {
1728     XC16X_INSN_ANDBR, "andbr", "andb", 16,
1729     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1730   },
1731 /* orb $drb,$srb */
1732   {
1733     XC16X_INSN_ORBR, "orbr", "orb", 16,
1734     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1735   },
1736 /* xorb $drb,$srb */
1737   {
1738     XC16X_INSN_XORBR, "xorbr", "xorb", 16,
1739     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1740   },
1741 /* and $dr,$hash$uimm3 */
1742   {
1743     XC16X_INSN_ANDRI, "andri", "and", 16,
1744     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1745   },
1746 /* or $dr,$hash$uimm3 */
1747   {
1748     XC16X_INSN_ORRI, "orri", "or", 16,
1749     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1750   },
1751 /* xor $dr,$hash$uimm3 */
1752   {
1753     XC16X_INSN_XORRI, "xorri", "xor", 16,
1754     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1755   },
1756 /* andb $drb,$hash$uimm3 */
1757   {
1758     XC16X_INSN_ANDBRI, "andbri", "andb", 16,
1759     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1760   },
1761 /* orb $drb,$hash$uimm3 */
1762   {
1763     XC16X_INSN_ORBRI, "orbri", "orb", 16,
1764     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1765   },
1766 /* xorb $drb,$hash$uimm3 */
1767   {
1768     XC16X_INSN_XORBRI, "xorbri", "xorb", 16,
1769     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1770   },
1771 /* and $reg8,$hash$uimm16 */
1772   {
1773     XC16X_INSN_ANDRIM, "andrim", "and", 32,
1774     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1775   },
1776 /* or $reg8,$hash$uimm16 */
1777   {
1778     XC16X_INSN_ORRIM, "orrim", "or", 32,
1779     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1780   },
1781 /* xor $reg8,$hash$uimm16 */
1782   {
1783     XC16X_INSN_XORRIM, "xorrim", "xor", 32,
1784     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1785   },
1786 /* andb $regb8,$hash$uimm8 */
1787   {
1788     XC16X_INSN_ANDBRIM, "andbrim", "andb", 32,
1789     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1790   },
1791 /* orb $regb8,$hash$uimm8 */
1792   {
1793     XC16X_INSN_ORBRIM, "orbrim", "orb", 32,
1794     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1795   },
1796 /* xorb $regb8,$hash$uimm8 */
1797   {
1798     XC16X_INSN_XORBRIM, "xorbrim", "xorb", 32,
1799     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1800   },
1801 /* and $dr,[$sr2] */
1802   {
1803     XC16X_INSN_AND2, "and2", "and", 16,
1804     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1805   },
1806 /* or $dr,[$sr2] */
1807   {
1808     XC16X_INSN_OR2, "or2", "or", 16,
1809     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1810   },
1811 /* xor $dr,[$sr2] */
1812   {
1813     XC16X_INSN_XOR2, "xor2", "xor", 16,
1814     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1815   },
1816 /* andb $drb,[$sr2] */
1817   {
1818     XC16X_INSN_ANDB2, "andb2", "andb", 16,
1819     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1820   },
1821 /* orb $drb,[$sr2] */
1822   {
1823     XC16X_INSN_ORB2, "orb2", "orb", 16,
1824     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1825   },
1826 /* xorb $drb,[$sr2] */
1827   {
1828     XC16X_INSN_XORB2, "xorb2", "xorb", 16,
1829     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1830   },
1831 /* and $dr,[$sr2+] */
1832   {
1833     XC16X_INSN_AND2I, "and2i", "and", 16,
1834     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1835   },
1836 /* or $dr,[$sr2+] */
1837   {
1838     XC16X_INSN_OR2I, "or2i", "or", 16,
1839     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1840   },
1841 /* xor $dr,[$sr2+] */
1842   {
1843     XC16X_INSN_XOR2I, "xor2i", "xor", 16,
1844     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1845   },
1846 /* andb $drb,[$sr2+] */
1847   {
1848     XC16X_INSN_ANDB2I, "andb2i", "andb", 16,
1849     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1850   },
1851 /* orb $drb,[$sr2+] */
1852   {
1853     XC16X_INSN_ORB2I, "orb2i", "orb", 16,
1854     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1855   },
1856 /* xorb $drb,[$sr2+] */
1857   {
1858     XC16X_INSN_XORB2I, "xorb2i", "xorb", 16,
1859     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1860   },
1861 /* and $pof$reg8,$upof16 */
1862   {
1863     XC16X_INSN_ANDPOFR, "andpofr", "and", 32,
1864     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1865   },
1866 /* or $pof$reg8,$upof16 */
1867   {
1868     XC16X_INSN_ORPOFR, "orpofr", "or", 32,
1869     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1870   },
1871 /* xor $pof$reg8,$upof16 */
1872   {
1873     XC16X_INSN_XORPOFR, "xorpofr", "xor", 32,
1874     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1875   },
1876 /* andb $pof$regb8,$upof16 */
1877   {
1878     XC16X_INSN_ANDBPOFR, "andbpofr", "andb", 32,
1879     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1880   },
1881 /* orb $pof$regb8,$upof16 */
1882   {
1883     XC16X_INSN_ORBPOFR, "orbpofr", "orb", 32,
1884     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1885   },
1886 /* xorb $pof$regb8,$upof16 */
1887   {
1888     XC16X_INSN_XORBPOFR, "xorbpofr", "xorb", 32,
1889     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1890   },
1891 /* and $pof$upof16,$reg8 */
1892   {
1893     XC16X_INSN_ANDRPOFR, "andrpofr", "and", 32,
1894     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1895   },
1896 /* or $pof$upof16,$reg8 */
1897   {
1898     XC16X_INSN_ORRPOFR, "orrpofr", "or", 32,
1899     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1900   },
1901 /* xor $pof$upof16,$reg8 */
1902   {
1903     XC16X_INSN_XORRPOFR, "xorrpofr", "xor", 32,
1904     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1905   },
1906 /* andb $pof$upof16,$regb8 */
1907   {
1908     XC16X_INSN_ANDBRPOFR, "andbrpofr", "andb", 32,
1909     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1910   },
1911 /* orb $pof$upof16,$regb8 */
1912   {
1913     XC16X_INSN_ORBRPOFR, "orbrpofr", "orb", 32,
1914     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1915   },
1916 /* xorb $pof$upof16,$regb8 */
1917   {
1918     XC16X_INSN_XORBRPOFR, "xorbrpofr", "xorb", 32,
1919     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1920   },
1921 /* and $regmem8,$memgr8 */
1922   {
1923     XC16X_INSN_ANDRM2, "andrm2", "and", 32,
1924     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1925   },
1926 /* and $memgr8,$regmem8 */
1927   {
1928     XC16X_INSN_ANDRM3, "andrm3", "and", 32,
1929     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1930   },
1931 /* and $reg8,$memory */
1932   {
1933     XC16X_INSN_ANDRM, "andrm", "and", 32,
1934     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1935   },
1936 /* and $memory,$reg8 */
1937   {
1938     XC16X_INSN_ANDRM1, "andrm1", "and", 32,
1939     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1940   },
1941 /* or $regmem8,$memgr8 */
1942   {
1943     XC16X_INSN_ORRM3, "orrm3", "or", 32,
1944     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1945   },
1946 /* or $memgr8,$regmem8 */
1947   {
1948     XC16X_INSN_ORRM2, "orrm2", "or", 32,
1949     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1950   },
1951 /* or $reg8,$memory */
1952   {
1953     XC16X_INSN_ORRM1, "orrm1", "or", 32,
1954     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1955   },
1956 /* or $memory,$reg8 */
1957   {
1958     XC16X_INSN_ORRM, "orrm", "or", 32,
1959     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1960   },
1961 /* xor $regmem8,$memgr8 */
1962   {
1963     XC16X_INSN_XORRM3, "xorrm3", "xor", 32,
1964     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1965   },
1966 /* xor $memgr8,$regmem8 */
1967   {
1968     XC16X_INSN_XORRM2, "xorrm2", "xor", 32,
1969     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1970   },
1971 /* xor $reg8,$memory */
1972   {
1973     XC16X_INSN_XORRM1, "xorrm1", "xor", 32,
1974     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1975   },
1976 /* xor $memory,$reg8 */
1977   {
1978     XC16X_INSN_XORRM, "xorrm", "xor", 32,
1979     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1980   },
1981 /* andb $regbmem8,$memgr8 */
1982   {
1983     XC16X_INSN_ANDBRM2, "andbrm2", "andb", 32,
1984     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1985   },
1986 /* andb $memgr8,$regbmem8 */
1987   {
1988     XC16X_INSN_ANDBRM3, "andbrm3", "andb", 32,
1989     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1990   },
1991 /* andb $regb8,$memory */
1992   {
1993     XC16X_INSN_ANDBRM, "andbrm", "andb", 32,
1994     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1995   },
1996 /* andb $memory,$regb8 */
1997   {
1998     XC16X_INSN_ANDBRM1, "andbrm1", "andb", 32,
1999     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2000   },
2001 /* orb $regbmem8,$memgr8 */
2002   {
2003     XC16X_INSN_ORBRM3, "orbrm3", "orb", 32,
2004     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2005   },
2006 /* orb $memgr8,$regbmem8 */
2007   {
2008     XC16X_INSN_ORBRM2, "orbrm2", "orb", 32,
2009     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2010   },
2011 /* orb $regb8,$memory */
2012   {
2013     XC16X_INSN_ORBRM1, "orbrm1", "orb", 32,
2014     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2015   },
2016 /* orb $memory,$regb8 */
2017   {
2018     XC16X_INSN_ORBRM, "orbrm", "orb", 32,
2019     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2020   },
2021 /* xorb $regbmem8,$memgr8 */
2022   {
2023     XC16X_INSN_XORBRM3, "xorbrm3", "xorb", 32,
2024     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2025   },
2026 /* xorb $memgr8,$regbmem8 */
2027   {
2028     XC16X_INSN_XORBRM2, "xorbrm2", "xorb", 32,
2029     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2030   },
2031 /* xorb $regb8,$memory */
2032   {
2033     XC16X_INSN_XORBRM1, "xorbrm1", "xorb", 32,
2034     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2035   },
2036 /* xorb $memory,$regb8 */
2037   {
2038     XC16X_INSN_XORBRM, "xorbrm", "xorb", 32,
2039     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2040   },
2041 /* mov $dr,$sr */
2042   {
2043     XC16X_INSN_MOVR, "movr", "mov", 16,
2044     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2045   },
2046 /* movb $drb,$srb */
2047   {
2048     XC16X_INSN_MOVRB, "movrb", "movb", 16,
2049     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2050   },
2051 /* mov $dri,$hash$u4 */
2052   {
2053     XC16X_INSN_MOVRI, "movri", "mov", 16,
2054     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2055   },
2056 /* movb $srb,$hash$u4 */
2057   {
2058     XC16X_INSN_MOVBRI, "movbri", "movb", 16,
2059     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2060   },
2061 /* mov $reg8,$hash$uimm16 */
2062   {
2063     XC16X_INSN_MOVI, "movi", "mov", 32,
2064     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2065   },
2066 /* movb $regb8,$hash$uimm8 */
2067   {
2068     XC16X_INSN_MOVBI, "movbi", "movb", 32,
2069     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2070   },
2071 /* mov $dr,[$sr] */
2072   {
2073     XC16X_INSN_MOVR2, "movr2", "mov", 16,
2074     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2075   },
2076 /* movb $drb,[$sr] */
2077   {
2078     XC16X_INSN_MOVBR2, "movbr2", "movb", 16,
2079     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2080   },
2081 /* mov [$sr],$dr */
2082   {
2083     XC16X_INSN_MOVRI2, "movri2", "mov", 16,
2084     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2085   },
2086 /* movb [$sr],$drb */
2087   {
2088     XC16X_INSN_MOVBRI2, "movbri2", "movb", 16,
2089     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2090   },
2091 /* mov [-$sr],$dr */
2092   {
2093     XC16X_INSN_MOVRI3, "movri3", "mov", 16,
2094     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2095   },
2096 /* movb [-$sr],$drb */
2097   {
2098     XC16X_INSN_MOVBRI3, "movbri3", "movb", 16,
2099     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2100   },
2101 /* mov $dr,[$sr+] */
2102   {
2103     XC16X_INSN_MOV2I, "mov2i", "mov", 16,
2104     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2105   },
2106 /* movb $drb,[$sr+] */
2107   {
2108     XC16X_INSN_MOVB2I, "movb2i", "movb", 16,
2109     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2110   },
2111 /* mov [$dr],[$sr] */
2112   {
2113     XC16X_INSN_MOV6I, "mov6i", "mov", 16,
2114     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2115   },
2116 /* movb [$dr],[$sr] */
2117   {
2118     XC16X_INSN_MOVB6I, "movb6i", "movb", 16,
2119     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2120   },
2121 /* mov [$dr+],[$sr] */
2122   {
2123     XC16X_INSN_MOV7I, "mov7i", "mov", 16,
2124     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2125   },
2126 /* movb [$dr+],[$sr] */
2127   {
2128     XC16X_INSN_MOVB7I, "movb7i", "movb", 16,
2129     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2130   },
2131 /* mov [$dr],[$sr+] */
2132   {
2133     XC16X_INSN_MOV8I, "mov8i", "mov", 16,
2134     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2135   },
2136 /* movb [$dr],[$sr+] */
2137   {
2138     XC16X_INSN_MOVB8I, "movb8i", "movb", 16,
2139     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2140   },
2141 /* mov $dr,[$sr+$hash$uimm16] */
2142   {
2143     XC16X_INSN_MOV9I, "mov9i", "mov", 32,
2144     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2145   },
2146 /* movb $drb,[$sr+$hash$uimm16] */
2147   {
2148     XC16X_INSN_MOVB9I, "movb9i", "movb", 32,
2149     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2150   },
2151 /* mov [$sr+$hash$uimm16],$dr */
2152   {
2153     XC16X_INSN_MOV10I, "mov10i", "mov", 32,
2154     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2155   },
2156 /* movb [$sr+$hash$uimm16],$drb */
2157   {
2158     XC16X_INSN_MOVB10I, "movb10i", "movb", 32,
2159     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2160   },
2161 /* mov [$src2],$memory */
2162   {
2163     XC16X_INSN_MOVRI11, "movri11", "mov", 32,
2164     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2165   },
2166 /* movb [$src2],$memory */
2167   {
2168     XC16X_INSN_MOVBRI11, "movbri11", "movb", 32,
2169     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2170   },
2171 /* mov $memory,[$src2] */
2172   {
2173     XC16X_INSN_MOVRI12, "movri12", "mov", 32,
2174     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2175   },
2176 /* movb $memory,[$src2] */
2177   {
2178     XC16X_INSN_MOVBRI12, "movbri12", "movb", 32,
2179     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2180   },
2181 /* mov $regoff8,$hash$pof$upof16 */
2182   {
2183     XC16X_INSN_MOVEHM5, "movehm5", "mov", 32,
2184     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2185   },
2186 /* mov $regoff8,$hash$pag$upag16 */
2187   {
2188     XC16X_INSN_MOVEHM6, "movehm6", "mov", 32,
2189     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2190   },
2191 /* mov $regoff8,$hash$segm$useg16 */
2192   {
2193     XC16X_INSN_MOVEHM7, "movehm7", "mov", 32,
2194     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2195   },
2196 /* mov $regoff8,$hash$sof$usof16 */
2197   {
2198     XC16X_INSN_MOVEHM8, "movehm8", "mov", 32,
2199     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2200   },
2201 /* movb $regb8,$hash$pof$uimm8 */
2202   {
2203     XC16X_INSN_MOVEHM9, "movehm9", "movb", 32,
2204     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2205   },
2206 /* movb $regoff8,$hash$pag$uimm8 */
2207   {
2208     XC16X_INSN_MOVEHM10, "movehm10", "movb", 32,
2209     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2210   },
2211 /* mov $regoff8,$pof$upof16 */
2212   {
2213     XC16X_INSN_MOVRMP, "movrmp", "mov", 32,
2214     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2215   },
2216 /* movb $regb8,$pof$upof16 */
2217   {
2218     XC16X_INSN_MOVRMP1, "movrmp1", "movb", 32,
2219     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2220   },
2221 /* mov $regoff8,$pag$upag16 */
2222   {
2223     XC16X_INSN_MOVRMP2, "movrmp2", "mov", 32,
2224     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2225   },
2226 /* movb $regb8,$pag$upag16 */
2227   {
2228     XC16X_INSN_MOVRMP3, "movrmp3", "movb", 32,
2229     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2230   },
2231 /* mov $pof$upof16,$regoff8 */
2232   {
2233     XC16X_INSN_MOVRMP4, "movrmp4", "mov", 32,
2234     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2235   },
2236 /* movb $pof$upof16,$regb8 */
2237   {
2238     XC16X_INSN_MOVRMP5, "movrmp5", "movb", 32,
2239     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2240   },
2241 /* mov $dri,$hash$pof$u4 */
2242   {
2243     XC16X_INSN_MOVEHM1, "movehm1", "mov", 16,
2244     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2245   },
2246 /* movb $srb,$hash$pof$u4 */
2247   {
2248     XC16X_INSN_MOVEHM2, "movehm2", "movb", 16,
2249     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2250   },
2251 /* mov $dri,$hash$pag$u4 */
2252   {
2253     XC16X_INSN_MOVEHM3, "movehm3", "mov", 16,
2254     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2255   },
2256 /* movb $srb,$hash$pag$u4 */
2257   {
2258     XC16X_INSN_MOVEHM4, "movehm4", "movb", 16,
2259     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2260   },
2261 /* mov $regmem8,$memgr8 */
2262   {
2263     XC16X_INSN_MVE12, "mve12", "mov", 32,
2264     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2265   },
2266 /* mov $memgr8,$regmem8 */
2267   {
2268     XC16X_INSN_MVE13, "mve13", "mov", 32,
2269     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2270   },
2271 /* mov $reg8,$memory */
2272   {
2273     XC16X_INSN_MOVER12, "mover12", "mov", 32,
2274     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2275   },
2276 /* mov $memory,$reg8 */
2277   {
2278     XC16X_INSN_MVR13, "mvr13", "mov", 32,
2279     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2280   },
2281 /* movb $regbmem8,$memgr8 */
2282   {
2283     XC16X_INSN_MVER12, "mver12", "movb", 32,
2284     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2285   },
2286 /* movb $memgr8,$regbmem8 */
2287   {
2288     XC16X_INSN_MVER13, "mver13", "movb", 32,
2289     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2290   },
2291 /* movb $regb8,$memory */
2292   {
2293     XC16X_INSN_MOVR12, "movr12", "movb", 32,
2294     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2295   },
2296 /* movb $memory,$regb8 */
2297   {
2298     XC16X_INSN_MOVR13, "movr13", "movb", 32,
2299     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2300   },
2301 /* movbs $sr,$drb */
2302   {
2303     XC16X_INSN_MOVBSRR, "movbsrr", "movbs", 16,
2304     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2305   },
2306 /* movbz $sr,$drb */
2307   {
2308     XC16X_INSN_MOVBZRR, "movbzrr", "movbz", 16,
2309     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2310   },
2311 /* movbs $regmem8,$pof$upof16 */
2312   {
2313     XC16X_INSN_MOVBSRPOFM, "movbsrpofm", "movbs", 32,
2314     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2315   },
2316 /* movbs $pof$upof16,$regbmem8 */
2317   {
2318     XC16X_INSN_MOVBSPOFMR, "movbspofmr", "movbs", 32,
2319     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2320   },
2321 /* movbz $reg8,$pof$upof16 */
2322   {
2323     XC16X_INSN_MOVBZRPOFM, "movbzrpofm", "movbz", 32,
2324     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2325   },
2326 /* movbz $pof$upof16,$regb8 */
2327   {
2328     XC16X_INSN_MOVBZPOFMR, "movbzpofmr", "movbz", 32,
2329     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2330   },
2331 /* movbs $regmem8,$memgr8 */
2332   {
2333     XC16X_INSN_MOVEBS14, "movebs14", "movbs", 32,
2334     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2335   },
2336 /* movbs $memgr8,$regbmem8 */
2337   {
2338     XC16X_INSN_MOVEBS15, "movebs15", "movbs", 32,
2339     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2340   },
2341 /* movbs $reg8,$memory */
2342   {
2343     XC16X_INSN_MOVERBS14, "moverbs14", "movbs", 32,
2344     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2345   },
2346 /* movbs $memory,$regb8 */
2347   {
2348     XC16X_INSN_MOVRBS15, "movrbs15", "movbs", 32,
2349     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2350   },
2351 /* movbz $regmem8,$memgr8 */
2352   {
2353     XC16X_INSN_MOVEBZ14, "movebz14", "movbz", 32,
2354     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2355   },
2356 /* movbz $memgr8,$regbmem8 */
2357   {
2358     XC16X_INSN_MOVEBZ15, "movebz15", "movbz", 32,
2359     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2360   },
2361 /* movbz $reg8,$memory */
2362   {
2363     XC16X_INSN_MOVERBZ14, "moverbz14", "movbz", 32,
2364     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2365   },
2366 /* movbz $memory,$regb8 */
2367   {
2368     XC16X_INSN_MOVRBZ15, "movrbz15", "movbz", 32,
2369     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2370   },
2371 /* movbs $sr,$drb */
2372   {
2373     XC16X_INSN_MOVRBS, "movrbs", "movbs", 16,
2374     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2375   },
2376 /* movbz $sr,$drb */
2377   {
2378     XC16X_INSN_MOVRBZ, "movrbz", "movbz", 16,
2379     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2380   },
2381 /* jmpa+ $extcond,$caddr */
2382   {
2383     XC16X_INSN_JMPA0, "jmpa0", "jmpa+", 32,
2384     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2385   },
2386 /* jmpa $extcond,$caddr */
2387   {
2388     XC16X_INSN_JMPA1, "jmpa1", "jmpa", 32,
2389     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2390   },
2391 /* jmpa- $extcond,$caddr */
2392   {
2393     XC16X_INSN_JMPA_, "jmpa-", "jmpa-", 32,
2394     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2395   },
2396 /* jmpi $icond,[$sr] */
2397   {
2398     XC16X_INSN_JMPI, "jmpi", "jmpi", 16,
2399     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2400   },
2401 /* jmpr $cond,$rel */
2402   {
2403     XC16X_INSN_JMPR_NENZ, "jmpr_nenz", "jmpr", 16,
2404     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2405   },
2406 /* jmpr $cond,$rel */
2407   {
2408     XC16X_INSN_JMPR_SGT, "jmpr_sgt", "jmpr", 16,
2409     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2410   },
2411 /* jmpr $cond,$rel */
2412   {
2413     XC16X_INSN_JMPR_Z, "jmpr_z", "jmpr", 16,
2414     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2415   },
2416 /* jmpr $cond,$rel */
2417   {
2418     XC16X_INSN_JMPR_V, "jmpr_v", "jmpr", 16,
2419     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2420   },
2421 /* jmpr $cond,$rel */
2422   {
2423     XC16X_INSN_JMPR_NV, "jmpr_nv", "jmpr", 16,
2424     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2425   },
2426 /* jmpr $cond,$rel */
2427   {
2428     XC16X_INSN_JMPR_N, "jmpr_n", "jmpr", 16,
2429     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2430   },
2431 /* jmpr $cond,$rel */
2432   {
2433     XC16X_INSN_JMPR_NN, "jmpr_nn", "jmpr", 16,
2434     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2435   },
2436 /* jmpr $cond,$rel */
2437   {
2438     XC16X_INSN_JMPR_C, "jmpr_c", "jmpr", 16,
2439     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2440   },
2441 /* jmpr $cond,$rel */
2442   {
2443     XC16X_INSN_JMPR_NC, "jmpr_nc", "jmpr", 16,
2444     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2445   },
2446 /* jmpr $cond,$rel */
2447   {
2448     XC16X_INSN_JMPR_EQ, "jmpr_eq", "jmpr", 16,
2449     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2450   },
2451 /* jmpr $cond,$rel */
2452   {
2453     XC16X_INSN_JMPR_NE, "jmpr_ne", "jmpr", 16,
2454     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2455   },
2456 /* jmpr $cond,$rel */
2457   {
2458     XC16X_INSN_JMPR_ULT, "jmpr_ult", "jmpr", 16,
2459     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2460   },
2461 /* jmpr $cond,$rel */
2462   {
2463     XC16X_INSN_JMPR_ULE, "jmpr_ule", "jmpr", 16,
2464     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2465   },
2466 /* jmpr $cond,$rel */
2467   {
2468     XC16X_INSN_JMPR_UGE, "jmpr_uge", "jmpr", 16,
2469     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2470   },
2471 /* jmpr $cond,$rel */
2472   {
2473     XC16X_INSN_JMPR_UGT, "jmpr_ugt", "jmpr", 16,
2474     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2475   },
2476 /* jmpr $cond,$rel */
2477   {
2478     XC16X_INSN_JMPR_SLE, "jmpr_sle", "jmpr", 16,
2479     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2480   },
2481 /* jmpr $cond,$rel */
2482   {
2483     XC16X_INSN_JMPR_SGE, "jmpr_sge", "jmpr", 16,
2484     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2485   },
2486 /* jmpr $cond,$rel */
2487   {
2488     XC16X_INSN_JMPR_NET, "jmpr_net", "jmpr", 16,
2489     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2490   },
2491 /* jmpr $cond,$rel */
2492   {
2493     XC16X_INSN_JMPR_UC, "jmpr_uc", "jmpr", 16,
2494     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2495   },
2496 /* jmpr $cond,$rel */
2497   {
2498     XC16X_INSN_JMPR_SLT, "jmpr_slt", "jmpr", 16,
2499     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2500   },
2501 /* jmps $hash$segm$useg8,$hash$sof$usof16 */
2502   {
2503     XC16X_INSN_JMPSEG, "jmpseg", "jmps", 32,
2504     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2505   },
2506 /* jmps $seg,$caddr */
2507   {
2508     XC16X_INSN_JMPS, "jmps", "jmps", 32,
2509     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2510   },
2511 /* jb $genreg$dot$qlobit,$relhi */
2512   {
2513     XC16X_INSN_JB, "jb", "jb", 32,
2514     { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2515   },
2516 /* jbc $genreg$dot$qlobit,$relhi */
2517   {
2518     XC16X_INSN_JBC, "jbc", "jbc", 32,
2519     { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2520   },
2521 /* jnb $genreg$dot$qlobit,$relhi */
2522   {
2523     XC16X_INSN_JNB, "jnb", "jnb", 32,
2524     { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2525   },
2526 /* jnbs $genreg$dot$qlobit,$relhi */
2527   {
2528     XC16X_INSN_JNBS, "jnbs", "jnbs", 32,
2529     { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2530   },
2531 /* calla+ $extcond,$caddr */
2532   {
2533     XC16X_INSN_CALLA0, "calla0", "calla+", 32,
2534     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2535   },
2536 /* calla $extcond,$caddr */
2537   {
2538     XC16X_INSN_CALLA1, "calla1", "calla", 32,
2539     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2540   },
2541 /* calla- $extcond,$caddr */
2542   {
2543     XC16X_INSN_CALLA_, "calla-", "calla-", 32,
2544     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2545   },
2546 /* calli $icond,[$sr] */
2547   {
2548     XC16X_INSN_CALLI, "calli", "calli", 16,
2549     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2550   },
2551 /* callr $rel */
2552   {
2553     XC16X_INSN_CALLR, "callr", "callr", 16,
2554     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2555   },
2556 /* calls $hash$segm$useg8,$hash$sof$usof16 */
2557   {
2558     XC16X_INSN_CALLSEG, "callseg", "calls", 32,
2559     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2560   },
2561 /* calls $seg,$caddr */
2562   {
2563     XC16X_INSN_CALLS, "calls", "calls", 32,
2564     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2565   },
2566 /* pcall $reg8,$caddr */
2567   {
2568     XC16X_INSN_PCALL, "pcall", "pcall", 32,
2569     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2570   },
2571 /* trap $hash$uimm7 */
2572   {
2573     XC16X_INSN_TRAP, "trap", "trap", 16,
2574     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2575   },
2576 /* ret */
2577   {
2578     XC16X_INSN_RET, "ret", "ret", 16,
2579     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2580   },
2581 /* rets */
2582   {
2583     XC16X_INSN_RETS, "rets", "rets", 16,
2584     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2585   },
2586 /* retp $reg8 */
2587   {
2588     XC16X_INSN_RETP, "retp", "retp", 16,
2589     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2590   },
2591 /* reti */
2592   {
2593     XC16X_INSN_RETI, "reti", "reti", 16,
2594     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2595   },
2596 /* pop $reg8 */
2597   {
2598     XC16X_INSN_POP, "pop", "pop", 16,
2599     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2600   },
2601 /* push $reg8 */
2602   {
2603     XC16X_INSN_PUSH, "push", "push", 16,
2604     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2605   },
2606 /* scxt $reg8,$hash$uimm16 */
2607   {
2608     XC16X_INSN_SCXTI, "scxti", "scxt", 32,
2609     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2610   },
2611 /* scxt $reg8,$pof$upof16 */
2612   {
2613     XC16X_INSN_SCXTRPOFM, "scxtrpofm", "scxt", 32,
2614     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2615   },
2616 /* scxt $regmem8,$memgr8 */
2617   {
2618     XC16X_INSN_SCXTMG, "scxtmg", "scxt", 32,
2619     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2620   },
2621 /* scxt $reg8,$memory */
2622   {
2623     XC16X_INSN_SCXTM, "scxtm", "scxt", 32,
2624     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2625   },
2626 /* nop */
2627   {
2628     XC16X_INSN_NOP, "nop", "nop", 16,
2629     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2630   },
2631 /* srst */
2632   {
2633     XC16X_INSN_SRSTM, "srstm", "srst", 32,
2634     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2635   },
2636 /* idle */
2637   {
2638     XC16X_INSN_IDLEM, "idlem", "idle", 32,
2639     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2640   },
2641 /* pwrdn */
2642   {
2643     XC16X_INSN_PWRDNM, "pwrdnm", "pwrdn", 32,
2644     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2645   },
2646 /* diswdt */
2647   {
2648     XC16X_INSN_DISWDTM, "diswdtm", "diswdt", 32,
2649     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2650   },
2651 /* enwdt */
2652   {
2653     XC16X_INSN_ENWDTM, "enwdtm", "enwdt", 32,
2654     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2655   },
2656 /* einit */
2657   {
2658     XC16X_INSN_EINITM, "einitm", "einit", 32,
2659     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2660   },
2661 /* srvwdt */
2662   {
2663     XC16X_INSN_SRVWDTM, "srvwdtm", "srvwdt", 32,
2664     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2665   },
2666 /* sbrk */
2667   {
2668     XC16X_INSN_SBRK, "sbrk", "sbrk", 16,
2669     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2670   },
2671 /* atomic $hash$uimm2 */
2672   {
2673     XC16X_INSN_ATOMIC, "atomic", "atomic", 16,
2674     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2675   },
2676 /* extr $hash$uimm2 */
2677   {
2678     XC16X_INSN_EXTR, "extr", "extr", 16,
2679     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2680   },
2681 /* extp $sr,$hash$uimm2 */
2682   {
2683     XC16X_INSN_EXTP, "extp", "extp", 16,
2684     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2685   },
2686 /* extp $hash$pagenum,$hash$uimm2 */
2687   {
2688     XC16X_INSN_EXTP1, "extp1", "extp", 32,
2689     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2690   },
2691 /* extp $hash$pag$upag16,$hash$uimm2 */
2692   {
2693     XC16X_INSN_EXTPG1, "extpg1", "extp", 32,
2694     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2695   },
2696 /* extpr $sr,$hash$uimm2 */
2697   {
2698     XC16X_INSN_EXTPR, "extpr", "extpr", 16,
2699     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2700   },
2701 /* extpr $hash$pagenum,$hash$uimm2 */
2702   {
2703     XC16X_INSN_EXTPR1, "extpr1", "extpr", 32,
2704     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2705   },
2706 /* exts $sr,$hash$uimm2 */
2707   {
2708     XC16X_INSN_EXTS, "exts", "exts", 16,
2709     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2710   },
2711 /* exts $hash$seghi8,$hash$uimm2 */
2712   {
2713     XC16X_INSN_EXTS1, "exts1", "exts", 32,
2714     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2715   },
2716 /* extsr $sr,$hash$uimm2 */
2717   {
2718     XC16X_INSN_EXTSR, "extsr", "extsr", 16,
2719     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2720   },
2721 /* extsr $hash$seghi8,$hash$uimm2 */
2722   {
2723     XC16X_INSN_EXTSR1, "extsr1", "extsr", 32,
2724     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2725   },
2726 /* prior $dr,$sr */
2727   {
2728     XC16X_INSN_PRIOR, "prior", "prior", 16,
2729     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2730   },
2731 /* bclr $RegNam */
2732   {
2733     XC16X_INSN_BCLR18, "bclr18", "bclr", 16,
2734     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2735   },
2736 /* bclr $reg8$dot$qbit */
2737   {
2738     XC16X_INSN_BCLR0, "bclr0", "bclr", 16,
2739     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2740   },
2741 /* bclr $reg8$dot$qbit */
2742   {
2743     XC16X_INSN_BCLR1, "bclr1", "bclr", 16,
2744     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2745   },
2746 /* bclr $reg8$dot$qbit */
2747   {
2748     XC16X_INSN_BCLR2, "bclr2", "bclr", 16,
2749     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2750   },
2751 /* bclr $reg8$dot$qbit */
2752   {
2753     XC16X_INSN_BCLR3, "bclr3", "bclr", 16,
2754     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2755   },
2756 /* bclr $reg8$dot$qbit */
2757   {
2758     XC16X_INSN_BCLR4, "bclr4", "bclr", 16,
2759     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2760   },
2761 /* bclr $reg8$dot$qbit */
2762   {
2763     XC16X_INSN_BCLR5, "bclr5", "bclr", 16,
2764     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2765   },
2766 /* bclr $reg8$dot$qbit */
2767   {
2768     XC16X_INSN_BCLR6, "bclr6", "bclr", 16,
2769     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2770   },
2771 /* bclr $reg8$dot$qbit */
2772   {
2773     XC16X_INSN_BCLR7, "bclr7", "bclr", 16,
2774     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2775   },
2776 /* bclr $reg8$dot$qbit */
2777   {
2778     XC16X_INSN_BCLR8, "bclr8", "bclr", 16,
2779     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2780   },
2781 /* bclr $reg8$dot$qbit */
2782   {
2783     XC16X_INSN_BCLR9, "bclr9", "bclr", 16,
2784     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2785   },
2786 /* bclr $reg8$dot$qbit */
2787   {
2788     XC16X_INSN_BCLR10, "bclr10", "bclr", 16,
2789     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2790   },
2791 /* bclr $reg8$dot$qbit */
2792   {
2793     XC16X_INSN_BCLR11, "bclr11", "bclr", 16,
2794     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2795   },
2796 /* bclr $reg8$dot$qbit */
2797   {
2798     XC16X_INSN_BCLR12, "bclr12", "bclr", 16,
2799     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2800   },
2801 /* bclr $reg8$dot$qbit */
2802   {
2803     XC16X_INSN_BCLR13, "bclr13", "bclr", 16,
2804     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2805   },
2806 /* bclr $reg8$dot$qbit */
2807   {
2808     XC16X_INSN_BCLR14, "bclr14", "bclr", 16,
2809     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2810   },
2811 /* bclr $reg8$dot$qbit */
2812   {
2813     XC16X_INSN_BCLR15, "bclr15", "bclr", 16,
2814     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2815   },
2816 /* bset $RegNam */
2817   {
2818     XC16X_INSN_BSET19, "bset19", "bset", 16,
2819     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2820   },
2821 /* bset $reg8$dot$qbit */
2822   {
2823     XC16X_INSN_BSET0, "bset0", "bset", 16,
2824     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2825   },
2826 /* bset $reg8$dot$qbit */
2827   {
2828     XC16X_INSN_BSET1, "bset1", "bset", 16,
2829     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2830   },
2831 /* bset $reg8$dot$qbit */
2832   {
2833     XC16X_INSN_BSET2, "bset2", "bset", 16,
2834     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2835   },
2836 /* bset $reg8$dot$qbit */
2837   {
2838     XC16X_INSN_BSET3, "bset3", "bset", 16,
2839     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2840   },
2841 /* bset $reg8$dot$qbit */
2842   {
2843     XC16X_INSN_BSET4, "bset4", "bset", 16,
2844     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2845   },
2846 /* bset $reg8$dot$qbit */
2847   {
2848     XC16X_INSN_BSET5, "bset5", "bset", 16,
2849     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2850   },
2851 /* bset $reg8$dot$qbit */
2852   {
2853     XC16X_INSN_BSET6, "bset6", "bset", 16,
2854     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2855   },
2856 /* bset $reg8$dot$qbit */
2857   {
2858     XC16X_INSN_BSET7, "bset7", "bset", 16,
2859     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2860   },
2861 /* bset $reg8$dot$qbit */
2862   {
2863     XC16X_INSN_BSET8, "bset8", "bset", 16,
2864     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2865   },
2866 /* bset $reg8$dot$qbit */
2867   {
2868     XC16X_INSN_BSET9, "bset9", "bset", 16,
2869     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2870   },
2871 /* bset $reg8$dot$qbit */
2872   {
2873     XC16X_INSN_BSET10, "bset10", "bset", 16,
2874     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2875   },
2876 /* bset $reg8$dot$qbit */
2877   {
2878     XC16X_INSN_BSET11, "bset11", "bset", 16,
2879     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2880   },
2881 /* bset $reg8$dot$qbit */
2882   {
2883     XC16X_INSN_BSET12, "bset12", "bset", 16,
2884     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2885   },
2886 /* bset $reg8$dot$qbit */
2887   {
2888     XC16X_INSN_BSET13, "bset13", "bset", 16,
2889     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2890   },
2891 /* bset $reg8$dot$qbit */
2892   {
2893     XC16X_INSN_BSET14, "bset14", "bset", 16,
2894     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2895   },
2896 /* bset $reg8$dot$qbit */
2897   {
2898     XC16X_INSN_BSET15, "bset15", "bset", 16,
2899     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2900   },
2901 /* bmov $reghi8$dot$qhibit,$reg8$dot$qlobit */
2902   {
2903     XC16X_INSN_BMOV, "bmov", "bmov", 32,
2904     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2905   },
2906 /* bmovn $reghi8$dot$qhibit,$reg8$dot$qlobit */
2907   {
2908     XC16X_INSN_BMOVN, "bmovn", "bmovn", 32,
2909     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2910   },
2911 /* band $reghi8$dot$qhibit,$reg8$dot$qlobit */
2912   {
2913     XC16X_INSN_BAND, "band", "band", 32,
2914     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2915   },
2916 /* bor $reghi8$dot$qhibit,$reg8$dot$qlobit */
2917   {
2918     XC16X_INSN_BOR, "bor", "bor", 32,
2919     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2920   },
2921 /* bxor $reghi8$dot$qhibit,$reg8$dot$qlobit */
2922   {
2923     XC16X_INSN_BXOR, "bxor", "bxor", 32,
2924     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2925   },
2926 /* bcmp $reghi8$dot$qhibit,$reg8$dot$qlobit */
2927   {
2928     XC16X_INSN_BCMP, "bcmp", "bcmp", 32,
2929     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2930   },
2931 /* bfldl $reg8,$hash$mask8,$hash$datahi8 */
2932   {
2933     XC16X_INSN_BFLDL, "bfldl", "bfldl", 32,
2934     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2935   },
2936 /* bfldh $reg8,$hash$masklo8,$hash$data8 */
2937   {
2938     XC16X_INSN_BFLDH, "bfldh", "bfldh", 32,
2939     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2940   },
2941 /* cmp $src1,$src2 */
2942   {
2943     XC16X_INSN_CMPR, "cmpr", "cmp", 16,
2944     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2945   },
2946 /* cmpb $drb,$srb */
2947   {
2948     XC16X_INSN_CMPBR, "cmpbr", "cmpb", 16,
2949     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2950   },
2951 /* cmp $src1,$hash$uimm3 */
2952   {
2953     XC16X_INSN_CMPRI, "cmpri", "cmp", 16,
2954     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2955   },
2956 /* cmpb $drb,$hash$uimm3 */
2957   {
2958     XC16X_INSN_CMPBRI, "cmpbri", "cmpb", 16,
2959     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2960   },
2961 /* cmp $reg8,$hash$uimm16 */
2962   {
2963     XC16X_INSN_CMPI, "cmpi", "cmp", 32,
2964     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2965   },
2966 /* cmpb $regb8,$hash$uimm8 */
2967   {
2968     XC16X_INSN_CMPBI, "cmpbi", "cmpb", 32,
2969     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2970   },
2971 /* cmp $dr,[$sr2] */
2972   {
2973     XC16X_INSN_CMPR2, "cmpr2", "cmp", 16,
2974     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2975   },
2976 /* cmpb $drb,[$sr2] */
2977   {
2978     XC16X_INSN_CMPBR2, "cmpbr2", "cmpb", 16,
2979     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2980   },
2981 /* cmp $dr,[$sr2+] */
2982   {
2983     XC16X_INSN_CMP2I, "cmp2i", "cmp", 16,
2984     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2985   },
2986 /* cmpb $drb,[$sr2+] */
2987   {
2988     XC16X_INSN_CMPB2I, "cmpb2i", "cmpb", 16,
2989     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2990   },
2991 /* cmp $reg8,$pof$upof16 */
2992   {
2993     XC16X_INSN_CMP04, "cmp04", "cmp", 32,
2994     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2995   },
2996 /* cmpb $regb8,$pof$upof16 */
2997   {
2998     XC16X_INSN_CMPB4, "cmpb4", "cmpb", 32,
2999     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3000   },
3001 /* cmp $regmem8,$memgr8 */
3002   {
3003     XC16X_INSN_CMP004, "cmp004", "cmp", 32,
3004     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3005   },
3006 /* cmp $reg8,$memory */
3007   {
3008     XC16X_INSN_CMP0004, "cmp0004", "cmp", 32,
3009     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3010   },
3011 /* cmpb $regbmem8,$memgr8 */
3012   {
3013     XC16X_INSN_CMPB04, "cmpb04", "cmpb", 32,
3014     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3015   },
3016 /* cmpb $regb8,$memory */
3017   {
3018     XC16X_INSN_CMPB004, "cmpb004", "cmpb", 32,
3019     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3020   },
3021 /* cmpd1 $sr,$hash$uimm4 */
3022   {
3023     XC16X_INSN_CMPD1RI, "cmpd1ri", "cmpd1", 16,
3024     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3025   },
3026 /* cmpd2 $sr,$hash$uimm4 */
3027   {
3028     XC16X_INSN_CMPD2RI, "cmpd2ri", "cmpd2", 16,
3029     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3030   },
3031 /* cmpi1 $sr,$hash$uimm4 */
3032   {
3033     XC16X_INSN_CMPI1RI, "cmpi1ri", "cmpi1", 16,
3034     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3035   },
3036 /* cmpi2 $sr,$hash$uimm4 */
3037   {
3038     XC16X_INSN_CMPI2RI, "cmpi2ri", "cmpi2", 16,
3039     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3040   },
3041 /* cmpd1 $reg8,$hash$uimm16 */
3042   {
3043     XC16X_INSN_CMPD1RIM, "cmpd1rim", "cmpd1", 32,
3044     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3045   },
3046 /* cmpd2 $reg8,$hash$uimm16 */
3047   {
3048     XC16X_INSN_CMPD2RIM, "cmpd2rim", "cmpd2", 32,
3049     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3050   },
3051 /* cmpi1 $reg8,$hash$uimm16 */
3052   {
3053     XC16X_INSN_CMPI1RIM, "cmpi1rim", "cmpi1", 32,
3054     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3055   },
3056 /* cmpi2 $reg8,$hash$uimm16 */
3057   {
3058     XC16X_INSN_CMPI2RIM, "cmpi2rim", "cmpi2", 32,
3059     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3060   },
3061 /* cmpd1 $reg8,$pof$upof16 */
3062   {
3063     XC16X_INSN_CMPD1RP, "cmpd1rp", "cmpd1", 32,
3064     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3065   },
3066 /* cmpd2 $reg8,$pof$upof16 */
3067   {
3068     XC16X_INSN_CMPD2RP, "cmpd2rp", "cmpd2", 32,
3069     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3070   },
3071 /* cmpi1 $reg8,$pof$upof16 */
3072   {
3073     XC16X_INSN_CMPI1RP, "cmpi1rp", "cmpi1", 32,
3074     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3075   },
3076 /* cmpi2 $reg8,$pof$upof16 */
3077   {
3078     XC16X_INSN_CMPI2RP, "cmpi2rp", "cmpi2", 32,
3079     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3080   },
3081 /* cmpd1 $regmem8,$memgr8 */
3082   {
3083     XC16X_INSN_CMPD1RM, "cmpd1rm", "cmpd1", 32,
3084     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3085   },
3086 /* cmpd2 $regmem8,$memgr8 */
3087   {
3088     XC16X_INSN_CMPD2RM, "cmpd2rm", "cmpd2", 32,
3089     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3090   },
3091 /* cmpi1 $regmem8,$memgr8 */
3092   {
3093     XC16X_INSN_CMPI1RM, "cmpi1rm", "cmpi1", 32,
3094     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3095   },
3096 /* cmpi2 $regmem8,$memgr8 */
3097   {
3098     XC16X_INSN_CMPI2RM, "cmpi2rm", "cmpi2", 32,
3099     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3100   },
3101 /* cmpd1 $reg8,$memory */
3102   {
3103     XC16X_INSN_CMPD1RMI, "cmpd1rmi", "cmpd1", 32,
3104     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3105   },
3106 /* cmpd2 $reg8,$memory */
3107   {
3108     XC16X_INSN_CMPD2RMI, "cmpd2rmi", "cmpd2", 32,
3109     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3110   },
3111 /* cmpi1 $reg8,$memory */
3112   {
3113     XC16X_INSN_CMPI1RMI, "cmpi1rmi", "cmpi1", 32,
3114     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3115   },
3116 /* cmpi2 $reg8,$memory */
3117   {
3118     XC16X_INSN_CMPI2RMI, "cmpi2rmi", "cmpi2", 32,
3119     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3120   },
3121 /* shl $dr,$sr */
3122   {
3123     XC16X_INSN_SHLR, "shlr", "shl", 16,
3124     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3125   },
3126 /* shr $dr,$sr */
3127   {
3128     XC16X_INSN_SHRR, "shrr", "shr", 16,
3129     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3130   },
3131 /* rol $dr,$sr */
3132   {
3133     XC16X_INSN_ROLR, "rolr", "rol", 16,
3134     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3135   },
3136 /* ror $dr,$sr */
3137   {
3138     XC16X_INSN_RORR, "rorr", "ror", 16,
3139     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3140   },
3141 /* ashr $dr,$sr */
3142   {
3143     XC16X_INSN_ASHRR, "ashrr", "ashr", 16,
3144     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3145   },
3146 /* shl $sr,$hash$uimm4 */
3147   {
3148     XC16X_INSN_SHLRI, "shlri", "shl", 16,
3149     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3150   },
3151 /* shr $sr,$hash$uimm4 */
3152   {
3153     XC16X_INSN_SHRRI, "shrri", "shr", 16,
3154     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3155   },
3156 /* rol $sr,$hash$uimm4 */
3157   {
3158     XC16X_INSN_ROLRI, "rolri", "rol", 16,
3159     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3160   },
3161 /* ror $sr,$hash$uimm4 */
3162   {
3163     XC16X_INSN_RORRI, "rorri", "ror", 16,
3164     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3165   },
3166 /* ashr $sr,$hash$uimm4 */
3167   {
3168     XC16X_INSN_ASHRRI, "ashrri", "ashr", 16,
3169     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3170   },
3171 };
3172
3173 #undef OP
3174 #undef A
3175
3176 /* Initialize anything needed to be done once, before any cpu_open call.  */
3177
3178 static void
3179 init_tables (void)
3180 {
3181 }
3182
3183 #ifndef opcodes_error_handler
3184 #define opcodes_error_handler(...) \
3185   fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
3186 #endif
3187
3188 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
3189 static void build_hw_table      (CGEN_CPU_TABLE *);
3190 static void build_ifield_table  (CGEN_CPU_TABLE *);
3191 static void build_operand_table (CGEN_CPU_TABLE *);
3192 static void build_insn_table    (CGEN_CPU_TABLE *);
3193 static void xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *);
3194
3195 /* Subroutine of xc16x_cgen_cpu_open to look up a mach via its bfd name.  */
3196
3197 static const CGEN_MACH *
3198 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
3199 {
3200   while (table->name)
3201     {
3202       if (strcmp (name, table->bfd_name) == 0)
3203         return table;
3204       ++table;
3205     }
3206   return NULL;
3207 }
3208
3209 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table.  */
3210
3211 static void
3212 build_hw_table (CGEN_CPU_TABLE *cd)
3213 {
3214   int i;
3215   int machs = cd->machs;
3216   const CGEN_HW_ENTRY *init = & xc16x_cgen_hw_table[0];
3217   /* MAX_HW is only an upper bound on the number of selected entries.
3218      However each entry is indexed by it's enum so there can be holes in
3219      the table.  */
3220   const CGEN_HW_ENTRY **selected =
3221     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
3222
3223   cd->hw_table.init_entries = init;
3224   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
3225   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
3226   /* ??? For now we just use machs to determine which ones we want.  */
3227   for (i = 0; init[i].name != NULL; ++i)
3228     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
3229         & machs)
3230       selected[init[i].type] = &init[i];
3231   cd->hw_table.entries = selected;
3232   cd->hw_table.num_entries = MAX_HW;
3233 }
3234
3235 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table.  */
3236
3237 static void
3238 build_ifield_table (CGEN_CPU_TABLE *cd)
3239 {
3240   cd->ifld_table = & xc16x_cgen_ifld_table[0];
3241 }
3242
3243 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table.  */
3244
3245 static void
3246 build_operand_table (CGEN_CPU_TABLE *cd)
3247 {
3248   int i;
3249   int machs = cd->machs;
3250   const CGEN_OPERAND *init = & xc16x_cgen_operand_table[0];
3251   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
3252      However each entry is indexed by it's enum so there can be holes in
3253      the table.  */
3254   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
3255
3256   cd->operand_table.init_entries = init;
3257   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
3258   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
3259   /* ??? For now we just use mach to determine which ones we want.  */
3260   for (i = 0; init[i].name != NULL; ++i)
3261     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
3262         & machs)
3263       selected[init[i].type] = &init[i];
3264   cd->operand_table.entries = selected;
3265   cd->operand_table.num_entries = MAX_OPERANDS;
3266 }
3267
3268 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table.
3269    ??? This could leave out insns not supported by the specified mach/isa,
3270    but that would cause errors like "foo only supported by bar" to become
3271    "unknown insn", so for now we include all insns and require the app to
3272    do the checking later.
3273    ??? On the other hand, parsing of such insns may require their hardware or
3274    operand elements to be in the table [which they mightn't be].  */
3275
3276 static void
3277 build_insn_table (CGEN_CPU_TABLE *cd)
3278 {
3279   int i;
3280   const CGEN_IBASE *ib = & xc16x_cgen_insn_table[0];
3281   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
3282
3283   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
3284   for (i = 0; i < MAX_INSNS; ++i)
3285     insns[i].base = &ib[i];
3286   cd->insn_table.init_entries = insns;
3287   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
3288   cd->insn_table.num_init_entries = MAX_INSNS;
3289 }
3290
3291 /* Subroutine of xc16x_cgen_cpu_open to rebuild the tables.  */
3292
3293 static void
3294 xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
3295 {
3296   int i;
3297   CGEN_BITSET *isas = cd->isas;
3298   unsigned int machs = cd->machs;
3299
3300   cd->int_insn_p = CGEN_INT_INSN_P;
3301
3302   /* Data derived from the isa spec.  */
3303 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
3304   cd->default_insn_bitsize = UNSET;
3305   cd->base_insn_bitsize = UNSET;
3306   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
3307   cd->max_insn_bitsize = 0;
3308   for (i = 0; i < MAX_ISAS; ++i)
3309     if (cgen_bitset_contains (isas, i))
3310       {
3311         const CGEN_ISA *isa = & xc16x_cgen_isa_table[i];
3312
3313         /* Default insn sizes of all selected isas must be
3314            equal or we set the result to 0, meaning "unknown".  */
3315         if (cd->default_insn_bitsize == UNSET)
3316           cd->default_insn_bitsize = isa->default_insn_bitsize;
3317         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
3318           ; /* This is ok.  */
3319         else
3320           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
3321
3322         /* Base insn sizes of all selected isas must be equal
3323            or we set the result to 0, meaning "unknown".  */
3324         if (cd->base_insn_bitsize == UNSET)
3325           cd->base_insn_bitsize = isa->base_insn_bitsize;
3326         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
3327           ; /* This is ok.  */
3328         else
3329           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
3330
3331         /* Set min,max insn sizes.  */
3332         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
3333           cd->min_insn_bitsize = isa->min_insn_bitsize;
3334         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
3335           cd->max_insn_bitsize = isa->max_insn_bitsize;
3336       }
3337
3338   /* Data derived from the mach spec.  */
3339   for (i = 0; i < MAX_MACHS; ++i)
3340     if (((1 << i) & machs) != 0)
3341       {
3342         const CGEN_MACH *mach = & xc16x_cgen_mach_table[i];
3343
3344         if (mach->insn_chunk_bitsize != 0)
3345         {
3346           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
3347             {
3348               opcodes_error_handler
3349                 (/* xgettext:c-format */
3350                  _("internal error: xc16x_cgen_rebuild_tables: "
3351                    "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
3352                  cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
3353               abort ();
3354             }
3355
3356           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
3357         }
3358       }
3359
3360   /* Determine which hw elements are used by MACH.  */
3361   build_hw_table (cd);
3362
3363   /* Build the ifield table.  */
3364   build_ifield_table (cd);
3365
3366   /* Determine which operands are used by MACH/ISA.  */
3367   build_operand_table (cd);
3368
3369   /* Build the instruction table.  */
3370   build_insn_table (cd);
3371 }
3372
3373 /* Initialize a cpu table and return a descriptor.
3374    It's much like opening a file, and must be the first function called.
3375    The arguments are a set of (type/value) pairs, terminated with
3376    CGEN_CPU_OPEN_END.
3377
3378    Currently supported values:
3379    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
3380    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
3381    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
3382    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
3383    CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice
3384    CGEN_CPU_OPEN_END:     terminates arguments
3385
3386    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
3387    precluded.  */
3388
3389 CGEN_CPU_DESC
3390 xc16x_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
3391 {
3392   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
3393   static int init_p;
3394   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
3395   unsigned int machs = 0; /* 0 = "unspecified" */
3396   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
3397   enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN;
3398   va_list ap;
3399
3400   if (! init_p)
3401     {
3402       init_tables ();
3403       init_p = 1;
3404     }
3405
3406   memset (cd, 0, sizeof (*cd));
3407
3408   va_start (ap, arg_type);
3409   while (arg_type != CGEN_CPU_OPEN_END)
3410     {
3411       switch (arg_type)
3412         {
3413         case CGEN_CPU_OPEN_ISAS :
3414           isas = va_arg (ap, CGEN_BITSET *);
3415           break;
3416         case CGEN_CPU_OPEN_MACHS :
3417           machs = va_arg (ap, unsigned int);
3418           break;
3419         case CGEN_CPU_OPEN_BFDMACH :
3420           {
3421             const char *name = va_arg (ap, const char *);
3422             const CGEN_MACH *mach =
3423               lookup_mach_via_bfd_name (xc16x_cgen_mach_table, name);
3424
3425             if (mach != NULL)
3426               machs |= 1 << mach->num;
3427             break;
3428           }
3429         case CGEN_CPU_OPEN_ENDIAN :
3430           endian = va_arg (ap, enum cgen_endian);
3431           break;
3432         case CGEN_CPU_OPEN_INSN_ENDIAN :
3433           insn_endian = va_arg (ap, enum cgen_endian);
3434           break;
3435         default :
3436           opcodes_error_handler
3437             (/* xgettext:c-format */
3438              _("internal error: xc16x_cgen_cpu_open: "
3439                "unsupported argument `%d'"),
3440              arg_type);
3441           abort (); /* ??? return NULL? */
3442         }
3443       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
3444     }
3445   va_end (ap);
3446
3447   /* Mach unspecified means "all".  */
3448   if (machs == 0)
3449     machs = (1 << MAX_MACHS) - 1;
3450   /* Base mach is always selected.  */
3451   machs |= 1;
3452   if (endian == CGEN_ENDIAN_UNKNOWN)
3453     {
3454       /* ??? If target has only one, could have a default.  */
3455       opcodes_error_handler
3456         (/* xgettext:c-format */
3457          _("internal error: xc16x_cgen_cpu_open: no endianness specified"));
3458       abort ();
3459     }
3460
3461   cd->isas = cgen_bitset_copy (isas);
3462   cd->machs = machs;
3463   cd->endian = endian;
3464   cd->insn_endian
3465     = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian);
3466
3467   /* Table (re)builder.  */
3468   cd->rebuild_tables = xc16x_cgen_rebuild_tables;
3469   xc16x_cgen_rebuild_tables (cd);
3470
3471   /* Default to not allowing signed overflow.  */
3472   cd->signed_overflow_ok_p = 0;
3473
3474   return (CGEN_CPU_DESC) cd;
3475 }
3476
3477 /* Cover fn to xc16x_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
3478    MACH_NAME is the bfd name of the mach.  */
3479
3480 CGEN_CPU_DESC
3481 xc16x_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
3482 {
3483   return xc16x_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
3484                                CGEN_CPU_OPEN_ENDIAN, endian,
3485                                CGEN_CPU_OPEN_END);
3486 }
3487
3488 /* Close a cpu table.
3489    ??? This can live in a machine independent file, but there's currently
3490    no place to put this file (there's no libcgen).  libopcodes is the wrong
3491    place as some simulator ports use this but they don't use libopcodes.  */
3492
3493 void
3494 xc16x_cgen_cpu_close (CGEN_CPU_DESC cd)
3495 {
3496   unsigned int i;
3497   const CGEN_INSN *insns;
3498
3499   if (cd->macro_insn_table.init_entries)
3500     {
3501       insns = cd->macro_insn_table.init_entries;
3502       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
3503         if (CGEN_INSN_RX ((insns)))
3504           regfree (CGEN_INSN_RX (insns));
3505     }
3506
3507   if (cd->insn_table.init_entries)
3508     {
3509       insns = cd->insn_table.init_entries;
3510       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
3511         if (CGEN_INSN_RX (insns))
3512           regfree (CGEN_INSN_RX (insns));
3513     }
3514
3515   free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
3516   free ((CGEN_INSN *) cd->insn_table.init_entries);
3517   free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
3518   free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
3519   free (cd);
3520 }
3521