3 #ld
: --no
-tls
-optimize tmpdir
/libtlslib
.so
5 #target
: powerpc64
*-*-*
9 Disassembly of section \
.text
:
11 .* <.*plt_call\
.__tls_get_addr(|_opt
)>:
12 .*: (e8
03 00 00|
00 00 03 e8
) ld r0
,0\
(r3\
)
13 .*: (e9
83 00 08|
08 00 83 e9
) ld r12
,8\
(r3\
)
14 .*: (2c
20 00 00|
00 00 20 2c
) cmpdi r0
,0
15 .*: (7c
60 1b 78|
78 1b 60 7c
) mr r0
,r3
16 .*: (7c
6c
6a
14|
14 6a
6c
7c
) add r3
,r12
,r13
17 .*: (4d 82 00 20|
20 00 82 4d) beqlr
*
18 .*: (7c
03 03 78|
78 03 03 7c
) mr r3
,r0
19 .*: (7c
08 02 a6|a6
02 08 7c
) mflr r0
20 .*: (f8
01 00 20|
20 00 01 f8
) std r0
,32\
(r1\
)
21 .*: (f8
41 00 28|
28 00 41 f8
) std r2
,40\
(r1\
)
22 .*: (e9
82 80 88|
88 80 82 e9
) ld r12
,-32632\
(r2\
)
23 .*: (7d 89 03 a6|a6
03 89 7d) mtctr r12
24 .*: (e8
42 80 90|
90 80 42 e8
) ld r2
,-32624\
(r2\
)
25 .*: (4e
80 04 21|
21 04 80 4e
) bctrl
26 .*: (e8
41 00 28|
28 00 41 e8
) ld r2
,40\
(r1\
)
27 .*: (e8
01 00 20|
20 00 01 e8
) ld r0
,32\
(r1\
)
28 .*: (7c
08 03 a6|a6
03 08 7c
) mtlr r0
29 .*: (4e
80 00 20|
20 00 80 4e
) blr
32 .*: (38 62 80 20|
20 80 62 38) addi r3
,r2
,-32736
33 .*: (4b ff ff b5|b5 ff ff
4b) bl
.*
34 .*: (60 00 00 00|
00 00 00 60) nop
35 .*: (38 62 80 30|
30 80 62 38) addi r3
,r2
,-32720
36 .*: (4b ff ff a9|a9 ff ff
4b) bl
.*
37 .*: (60 00 00 00|
00 00 00 60) nop
38 .*: (38 62 80 48|
48 80 62 38) addi r3
,r2
,-32696
39 .*: (4b ff ff
9d|
9d ff ff
4b) bl
.*
40 .*: (60 00 00 00|
00 00 00 60) nop
41 .*: (38 62 80 60|
60 80 62 38) addi r3
,r2
,-32672
42 .*: (4b ff ff
91|
91 ff ff
4b) bl
.*
43 .*: (60 00 00 00|
00 00 00 60) nop
44 .*: (39 23 80 40|
40 80 23 39) addi r9
,r3
,-32704
45 .*: (3d 23 00 00|
00 00 23 3d) addis r9
,r3
,0
46 .*: (81 49 80 48|
48 80 49 81) lwz r10
,-32696\
(r9\
)
47 .*: (e9
22 80 40|
40 80 22 e9
) ld r9
,-32704\
(r2\
)
48 .*: (7d 49 18 2a|
2a
18 49 7d) ldx r10
,r9
,r3
49 .*: (e9
22 80 58|
58 80 22 e9
) ld r9
,-32680\
(r2\
)
50 .*: (7d 49 6a
2e|
2e
6a
49 7d) lhzx r10
,r9
,r13
51 .*: (89 4d 90 60|
60 90 4d 89) lbz r10
,-28576\
(r13\
)
52 .*: (3d 2d 00 00|
00 00 2d 3d) addis r9
,r13
,0
53 .*: (99 49 90 68|
68 90 49 99) stb r10
,-28568\
(r9\
)
54 .*: (38 62 80 08|
08 80 62 38) addi r3
,r2
,-32760
55 .*: (4b ff ff
5d|
5d ff ff
4b) bl
.*
56 .*: (60 00 00 00|
00 00 00 60) nop
57 .*: (38 62 80 60|
60 80 62 38) addi r3
,r2
,-32672
58 .*: (4b ff ff
51|
51 ff ff
4b) bl
.*
59 .*: (60 00 00 00|
00 00 00 60) nop
60 .*: (f9
43 80 08|
08 80 43 f9
) std r10
,-32760\
(r3\
)
61 .*: (3d 23 00 00|
00 00 23 3d) addis r9
,r3
,0
62 .*: (91 49 80 10|
10 80 49 91) stw r10
,-32752\
(r9\
)
63 .*: (e9
22 80 18|
18 80 22 e9
) ld r9
,-32744\
(r2\
)
64 .*: (7d 49 19 2a|
2a
19 49 7d) stdx r10
,r9
,r3
65 .*: (e9
22 80 58|
58 80 22 e9
) ld r9
,-32680\
(r2\
)
66 .*: (7d 49 6b 2e|
2e
6b 49 7d) sthx r10
,r9
,r13
67 .*: (e9
4d 90 2a|
2a
90 4d e9
) lwa r10
,-28632\
(r13\
)
68 .*: (3d 2d 00 00|
00 00 2d 3d) addis r9
,r13
,0
69 .*: (a9
49 90 30|
30 90 49 a9
) lha r10
,-28624\
(r9\
)
70 .*: (00 00 00 00|c0
02 01 00) .*
71 .*: (00 01 02 c0|
00 00 00 00) .*
73 .* <__glink_PLTresolve
>:
74 .*: (7d 88 02 a6|a6
02 88 7d) mflr r12
75 .*: (42 9f 00 05|
05 00 9f 42) bcl
.*
76 .*: (7d 68 02 a6|a6
02 68 7d) mflr r11
77 .*: (e8
4b ff f0|f0 ff
4b e8
) ld r2
,-16\
(r11\
)
78 .*: (7d 88 03 a6|a6
03 88 7d) mtlr r12
79 .*: (7d 62 5a
14|
14 5a
62 7d) add r11
,r2
,r11
80 .*: (e9
8b 00 00|
00 00 8b e9
) ld r12
,0\
(r11\
)
81 .*: (e8
4b 00 08|
08 00 4b e8
) ld r2
,8\
(r11\
)
82 .*: (7d 89 03 a6|a6
03 89 7d) mtctr r12
83 .*: (e9
6b 00 10|
10 00 6b e9
) ld r11
,16\
(r11\
)
84 .*: (4e
80 04 20|
20 04 80 4e
) bctr
86 .* <__tls_get_addr_opt
@plt>:
87 .*: (38 00 00 00|
00 00 00 38) li r0
,0
88 .*: (4b ff ff d0|d0 ff ff
4b) b
.* <__glink_PLTresolve
>
