gas/itbl-parse.y

   1
   2 /* itbl-parse.y
   3
   4          Copyright (C) 1997  Free Software Foundation, Inc.
   5
   6          This file is part of GAS, the GNU Assembler.
   7
   8          GAS is free software; you can redistribute it and/or modify
   9          it under the terms of the GNU General Public License as published by
  10          the Free Software Foundation; either version 2, or (at your option)
  11          any later version.
  12
  13          GAS is distributed in the hope that it will be useful,
  14          but WITHOUT ANY WARRANTY; without even the implied warranty of
  15          MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16          GNU General Public License for more details.
  17
  18          You should have received a copy of the GNU General Public License
  19          along with GAS; see the file COPYING.  If not, write to the Free
  20          Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21          02111-1307, USA.  */
  22
  23 %{
  24
  25 /*
  26
  27 Yacc grammar for instruction table entries.
  28
  29 =======================================================================
  30 Original Instruction table specification document:
  31
  32             MIPS Coprocessor Table Specification
  33             ====================================
  34
  35 This document describes the format of the MIPS coprocessor table.  The
  36 table specifies a list of valid functions, data registers and control
  37 registers that can be used in coprocessor instructions.  This list,
  38 together with the coprocessor instruction classes listed below,
  39 specifies the complete list of coprocessor instructions that will
  40 be recognized and assembled by the GNU assembler.  In effect,
  41 this makes the GNU assembler table-driven, where the table is
  42 specified by the programmer.
  43
  44 The table is an ordinary text file that the GNU assembler reads when
  45 it starts.  Using the information in the table, the assembler
  46 generates an internal list of valid coprocessor registers and
  47 functions.  The assembler uses this internal list in addition to the
  48 standard MIPS registers and instructions which are built-in to the
  49 assembler during code generation.
  50
  51 To specify the coprocessor table when invoking the GNU assembler, use
  52 the command line option "--itbl file", where file is the
  53 complete name of the table, including path and extension.
  54
  55 Examples:
  56
  57             gas -t cop.tbl test.s -o test.o
  58             gas -t /usr/local/lib/cop.tbl test.s -o test.o
  59             gas --itbl d:\gnu\data\cop.tbl test.s -o test.o
  60
  61 Only one table may be supplied during a single invocation of
  62 the assembler.
  63
  64
  65 Instruction classes
  66 ===================
  67
  68 Below is a list of the valid coprocessor instruction classes for
  69 any given coprocessor "z".  These instructions are already recognized
  70 by the assembler, and are listed here only for reference.
  71
  72 Class   format                        instructions
  73 -------------------------------------------------
  74 Class1:
  75         op base rt offset
  76                                                             LWCz rt,offset (base)
  77                                                             SWCz rt,offset (base)
  78 Class2:
  79         COPz sub rt rd 0
  80                                                             MTCz rt,rd
  81                                                             MFCz rt,rd
  82                                                             CTCz rt,rd
  83                                                             CFCz rt,rd
  84 Class3:
  85         COPz CO cofun
  86                                                             COPz cofun
  87 Class4:
  88         COPz BC br offset
  89                                                             BCzT offset
  90                                                             BCzF offset
  91 Class5:
  92         COPz sub rt rd 0
  93                                                             DMFCz rt,rd
  94                                                             DMTCz rt,rd
  95 Class6:
  96         op base rt offset
  97                                                             LDCz rt,offset (base)
  98                                                             SDCz rt,offset (base)
  99 Class7:
 100         COPz BC br offset
 101                                                             BCzTL offset
 102                                                             BCzFL offset
 103
 104 The coprocessor table defines coprocessor-specific registers that can
 105 be used with all of the above classes of instructions, where
 106 appropriate.  It also defines additional coprocessor-specific
 107 functions for Class3 (COPz cofun) instructions, Thus, the table allows
 108 the programmer to use convenient mnemonics and operands for these
 109 functions, instead of the COPz mmenmonic and cofun operand.
 110
 111 The names of the MIPS general registers and their aliases are defined
 112 by the assembler and will be recognized as valid register names by the
 113 assembler when used (where allowed) in coprocessor instructions.
 114 However, the names and values of all coprocessor data and control
 115 register mnemonics must be specified in the coprocessor table.
 116
 117
 118 Table Grammar
 119 =============
 120
 121 Here is the grammar for the coprocessor table:
 122
 123             table -> entry*
 124
 125             entry -> [z entrydef] [comment] '\n'
 126
 127             entrydef -> type name val
 128             entrydef -> 'insn' name val funcdef ; type of entry (instruction)
 129
 130             z -> 'p'['0'..'3']               ; processor number
 131             type -> ['dreg' | 'creg' | 'greg' ]      ; type of entry (register)
 132         ; 'dreg', 'creg' or 'greg' specifies a data, control, or general
 133         ;           register mnemonic, respectively
 134             name -> [ltr|dec]*               ; mnemonic of register/function
 135             val -> [dec|hex]                 ; register/function number (integer constant)
 136
 137             funcdef -> frange flags fields
 138                                 ; bitfield range for opcode
 139                                 ; list of fields' formats
 140             fields -> field*
 141             field -> [','] ftype frange flags
 142             flags -> ['*' flagexpr]
 143             flagexpr -> '[' flagexpr ']'
 144             flagexpr -> val '|' flagexpr
 145             ftype -> [ type | 'immed' | 'addr' ]
 146         ; 'immed' specifies an immediate value; see grammar for "val" above
 147                 ; 'addr' specifies a C identifier; name of symbol to be resolved at
 148         ;           link time
 149             frange -> ':' val '-' val   ; starting to ending bit positions, where
 150                                 ; where 0 is least significant bit
 151             frange -> (null)            ; default range of 31-0 will be assumed
 152
 153             comment -> [';'|'#'] [char]*
 154             char -> any printable character
 155             ltr -> ['a'..'z'|'A'..'Z']
 156             dec -> ['0'..'9']*                                       ; value in decimal
 157             hex -> '0x'['0'..'9' | 'a'..'f' | 'A'..'F']*        ; value in hexidecimal
 158
 159
 160 Examples
 161 ========
 162
 163 Example 1:
 164
 165 The table:
 166
 167             p1 dreg d1 1             ; data register "d1" for COP1 has value 1
 168             p1 creg c3 3             ; ctrl register "c3" for COP1 has value 3
 169             p3 func fill 0x1f:24-20           ; function "fill" for COP3 has value 31 and
 170                         ; no fields
 171
 172 will allow the assembler to accept the following coprocessor instructions:
 173
 174             LWC1 d1,0x100 ($2)
 175             fill
 176
 177 Here, the general purpose register "$2", and instruction "LWC1", are standard
 178 mnemonics built-in to the MIPS assembler.
 179
 180
 181 Example 2:
 182
 183 The table:
 184
 185             p3 dreg d3 3             ; data register "d3" for COP3 has value 3
 186             p3 creg c2 22            ; control register "c2" for COP3 has value 22
 187             p3 func fee 0x1f:24-20 dreg:17-13 creg:12-8 immed:7-0
 188                 ; function "fee" for COP3 has value 31, and 3 fields
 189                 ; consisting of a data register, a control register,
 190                 ; and an immediate value.
 191
 192 will allow the assembler to accept the following coprocessor instruction:
 193
 194             fee d3,c2,0x1
 195
 196 and will emit the object code:
 197
 198             31-26  25 24-20 19-18  17-13 12-8  7-0
 199             COPz   CO fun                     dreg  creg  immed
 200             010011 1  11111 00       00011 10110 00000001
 201
 202             0x4ff07601
 203
 204
 205 Example 3:
 206
 207 The table:
 208
 209             p3 dreg d3 3             ; data register "d3" for COP3 has value 3
 210             p3 creg c2 22            ; control register "c2" for COP3 has value 22
 211             p3 func fuu 0x01f00001 dreg:17-13 creg:12-8
 212
 213 will allow the assembler to accept the following coprocessor
 214 instruction:
 215
 216             fuu d3,c2
 217
 218 and will emit the object code:
 219
 220             31-26  25 24-20 19-18  17-13 12-8  7-0
 221             COPz   CO fun                     dreg  creg
 222             010011 1  11111 00       00011 10110 00000001
 223
 224             0x4ff07601
 225
 226 In this way, the programmer can force arbitrary bits of an instruction
 227 to have predefined values.
 228
 229 =======================================================================
 230 Additional notes:
 231
 232 Encoding of ranges:
 233 To handle more than one bit position range within an instruction,
 234 use 0s to mask out the ranges which don't apply.
 235 May decide to modify the syntax to allow commas separate multiple
 236 ranges within an instruction (range','range).
 237
 238 Changes in grammar:
 239         The number of parms argument to the function entry
 240 was deleted from the original format such that we now count the fields.
 241
 242 ----
 243 FIXME! should really change lexical analyzer
 244 to recognize 'dreg' etc. in context sensative way.
 245 Currently function names or mnemonics may be incorrectly parsed as keywords
 246
 247 FIXME! hex is ambiguous with any digit
 248
 249 */
 250
 251 #include <stdio.h>
 252 #include "itbl-ops.h"
 253
 254 /* #define DEBUG */
 255
 256 #ifdef DEBUG
 257 #ifndef DBG_LVL
 258 #define DBG_LVL 1
 259 #endif
 260 #else
 261 #define DBG_LVL 0
 262 #endif
 263
 264 #if DBG_LVL >= 1
 265 #define DBG(x) printf x
 266 #else
 267 #define DBG(x)
 268 #endif
 269
 270 #if DBG_LVL >= 2
 271 #define DBGL2(x) printf x
 272 #else
 273 #define DBGL2(x)
 274 #endif
 275
 276 static int sbit, ebit;
 277 static struct itbl_entry *insn=0;
 278 extern int insntbl_line;
 279 int yyparse (void);
 280 int yylex (void);
 281
 282 %}
 283
 284 %union
 285   {
 286     char *str;
 287     int num;
 288     int processor;
 289     unsigned long val;
 290   }
 291
 292 %token      DREG CREG GREG IMMED ADDR INSN NUM ID NL PNUM
 293 %type       <val> value flags flagexpr
 294 %type       <num> number NUM ftype regtype pnum PNUM
 295 %type       <str> ID name
 296
 297 %start insntbl
 298
 299 %%
 300
 301 insntbl:
 302         entrys
 303         ;
 304
 305 entrys:
 306         entry entrys
 307         |
 308         ;
 309
 310 entry:
 311         pnum regtype name value NL
 312           {
 313             DBG (("line %d: entry pnum=%d type=%d name=%s value=x%x\n",
 314                     insntbl_line, $1, $2, $3, $4));
 315             itbl_add_reg ($1, $2, $3, $4);
 316           }
 317         | pnum INSN name value range flags
 318           {
 319             DBG (("line %d: entry pnum=%d type=INSN name=%s value=x%x",
 320                     insntbl_line, $1, $3, $4));
 321             DBG ((" sbit=%d ebit=%d flags=0x%x\n", sbit, ebit, $6));
 322             insn=itbl_add_insn ($1, $3, $4, sbit, ebit, $6);
 323           }
 324         fieldspecs NL
 325         | NL
 326         | error NL
 327         ;
 328
 329 fieldspecs:
 330         ',' fieldspec fieldspecs
 331         | fieldspec fieldspecs
 332         |
 333         ;
 334
 335 ftype:
 336         regtype
 337           {
 338             DBGL2 (("ftype\n"));
 339             $$ = $1;
 340           }
 341         | ADDR
 342           {
 343             DBGL2 (("addr\n"));
 344             $$ = ADDR;
 345           }
 346         | IMMED
 347           {
 348             DBGL2 (("immed\n"));
 349             $$ = IMMED;
 350           }
 351         ;
 352
 353 fieldspec:
 354         ftype range flags
 355           {
 356             DBG (("line %d: field type=%d sbit=%d ebit=%d, flags=0x%x\n",
 357                     insntbl_line, $1, sbit, ebit, $3));
 358             itbl_add_operand (insn, $1, sbit, ebit, $3);
 359           }
 360         ;
 361
 362 flagexpr:
 363         NUM '|' flagexpr
 364           {
 365             $$ = $1 | $3;
 366           }
 367         | '[' flagexpr ']'
 368           {
 369             $$ = $2;
 370           }
 371         | NUM
 372           {
 373             $$ = $1;
 374           }
 375         ;
 376
 377 flags:
 378         '*' flagexpr
 379           {
 380             DBGL2 (("flags=%d\n", $2));
 381             $$ = $2;
 382           }
 383         |
 384           {
 385             $$ = 0;
 386           }
 387         ;
 388
 389 range:
 390         ':' NUM '-' NUM
 391           {
 392             DBGL2 (("range %d %d\n", $2, $4));
 393             sbit = $2;
 394             ebit = $4;
 395           }
 396         |
 397           {
 398             sbit = 31;
 399             ebit = 0;
 400           }
 401         ;
 402
 403 pnum:
 404         PNUM
 405           {
 406             DBGL2 (("pnum=%d\n",$1));
 407             $$ = $1;
 408           }
 409         ;
 410
 411 regtype:
 412              DREG
 413           {
 414             DBGL2 (("dreg\n"));
 415             $$ = DREG;
 416           }
 417         | CREG
 418           {
 419             DBGL2 (("creg\n"));
 420             $$ = CREG;
 421           }
 422         | GREG
 423           {
 424             DBGL2 (("greg\n"));
 425             $$ = GREG;
 426           }
 427         ;
 428
 429 name:
 430         ID
 431           {
 432             DBGL2 (("name=%s\n",$1));
 433             $$ = $1;
 434           }
 435         ;
 436
 437 number:
 438         NUM
 439           {
 440             DBGL2 (("num=%d\n",$1));
 441             $$ = $1;
 442           }
 443         ;
 444
 445 value:
 446         NUM
 447           {
 448             DBGL2 (("val=x%x\n",$1));
 449             $$ = $1;
 450           }
 451         ;
 452 %%
 453
 454 void
 455 yyerror (char *msg)
 456 {
 457   printf ("line %d: %s\n", insntbl_line, msg);
 458 }
 459