opcodes/
[binutils-gdb.git] / opcodes / i386-opc.h
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1 /* Declarations for Intel 80386 opcode table
2 Copyright 2007, 2008, 2009, 2010, 2012
3 Free Software Foundation, Inc.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
22 #include "opcode/i386.h"
23 #ifdef HAVE_LIMITS_H
24 #include <limits.h>
25 #endif
27 #ifndef CHAR_BIT
28 #define CHAR_BIT 8
29 #endif
31 /* Position of cpu flags bitfiled. */
33 enum
35 /* i186 or better required */
36 Cpu186 = 0,
37 /* i286 or better required */
38 Cpu286,
39 /* i386 or better required */
40 Cpu386,
41 /* i486 or better required */
42 Cpu486,
43 /* i585 or better required */
44 Cpu586,
45 /* i686 or better required */
46 Cpu686,
47 /* CLFLUSH Instruction support required */
48 CpuClflush,
49 /* NOP Instruction support required */
50 CpuNop,
51 /* SYSCALL Instructions support required */
52 CpuSYSCALL,
53 /* Floating point support required */
54 Cpu8087,
55 /* i287 support required */
56 Cpu287,
57 /* i387 support required */
58 Cpu387,
59 /* i686 and floating point support required */
60 Cpu687,
61 /* SSE3 and floating point support required */
62 CpuFISTTP,
63 /* MMX support required */
64 CpuMMX,
65 /* SSE support required */
66 CpuSSE,
67 /* SSE2 support required */
68 CpuSSE2,
69 /* 3dnow! support required */
70 Cpu3dnow,
71 /* 3dnow! Extensions support required */
72 Cpu3dnowA,
73 /* SSE3 support required */
74 CpuSSE3,
75 /* VIA PadLock required */
76 CpuPadLock,
77 /* AMD Secure Virtual Machine Ext-s required */
78 CpuSVME,
79 /* VMX Instructions required */
80 CpuVMX,
81 /* SMX Instructions required */
82 CpuSMX,
83 /* SSSE3 support required */
84 CpuSSSE3,
85 /* SSE4a support required */
86 CpuSSE4a,
87 /* ABM New Instructions required */
88 CpuABM,
89 /* SSE4.1 support required */
90 CpuSSE4_1,
91 /* SSE4.2 support required */
92 CpuSSE4_2,
93 /* AVX support required */
94 CpuAVX,
95 /* AVX2 support required */
96 CpuAVX2,
97 /* Intel L1OM support required */
98 CpuL1OM,
99 /* Intel K1OM support required */
100 CpuK1OM,
101 /* Xsave/xrstor New Instructions support required */
102 CpuXsave,
103 /* Xsaveopt New Instructions support required */
104 CpuXsaveopt,
105 /* AES support required */
106 CpuAES,
107 /* PCLMUL support required */
108 CpuPCLMUL,
109 /* FMA support required */
110 CpuFMA,
111 /* FMA4 support required */
112 CpuFMA4,
113 /* XOP support required */
114 CpuXOP,
115 /* LWP support required */
116 CpuLWP,
117 /* BMI support required */
118 CpuBMI,
119 /* TBM support required */
120 CpuTBM,
121 /* MOVBE Instruction support required */
122 CpuMovbe,
123 /* EPT Instructions required */
124 CpuEPT,
125 /* RDTSCP Instruction support required */
126 CpuRdtscp,
127 /* FSGSBASE Instructions required */
128 CpuFSGSBase,
129 /* RDRND Instructions required */
130 CpuRdRnd,
131 /* F16C Instructions required */
132 CpuF16C,
133 /* Intel BMI2 support required */
134 CpuBMI2,
135 /* LZCNT support required */
136 CpuLZCNT,
137 /* HLE support required */
138 CpuHLE,
139 /* RTM support required */
140 CpuRTM,
141 /* INVPCID Instructions required */
142 CpuINVPCID,
143 /* VMFUNC Instruction required */
144 CpuVMFUNC,
145 /* 64bit support available, used by -march= in assembler. */
146 CpuLM,
147 /* RDRSEED instruction required. */
148 CpuRDSEED,
149 /* Multi-presisionn add-carry instructions are required. */
150 CpuADX,
151 /* Supports prefetchw instruction. */
152 CpuPRFCHW,
153 /* 64bit support required */
154 Cpu64,
155 /* Not supported in the 64bit mode */
156 CpuNo64,
157 /* The last bitfield in i386_cpu_flags. */
158 CpuMax = CpuNo64
161 #define CpuNumOfUints \
162 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
163 #define CpuNumOfBits \
164 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
166 /* If you get a compiler error for zero width of the unused field,
167 comment it out. */
168 #define CpuUnused (CpuMax + 1)
170 /* We can check if an instruction is available with array instead
171 of bitfield. */
172 typedef union i386_cpu_flags
174 struct
176 unsigned int cpui186:1;
177 unsigned int cpui286:1;
178 unsigned int cpui386:1;
179 unsigned int cpui486:1;
180 unsigned int cpui586:1;
181 unsigned int cpui686:1;
182 unsigned int cpuclflush:1;
183 unsigned int cpunop:1;
184 unsigned int cpusyscall:1;
185 unsigned int cpu8087:1;
186 unsigned int cpu287:1;
187 unsigned int cpu387:1;
188 unsigned int cpu687:1;
189 unsigned int cpufisttp:1;
190 unsigned int cpummx:1;
191 unsigned int cpusse:1;
192 unsigned int cpusse2:1;
193 unsigned int cpua3dnow:1;
194 unsigned int cpua3dnowa:1;
195 unsigned int cpusse3:1;
196 unsigned int cpupadlock:1;
197 unsigned int cpusvme:1;
198 unsigned int cpuvmx:1;
199 unsigned int cpusmx:1;
200 unsigned int cpussse3:1;
201 unsigned int cpusse4a:1;
202 unsigned int cpuabm:1;
203 unsigned int cpusse4_1:1;
204 unsigned int cpusse4_2:1;
205 unsigned int cpuavx:1;
206 unsigned int cpuavx2:1;
207 unsigned int cpul1om:1;
208 unsigned int cpuk1om:1;
209 unsigned int cpuxsave:1;
210 unsigned int cpuxsaveopt:1;
211 unsigned int cpuaes:1;
212 unsigned int cpupclmul:1;
213 unsigned int cpufma:1;
214 unsigned int cpufma4:1;
215 unsigned int cpuxop:1;
216 unsigned int cpulwp:1;
217 unsigned int cpubmi:1;
218 unsigned int cputbm:1;
219 unsigned int cpumovbe:1;
220 unsigned int cpuept:1;
221 unsigned int cpurdtscp:1;
222 unsigned int cpufsgsbase:1;
223 unsigned int cpurdrnd:1;
224 unsigned int cpuf16c:1;
225 unsigned int cpubmi2:1;
226 unsigned int cpulzcnt:1;
227 unsigned int cpuhle:1;
228 unsigned int cpurtm:1;
229 unsigned int cpuinvpcid:1;
230 unsigned int cpuvmfunc:1;
231 unsigned int cpulm:1;
232 unsigned int cpurdseed:1;
233 unsigned int cpuadx:1;
234 unsigned int cpuprfchw:1;
235 unsigned int cpu64:1;
236 unsigned int cpuno64:1;
237 #ifdef CpuUnused
238 unsigned int unused:(CpuNumOfBits - CpuUnused);
239 #endif
240 } bitfield;
241 unsigned int array[CpuNumOfUints];
242 } i386_cpu_flags;
244 /* Position of opcode_modifier bits. */
246 enum
248 /* has direction bit. */
249 D = 0,
250 /* set if operands can be words or dwords encoded the canonical way */
252 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
253 operand in encoding. */
255 /* insn has a modrm byte. */
256 Modrm,
257 /* register is in low 3 bits of opcode */
258 ShortForm,
259 /* special case for jump insns. */
260 Jump,
261 /* call and jump */
262 JumpDword,
263 /* loop and jecxz */
264 JumpByte,
265 /* special case for intersegment leaps/calls */
266 JumpInterSegment,
267 /* FP insn memory format bit, sized by 0x4 */
268 FloatMF,
269 /* src/dest swap for floats. */
270 FloatR,
271 /* has float insn direction bit. */
272 FloatD,
273 /* needs size prefix if in 32-bit mode */
274 Size16,
275 /* needs size prefix if in 16-bit mode */
276 Size32,
277 /* needs size prefix if in 64-bit mode */
278 Size64,
279 /* check register size. */
280 CheckRegSize,
281 /* instruction ignores operand size prefix and in Intel mode ignores
282 mnemonic size suffix check. */
283 IgnoreSize,
284 /* default insn size depends on mode */
285 DefaultSize,
286 /* b suffix on instruction illegal */
287 No_bSuf,
288 /* w suffix on instruction illegal */
289 No_wSuf,
290 /* l suffix on instruction illegal */
291 No_lSuf,
292 /* s suffix on instruction illegal */
293 No_sSuf,
294 /* q suffix on instruction illegal */
295 No_qSuf,
296 /* long double suffix on instruction illegal */
297 No_ldSuf,
298 /* instruction needs FWAIT */
299 FWait,
300 /* quick test for string instructions */
301 IsString,
302 /* quick test for lockable instructions */
303 IsLockable,
304 /* fake an extra reg operand for clr, imul and special register
305 processing for some instructions. */
306 RegKludge,
307 /* The first operand must be xmm0 */
308 FirstXmm0,
309 /* An implicit xmm0 as the first operand */
310 Implicit1stXmm0,
311 /* The HLE prefix is OK:
312 1. With a LOCK prefix.
313 2. With or without a LOCK prefix.
314 3. With a RELEASE (0xf3) prefix.
316 #define HLEPrefixNone 0
317 #define HLEPrefixLock 1
318 #define HLEPrefixAny 2
319 #define HLEPrefixRelease 3
320 HLEPrefixOk,
321 /* An instruction on which a "rep" prefix is acceptable. */
322 RepPrefixOk,
323 /* Convert to DWORD */
324 ToDword,
325 /* Convert to QWORD */
326 ToQword,
327 /* Address prefix changes operand 0 */
328 AddrPrefixOp0,
329 /* opcode is a prefix */
330 IsPrefix,
331 /* instruction has extension in 8 bit imm */
332 ImmExt,
333 /* instruction don't need Rex64 prefix. */
334 NoRex64,
335 /* instruction require Rex64 prefix. */
336 Rex64,
337 /* deprecated fp insn, gets a warning */
338 Ugh,
339 /* insn has VEX prefix:
340 1: 128bit VEX prefix.
341 2: 256bit VEX prefix.
342 3: Scalar VEX prefix.
344 #define VEX128 1
345 #define VEX256 2
346 #define VEXScalar 3
347 Vex,
348 /* How to encode VEX.vvvv:
349 0: VEX.vvvv must be 1111b.
350 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
351 the content of source registers will be preserved.
352 VEX.DDS. The second register operand is encoded in VEX.vvvv
353 where the content of first source register will be overwritten
354 by the result.
355 VEX.NDD2. The second destination register operand is encoded in
356 VEX.vvvv for instructions with 2 destination register operands.
357 For assembler, there are no difference between VEX.NDS, VEX.DDS
358 and VEX.NDD2.
359 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
360 instructions with 1 destination register operand.
361 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
362 of the operands can access a memory location.
364 #define VEXXDS 1
365 #define VEXNDD 2
366 #define VEXLWP 3
367 VexVVVV,
368 /* How the VEX.W bit is used:
369 0: Set by the REX.W bit.
370 1: VEX.W0. Should always be 0.
371 2: VEX.W1. Should always be 1.
373 #define VEXW0 1
374 #define VEXW1 2
375 VexW,
376 /* VEX opcode prefix:
377 0: VEX 0x0F opcode prefix.
378 1: VEX 0x0F38 opcode prefix.
379 2: VEX 0x0F3A opcode prefix
380 3: XOP 0x08 opcode prefix.
381 4: XOP 0x09 opcode prefix
382 5: XOP 0x0A opcode prefix.
384 #define VEX0F 0
385 #define VEX0F38 1
386 #define VEX0F3A 2
387 #define XOP08 3
388 #define XOP09 4
389 #define XOP0A 5
390 VexOpcode,
391 /* number of VEX source operands:
392 0: <= 2 source operands.
393 1: 2 XOP source operands.
394 2: 3 source operands.
396 #define XOP2SOURCES 1
397 #define VEX3SOURCES 2
398 VexSources,
399 /* instruction has VEX 8 bit imm */
400 VexImmExt,
401 /* Instruction with vector SIB byte:
402 1: 128bit vector register.
403 2: 256bit vector register.
405 #define VecSIB128 1
406 #define VecSIB256 2
407 VecSIB,
408 /* SSE to AVX support required */
409 SSE2AVX,
410 /* No AVX equivalent */
411 NoAVX,
412 /* Compatible with old (<= 2.8.1) versions of gcc */
413 OldGcc,
414 /* AT&T mnemonic. */
415 ATTMnemonic,
416 /* AT&T syntax. */
417 ATTSyntax,
418 /* Intel syntax. */
419 IntelSyntax,
420 /* The last bitfield in i386_opcode_modifier. */
421 Opcode_Modifier_Max
424 typedef struct i386_opcode_modifier
426 unsigned int d:1;
427 unsigned int w:1;
428 unsigned int s:1;
429 unsigned int modrm:1;
430 unsigned int shortform:1;
431 unsigned int jump:1;
432 unsigned int jumpdword:1;
433 unsigned int jumpbyte:1;
434 unsigned int jumpintersegment:1;
435 unsigned int floatmf:1;
436 unsigned int floatr:1;
437 unsigned int floatd:1;
438 unsigned int size16:1;
439 unsigned int size32:1;
440 unsigned int size64:1;
441 unsigned int checkregsize:1;
442 unsigned int ignoresize:1;
443 unsigned int defaultsize:1;
444 unsigned int no_bsuf:1;
445 unsigned int no_wsuf:1;
446 unsigned int no_lsuf:1;
447 unsigned int no_ssuf:1;
448 unsigned int no_qsuf:1;
449 unsigned int no_ldsuf:1;
450 unsigned int fwait:1;
451 unsigned int isstring:1;
452 unsigned int islockable:1;
453 unsigned int regkludge:1;
454 unsigned int firstxmm0:1;
455 unsigned int implicit1stxmm0:1;
456 unsigned int hleprefixok:2;
457 unsigned int repprefixok:1;
458 unsigned int todword:1;
459 unsigned int toqword:1;
460 unsigned int addrprefixop0:1;
461 unsigned int isprefix:1;
462 unsigned int immext:1;
463 unsigned int norex64:1;
464 unsigned int rex64:1;
465 unsigned int ugh:1;
466 unsigned int vex:2;
467 unsigned int vexvvvv:2;
468 unsigned int vexw:2;
469 unsigned int vexopcode:3;
470 unsigned int vexsources:2;
471 unsigned int veximmext:1;
472 unsigned int vecsib:2;
473 unsigned int sse2avx:1;
474 unsigned int noavx:1;
475 unsigned int oldgcc:1;
476 unsigned int attmnemonic:1;
477 unsigned int attsyntax:1;
478 unsigned int intelsyntax:1;
479 } i386_opcode_modifier;
481 /* Position of operand_type bits. */
483 enum
485 /* 8bit register */
486 Reg8 = 0,
487 /* 16bit register */
488 Reg16,
489 /* 32bit register */
490 Reg32,
491 /* 64bit register */
492 Reg64,
493 /* Floating pointer stack register */
494 FloatReg,
495 /* MMX register */
496 RegMMX,
497 /* SSE register */
498 RegXMM,
499 /* AVX registers */
500 RegYMM,
501 /* Control register */
502 Control,
503 /* Debug register */
504 Debug,
505 /* Test register */
506 Test,
507 /* 2 bit segment register */
508 SReg2,
509 /* 3 bit segment register */
510 SReg3,
511 /* 1 bit immediate */
512 Imm1,
513 /* 8 bit immediate */
514 Imm8,
515 /* 8 bit immediate sign extended */
516 Imm8S,
517 /* 16 bit immediate */
518 Imm16,
519 /* 32 bit immediate */
520 Imm32,
521 /* 32 bit immediate sign extended */
522 Imm32S,
523 /* 64 bit immediate */
524 Imm64,
525 /* 8bit/16bit/32bit displacements are used in different ways,
526 depending on the instruction. For jumps, they specify the
527 size of the PC relative displacement, for instructions with
528 memory operand, they specify the size of the offset relative
529 to the base register, and for instructions with memory offset
530 such as `mov 1234,%al' they specify the size of the offset
531 relative to the segment base. */
532 /* 8 bit displacement */
533 Disp8,
534 /* 16 bit displacement */
535 Disp16,
536 /* 32 bit displacement */
537 Disp32,
538 /* 32 bit signed displacement */
539 Disp32S,
540 /* 64 bit displacement */
541 Disp64,
542 /* Accumulator %al/%ax/%eax/%rax */
543 Acc,
544 /* Floating pointer top stack register %st(0) */
545 FloatAcc,
546 /* Register which can be used for base or index in memory operand. */
547 BaseIndex,
548 /* Register to hold in/out port addr = dx */
549 InOutPortReg,
550 /* Register to hold shift count = cl */
551 ShiftCount,
552 /* Absolute address for jump. */
553 JumpAbsolute,
554 /* String insn operand with fixed es segment */
555 EsSeg,
556 /* RegMem is for instructions with a modrm byte where the register
557 destination operand should be encoded in the mod and regmem fields.
558 Normally, it will be encoded in the reg field. We add a RegMem
559 flag to the destination register operand to indicate that it should
560 be encoded in the regmem field. */
561 RegMem,
562 /* Memory. */
563 Mem,
564 /* BYTE memory. */
565 Byte,
566 /* WORD memory. 2 byte */
567 Word,
568 /* DWORD memory. 4 byte */
569 Dword,
570 /* FWORD memory. 6 byte */
571 Fword,
572 /* QWORD memory. 8 byte */
573 Qword,
574 /* TBYTE memory. 10 byte */
575 Tbyte,
576 /* XMMWORD memory. */
577 Xmmword,
578 /* YMMWORD memory. */
579 Ymmword,
580 /* Unspecified memory size. */
581 Unspecified,
582 /* Any memory size. */
583 Anysize,
585 /* Vector 4 bit immediate. */
586 Vec_Imm4,
588 /* The last bitfield in i386_operand_type. */
589 OTMax
592 #define OTNumOfUints \
593 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
594 #define OTNumOfBits \
595 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
597 /* If you get a compiler error for zero width of the unused field,
598 comment it out. */
599 #define OTUnused (OTMax + 1)
601 typedef union i386_operand_type
603 struct
605 unsigned int reg8:1;
606 unsigned int reg16:1;
607 unsigned int reg32:1;
608 unsigned int reg64:1;
609 unsigned int floatreg:1;
610 unsigned int regmmx:1;
611 unsigned int regxmm:1;
612 unsigned int regymm:1;
613 unsigned int control:1;
614 unsigned int debug:1;
615 unsigned int test:1;
616 unsigned int sreg2:1;
617 unsigned int sreg3:1;
618 unsigned int imm1:1;
619 unsigned int imm8:1;
620 unsigned int imm8s:1;
621 unsigned int imm16:1;
622 unsigned int imm32:1;
623 unsigned int imm32s:1;
624 unsigned int imm64:1;
625 unsigned int disp8:1;
626 unsigned int disp16:1;
627 unsigned int disp32:1;
628 unsigned int disp32s:1;
629 unsigned int disp64:1;
630 unsigned int acc:1;
631 unsigned int floatacc:1;
632 unsigned int baseindex:1;
633 unsigned int inoutportreg:1;
634 unsigned int shiftcount:1;
635 unsigned int jumpabsolute:1;
636 unsigned int esseg:1;
637 unsigned int regmem:1;
638 unsigned int mem:1;
639 unsigned int byte:1;
640 unsigned int word:1;
641 unsigned int dword:1;
642 unsigned int fword:1;
643 unsigned int qword:1;
644 unsigned int tbyte:1;
645 unsigned int xmmword:1;
646 unsigned int ymmword:1;
647 unsigned int unspecified:1;
648 unsigned int anysize:1;
649 unsigned int vec_imm4:1;
650 #ifdef OTUnused
651 unsigned int unused:(OTNumOfBits - OTUnused);
652 #endif
653 } bitfield;
654 unsigned int array[OTNumOfUints];
655 } i386_operand_type;
657 typedef struct insn_template
659 /* instruction name sans width suffix ("mov" for movl insns) */
660 char *name;
662 /* how many operands */
663 unsigned int operands;
665 /* base_opcode is the fundamental opcode byte without optional
666 prefix(es). */
667 unsigned int base_opcode;
668 #define Opcode_D 0x2 /* Direction bit:
669 set if Reg --> Regmem;
670 unset if Regmem --> Reg. */
671 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
672 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
674 /* extension_opcode is the 3 bit extension for group <n> insns.
675 This field is also used to store the 8-bit opcode suffix for the
676 AMD 3DNow! instructions.
677 If this template has no extension opcode (the usual case) use None
678 Instructions */
679 unsigned int extension_opcode;
680 #define None 0xffff /* If no extension_opcode is possible. */
682 /* Opcode length. */
683 unsigned char opcode_length;
685 /* cpu feature flags */
686 i386_cpu_flags cpu_flags;
688 /* the bits in opcode_modifier are used to generate the final opcode from
689 the base_opcode. These bits also are used to detect alternate forms of
690 the same instruction */
691 i386_opcode_modifier opcode_modifier;
693 /* operand_types[i] describes the type of operand i. This is made
694 by OR'ing together all of the possible type masks. (e.g.
695 'operand_types[i] = Reg|Imm' specifies that operand i can be
696 either a register or an immediate operand. */
697 i386_operand_type operand_types[MAX_OPERANDS];
699 insn_template;
701 extern const insn_template i386_optab[];
703 /* these are for register name --> number & type hash lookup */
704 typedef struct
706 char *reg_name;
707 i386_operand_type reg_type;
708 unsigned char reg_flags;
709 #define RegRex 0x1 /* Extended register. */
710 #define RegRex64 0x2 /* Extended 8 bit register. */
711 unsigned char reg_num;
712 #define RegRip ((unsigned char ) ~0)
713 #define RegEip (RegRip - 1)
714 /* EIZ and RIZ are fake index registers. */
715 #define RegEiz (RegEip - 1)
716 #define RegRiz (RegEiz - 1)
717 /* FLAT is a fake segment register (Intel mode). */
718 #define RegFlat ((unsigned char) ~0)
719 signed char dw2_regnum[2];
720 #define Dw2Inval (-1)
722 reg_entry;
724 /* Entries in i386_regtab. */
725 #define REGNAM_AL 1
726 #define REGNAM_AX 25
727 #define REGNAM_EAX 41
729 extern const reg_entry i386_regtab[];
730 extern const unsigned int i386_regtab_size;
732 typedef struct
734 char *seg_name;
735 unsigned int seg_prefix;
737 seg_entry;
739 extern const seg_entry cs;
740 extern const seg_entry ds;
741 extern const seg_entry ss;
742 extern const seg_entry es;
743 extern const seg_entry fs;
744 extern const seg_entry gs;