sim/bfin/dv-bfin_jtag.c

   1 /* Blackfin JTAG model.
   2
   3    Copyright (C) 2010-2024 Free Software Foundation, Inc.
   4    Contributed by Analog Devices, Inc.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 /* This must come before any other includes.  */
  22 #include "defs.h"
  23
  24 #include "sim-main.h"
  25 #include "devices.h"
  26 #include "dv-bfin_jtag.h"
  27
  28 /* XXX: This is mostly a stub.  There are more registers, but they're only
  29         accessible via the JTAG scan chain and not the MMR interface.  */
  30
  31 struct bfin_jtag
  32 {
  33   bu32 base;
  34
  35   /* Order after here is important -- matches hardware MMR layout.  */
  36   bu32 dspid;
  37   bu32 _pad0;
  38   bu32 dbgstat;
  39 };
  40 #define mmr_base()      offsetof(struct bfin_jtag, dspid)
  41 #define mmr_offset(mmr) (offsetof(struct bfin_jtag, mmr) - mmr_base())
  42
  43 static const char * const mmr_names[] =
  44 {
  45   "DSPID", NULL, "DBGSTAT",
  46 };
  47 #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
  48
  49 static unsigned
  50 bfin_jtag_io_write_buffer (struct hw *me, const void *source, int space,
  51                            address_word addr, unsigned nr_bytes)
  52 {
  53   struct bfin_jtag *jtag = hw_data (me);
  54   bu32 mmr_off;
  55   bu32 value;
  56   bu32 *valuep;
  57
  58   /* Invalid access mode is higher priority than missing register.  */
  59   if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
  60     return 0;
  61
  62   value = dv_load_4 (source);
  63   mmr_off = addr - jtag->base;
  64   valuep = (void *)((uintptr_t)jtag + mmr_base() + mmr_off);
  65
  66   HW_TRACE_WRITE ();
  67
  68   switch (mmr_off)
  69     {
  70     case mmr_offset(dbgstat):
  71       dv_w1c_4 (valuep, value, 0xc);
  72       break;
  73     case mmr_offset(dspid):
  74       /* Discard writes to these.  */
  75       break;
  76     default:
  77       dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
  78       return 0;
  79     }
  80
  81   return nr_bytes;
  82 }
  83
  84 static unsigned
  85 bfin_jtag_io_read_buffer (struct hw *me, void *dest, int space,
  86                           address_word addr, unsigned nr_bytes)
  87 {
  88   struct bfin_jtag *jtag = hw_data (me);
  89   bu32 mmr_off;
  90   bu32 value;
  91   bu32 *valuep;
  92
  93   /* Invalid access mode is higher priority than missing register.  */
  94   if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
  95     return 0;
  96
  97   mmr_off = addr - jtag->base;
  98   valuep = (void *)((uintptr_t)jtag + mmr_base() + mmr_off);
  99
 100   HW_TRACE_READ ();
 101
 102   switch (mmr_off)
 103     {
 104     case mmr_offset(dbgstat):
 105     case mmr_offset(dspid):
 106       value = *valuep;
 107       break;
 108     default:
 109       dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
 110       return 0;
 111     }
 112
 113   dv_store_4 (dest, value);
 114
 115   return nr_bytes;
 116 }
 117
 118 static void
 119 attach_bfin_jtag_regs (struct hw *me, struct bfin_jtag *jtag)
 120 {
 121   address_word attach_address;
 122   int attach_space;
 123   unsigned attach_size;
 124   reg_property_spec reg;
 125
 126   if (hw_find_property (me, "reg") == NULL)
 127     hw_abort (me, "Missing \"reg\" property");
 128
 129   if (!hw_find_reg_array_property (me, "reg", 0, &reg))
 130     hw_abort (me, "\"reg\" property must contain three addr/size entries");
 131
 132   hw_unit_address_to_attach_address (hw_parent (me),
 133                                      &reg.address,
 134                                      &attach_space, &attach_address, me);
 135   hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
 136
 137   if (attach_size != BFIN_COREMMR_JTAG_SIZE)
 138     hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_JTAG_SIZE);
 139
 140   hw_attach_address (hw_parent (me),
 141                      0, attach_space, attach_address, attach_size, me);
 142
 143   jtag->base = attach_address;
 144 }
 145
 146 static void
 147 bfin_jtag_finish (struct hw *me)
 148 {
 149   struct bfin_jtag *jtag;
 150
 151   jtag = HW_ZALLOC (me, struct bfin_jtag);
 152
 153   set_hw_data (me, jtag);
 154   set_hw_io_read_buffer (me, bfin_jtag_io_read_buffer);
 155   set_hw_io_write_buffer (me, bfin_jtag_io_write_buffer);
 156
 157   attach_bfin_jtag_regs (me, jtag);
 158
 159   /* Initialize the JTAG state.  */
 160   jtag->dspid = bfin_model_get_dspid (hw_system (me));
 161 }
 162
 163 const struct hw_descriptor dv_bfin_jtag_descriptor[] =
 164 {
 165   {"bfin_jtag", bfin_jtag_finish,},
 166   {NULL, NULL},
 167 };