bfd/xtensa-modules.c

   1 /* Xtensa configuration-specific ISA information.
   2    Copyright (C) 2003-2017 Free Software Foundation, Inc.
   3
   4    This file is part of BFD, the Binary File Descriptor library.
   5
   6    This program is free software; you can redistribute it and/or
   7    modify it under the terms of the GNU General Public License as
   8    published by the Free Software Foundation; either version 2 of the
   9    License, or (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14    General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "ansidecl.h"
  22 #include <xtensa-isa.h>
  23 #include "xtensa-isa-internal.h"
  24
  25 \f
  26 /* Sysregs.  */
  27
  28 static xtensa_sysreg_internal sysregs[] = {
  29   { "LBEG", 0, 0 },
  30   { "LEND", 1, 0 },
  31   { "LCOUNT", 2, 0 },
  32   { "BR", 4, 0 },
  33   { "ACCLO", 16, 0 },
  34   { "ACCHI", 17, 0 },
  35   { "M0", 32, 0 },
  36   { "M1", 33, 0 },
  37   { "M2", 34, 0 },
  38   { "M3", 35, 0 },
  39   { "PTEVADDR", 83, 0 },
  40   { "MMID", 89, 0 },
  41   { "DDR", 104, 0 },
  42   { "176", 176, 0 },
  43   { "208", 208, 0 },
  44   { "INTERRUPT", 226, 0 },
  45   { "INTCLEAR", 227, 0 },
  46   { "CCOUNT", 234, 0 },
  47   { "PRID", 235, 0 },
  48   { "ICOUNT", 236, 0 },
  49   { "CCOMPARE0", 240, 0 },
  50   { "CCOMPARE1", 241, 0 },
  51   { "CCOMPARE2", 242, 0 },
  52   { "VECBASE", 231, 0 },
  53   { "EPC1", 177, 0 },
  54   { "EPC2", 178, 0 },
  55   { "EPC3", 179, 0 },
  56   { "EPC4", 180, 0 },
  57   { "EPC5", 181, 0 },
  58   { "EPC6", 182, 0 },
  59   { "EPC7", 183, 0 },
  60   { "EXCSAVE1", 209, 0 },
  61   { "EXCSAVE2", 210, 0 },
  62   { "EXCSAVE3", 211, 0 },
  63   { "EXCSAVE4", 212, 0 },
  64   { "EXCSAVE5", 213, 0 },
  65   { "EXCSAVE6", 214, 0 },
  66   { "EXCSAVE7", 215, 0 },
  67   { "EPS2", 194, 0 },
  68   { "EPS3", 195, 0 },
  69   { "EPS4", 196, 0 },
  70   { "EPS5", 197, 0 },
  71   { "EPS6", 198, 0 },
  72   { "EPS7", 199, 0 },
  73   { "EXCCAUSE", 232, 0 },
  74   { "DEPC", 192, 0 },
  75   { "EXCVADDR", 238, 0 },
  76   { "WINDOWBASE", 72, 0 },
  77   { "WINDOWSTART", 73, 0 },
  78   { "SAR", 3, 0 },
  79   { "LITBASE", 5, 0 },
  80   { "PS", 230, 0 },
  81   { "MISC0", 244, 0 },
  82   { "MISC1", 245, 0 },
  83   { "MISC2", 246, 0 },
  84   { "MISC3", 247, 0 },
  85   { "INTENABLE", 228, 0 },
  86   { "DBREAKA0", 144, 0 },
  87   { "DBREAKC0", 160, 0 },
  88   { "DBREAKA1", 145, 0 },
  89   { "DBREAKC1", 161, 0 },
  90   { "IBREAKA0", 128, 0 },
  91   { "IBREAKA1", 129, 0 },
  92   { "IBREAKENABLE", 96, 0 },
  93   { "ICOUNTLEVEL", 237, 0 },
  94   { "DEBUGCAUSE", 233, 0 },
  95   { "RASID", 90, 0 },
  96   { "ITLBCFG", 91, 0 },
  97   { "DTLBCFG", 92, 0 },
  98   { "CPENABLE", 224, 0 },
  99   { "SCOMPARE1", 12, 0 },
 100   { "THREADPTR", 231, 1 },
 101   { "FCR", 232, 1 },
 102   { "FSR", 233, 1 }
 103 };
 104
 105 #define NUM_SYSREGS 74
 106 #define MAX_SPECIAL_REG 247
 107 #define MAX_USER_REG 233
 108
 109 \f
 110 /* Processor states.  */
 111
 112 static xtensa_state_internal states[] = {
 113   { "LCOUNT", 32, 0 },
 114   { "PC", 32, 0 },
 115   { "ICOUNT", 32, 0 },
 116   { "DDR", 32, 0 },
 117   { "INTERRUPT", 32, 0 },
 118   { "CCOUNT", 32, 0 },
 119   { "XTSYNC", 1, 0 },
 120   { "VECBASE", 22, 0 },
 121   { "EPC1", 32, 0 },
 122   { "EPC2", 32, 0 },
 123   { "EPC3", 32, 0 },
 124   { "EPC4", 32, 0 },
 125   { "EPC5", 32, 0 },
 126   { "EPC6", 32, 0 },
 127   { "EPC7", 32, 0 },
 128   { "EXCSAVE1", 32, 0 },
 129   { "EXCSAVE2", 32, 0 },
 130   { "EXCSAVE3", 32, 0 },
 131   { "EXCSAVE4", 32, 0 },
 132   { "EXCSAVE5", 32, 0 },
 133   { "EXCSAVE6", 32, 0 },
 134   { "EXCSAVE7", 32, 0 },
 135   { "EPS2", 15, 0 },
 136   { "EPS3", 15, 0 },
 137   { "EPS4", 15, 0 },
 138   { "EPS5", 15, 0 },
 139   { "EPS6", 15, 0 },
 140   { "EPS7", 15, 0 },
 141   { "EXCCAUSE", 6, 0 },
 142   { "PSINTLEVEL", 4, 0 },
 143   { "PSUM", 1, 0 },
 144   { "PSWOE", 1, 0 },
 145   { "PSRING", 2, 0 },
 146   { "PSEXCM", 1, 0 },
 147   { "DEPC", 32, 0 },
 148   { "EXCVADDR", 32, 0 },
 149   { "WindowBase", 4, 0 },
 150   { "WindowStart", 16, 0 },
 151   { "PSCALLINC", 2, 0 },
 152   { "PSOWB", 4, 0 },
 153   { "LBEG", 32, 0 },
 154   { "LEND", 32, 0 },
 155   { "SAR", 6, 0 },
 156   { "THREADPTR", 32, 0 },
 157   { "LITBADDR", 20, 0 },
 158   { "LITBEN", 1, 0 },
 159   { "MISC0", 32, 0 },
 160   { "MISC1", 32, 0 },
 161   { "MISC2", 32, 0 },
 162   { "MISC3", 32, 0 },
 163   { "ACC", 40, 0 },
 164   { "InOCDMode", 1, 0 },
 165   { "INTENABLE", 32, 0 },
 166   { "DBREAKA0", 32, 0 },
 167   { "DBREAKC0", 8, 0 },
 168   { "DBREAKA1", 32, 0 },
 169   { "DBREAKC1", 8, 0 },
 170   { "IBREAKA0", 32, 0 },
 171   { "IBREAKA1", 32, 0 },
 172   { "IBREAKENABLE", 2, 0 },
 173   { "ICOUNTLEVEL", 4, 0 },
 174   { "DEBUGCAUSE", 6, 0 },
 175   { "DBNUM", 4, 0 },
 176   { "CCOMPARE0", 32, 0 },
 177   { "CCOMPARE1", 32, 0 },
 178   { "CCOMPARE2", 32, 0 },
 179   { "ASID3", 8, 0 },
 180   { "ASID2", 8, 0 },
 181   { "ASID1", 8, 0 },
 182   { "INSTPGSZID4", 2, 0 },
 183   { "DATAPGSZID4", 2, 0 },
 184   { "PTBASE", 10, 0 },
 185   { "CPENABLE", 1, 0 },
 186   { "SCOMPARE1", 32, 0 },
 187   { "RoundMode", 2, 0 },
 188   { "InvalidEnable", 1, 0 },
 189   { "DivZeroEnable", 1, 0 },
 190   { "OverflowEnable", 1, 0 },
 191   { "UnderflowEnable", 1, 0 },
 192   { "InexactEnable", 1, 0 },
 193   { "InvalidFlag", 1, 0 },
 194   { "DivZeroFlag", 1, 0 },
 195   { "OverflowFlag", 1, 0 },
 196   { "UnderflowFlag", 1, 0 },
 197   { "InexactFlag", 1, 0 },
 198   { "FPreserved20", 20, 0 },
 199   { "FPreserved20a", 20, 0 },
 200   { "FPreserved5", 5, 0 },
 201   { "FPreserved7", 7, 0 }
 202 };
 203
 204 #define NUM_STATES 89
 205
 206 /* Macros for xtensa_state numbers (for use in iclasses because the
 207    state numbers are not available when the iclass table is generated).  */
 208
 209 #define STATE_LCOUNT 0
 210 #define STATE_PC 1
 211 #define STATE_ICOUNT 2
 212 #define STATE_DDR 3
 213 #define STATE_INTERRUPT 4
 214 #define STATE_CCOUNT 5
 215 #define STATE_XTSYNC 6
 216 #define STATE_VECBASE 7
 217 #define STATE_EPC1 8
 218 #define STATE_EPC2 9
 219 #define STATE_EPC3 10
 220 #define STATE_EPC4 11
 221 #define STATE_EPC5 12
 222 #define STATE_EPC6 13
 223 #define STATE_EPC7 14
 224 #define STATE_EXCSAVE1 15
 225 #define STATE_EXCSAVE2 16
 226 #define STATE_EXCSAVE3 17
 227 #define STATE_EXCSAVE4 18
 228 #define STATE_EXCSAVE5 19
 229 #define STATE_EXCSAVE6 20
 230 #define STATE_EXCSAVE7 21
 231 #define STATE_EPS2 22
 232 #define STATE_EPS3 23
 233 #define STATE_EPS4 24
 234 #define STATE_EPS5 25
 235 #define STATE_EPS6 26
 236 #define STATE_EPS7 27
 237 #define STATE_EXCCAUSE 28
 238 #define STATE_PSINTLEVEL 29
 239 #define STATE_PSUM 30
 240 #define STATE_PSWOE 31
 241 #define STATE_PSRING 32
 242 #define STATE_PSEXCM 33
 243 #define STATE_DEPC 34
 244 #define STATE_EXCVADDR 35
 245 #define STATE_WindowBase 36
 246 #define STATE_WindowStart 37
 247 #define STATE_PSCALLINC 38
 248 #define STATE_PSOWB 39
 249 #define STATE_LBEG 40
 250 #define STATE_LEND 41
 251 #define STATE_SAR 42
 252 #define STATE_THREADPTR 43
 253 #define STATE_LITBADDR 44
 254 #define STATE_LITBEN 45
 255 #define STATE_MISC0 46
 256 #define STATE_MISC1 47
 257 #define STATE_MISC2 48
 258 #define STATE_MISC3 49
 259 #define STATE_ACC 50
 260 #define STATE_InOCDMode 51
 261 #define STATE_INTENABLE 52
 262 #define STATE_DBREAKA0 53
 263 #define STATE_DBREAKC0 54
 264 #define STATE_DBREAKA1 55
 265 #define STATE_DBREAKC1 56
 266 #define STATE_IBREAKA0 57
 267 #define STATE_IBREAKA1 58
 268 #define STATE_IBREAKENABLE 59
 269 #define STATE_ICOUNTLEVEL 60
 270 #define STATE_DEBUGCAUSE 61
 271 #define STATE_DBNUM 62
 272 #define STATE_CCOMPARE0 63
 273 #define STATE_CCOMPARE1 64
 274 #define STATE_CCOMPARE2 65
 275 #define STATE_ASID3 66
 276 #define STATE_ASID2 67
 277 #define STATE_ASID1 68
 278 #define STATE_INSTPGSZID4 69
 279 #define STATE_DATAPGSZID4 70
 280 #define STATE_PTBASE 71
 281 #define STATE_CPENABLE 72
 282 #define STATE_SCOMPARE1 73
 283 #define STATE_RoundMode 74
 284 #define STATE_InvalidEnable 75
 285 #define STATE_DivZeroEnable 76
 286 #define STATE_OverflowEnable 77
 287 #define STATE_UnderflowEnable 78
 288 #define STATE_InexactEnable 79
 289 #define STATE_InvalidFlag 80
 290 #define STATE_DivZeroFlag 81
 291 #define STATE_OverflowFlag 82
 292 #define STATE_UnderflowFlag 83
 293 #define STATE_InexactFlag 84
 294 #define STATE_FPreserved20 85
 295 #define STATE_FPreserved20a 86
 296 #define STATE_FPreserved5 87
 297 #define STATE_FPreserved7 88
 298
 299 \f
 300 /* Field definitions.  */
 301
 302 static unsigned
 303 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
 304 {
 305   unsigned tie_t = 0;
 306   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 307   return tie_t;
 308 }
 309
 310 static void
 311 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 312 {
 313   uint32 tie_t;
 314   tie_t = (val << 28) >> 28;
 315   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 316 }
 317
 318 static unsigned
 319 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
 320 {
 321   unsigned tie_t = 0;
 322   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 323   return tie_t;
 324 }
 325
 326 static void
 327 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 328 {
 329   uint32 tie_t;
 330   tie_t = (val << 28) >> 28;
 331   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 332 }
 333
 334 static unsigned
 335 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
 336 {
 337   unsigned tie_t = 0;
 338   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 339   return tie_t;
 340 }
 341
 342 static void
 343 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 344 {
 345   uint32 tie_t;
 346   tie_t = (val << 28) >> 28;
 347   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 348 }
 349
 350 static unsigned
 351 Field_t_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 352 {
 353   unsigned tie_t = 0;
 354   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 355   return tie_t;
 356 }
 357
 358 static void
 359 Field_t_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 360 {
 361   uint32 tie_t;
 362   tie_t = (val << 28) >> 28;
 363   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 364 }
 365
 366 static unsigned
 367 Field_t_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
 368 {
 369   unsigned tie_t = 0;
 370   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 371   return tie_t;
 372 }
 373
 374 static void
 375 Field_t_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
 376 {
 377   uint32 tie_t;
 378   tie_t = (val << 28) >> 28;
 379   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 380 }
 381
 382 static unsigned
 383 Field_t_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
 384 {
 385   unsigned tie_t = 0;
 386   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 387   return tie_t;
 388 }
 389
 390 static void
 391 Field_t_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
 392 {
 393   uint32 tie_t;
 394   tie_t = (val << 28) >> 28;
 395   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 396 }
 397
 398 static unsigned
 399 Field_t_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
 400 {
 401   unsigned tie_t = 0;
 402   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 403   return tie_t;
 404 }
 405
 406 static void
 407 Field_t_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
 408 {
 409   uint32 tie_t;
 410   tie_t = (val << 28) >> 28;
 411   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 412 }
 413
 414 static unsigned
 415 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
 416 {
 417   unsigned tie_t = 0;
 418   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
 419   return tie_t;
 420 }
 421
 422 static void
 423 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 424 {
 425   uint32 tie_t;
 426   tie_t = (val << 31) >> 31;
 427   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
 428 }
 429
 430 static unsigned
 431 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
 432 {
 433   unsigned tie_t = 0;
 434   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
 435   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 436   return tie_t;
 437 }
 438
 439 static void
 440 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 441 {
 442   uint32 tie_t;
 443   tie_t = (val << 28) >> 28;
 444   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 445   tie_t = (val << 27) >> 31;
 446   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
 447 }
 448
 449 static unsigned
 450 Field_bbi_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
 451 {
 452   unsigned tie_t = 0;
 453   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
 454   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 455   return tie_t;
 456 }
 457
 458 static void
 459 Field_bbi_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
 460 {
 461   uint32 tie_t;
 462   tie_t = (val << 28) >> 28;
 463   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 464   tie_t = (val << 27) >> 31;
 465   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
 466 }
 467
 468 static unsigned
 469 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
 470 {
 471   unsigned tie_t = 0;
 472   tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
 473   return tie_t;
 474 }
 475
 476 static void
 477 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 478 {
 479   uint32 tie_t;
 480   tie_t = (val << 20) >> 20;
 481   insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
 482 }
 483
 484 static unsigned
 485 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
 486 {
 487   unsigned tie_t = 0;
 488   tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
 489   return tie_t;
 490 }
 491
 492 static void
 493 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 494 {
 495   uint32 tie_t;
 496   tie_t = (val << 24) >> 24;
 497   insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
 498 }
 499
 500 static unsigned
 501 Field_imm8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 502 {
 503   unsigned tie_t = 0;
 504   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
 505   return tie_t;
 506 }
 507
 508 static void
 509 Field_imm8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 510 {
 511   uint32 tie_t;
 512   tie_t = (val << 24) >> 24;
 513   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
 514 }
 515
 516 static unsigned
 517 Field_imm8_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
 518 {
 519   unsigned tie_t = 0;
 520   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 521   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 522   return tie_t;
 523 }
 524
 525 static void
 526 Field_imm8_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
 527 {
 528   uint32 tie_t;
 529   tie_t = (val << 28) >> 28;
 530   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 531   tie_t = (val << 24) >> 28;
 532   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 533 }
 534
 535 static unsigned
 536 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
 537 {
 538   unsigned tie_t = 0;
 539   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 540   return tie_t;
 541 }
 542
 543 static void
 544 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 545 {
 546   uint32 tie_t;
 547   tie_t = (val << 28) >> 28;
 548   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 549 }
 550
 551 static unsigned
 552 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
 553 {
 554   unsigned tie_t = 0;
 555   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 556   return tie_t;
 557 }
 558
 559 static void
 560 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 561 {
 562   uint32 tie_t;
 563   tie_t = (val << 28) >> 28;
 564   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 565 }
 566
 567 static unsigned
 568 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
 569 {
 570   unsigned tie_t = 0;
 571   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 572   return tie_t;
 573 }
 574
 575 static void
 576 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 577 {
 578   uint32 tie_t;
 579   tie_t = (val << 28) >> 28;
 580   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 581 }
 582
 583 static unsigned
 584 Field_s_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 585 {
 586   unsigned tie_t = 0;
 587   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 588   return tie_t;
 589 }
 590
 591 static void
 592 Field_s_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 593 {
 594   uint32 tie_t;
 595   tie_t = (val << 28) >> 28;
 596   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 597 }
 598
 599 static unsigned
 600 Field_s_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
 601 {
 602   unsigned tie_t = 0;
 603   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 604   return tie_t;
 605 }
 606
 607 static void
 608 Field_s_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
 609 {
 610   uint32 tie_t;
 611   tie_t = (val << 28) >> 28;
 612   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 613 }
 614
 615 static unsigned
 616 Field_s_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
 617 {
 618   unsigned tie_t = 0;
 619   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 620   return tie_t;
 621 }
 622
 623 static void
 624 Field_s_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
 625 {
 626   uint32 tie_t;
 627   tie_t = (val << 28) >> 28;
 628   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 629 }
 630
 631 static unsigned
 632 Field_s_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
 633 {
 634   unsigned tie_t = 0;
 635   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 636   return tie_t;
 637 }
 638
 639 static void
 640 Field_s_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
 641 {
 642   uint32 tie_t;
 643   tie_t = (val << 28) >> 28;
 644   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 645 }
 646
 647 static unsigned
 648 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
 649 {
 650   unsigned tie_t = 0;
 651   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 652   tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
 653   return tie_t;
 654 }
 655
 656 static void
 657 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 658 {
 659   uint32 tie_t;
 660   tie_t = (val << 24) >> 24;
 661   insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
 662   tie_t = (val << 20) >> 28;
 663   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 664 }
 665
 666 static unsigned
 667 Field_imm12b_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 668 {
 669   unsigned tie_t = 0;
 670   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
 671   tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
 672   return tie_t;
 673 }
 674
 675 static void
 676 Field_imm12b_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 677 {
 678   uint32 tie_t;
 679   tie_t = (val << 24) >> 24;
 680   insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
 681   tie_t = (val << 20) >> 28;
 682   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
 683 }
 684
 685 static unsigned
 686 Field_imm12b_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
 687 {
 688   unsigned tie_t = 0;
 689   tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20);
 690   return tie_t;
 691 }
 692
 693 static void
 694 Field_imm12b_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
 695 {
 696   uint32 tie_t;
 697   tie_t = (val << 20) >> 20;
 698   insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4);
 699 }
 700
 701 static unsigned
 702 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
 703 {
 704   unsigned tie_t = 0;
 705   tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
 706   return tie_t;
 707 }
 708
 709 static void
 710 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 711 {
 712   uint32 tie_t;
 713   tie_t = (val << 16) >> 16;
 714   insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
 715 }
 716
 717 static unsigned
 718 Field_imm16_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 719 {
 720   unsigned tie_t = 0;
 721   tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16);
 722   return tie_t;
 723 }
 724
 725 static void
 726 Field_imm16_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 727 {
 728   uint32 tie_t;
 729   tie_t = (val << 16) >> 16;
 730   insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4);
 731 }
 732
 733 static unsigned
 734 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
 735 {
 736   unsigned tie_t = 0;
 737   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
 738   return tie_t;
 739 }
 740
 741 static void
 742 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 743 {
 744   uint32 tie_t;
 745   tie_t = (val << 30) >> 30;
 746   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
 747 }
 748
 749 static unsigned
 750 Field_m_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 751 {
 752   unsigned tie_t = 0;
 753   tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30);
 754   return tie_t;
 755 }
 756
 757 static void
 758 Field_m_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 759 {
 760   uint32 tie_t;
 761   tie_t = (val << 30) >> 30;
 762   insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
 763 }
 764
 765 static unsigned
 766 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
 767 {
 768   unsigned tie_t = 0;
 769   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
 770   return tie_t;
 771 }
 772
 773 static void
 774 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 775 {
 776   uint32 tie_t;
 777   tie_t = (val << 30) >> 30;
 778   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
 779 }
 780
 781 static unsigned
 782 Field_n_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 783 {
 784   unsigned tie_t = 0;
 785   tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
 786   return tie_t;
 787 }
 788
 789 static void
 790 Field_n_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 791 {
 792   uint32 tie_t;
 793   tie_t = (val << 30) >> 30;
 794   insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
 795 }
 796
 797 static unsigned
 798 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
 799 {
 800   unsigned tie_t = 0;
 801   tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
 802   return tie_t;
 803 }
 804
 805 static void
 806 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 807 {
 808   uint32 tie_t;
 809   tie_t = (val << 14) >> 14;
 810   insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
 811 }
 812
 813 static unsigned
 814 Field_offset_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
 815 {
 816   unsigned tie_t = 0;
 817   tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
 818   return tie_t;
 819 }
 820
 821 static void
 822 Field_offset_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
 823 {
 824   uint32 tie_t;
 825   tie_t = (val << 14) >> 14;
 826   insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
 827 }
 828
 829 static unsigned
 830 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
 831 {
 832   unsigned tie_t = 0;
 833   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 834   return tie_t;
 835 }
 836
 837 static void
 838 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 839 {
 840   uint32 tie_t;
 841   tie_t = (val << 28) >> 28;
 842   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 843 }
 844
 845 static unsigned
 846 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
 847 {
 848   unsigned tie_t = 0;
 849   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 850   return tie_t;
 851 }
 852
 853 static void
 854 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 855 {
 856   uint32 tie_t;
 857   tie_t = (val << 28) >> 28;
 858   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 859 }
 860
 861 static unsigned
 862 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
 863 {
 864   unsigned tie_t = 0;
 865   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
 866   return tie_t;
 867 }
 868
 869 static void
 870 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 871 {
 872   uint32 tie_t;
 873   tie_t = (val << 28) >> 28;
 874   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
 875 }
 876
 877 static unsigned
 878 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
 879 {
 880   unsigned tie_t = 0;
 881   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 882   return tie_t;
 883 }
 884
 885 static void
 886 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 887 {
 888   uint32 tie_t;
 889   tie_t = (val << 28) >> 28;
 890   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 891 }
 892
 893 static unsigned
 894 Field_op1_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 895 {
 896   unsigned tie_t = 0;
 897   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 898   return tie_t;
 899 }
 900
 901 static void
 902 Field_op1_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 903 {
 904   uint32 tie_t;
 905   tie_t = (val << 28) >> 28;
 906   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 907 }
 908
 909 static unsigned
 910 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
 911 {
 912   unsigned tie_t = 0;
 913   tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
 914   return tie_t;
 915 }
 916
 917 static void
 918 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 919 {
 920   uint32 tie_t;
 921   tie_t = (val << 28) >> 28;
 922   insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
 923 }
 924
 925 static unsigned
 926 Field_op2_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
 927 {
 928   unsigned tie_t = 0;
 929   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
 930   return tie_t;
 931 }
 932
 933 static void
 934 Field_op2_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
 935 {
 936   uint32 tie_t;
 937   tie_t = (val << 28) >> 28;
 938   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
 939 }
 940
 941 static unsigned
 942 Field_op2_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
 943 {
 944   unsigned tie_t = 0;
 945   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
 946   return tie_t;
 947 }
 948
 949 static void
 950 Field_op2_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
 951 {
 952   uint32 tie_t;
 953   tie_t = (val << 28) >> 28;
 954   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
 955 }
 956
 957 static unsigned
 958 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
 959 {
 960   unsigned tie_t = 0;
 961   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 962   return tie_t;
 963 }
 964
 965 static void
 966 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
 967 {
 968   uint32 tie_t;
 969   tie_t = (val << 28) >> 28;
 970   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 971 }
 972
 973 static unsigned
 974 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
 975 {
 976   unsigned tie_t = 0;
 977   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 978   return tie_t;
 979 }
 980
 981 static void
 982 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
 983 {
 984   uint32 tie_t;
 985   tie_t = (val << 28) >> 28;
 986   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
 987 }
 988
 989 static unsigned
 990 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
 991 {
 992   unsigned tie_t = 0;
 993   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
 994   return tie_t;
 995 }
 996
 997 static void
 998 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
 999 {
1000   uint32 tie_t;
1001   tie_t = (val << 28) >> 28;
1002   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1003 }
1004
1005 static unsigned
1006 Field_r_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1007 {
1008   unsigned tie_t = 0;
1009   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1010   return tie_t;
1011 }
1012
1013 static void
1014 Field_r_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1015 {
1016   uint32 tie_t;
1017   tie_t = (val << 28) >> 28;
1018   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1019 }
1020
1021 static unsigned
1022 Field_r_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1023 {
1024   unsigned tie_t = 0;
1025   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1026   return tie_t;
1027 }
1028
1029 static void
1030 Field_r_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1031 {
1032   uint32 tie_t;
1033   tie_t = (val << 28) >> 28;
1034   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1035 }
1036
1037 static unsigned
1038 Field_r_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
1039 {
1040   unsigned tie_t = 0;
1041   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1042   return tie_t;
1043 }
1044
1045 static void
1046 Field_r_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
1047 {
1048   uint32 tie_t;
1049   tie_t = (val << 28) >> 28;
1050   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1051 }
1052
1053 static unsigned
1054 Field_r_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
1055 {
1056   unsigned tie_t = 0;
1057   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1058   return tie_t;
1059 }
1060
1061 static void
1062 Field_r_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
1063 {
1064   uint32 tie_t;
1065   tie_t = (val << 28) >> 28;
1066   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1067 }
1068
1069 static unsigned
1070 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
1071 {
1072   unsigned tie_t = 0;
1073   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1074   return tie_t;
1075 }
1076
1077 static void
1078 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1079 {
1080   uint32 tie_t;
1081   tie_t = (val << 31) >> 31;
1082   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1083 }
1084
1085 static unsigned
1086 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
1087 {
1088   unsigned tie_t = 0;
1089   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1090   return tie_t;
1091 }
1092
1093 static void
1094 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1095 {
1096   uint32 tie_t;
1097   tie_t = (val << 31) >> 31;
1098   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1099 }
1100
1101 static unsigned
1102 Field_sae4_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1103 {
1104   unsigned tie_t = 0;
1105   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1106   return tie_t;
1107 }
1108
1109 static void
1110 Field_sae4_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1111 {
1112   uint32 tie_t;
1113   tie_t = (val << 31) >> 31;
1114   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1115 }
1116
1117 static unsigned
1118 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
1119 {
1120   unsigned tie_t = 0;
1121   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1122   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1123   return tie_t;
1124 }
1125
1126 static void
1127 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1128 {
1129   uint32 tie_t;
1130   tie_t = (val << 28) >> 28;
1131   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1132   tie_t = (val << 27) >> 31;
1133   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1134 }
1135
1136 static unsigned
1137 Field_sae_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1138 {
1139   unsigned tie_t = 0;
1140   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1141   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1142   return tie_t;
1143 }
1144
1145 static void
1146 Field_sae_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1147 {
1148   uint32 tie_t;
1149   tie_t = (val << 28) >> 28;
1150   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1151   tie_t = (val << 27) >> 31;
1152   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1153 }
1154
1155 static unsigned
1156 Field_sae_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1157 {
1158   unsigned tie_t = 0;
1159   tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27);
1160   return tie_t;
1161 }
1162
1163 static void
1164 Field_sae_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1165 {
1166   uint32 tie_t;
1167   tie_t = (val << 27) >> 27;
1168   insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12);
1169 }
1170
1171 static unsigned
1172 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
1173 {
1174   unsigned tie_t = 0;
1175   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1176   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1177   return tie_t;
1178 }
1179
1180 static void
1181 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1182 {
1183   uint32 tie_t;
1184   tie_t = (val << 28) >> 28;
1185   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1186   tie_t = (val << 27) >> 31;
1187   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1188 }
1189
1190 static unsigned
1191 Field_sal_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1192 {
1193   unsigned tie_t = 0;
1194   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1195   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1196   return tie_t;
1197 }
1198
1199 static void
1200 Field_sal_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1201 {
1202   uint32 tie_t;
1203   tie_t = (val << 28) >> 28;
1204   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1205   tie_t = (val << 27) >> 31;
1206   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1207 }
1208
1209 static unsigned
1210 Field_sal_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1211 {
1212   unsigned tie_t = 0;
1213   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1214   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1215   return tie_t;
1216 }
1217
1218 static void
1219 Field_sal_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1220 {
1221   uint32 tie_t;
1222   tie_t = (val << 28) >> 28;
1223   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1224   tie_t = (val << 27) >> 31;
1225   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1226 }
1227
1228 static unsigned
1229 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
1230 {
1231   unsigned tie_t = 0;
1232   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1233   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1234   return tie_t;
1235 }
1236
1237 static void
1238 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1239 {
1240   uint32 tie_t;
1241   tie_t = (val << 28) >> 28;
1242   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1243   tie_t = (val << 27) >> 31;
1244   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1245 }
1246
1247 static unsigned
1248 Field_sargt_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1249 {
1250   unsigned tie_t = 0;
1251   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1252   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1253   return tie_t;
1254 }
1255
1256 static void
1257 Field_sargt_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1258 {
1259   uint32 tie_t;
1260   tie_t = (val << 28) >> 28;
1261   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1262   tie_t = (val << 27) >> 31;
1263   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1264 }
1265
1266 static unsigned
1267 Field_sargt_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1268 {
1269   unsigned tie_t = 0;
1270   tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
1271   return tie_t;
1272 }
1273
1274 static void
1275 Field_sargt_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1276 {
1277   uint32 tie_t;
1278   tie_t = (val << 27) >> 27;
1279   insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
1280 }
1281
1282 static unsigned
1283 Field_sargt_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
1284 {
1285   unsigned tie_t = 0;
1286   tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
1287   return tie_t;
1288 }
1289
1290 static void
1291 Field_sargt_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
1292 {
1293   uint32 tie_t;
1294   tie_t = (val << 27) >> 27;
1295   insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
1296 }
1297
1298 static unsigned
1299 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
1300 {
1301   unsigned tie_t = 0;
1302   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1303   return tie_t;
1304 }
1305
1306 static void
1307 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1308 {
1309   uint32 tie_t;
1310   tie_t = (val << 31) >> 31;
1311   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1312 }
1313
1314 static unsigned
1315 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
1316 {
1317   unsigned tie_t = 0;
1318   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1319   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1320   return tie_t;
1321 }
1322
1323 static void
1324 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1325 {
1326   uint32 tie_t;
1327   tie_t = (val << 28) >> 28;
1328   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1329   tie_t = (val << 27) >> 31;
1330   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1331 }
1332
1333 static unsigned
1334 Field_sas_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1335 {
1336   unsigned tie_t = 0;
1337   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
1338   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1339   return tie_t;
1340 }
1341
1342 static void
1343 Field_sas_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1344 {
1345   uint32 tie_t;
1346   tie_t = (val << 28) >> 28;
1347   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1348   tie_t = (val << 27) >> 31;
1349   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
1350 }
1351
1352 static unsigned
1353 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
1354 {
1355   unsigned tie_t = 0;
1356   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1357   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1358   return tie_t;
1359 }
1360
1361 static void
1362 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1363 {
1364   uint32 tie_t;
1365   tie_t = (val << 28) >> 28;
1366   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1367   tie_t = (val << 24) >> 28;
1368   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1369 }
1370
1371 static unsigned
1372 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
1373 {
1374   unsigned tie_t = 0;
1375   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1376   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1377   return tie_t;
1378 }
1379
1380 static void
1381 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1382 {
1383   uint32 tie_t;
1384   tie_t = (val << 28) >> 28;
1385   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1386   tie_t = (val << 24) >> 28;
1387   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1388 }
1389
1390 static unsigned
1391 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
1392 {
1393   unsigned tie_t = 0;
1394   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1395   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1396   return tie_t;
1397 }
1398
1399 static void
1400 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1401 {
1402   uint32 tie_t;
1403   tie_t = (val << 28) >> 28;
1404   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1405   tie_t = (val << 24) >> 28;
1406   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1407 }
1408
1409 static unsigned
1410 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
1411 {
1412   unsigned tie_t = 0;
1413   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1414   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1415   return tie_t;
1416 }
1417
1418 static void
1419 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1420 {
1421   uint32 tie_t;
1422   tie_t = (val << 28) >> 28;
1423   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1424   tie_t = (val << 24) >> 28;
1425   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1426 }
1427
1428 static unsigned
1429 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
1430 {
1431   unsigned tie_t = 0;
1432   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1433   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1434   return tie_t;
1435 }
1436
1437 static void
1438 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1439 {
1440   uint32 tie_t;
1441   tie_t = (val << 28) >> 28;
1442   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1443   tie_t = (val << 24) >> 28;
1444   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1445 }
1446
1447 static unsigned
1448 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
1449 {
1450   unsigned tie_t = 0;
1451   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1452   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1453   return tie_t;
1454 }
1455
1456 static void
1457 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1458 {
1459   uint32 tie_t;
1460   tie_t = (val << 28) >> 28;
1461   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1462   tie_t = (val << 24) >> 28;
1463   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1464 }
1465
1466 static unsigned
1467 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
1468 {
1469   unsigned tie_t = 0;
1470   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
1471   return tie_t;
1472 }
1473
1474 static void
1475 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1476 {
1477   uint32 tie_t;
1478   tie_t = (val << 29) >> 29;
1479   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
1480 }
1481
1482 static unsigned
1483 Field_thi3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1484 {
1485   unsigned tie_t = 0;
1486   tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
1487   return tie_t;
1488 }
1489
1490 static void
1491 Field_thi3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1492 {
1493   uint32 tie_t;
1494   tie_t = (val << 29) >> 29;
1495   insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
1496 }
1497
1498 static unsigned
1499 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
1500 {
1501   unsigned tie_t = 0;
1502   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1503   return tie_t;
1504 }
1505
1506 static void
1507 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1508 {
1509   uint32 tie_t;
1510   tie_t = (val << 28) >> 28;
1511   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1512 }
1513
1514 static unsigned
1515 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
1516 {
1517   unsigned tie_t = 0;
1518   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1519   return tie_t;
1520 }
1521
1522 static void
1523 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1524 {
1525   uint32 tie_t;
1526   tie_t = (val << 28) >> 28;
1527   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1528 }
1529
1530 static unsigned
1531 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
1532 {
1533   unsigned tie_t = 0;
1534   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1535   return tie_t;
1536 }
1537
1538 static void
1539 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1540 {
1541   uint32 tie_t;
1542   tie_t = (val << 28) >> 28;
1543   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1544 }
1545
1546 static unsigned
1547 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
1548 {
1549   unsigned tie_t = 0;
1550   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
1551   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1552   return tie_t;
1553 }
1554
1555 static void
1556 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1557 {
1558   uint32 tie_t;
1559   tie_t = (val << 30) >> 30;
1560   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1561   tie_t = (val << 28) >> 30;
1562   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1563 }
1564
1565 static unsigned
1566 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
1567 {
1568   unsigned tie_t = 0;
1569   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1570   return tie_t;
1571 }
1572
1573 static void
1574 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1575 {
1576   uint32 tie_t;
1577   tie_t = (val << 31) >> 31;
1578   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1579 }
1580
1581 static unsigned
1582 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
1583 {
1584   unsigned tie_t = 0;
1585   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1586   return tie_t;
1587 }
1588
1589 static void
1590 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1591 {
1592   uint32 tie_t;
1593   tie_t = (val << 31) >> 31;
1594   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1595 }
1596
1597 static unsigned
1598 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1599 {
1600   unsigned tie_t = 0;
1601   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1602   return tie_t;
1603 }
1604
1605 static void
1606 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1607 {
1608   uint32 tie_t;
1609   tie_t = (val << 28) >> 28;
1610   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1611 }
1612
1613 static unsigned
1614 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1615 {
1616   unsigned tie_t = 0;
1617   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1618   return tie_t;
1619 }
1620
1621 static void
1622 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1623 {
1624   uint32 tie_t;
1625   tie_t = (val << 28) >> 28;
1626   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1627 }
1628
1629 static unsigned
1630 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1631 {
1632   unsigned tie_t = 0;
1633   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1634   return tie_t;
1635 }
1636
1637 static void
1638 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1639 {
1640   uint32 tie_t;
1641   tie_t = (val << 30) >> 30;
1642   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1643 }
1644
1645 static unsigned
1646 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1647 {
1648   unsigned tie_t = 0;
1649   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1650   return tie_t;
1651 }
1652
1653 static void
1654 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1655 {
1656   uint32 tie_t;
1657   tie_t = (val << 30) >> 30;
1658   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1659 }
1660
1661 static unsigned
1662 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1663 {
1664   unsigned tie_t = 0;
1665   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1666   return tie_t;
1667 }
1668
1669 static void
1670 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1671 {
1672   uint32 tie_t;
1673   tie_t = (val << 28) >> 28;
1674   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1675 }
1676
1677 static unsigned
1678 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1679 {
1680   unsigned tie_t = 0;
1681   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1682   return tie_t;
1683 }
1684
1685 static void
1686 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1687 {
1688   uint32 tie_t;
1689   tie_t = (val << 28) >> 28;
1690   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1691 }
1692
1693 static unsigned
1694 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1695 {
1696   unsigned tie_t = 0;
1697   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1698   return tie_t;
1699 }
1700
1701 static void
1702 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1703 {
1704   uint32 tie_t;
1705   tie_t = (val << 29) >> 29;
1706   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1707 }
1708
1709 static unsigned
1710 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1711 {
1712   unsigned tie_t = 0;
1713   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1714   return tie_t;
1715 }
1716
1717 static void
1718 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1719 {
1720   uint32 tie_t;
1721   tie_t = (val << 29) >> 29;
1722   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1723 }
1724
1725 static unsigned
1726 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1727 {
1728   unsigned tie_t = 0;
1729   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1730   return tie_t;
1731 }
1732
1733 static void
1734 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1735 {
1736   uint32 tie_t;
1737   tie_t = (val << 31) >> 31;
1738   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1739 }
1740
1741 static unsigned
1742 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
1743 {
1744   unsigned tie_t = 0;
1745   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1746   return tie_t;
1747 }
1748
1749 static void
1750 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1751 {
1752   uint32 tie_t;
1753   tie_t = (val << 31) >> 31;
1754   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1755 }
1756
1757 static unsigned
1758 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1759 {
1760   unsigned tie_t = 0;
1761   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1762   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1763   return tie_t;
1764 }
1765
1766 static void
1767 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1768 {
1769   uint32 tie_t;
1770   tie_t = (val << 28) >> 28;
1771   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1772   tie_t = (val << 26) >> 30;
1773   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1774 }
1775
1776 static unsigned
1777 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1778 {
1779   unsigned tie_t = 0;
1780   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1781   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1782   return tie_t;
1783 }
1784
1785 static void
1786 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1787 {
1788   uint32 tie_t;
1789   tie_t = (val << 28) >> 28;
1790   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1791   tie_t = (val << 26) >> 30;
1792   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1793 }
1794
1795 static unsigned
1796 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1797 {
1798   unsigned tie_t = 0;
1799   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1800   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1801   return tie_t;
1802 }
1803
1804 static void
1805 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1806 {
1807   uint32 tie_t;
1808   tie_t = (val << 28) >> 28;
1809   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1810   tie_t = (val << 25) >> 29;
1811   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1812 }
1813
1814 static unsigned
1815 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1816 {
1817   unsigned tie_t = 0;
1818   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1819   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1820   return tie_t;
1821 }
1822
1823 static void
1824 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1825 {
1826   uint32 tie_t;
1827   tie_t = (val << 28) >> 28;
1828   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1829   tie_t = (val << 25) >> 29;
1830   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1831 }
1832
1833 static unsigned
1834 Field_imm7_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
1835 {
1836   unsigned tie_t = 0;
1837   tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1838   return tie_t;
1839 }
1840
1841 static void
1842 Field_imm7_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
1843 {
1844   uint32 tie_t;
1845   tie_t = (val << 25) >> 25;
1846   insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1847 }
1848
1849 static unsigned
1850 Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
1851 {
1852   unsigned tie_t = 0;
1853   tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
1854   return tie_t;
1855 }
1856
1857 static void
1858 Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1859 {
1860   uint32 tie_t;
1861   tie_t = (val << 31) >> 31;
1862   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
1863 }
1864
1865 static unsigned
1866 Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
1867 {
1868   unsigned tie_t = 0;
1869   tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1870   return tie_t;
1871 }
1872
1873 static void
1874 Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1875 {
1876   uint32 tie_t;
1877   tie_t = (val << 31) >> 31;
1878   insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1879 }
1880
1881 static unsigned
1882 Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
1883 {
1884   unsigned tie_t = 0;
1885   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1886   return tie_t;
1887 }
1888
1889 static void
1890 Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1891 {
1892   uint32 tie_t;
1893   tie_t = (val << 30) >> 30;
1894   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1895 }
1896
1897 static unsigned
1898 Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
1899 {
1900   unsigned tie_t = 0;
1901   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1902   return tie_t;
1903 }
1904
1905 static void
1906 Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1907 {
1908   uint32 tie_t;
1909   tie_t = (val << 31) >> 31;
1910   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1911 }
1912
1913 static unsigned
1914 Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
1915 {
1916   unsigned tie_t = 0;
1917   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1918   return tie_t;
1919 }
1920
1921 static void
1922 Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1923 {
1924   uint32 tie_t;
1925   tie_t = (val << 31) >> 31;
1926   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1927 }
1928
1929 static unsigned
1930 Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
1931 {
1932   unsigned tie_t = 0;
1933   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1934   return tie_t;
1935 }
1936
1937 static void
1938 Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1939 {
1940   uint32 tie_t;
1941   tie_t = (val << 30) >> 30;
1942   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1943 }
1944
1945 static unsigned
1946 Field_w_Slot_inst_get (const xtensa_insnbuf insn)
1947 {
1948   unsigned tie_t = 0;
1949   tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
1950   return tie_t;
1951 }
1952
1953 static void
1954 Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1955 {
1956   uint32 tie_t;
1957   tie_t = (val << 30) >> 30;
1958   insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
1959 }
1960
1961 static unsigned
1962 Field_y_Slot_inst_get (const xtensa_insnbuf insn)
1963 {
1964   unsigned tie_t = 0;
1965   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1966   return tie_t;
1967 }
1968
1969 static void
1970 Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1971 {
1972   uint32 tie_t;
1973   tie_t = (val << 31) >> 31;
1974   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1975 }
1976
1977 static unsigned
1978 Field_x_Slot_inst_get (const xtensa_insnbuf insn)
1979 {
1980   unsigned tie_t = 0;
1981   tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1982   return tie_t;
1983 }
1984
1985 static void
1986 Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1987 {
1988   uint32 tie_t;
1989   tie_t = (val << 31) >> 31;
1990   insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1991 }
1992
1993 static unsigned
1994 Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
1995 {
1996   unsigned tie_t = 0;
1997   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
1998   return tie_t;
1999 }
2000
2001 static void
2002 Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2003 {
2004   uint32 tie_t;
2005   tie_t = (val << 29) >> 29;
2006   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
2007 }
2008
2009 static unsigned
2010 Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
2011 {
2012   unsigned tie_t = 0;
2013   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
2014   return tie_t;
2015 }
2016
2017 static void
2018 Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2019 {
2020   uint32 tie_t;
2021   tie_t = (val << 29) >> 29;
2022   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
2023 }
2024
2025 static unsigned
2026 Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
2027 {
2028   unsigned tie_t = 0;
2029   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
2030   return tie_t;
2031 }
2032
2033 static void
2034 Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2035 {
2036   uint32 tie_t;
2037   tie_t = (val << 29) >> 29;
2038   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
2039 }
2040
2041 static unsigned
2042 Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
2043 {
2044   unsigned tie_t = 0;
2045   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
2046   return tie_t;
2047 }
2048
2049 static void
2050 Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2051 {
2052   uint32 tie_t;
2053   tie_t = (val << 29) >> 29;
2054   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
2055 }
2056
2057 static unsigned
2058 Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
2059 {
2060   unsigned tie_t = 0;
2061   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
2062   return tie_t;
2063 }
2064
2065 static void
2066 Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2067 {
2068   uint32 tie_t;
2069   tie_t = (val << 29) >> 29;
2070   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
2071 }
2072
2073 static unsigned
2074 Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
2075 {
2076   unsigned tie_t = 0;
2077   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
2078   return tie_t;
2079 }
2080
2081 static void
2082 Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2083 {
2084   uint32 tie_t;
2085   tie_t = (val << 29) >> 29;
2086   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
2087 }
2088
2089 static unsigned
2090 Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
2091 {
2092   unsigned tie_t = 0;
2093   tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2094   return tie_t;
2095 }
2096
2097 static void
2098 Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2099 {
2100   uint32 tie_t;
2101   tie_t = (val << 29) >> 29;
2102   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2103 }
2104
2105 static unsigned
2106 Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
2107 {
2108   unsigned tie_t = 0;
2109   tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2110   return tie_t;
2111 }
2112
2113 static void
2114 Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2115 {
2116   uint32 tie_t;
2117   tie_t = (val << 29) >> 29;
2118   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2119 }
2120
2121 static unsigned
2122 Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
2123 {
2124   unsigned tie_t = 0;
2125   tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2126   return tie_t;
2127 }
2128
2129 static void
2130 Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2131 {
2132   uint32 tie_t;
2133   tie_t = (val << 29) >> 29;
2134   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2135 }
2136
2137 static unsigned
2138 Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
2139 {
2140   unsigned tie_t = 0;
2141   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
2142   return tie_t;
2143 }
2144
2145 static void
2146 Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2147 {
2148   uint32 tie_t;
2149   tie_t = (val << 30) >> 30;
2150   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
2151 }
2152
2153 static unsigned
2154 Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
2155 {
2156   unsigned tie_t = 0;
2157   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
2158   return tie_t;
2159 }
2160
2161 static void
2162 Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2163 {
2164   uint32 tie_t;
2165   tie_t = (val << 30) >> 30;
2166   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
2167 }
2168
2169 static unsigned
2170 Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
2171 {
2172   unsigned tie_t = 0;
2173   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
2174   return tie_t;
2175 }
2176
2177 static void
2178 Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2179 {
2180   uint32 tie_t;
2181   tie_t = (val << 30) >> 30;
2182   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
2183 }
2184
2185 static unsigned
2186 Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
2187 {
2188   unsigned tie_t = 0;
2189   tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
2190   return tie_t;
2191 }
2192
2193 static void
2194 Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2195 {
2196   uint32 tie_t;
2197   tie_t = (val << 30) >> 30;
2198   insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2199 }
2200
2201 static unsigned
2202 Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
2203 {
2204   unsigned tie_t = 0;
2205   tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
2206   return tie_t;
2207 }
2208
2209 static void
2210 Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2211 {
2212   uint32 tie_t;
2213   tie_t = (val << 30) >> 30;
2214   insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2215 }
2216
2217 static unsigned
2218 Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
2219 {
2220   unsigned tie_t = 0;
2221   tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
2222   return tie_t;
2223 }
2224
2225 static void
2226 Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2227 {
2228   uint32 tie_t;
2229   tie_t = (val << 30) >> 30;
2230   insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2231 }
2232
2233 static unsigned
2234 Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
2235 {
2236   unsigned tie_t = 0;
2237   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2238   return tie_t;
2239 }
2240
2241 static void
2242 Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2243 {
2244   uint32 tie_t;
2245   tie_t = (val << 30) >> 30;
2246   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2247 }
2248
2249 static unsigned
2250 Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
2251 {
2252   unsigned tie_t = 0;
2253   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2254   return tie_t;
2255 }
2256
2257 static void
2258 Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2259 {
2260   uint32 tie_t;
2261   tie_t = (val << 30) >> 30;
2262   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2263 }
2264
2265 static unsigned
2266 Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
2267 {
2268   unsigned tie_t = 0;
2269   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2270   return tie_t;
2271 }
2272
2273 static void
2274 Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2275 {
2276   uint32 tie_t;
2277   tie_t = (val << 30) >> 30;
2278   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2279 }
2280
2281 static unsigned
2282 Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
2283 {
2284   unsigned tie_t = 0;
2285   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2286   return tie_t;
2287 }
2288
2289 static void
2290 Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2291 {
2292   uint32 tie_t;
2293   tie_t = (val << 31) >> 31;
2294   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2295 }
2296
2297 static unsigned
2298 Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
2299 {
2300   unsigned tie_t = 0;
2301   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2302   return tie_t;
2303 }
2304
2305 static void
2306 Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2307 {
2308   uint32 tie_t;
2309   tie_t = (val << 31) >> 31;
2310   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2311 }
2312
2313 static unsigned
2314 Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
2315 {
2316   unsigned tie_t = 0;
2317   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2318   return tie_t;
2319 }
2320
2321 static void
2322 Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2323 {
2324   uint32 tie_t;
2325   tie_t = (val << 31) >> 31;
2326   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2327 }
2328
2329 static unsigned
2330 Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
2331 {
2332   unsigned tie_t = 0;
2333   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
2334   return tie_t;
2335 }
2336
2337 static void
2338 Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2339 {
2340   uint32 tie_t;
2341   tie_t = (val << 31) >> 31;
2342   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
2343 }
2344
2345 static unsigned
2346 Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
2347 {
2348   unsigned tie_t = 0;
2349   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
2350   return tie_t;
2351 }
2352
2353 static void
2354 Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2355 {
2356   uint32 tie_t;
2357   tie_t = (val << 31) >> 31;
2358   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
2359 }
2360
2361 static unsigned
2362 Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
2363 {
2364   unsigned tie_t = 0;
2365   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
2366   return tie_t;
2367 }
2368
2369 static void
2370 Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2371 {
2372   uint32 tie_t;
2373   tie_t = (val << 31) >> 31;
2374   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
2375 }
2376
2377 static unsigned
2378 Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
2379 {
2380   unsigned tie_t = 0;
2381   tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
2382   return tie_t;
2383 }
2384
2385 static void
2386 Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2387 {
2388   uint32 tie_t;
2389   tie_t = (val << 31) >> 31;
2390   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2391 }
2392
2393 static unsigned
2394 Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
2395 {
2396   unsigned tie_t = 0;
2397   tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
2398   return tie_t;
2399 }
2400
2401 static void
2402 Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2403 {
2404   uint32 tie_t;
2405   tie_t = (val << 31) >> 31;
2406   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2407 }
2408
2409 static unsigned
2410 Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
2411 {
2412   unsigned tie_t = 0;
2413   tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
2414   return tie_t;
2415 }
2416
2417 static void
2418 Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2419 {
2420   uint32 tie_t;
2421   tie_t = (val << 31) >> 31;
2422   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2423 }
2424
2425 static unsigned
2426 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
2427 {
2428   unsigned tie_t = 0;
2429   tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
2430   return tie_t;
2431 }
2432
2433 static void
2434 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2435 {
2436   uint32 tie_t;
2437   tie_t = (val << 17) >> 17;
2438   insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
2439 }
2440
2441 static unsigned
2442 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
2443 {
2444   unsigned tie_t = 0;
2445   tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
2446   return tie_t;
2447 }
2448
2449 static void
2450 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2451 {
2452   uint32 tie_t;
2453   tie_t = (val << 14) >> 14;
2454   insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
2455 }
2456
2457 static unsigned
2458 Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
2459 {
2460   unsigned tie_t = 0;
2461   tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14);
2462   return tie_t;
2463 }
2464
2465 static void
2466 Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
2467 {
2468   uint32 tie_t;
2469   tie_t = (val << 14) >> 14;
2470   insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8);
2471 }
2472
2473 static unsigned
2474 Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2475 {
2476   unsigned tie_t = 0;
2477   tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
2478   return tie_t;
2479 }
2480
2481 static void
2482 Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2483 {
2484   uint32 tie_t;
2485   tie_t = (val << 28) >> 28;
2486   insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
2487 }
2488
2489 static unsigned
2490 Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2491 {
2492   unsigned tie_t = 0;
2493   tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2494   return tie_t;
2495 }
2496
2497 static void
2498 Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2499 {
2500   uint32 tie_t;
2501   tie_t = (val << 29) >> 29;
2502   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2503 }
2504
2505 static unsigned
2506 Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2507 {
2508   unsigned tie_t = 0;
2509   tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2510   return tie_t;
2511 }
2512
2513 static void
2514 Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2515 {
2516   uint32 tie_t;
2517   tie_t = (val << 29) >> 29;
2518   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2519 }
2520
2521 static unsigned
2522 Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2523 {
2524   unsigned tie_t = 0;
2525   tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
2526   return tie_t;
2527 }
2528
2529 static void
2530 Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2531 {
2532   uint32 tie_t;
2533   tie_t = (val << 29) >> 29;
2534   insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
2535 }
2536
2537 static unsigned
2538 Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2539 {
2540   unsigned tie_t = 0;
2541   tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
2542   return tie_t;
2543 }
2544
2545 static void
2546 Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2547 {
2548   uint32 tie_t;
2549   tie_t = (val << 29) >> 29;
2550   insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
2551 }
2552
2553 static unsigned
2554 Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2555 {
2556   unsigned tie_t = 0;
2557   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
2558   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
2559   return tie_t;
2560 }
2561
2562 static void
2563 Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2564 {
2565   uint32 tie_t;
2566   tie_t = (val << 28) >> 28;
2567   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
2568   tie_t = (val << 24) >> 28;
2569   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
2570 }
2571
2572 static unsigned
2573 Field_op0_s4_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2574 {
2575   unsigned tie_t = 0;
2576   tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
2577   return tie_t;
2578 }
2579
2580 static void
2581 Field_op0_s4_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2582 {
2583   uint32 tie_t;
2584   tie_t = (val << 30) >> 30;
2585   insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
2586 }
2587
2588 static unsigned
2589 Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2590 {
2591   unsigned tie_t = 0;
2592   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2593   return tie_t;
2594 }
2595
2596 static void
2597 Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2598 {
2599   uint32 tie_t;
2600   tie_t = (val << 28) >> 28;
2601   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2602 }
2603
2604 static unsigned
2605 Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2606 {
2607   unsigned tie_t = 0;
2608   tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31);
2609   return tie_t;
2610 }
2611
2612 static void
2613 Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2614 {
2615   uint32 tie_t;
2616   tie_t = (val << 31) >> 31;
2617   insn[0] = (insn[0] & ~0x20000) | (tie_t << 17);
2618 }
2619
2620 static unsigned
2621 Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2622 {
2623   unsigned tie_t = 0;
2624   tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
2625   return tie_t;
2626 }
2627
2628 static void
2629 Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2630 {
2631   uint32 tie_t;
2632   tie_t = (val << 30) >> 30;
2633   insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
2634 }
2635
2636 static unsigned
2637 Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2638 {
2639   unsigned tie_t = 0;
2640   tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27);
2641   return tie_t;
2642 }
2643
2644 static void
2645 Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2646 {
2647   uint32 tie_t;
2648   tie_t = (val << 27) >> 27;
2649   insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13);
2650 }
2651
2652 static unsigned
2653 Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2654 {
2655   unsigned tie_t = 0;
2656   tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2657   return tie_t;
2658 }
2659
2660 static void
2661 Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2662 {
2663   uint32 tie_t;
2664   tie_t = (val << 26) >> 26;
2665   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2666 }
2667
2668 static unsigned
2669 Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2670 {
2671   unsigned tie_t = 0;
2672   tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2673   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2674   return tie_t;
2675 }
2676
2677 static void
2678 Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2679 {
2680   uint32 tie_t;
2681   tie_t = (val << 29) >> 29;
2682   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2683   tie_t = (val << 23) >> 26;
2684   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2685 }
2686
2687 static unsigned
2688 Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2689 {
2690   unsigned tie_t = 0;
2691   tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2692   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2693   return tie_t;
2694 }
2695
2696 static void
2697 Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2698 {
2699   uint32 tie_t;
2700   tie_t = (val << 29) >> 29;
2701   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2702   tie_t = (val << 23) >> 26;
2703   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2704 }
2705
2706 static unsigned
2707 Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2708 {
2709   unsigned tie_t = 0;
2710   tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2711   tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
2712   return tie_t;
2713 }
2714
2715 static void
2716 Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2717 {
2718   uint32 tie_t;
2719   tie_t = (val << 30) >> 30;
2720   insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
2721   tie_t = (val << 24) >> 26;
2722   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2723 }
2724
2725 static unsigned
2726 Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2727 {
2728   unsigned tie_t = 0;
2729   tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2730   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2731   return tie_t;
2732 }
2733
2734 static void
2735 Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2736 {
2737   uint32 tie_t;
2738   tie_t = (val << 31) >> 31;
2739   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2740   tie_t = (val << 25) >> 26;
2741   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2742 }
2743
2744 static unsigned
2745 Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2746 {
2747   unsigned tie_t = 0;
2748   tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2749   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
2750   return tie_t;
2751 }
2752
2753 static void
2754 Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2755 {
2756   uint32 tie_t;
2757   tie_t = (val << 30) >> 30;
2758   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
2759   tie_t = (val << 24) >> 26;
2760   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2761 }
2762
2763 static unsigned
2764 Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2765 {
2766   unsigned tie_t = 0;
2767   tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2768   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
2769   return tie_t;
2770 }
2771
2772 static void
2773 Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2774 {
2775   uint32 tie_t;
2776   tie_t = (val << 30) >> 30;
2777   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
2778   tie_t = (val << 24) >> 26;
2779   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2780 }
2781
2782 static unsigned
2783 Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2784 {
2785   unsigned tie_t = 0;
2786   tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2787   tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31);
2788   return tie_t;
2789 }
2790
2791 static void
2792 Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2793 {
2794   uint32 tie_t;
2795   tie_t = (val << 31) >> 31;
2796   insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
2797   tie_t = (val << 25) >> 26;
2798   insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2799 }
2800
2801 static unsigned
2802 Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2803 {
2804   unsigned tie_t = 0;
2805   tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29);
2806   return tie_t;
2807 }
2808
2809 static void
2810 Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2811 {
2812   uint32 tie_t;
2813   tie_t = (val << 29) >> 29;
2814   insn[0] = (insn[0] & ~0x38000) | (tie_t << 15);
2815 }
2816
2817 static unsigned
2818 Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2819 {
2820   unsigned tie_t = 0;
2821   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2822   return tie_t;
2823 }
2824
2825 static void
2826 Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2827 {
2828   uint32 tie_t;
2829   tie_t = (val << 31) >> 31;
2830   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2831 }
2832
2833 static unsigned
2834 Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2835 {
2836   unsigned tie_t = 0;
2837   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2838   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2839   return tie_t;
2840 }
2841
2842 static void
2843 Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2844 {
2845   uint32 tie_t;
2846   tie_t = (val << 28) >> 28;
2847   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2848   tie_t = (val << 27) >> 31;
2849   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2850 }
2851
2852 static unsigned
2853 Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2854 {
2855   unsigned tie_t = 0;
2856   tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
2857   return tie_t;
2858 }
2859
2860 static void
2861 Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2862 {
2863   uint32 tie_t;
2864   tie_t = (val << 30) >> 30;
2865   insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2866 }
2867
2868 static unsigned
2869 Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2870 {
2871   unsigned tie_t = 0;
2872   tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
2873   tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
2874   return tie_t;
2875 }
2876
2877 static void
2878 Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2879 {
2880   uint32 tie_t;
2881   tie_t = (val << 26) >> 26;
2882   insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
2883   tie_t = (val << 21) >> 27;
2884   insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
2885 }
2886
2887 static unsigned
2888 Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2889 {
2890   unsigned tie_t = 0;
2891   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
2892   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2893   return tie_t;
2894 }
2895
2896 static void
2897 Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2898 {
2899   uint32 tie_t;
2900   tie_t = (val << 28) >> 28;
2901   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2902   tie_t = (val << 27) >> 31;
2903   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
2904 }
2905
2906 static unsigned
2907 Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2908 {
2909   unsigned tie_t = 0;
2910   tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
2911   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
2912   return tie_t;
2913 }
2914
2915 static void
2916 Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2917 {
2918   uint32 tie_t;
2919   tie_t = (val << 31) >> 31;
2920   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
2921   tie_t = (val << 29) >> 30;
2922   insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2923 }
2924
2925 static unsigned
2926 Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2927 {
2928   unsigned tie_t = 0;
2929   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2930   tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
2931   return tie_t;
2932 }
2933
2934 static void
2935 Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2936 {
2937   uint32 tie_t;
2938   tie_t = (val << 27) >> 27;
2939   insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
2940   tie_t = (val << 26) >> 31;
2941   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2942 }
2943
2944 static unsigned
2945 Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2946 {
2947   unsigned tie_t = 0;
2948   tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
2949   return tie_t;
2950 }
2951
2952 static void
2953 Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2954 {
2955   uint32 tie_t;
2956   tie_t = (val << 29) >> 29;
2957   insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
2958 }
2959
2960 static unsigned
2961 Field_op0_s5_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2962 {
2963   unsigned tie_t = 0;
2964   tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2965   return tie_t;
2966 }
2967
2968 static void
2969 Field_op0_s5_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2970 {
2971   uint32 tie_t;
2972   tie_t = (val << 29) >> 29;
2973   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2974 }
2975
2976 static unsigned
2977 Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2978 {
2979   unsigned tie_t = 0;
2980   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
2981   return tie_t;
2982 }
2983
2984 static void
2985 Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2986 {
2987   uint32 tie_t;
2988   tie_t = (val << 31) >> 31;
2989   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
2990 }
2991
2992 static unsigned
2993 Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2994 {
2995   unsigned tie_t = 0;
2996   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
2997   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2998   return tie_t;
2999 }
3000
3001 static void
3002 Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3003 {
3004   uint32 tie_t;
3005   tie_t = (val << 31) >> 31;
3006   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3007   tie_t = (val << 30) >> 31;
3008   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3009 }
3010
3011 static unsigned
3012 Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3013 {
3014   unsigned tie_t = 0;
3015   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3016   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3017   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
3018   return tie_t;
3019 }
3020
3021 static void
3022 Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3023 {
3024   uint32 tie_t;
3025   tie_t = (val << 31) >> 31;
3026   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
3027   tie_t = (val << 30) >> 31;
3028   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3029   tie_t = (val << 29) >> 31;
3030   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3031 }
3032
3033 static unsigned
3034 Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3035 {
3036   unsigned tie_t = 0;
3037   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3038   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3039   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
3040   return tie_t;
3041 }
3042
3043 static void
3044 Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3045 {
3046   uint32 tie_t;
3047   tie_t = (val << 31) >> 31;
3048   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
3049   tie_t = (val << 30) >> 31;
3050   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3051   tie_t = (val << 29) >> 31;
3052   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3053 }
3054
3055 static unsigned
3056 Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3057 {
3058   unsigned tie_t = 0;
3059   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3060   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
3061   return tie_t;
3062 }
3063
3064 static void
3065 Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3066 {
3067   uint32 tie_t;
3068   tie_t = (val << 29) >> 29;
3069   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
3070   tie_t = (val << 28) >> 31;
3071   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3072 }
3073
3074 static unsigned
3075 Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3076 {
3077   unsigned tie_t = 0;
3078   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3079   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
3080   return tie_t;
3081 }
3082
3083 static void
3084 Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3085 {
3086   uint32 tie_t;
3087   tie_t = (val << 29) >> 29;
3088   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
3089   tie_t = (val << 28) >> 31;
3090   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3091 }
3092
3093 static unsigned
3094 Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3095 {
3096   unsigned tie_t = 0;
3097   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3098   tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
3099   return tie_t;
3100 }
3101
3102 static void
3103 Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3104 {
3105   uint32 tie_t;
3106   tie_t = (val << 30) >> 30;
3107   insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
3108   tie_t = (val << 29) >> 31;
3109   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3110 }
3111
3112 static unsigned
3113 Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3114 {
3115   unsigned tie_t = 0;
3116   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3117   tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
3118   return tie_t;
3119 }
3120
3121 static void
3122 Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3123 {
3124   uint32 tie_t;
3125   tie_t = (val << 31) >> 31;
3126   insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
3127   tie_t = (val << 30) >> 31;
3128   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3129 }
3130
3131 static unsigned
3132 Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3133 {
3134   unsigned tie_t = 0;
3135   tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
3136   return tie_t;
3137 }
3138
3139 static void
3140 Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3141 {
3142   uint32 tie_t;
3143   tie_t = (val << 30) >> 30;
3144   insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
3145 }
3146
3147 static unsigned
3148 Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3149 {
3150   unsigned tie_t = 0;
3151   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3152   return tie_t;
3153 }
3154
3155 static void
3156 Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3157 {
3158   uint32 tie_t;
3159   tie_t = (val << 31) >> 31;
3160   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3161 }
3162
3163 static unsigned
3164 Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3165 {
3166   unsigned tie_t = 0;
3167   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
3168   tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
3169   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3170   return tie_t;
3171 }
3172
3173 static void
3174 Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3175 {
3176   uint32 tie_t;
3177   tie_t = (val << 28) >> 28;
3178   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3179   tie_t = (val << 26) >> 30;
3180   insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
3181   tie_t = (val << 22) >> 28;
3182   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
3183 }
3184
3185 static unsigned
3186 Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3187 {
3188   unsigned tie_t = 0;
3189   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3190   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
3191   return tie_t;
3192 }
3193
3194 static void
3195 Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3196 {
3197   uint32 tie_t;
3198   tie_t = (val << 31) >> 31;
3199   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
3200   tie_t = (val << 30) >> 31;
3201   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3202 }
3203
3204 static unsigned
3205 Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3206 {
3207   unsigned tie_t = 0;
3208   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3209   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
3210   return tie_t;
3211 }
3212
3213 static void
3214 Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3215 {
3216   uint32 tie_t;
3217   tie_t = (val << 30) >> 30;
3218   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
3219   tie_t = (val << 29) >> 31;
3220   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3221 }
3222
3223 static unsigned
3224 Field_op0_s6_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3225 {
3226   unsigned tie_t = 0;
3227   tie_t = (tie_t << 5) | ((insn[0] << 0) >> 27);
3228   return tie_t;
3229 }
3230
3231 static void
3232 Field_op0_s6_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3233 {
3234   uint32 tie_t;
3235   tie_t = (val << 27) >> 27;
3236   insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27);
3237 }
3238
3239 static unsigned
3240 Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3241 {
3242   unsigned tie_t = 0;
3243   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3244   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3245   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3246   return tie_t;
3247 }
3248
3249 static void
3250 Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3251 {
3252   uint32 tie_t;
3253   tie_t = (val << 28) >> 28;
3254   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3255   tie_t = (val << 27) >> 31;
3256   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3257   tie_t = (val << 24) >> 29;
3258   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3259 }
3260
3261 static unsigned
3262 Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3263 {
3264   unsigned tie_t = 0;
3265   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3266   return tie_t;
3267 }
3268
3269 static void
3270 Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3271 {
3272   uint32 tie_t;
3273   tie_t = (val << 29) >> 29;
3274   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3275 }
3276
3277 static unsigned
3278 Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3279 {
3280   unsigned tie_t = 0;
3281   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3282   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3283   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3284   return tie_t;
3285 }
3286
3287 static void
3288 Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3289 {
3290   uint32 tie_t;
3291   tie_t = (val << 28) >> 28;
3292   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3293   tie_t = (val << 27) >> 31;
3294   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3295   tie_t = (val << 24) >> 29;
3296   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3297 }
3298
3299 static unsigned
3300 Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3301 {
3302   unsigned tie_t = 0;
3303   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3304   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3305   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3306   return tie_t;
3307 }
3308
3309 static void
3310 Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3311 {
3312   uint32 tie_t;
3313   tie_t = (val << 28) >> 28;
3314   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3315   tie_t = (val << 27) >> 31;
3316   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3317   tie_t = (val << 24) >> 29;
3318   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3319 }
3320
3321 static unsigned
3322 Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3323 {
3324   unsigned tie_t = 0;
3325   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3326   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3327   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3328   return tie_t;
3329 }
3330
3331 static void
3332 Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3333 {
3334   uint32 tie_t;
3335   tie_t = (val << 28) >> 28;
3336   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3337   tie_t = (val << 27) >> 31;
3338   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3339   tie_t = (val << 24) >> 29;
3340   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3341 }
3342
3343 static unsigned
3344 Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3345 {
3346   unsigned tie_t = 0;
3347   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3348   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3349   return tie_t;
3350 }
3351
3352 static void
3353 Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3354 {
3355   uint32 tie_t;
3356   tie_t = (val << 31) >> 31;
3357   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3358   tie_t = (val << 28) >> 29;
3359   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3360 }
3361
3362 static unsigned
3363 Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3364 {
3365   unsigned tie_t = 0;
3366   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3367   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3368   return tie_t;
3369 }
3370
3371 static void
3372 Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3373 {
3374   uint32 tie_t;
3375   tie_t = (val << 31) >> 31;
3376   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3377   tie_t = (val << 28) >> 29;
3378   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3379 }
3380
3381 static unsigned
3382 Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3383 {
3384   unsigned tie_t = 0;
3385   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3386   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3387   return tie_t;
3388 }
3389
3390 static void
3391 Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3392 {
3393   uint32 tie_t;
3394   tie_t = (val << 31) >> 31;
3395   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3396   tie_t = (val << 28) >> 29;
3397   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3398 }
3399
3400 static unsigned
3401 Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3402 {
3403   unsigned tie_t = 0;
3404   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3405   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3406   return tie_t;
3407 }
3408
3409 static void
3410 Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3411 {
3412   uint32 tie_t;
3413   tie_t = (val << 31) >> 31;
3414   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3415   tie_t = (val << 28) >> 29;
3416   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3417 }
3418
3419 static unsigned
3420 Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3421 {
3422   unsigned tie_t = 0;
3423   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3424   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3425   return tie_t;
3426 }
3427
3428 static void
3429 Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3430 {
3431   uint32 tie_t;
3432   tie_t = (val << 31) >> 31;
3433   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3434   tie_t = (val << 28) >> 29;
3435   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3436 }
3437
3438 static unsigned
3439 Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3440 {
3441   unsigned tie_t = 0;
3442   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3443   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3444   return tie_t;
3445 }
3446
3447 static void
3448 Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3449 {
3450   uint32 tie_t;
3451   tie_t = (val << 31) >> 31;
3452   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3453   tie_t = (val << 28) >> 29;
3454   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3455 }
3456
3457 static unsigned
3458 Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3459 {
3460   unsigned tie_t = 0;
3461   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3462   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3463   return tie_t;
3464 }
3465
3466 static void
3467 Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3468 {
3469   uint32 tie_t;
3470   tie_t = (val << 31) >> 31;
3471   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3472   tie_t = (val << 28) >> 29;
3473   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3474 }
3475
3476 static unsigned
3477 Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3478 {
3479   unsigned tie_t = 0;
3480   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3481   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3482   return tie_t;
3483 }
3484
3485 static void
3486 Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3487 {
3488   uint32 tie_t;
3489   tie_t = (val << 31) >> 31;
3490   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3491   tie_t = (val << 28) >> 29;
3492   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3493 }
3494
3495 static unsigned
3496 Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3497 {
3498   unsigned tie_t = 0;
3499   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3500   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3501   return tie_t;
3502 }
3503
3504 static void
3505 Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3506 {
3507   uint32 tie_t;
3508   tie_t = (val << 31) >> 31;
3509   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3510   tie_t = (val << 28) >> 29;
3511   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3512 }
3513
3514 static unsigned
3515 Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3516 {
3517   unsigned tie_t = 0;
3518   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3519   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3520   return tie_t;
3521 }
3522
3523 static void
3524 Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3525 {
3526   uint32 tie_t;
3527   tie_t = (val << 31) >> 31;
3528   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3529   tie_t = (val << 28) >> 29;
3530   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3531 }
3532
3533 static unsigned
3534 Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3535 {
3536   unsigned tie_t = 0;
3537   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3538   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3539   return tie_t;
3540 }
3541
3542 static void
3543 Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3544 {
3545   uint32 tie_t;
3546   tie_t = (val << 31) >> 31;
3547   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3548   tie_t = (val << 28) >> 29;
3549   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3550 }
3551
3552 static unsigned
3553 Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3554 {
3555   unsigned tie_t = 0;
3556   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3557   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3558   return tie_t;
3559 }
3560
3561 static void
3562 Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3563 {
3564   uint32 tie_t;
3565   tie_t = (val << 31) >> 31;
3566   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3567   tie_t = (val << 28) >> 29;
3568   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3569 }
3570
3571 static unsigned
3572 Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3573 {
3574   unsigned tie_t = 0;
3575   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3576   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3577   return tie_t;
3578 }
3579
3580 static void
3581 Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3582 {
3583   uint32 tie_t;
3584   tie_t = (val << 31) >> 31;
3585   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3586   tie_t = (val << 28) >> 29;
3587   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3588 }
3589
3590 static unsigned
3591 Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3592 {
3593   unsigned tie_t = 0;
3594   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3595   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3596   return tie_t;
3597 }
3598
3599 static void
3600 Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3601 {
3602   uint32 tie_t;
3603   tie_t = (val << 31) >> 31;
3604   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3605   tie_t = (val << 28) >> 29;
3606   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3607 }
3608
3609 static unsigned
3610 Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3611 {
3612   unsigned tie_t = 0;
3613   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3614   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3615   return tie_t;
3616 }
3617
3618 static void
3619 Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3620 {
3621   uint32 tie_t;
3622   tie_t = (val << 31) >> 31;
3623   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3624   tie_t = (val << 28) >> 29;
3625   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3626 }
3627
3628 static unsigned
3629 Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3630 {
3631   unsigned tie_t = 0;
3632   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3633   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3634   return tie_t;
3635 }
3636
3637 static void
3638 Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3639 {
3640   uint32 tie_t;
3641   tie_t = (val << 31) >> 31;
3642   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3643   tie_t = (val << 28) >> 29;
3644   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3645 }
3646
3647 static unsigned
3648 Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3649 {
3650   unsigned tie_t = 0;
3651   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3652   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3653   return tie_t;
3654 }
3655
3656 static void
3657 Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3658 {
3659   uint32 tie_t;
3660   tie_t = (val << 31) >> 31;
3661   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3662   tie_t = (val << 28) >> 29;
3663   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3664 }
3665
3666 static unsigned
3667 Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3668 {
3669   unsigned tie_t = 0;
3670   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3671   tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3672   return tie_t;
3673 }
3674
3675 static void
3676 Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3677 {
3678   uint32 tie_t;
3679   tie_t = (val << 31) >> 31;
3680   insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3681   tie_t = (val << 28) >> 29;
3682   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3683 }
3684
3685 static unsigned
3686 Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3687 {
3688   unsigned tie_t = 0;
3689   tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3690   tie_t = (tie_t << 27) | ((insn[0] << 5) >> 5);
3691   return tie_t;
3692 }
3693
3694 static void
3695 Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3696 {
3697   uint32 tie_t;
3698   tie_t = (val << 5) >> 5;
3699   insn[0] = (insn[0] & ~0x7ffffff) | (tie_t << 0);
3700   tie_t = (val << 2) >> 29;
3701   insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3702 }
3703
3704 static unsigned
3705 Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3706 {
3707   unsigned tie_t = 0;
3708   tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
3709   return tie_t;
3710 }
3711
3712 static void
3713 Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3714 {
3715   uint32 tie_t;
3716   tie_t = (val << 28) >> 28;
3717   insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
3718 }
3719
3720 static void
3721 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
3722                     uint32 val ATTRIBUTE_UNUSED)
3723 {
3724   /* Do nothing.  */
3725 }
3726
3727 static unsigned
3728 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3729 {
3730   return 0;
3731 }
3732
3733 static unsigned
3734 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3735 {
3736   return 4;
3737 }
3738
3739 static unsigned
3740 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3741 {
3742   return 8;
3743 }
3744
3745 static unsigned
3746 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3747 {
3748   return 12;
3749 }
3750
3751 static unsigned
3752 Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3753 {
3754   return 0;
3755 }
3756
3757 static unsigned
3758 Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3759 {
3760   return 1;
3761 }
3762
3763 static unsigned
3764 Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3765 {
3766   return 2;
3767 }
3768
3769 static unsigned
3770 Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3771 {
3772   return 3;
3773 }
3774
3775 static unsigned
3776 Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3777 {
3778   return 0;
3779 }
3780
3781 static unsigned
3782 Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3783 {
3784   return 0;
3785 }
3786
3787 static unsigned
3788 Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3789 {
3790   return 0;
3791 }
3792
3793 static unsigned
3794 Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3795 {
3796   return 0;
3797 }
3798
3799 \f
3800 /* Functional units.  */
3801
3802 static xtensa_funcUnit_internal funcUnits[] = {
3803
3804 };
3805
3806 \f
3807 /* Register files.  */
3808
3809 static xtensa_regfile_internal regfiles[] = {
3810   { "AR", "a", 0, 32, 64 },
3811   { "MR", "m", 1, 32, 4 },
3812   { "BR", "b", 2, 1, 16 },
3813   { "FR", "f", 3, 32, 16 },
3814   { "BR2", "b", 2, 2, 8 },
3815   { "BR4", "b", 2, 4, 4 },
3816   { "BR8", "b", 2, 8, 2 },
3817   { "BR16", "b", 2, 16, 1 }
3818 };
3819
3820 \f
3821 /* Interfaces.  */
3822
3823 static xtensa_interface_internal interfaces[] = {
3824
3825 };
3826
3827 \f
3828 /* Constant tables.  */
3829
3830 /* constant table ai4c */
3831 static const unsigned CONST_TBL_ai4c_0[] = {
3832   0xffffffff,
3833   0x1,
3834   0x2,
3835   0x3,
3836   0x4,
3837   0x5,
3838   0x6,
3839   0x7,
3840   0x8,
3841   0x9,
3842   0xa,
3843   0xb,
3844   0xc,
3845   0xd,
3846   0xe,
3847   0xf,
3848   0
3849 };
3850
3851 /* constant table b4c */
3852 static const unsigned CONST_TBL_b4c_0[] = {
3853   0xffffffff,
3854   0x1,
3855   0x2,
3856   0x3,
3857   0x4,
3858   0x5,
3859   0x6,
3860   0x7,
3861   0x8,
3862   0xa,
3863   0xc,
3864   0x10,
3865   0x20,
3866   0x40,
3867   0x80,
3868   0x100,
3869   0
3870 };
3871
3872 /* constant table b4cu */
3873 static const unsigned CONST_TBL_b4cu_0[] = {
3874   0x8000,
3875   0x10000,
3876   0x2,
3877   0x3,
3878   0x4,
3879   0x5,
3880   0x6,
3881   0x7,
3882   0x8,
3883   0xa,
3884   0xc,
3885   0x10,
3886   0x20,
3887   0x40,
3888   0x80,
3889   0x100,
3890   0
3891 };
3892
3893 \f
3894 /* Instruction operands.  */
3895
3896 static int
3897 Operand_soffsetx4_decode (uint32 *valp)
3898 {
3899   unsigned soffsetx4_0, offset_0;
3900   offset_0 = *valp & 0x3ffff;
3901   soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
3902   *valp = soffsetx4_0;
3903   return 0;
3904 }
3905
3906 static int
3907 Operand_soffsetx4_encode (uint32 *valp)
3908 {
3909   unsigned offset_0, soffsetx4_0;
3910   soffsetx4_0 = *valp;
3911   offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
3912   *valp = offset_0;
3913   return 0;
3914 }
3915
3916 static int
3917 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
3918 {
3919   *valp -= (pc & ~0x3);
3920   return 0;
3921 }
3922
3923 static int
3924 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
3925 {
3926   *valp += (pc & ~0x3);
3927   return 0;
3928 }
3929
3930 static int
3931 Operand_uimm12x8_decode (uint32 *valp)
3932 {
3933   unsigned uimm12x8_0, imm12_0;
3934   imm12_0 = *valp & 0xfff;
3935   uimm12x8_0 = imm12_0 << 3;
3936   *valp = uimm12x8_0;
3937   return 0;
3938 }
3939
3940 static int
3941 Operand_uimm12x8_encode (uint32 *valp)
3942 {
3943   unsigned imm12_0, uimm12x8_0;
3944   uimm12x8_0 = *valp;
3945   imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
3946   *valp = imm12_0;
3947   return 0;
3948 }
3949
3950 static int
3951 Operand_simm4_decode (uint32 *valp)
3952 {
3953   unsigned simm4_0, mn_0;
3954   mn_0 = *valp & 0xf;
3955   simm4_0 = ((int) mn_0 << 28) >> 28;
3956   *valp = simm4_0;
3957   return 0;
3958 }
3959
3960 static int
3961 Operand_simm4_encode (uint32 *valp)
3962 {
3963   unsigned mn_0, simm4_0;
3964   simm4_0 = *valp;
3965   mn_0 = (simm4_0 & 0xf);
3966   *valp = mn_0;
3967   return 0;
3968 }
3969
3970 static int
3971 Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
3972 {
3973   return 0;
3974 }
3975
3976 static int
3977 Operand_arr_encode (uint32 *valp)
3978 {
3979   int error;
3980   error = (*valp & ~0xf) != 0;
3981   return error;
3982 }
3983
3984 static int
3985 Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
3986 {
3987   return 0;
3988 }
3989
3990 static int
3991 Operand_ars_encode (uint32 *valp)
3992 {
3993   int error;
3994   error = (*valp & ~0xf) != 0;
3995   return error;
3996 }
3997
3998 static int
3999 Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
4000 {
4001   return 0;
4002 }
4003
4004 static int
4005 Operand_art_encode (uint32 *valp)
4006 {
4007   int error;
4008   error = (*valp & ~0xf) != 0;
4009   return error;
4010 }
4011
4012 static int
4013 Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
4014 {
4015   return 0;
4016 }
4017
4018 static int
4019 Operand_ar0_encode (uint32 *valp)
4020 {
4021   int error;
4022   error = (*valp & ~0x3f) != 0;
4023   return error;
4024 }
4025
4026 static int
4027 Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
4028 {
4029   return 0;
4030 }
4031
4032 static int
4033 Operand_ar4_encode (uint32 *valp)
4034 {
4035   int error;
4036   error = (*valp & ~0x3f) != 0;
4037   return error;
4038 }
4039
4040 static int
4041 Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
4042 {
4043   return 0;
4044 }
4045
4046 static int
4047 Operand_ar8_encode (uint32 *valp)
4048 {
4049   int error;
4050   error = (*valp & ~0x3f) != 0;
4051   return error;
4052 }
4053
4054 static int
4055 Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
4056 {
4057   return 0;
4058 }
4059
4060 static int
4061 Operand_ar12_encode (uint32 *valp)
4062 {
4063   int error;
4064   error = (*valp & ~0x3f) != 0;
4065   return error;
4066 }
4067
4068 static int
4069 Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
4070 {
4071   return 0;
4072 }
4073
4074 static int
4075 Operand_ars_entry_encode (uint32 *valp)
4076 {
4077   int error;
4078   error = (*valp & ~0x3f) != 0;
4079   return error;
4080 }
4081
4082 static int
4083 Operand_immrx4_decode (uint32 *valp)
4084 {
4085   unsigned immrx4_0, r_0;
4086   r_0 = *valp & 0xf;
4087   immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
4088   *valp = immrx4_0;
4089   return 0;
4090 }
4091
4092 static int
4093 Operand_immrx4_encode (uint32 *valp)
4094 {
4095   unsigned r_0, immrx4_0;
4096   immrx4_0 = *valp;
4097   r_0 = ((immrx4_0 >> 2) & 0xf);
4098   *valp = r_0;
4099   return 0;
4100 }
4101
4102 static int
4103 Operand_lsi4x4_decode (uint32 *valp)
4104 {
4105   unsigned lsi4x4_0, r_0;
4106   r_0 = *valp & 0xf;
4107   lsi4x4_0 = r_0 << 2;
4108   *valp = lsi4x4_0;
4109   return 0;
4110 }
4111
4112 static int
4113 Operand_lsi4x4_encode (uint32 *valp)
4114 {
4115   unsigned r_0, lsi4x4_0;
4116   lsi4x4_0 = *valp;
4117   r_0 = ((lsi4x4_0 >> 2) & 0xf);
4118   *valp = r_0;
4119   return 0;
4120 }
4121
4122 static int
4123 Operand_simm7_decode (uint32 *valp)
4124 {
4125   unsigned simm7_0, imm7_0;
4126   imm7_0 = *valp & 0x7f;
4127   simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
4128   *valp = simm7_0;
4129   return 0;
4130 }
4131
4132 static int
4133 Operand_simm7_encode (uint32 *valp)
4134 {
4135   unsigned imm7_0, simm7_0;
4136   simm7_0 = *valp;
4137   imm7_0 = (simm7_0 & 0x7f);
4138   *valp = imm7_0;
4139   return 0;
4140 }
4141
4142 static int
4143 Operand_uimm6_decode (uint32 *valp)
4144 {
4145   unsigned uimm6_0, imm6_0;
4146   imm6_0 = *valp & 0x3f;
4147   uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
4148   *valp = uimm6_0;
4149   return 0;
4150 }
4151
4152 static int
4153 Operand_uimm6_encode (uint32 *valp)
4154 {
4155   unsigned imm6_0, uimm6_0;
4156   uimm6_0 = *valp;
4157   imm6_0 = (uimm6_0 - 0x4) & 0x3f;
4158   *valp = imm6_0;
4159   return 0;
4160 }
4161
4162 static int
4163 Operand_uimm6_ator (uint32 *valp, uint32 pc)
4164 {
4165   *valp -= pc;
4166   return 0;
4167 }
4168
4169 static int
4170 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
4171 {
4172   *valp += pc;
4173   return 0;
4174 }
4175
4176 static int
4177 Operand_ai4const_decode (uint32 *valp)
4178 {
4179   unsigned ai4const_0, t_0;
4180   t_0 = *valp & 0xf;
4181   ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
4182   *valp = ai4const_0;
4183   return 0;
4184 }
4185
4186 static int
4187 Operand_ai4const_encode (uint32 *valp)
4188 {
4189   unsigned t_0, ai4const_0;
4190   ai4const_0 = *valp;
4191   switch (ai4const_0)
4192     {
4193     case 0xffffffff: t_0 = 0; break;
4194     case 0x1: t_0 = 0x1; break;
4195     case 0x2: t_0 = 0x2; break;
4196     case 0x3: t_0 = 0x3; break;
4197     case 0x4: t_0 = 0x4; break;
4198     case 0x5: t_0 = 0x5; break;
4199     case 0x6: t_0 = 0x6; break;
4200     case 0x7: t_0 = 0x7; break;
4201     case 0x8: t_0 = 0x8; break;
4202     case 0x9: t_0 = 0x9; break;
4203     case 0xa: t_0 = 0xa; break;
4204     case 0xb: t_0 = 0xb; break;
4205     case 0xc: t_0 = 0xc; break;
4206     case 0xd: t_0 = 0xd; break;
4207     case 0xe: t_0 = 0xe; break;
4208     default: t_0 = 0xf; break;
4209     }
4210   *valp = t_0;
4211   return 0;
4212 }
4213
4214 static int
4215 Operand_b4const_decode (uint32 *valp)
4216 {
4217   unsigned b4const_0, r_0;
4218   r_0 = *valp & 0xf;
4219   b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
4220   *valp = b4const_0;
4221   return 0;
4222 }
4223
4224 static int
4225 Operand_b4const_encode (uint32 *valp)
4226 {
4227   unsigned r_0, b4const_0;
4228   b4const_0 = *valp;
4229   switch (b4const_0)
4230     {
4231     case 0xffffffff: r_0 = 0; break;
4232     case 0x1: r_0 = 0x1; break;
4233     case 0x2: r_0 = 0x2; break;
4234     case 0x3: r_0 = 0x3; break;
4235     case 0x4: r_0 = 0x4; break;
4236     case 0x5: r_0 = 0x5; break;
4237     case 0x6: r_0 = 0x6; break;
4238     case 0x7: r_0 = 0x7; break;
4239     case 0x8: r_0 = 0x8; break;
4240     case 0xa: r_0 = 0x9; break;
4241     case 0xc: r_0 = 0xa; break;
4242     case 0x10: r_0 = 0xb; break;
4243     case 0x20: r_0 = 0xc; break;
4244     case 0x40: r_0 = 0xd; break;
4245     case 0x80: r_0 = 0xe; break;
4246     default: r_0 = 0xf; break;
4247     }
4248   *valp = r_0;
4249   return 0;
4250 }
4251
4252 static int
4253 Operand_b4constu_decode (uint32 *valp)
4254 {
4255   unsigned b4constu_0, r_0;
4256   r_0 = *valp & 0xf;
4257   b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
4258   *valp = b4constu_0;
4259   return 0;
4260 }
4261
4262 static int
4263 Operand_b4constu_encode (uint32 *valp)
4264 {
4265   unsigned r_0, b4constu_0;
4266   b4constu_0 = *valp;
4267   switch (b4constu_0)
4268     {
4269     case 0x8000: r_0 = 0; break;
4270     case 0x10000: r_0 = 0x1; break;
4271     case 0x2: r_0 = 0x2; break;
4272     case 0x3: r_0 = 0x3; break;
4273     case 0x4: r_0 = 0x4; break;
4274     case 0x5: r_0 = 0x5; break;
4275     case 0x6: r_0 = 0x6; break;
4276     case 0x7: r_0 = 0x7; break;
4277     case 0x8: r_0 = 0x8; break;
4278     case 0xa: r_0 = 0x9; break;
4279     case 0xc: r_0 = 0xa; break;
4280     case 0x10: r_0 = 0xb; break;
4281     case 0x20: r_0 = 0xc; break;
4282     case 0x40: r_0 = 0xd; break;
4283     case 0x80: r_0 = 0xe; break;
4284     default: r_0 = 0xf; break;
4285     }
4286   *valp = r_0;
4287   return 0;
4288 }
4289
4290 static int
4291 Operand_uimm8_decode (uint32 *valp)
4292 {
4293   unsigned uimm8_0, imm8_0;
4294   imm8_0 = *valp & 0xff;
4295   uimm8_0 = imm8_0;
4296   *valp = uimm8_0;
4297   return 0;
4298 }
4299
4300 static int
4301 Operand_uimm8_encode (uint32 *valp)
4302 {
4303   unsigned imm8_0, uimm8_0;
4304   uimm8_0 = *valp;
4305   imm8_0 = (uimm8_0 & 0xff);
4306   *valp = imm8_0;
4307   return 0;
4308 }
4309
4310 static int
4311 Operand_uimm8x2_decode (uint32 *valp)
4312 {
4313   unsigned uimm8x2_0, imm8_0;
4314   imm8_0 = *valp & 0xff;
4315   uimm8x2_0 = imm8_0 << 1;
4316   *valp = uimm8x2_0;
4317   return 0;
4318 }
4319
4320 static int
4321 Operand_uimm8x2_encode (uint32 *valp)
4322 {
4323   unsigned imm8_0, uimm8x2_0;
4324   uimm8x2_0 = *valp;
4325   imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
4326   *valp = imm8_0;
4327   return 0;
4328 }
4329
4330 static int
4331 Operand_uimm8x4_decode (uint32 *valp)
4332 {
4333   unsigned uimm8x4_0, imm8_0;
4334   imm8_0 = *valp & 0xff;
4335   uimm8x4_0 = imm8_0 << 2;
4336   *valp = uimm8x4_0;
4337   return 0;
4338 }
4339
4340 static int
4341 Operand_uimm8x4_encode (uint32 *valp)
4342 {
4343   unsigned imm8_0, uimm8x4_0;
4344   uimm8x4_0 = *valp;
4345   imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
4346   *valp = imm8_0;
4347   return 0;
4348 }
4349
4350 static int
4351 Operand_uimm4x16_decode (uint32 *valp)
4352 {
4353   unsigned uimm4x16_0, op2_0;
4354   op2_0 = *valp & 0xf;
4355   uimm4x16_0 = op2_0 << 4;
4356   *valp = uimm4x16_0;
4357   return 0;
4358 }
4359
4360 static int
4361 Operand_uimm4x16_encode (uint32 *valp)
4362 {
4363   unsigned op2_0, uimm4x16_0;
4364   uimm4x16_0 = *valp;
4365   op2_0 = ((uimm4x16_0 >> 4) & 0xf);
4366   *valp = op2_0;
4367   return 0;
4368 }
4369
4370 static int
4371 Operand_simm8_decode (uint32 *valp)
4372 {
4373   unsigned simm8_0, imm8_0;
4374   imm8_0 = *valp & 0xff;
4375   simm8_0 = ((int) imm8_0 << 24) >> 24;
4376   *valp = simm8_0;
4377   return 0;
4378 }
4379
4380 static int
4381 Operand_simm8_encode (uint32 *valp)
4382 {
4383   unsigned imm8_0, simm8_0;
4384   simm8_0 = *valp;
4385   imm8_0 = (simm8_0 & 0xff);
4386   *valp = imm8_0;
4387   return 0;
4388 }
4389
4390 static int
4391 Operand_simm8x256_decode (uint32 *valp)
4392 {
4393   unsigned simm8x256_0, imm8_0;
4394   imm8_0 = *valp & 0xff;
4395   simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
4396   *valp = simm8x256_0;
4397   return 0;
4398 }
4399
4400 static int
4401 Operand_simm8x256_encode (uint32 *valp)
4402 {
4403   unsigned imm8_0, simm8x256_0;
4404   simm8x256_0 = *valp;
4405   imm8_0 = ((simm8x256_0 >> 8) & 0xff);
4406   *valp = imm8_0;
4407   return 0;
4408 }
4409
4410 static int
4411 Operand_simm12b_decode (uint32 *valp)
4412 {
4413   unsigned simm12b_0, imm12b_0;
4414   imm12b_0 = *valp & 0xfff;
4415   simm12b_0 = ((int) imm12b_0 << 20) >> 20;
4416   *valp = simm12b_0;
4417   return 0;
4418 }
4419
4420 static int
4421 Operand_simm12b_encode (uint32 *valp)
4422 {
4423   unsigned imm12b_0, simm12b_0;
4424   simm12b_0 = *valp;
4425   imm12b_0 = (simm12b_0 & 0xfff);
4426   *valp = imm12b_0;
4427   return 0;
4428 }
4429
4430 static int
4431 Operand_msalp32_decode (uint32 *valp)
4432 {
4433   unsigned msalp32_0, sal_0;
4434   sal_0 = *valp & 0x1f;
4435   msalp32_0 = 0x20 - sal_0;
4436   *valp = msalp32_0;
4437   return 0;
4438 }
4439
4440 static int
4441 Operand_msalp32_encode (uint32 *valp)
4442 {
4443   unsigned sal_0, msalp32_0;
4444   msalp32_0 = *valp;
4445   sal_0 = (0x20 - msalp32_0) & 0x1f;
4446   *valp = sal_0;
4447   return 0;
4448 }
4449
4450 static int
4451 Operand_op2p1_decode (uint32 *valp)
4452 {
4453   unsigned op2p1_0, op2_0;
4454   op2_0 = *valp & 0xf;
4455   op2p1_0 = op2_0 + 0x1;
4456   *valp = op2p1_0;
4457   return 0;
4458 }
4459
4460 static int
4461 Operand_op2p1_encode (uint32 *valp)
4462 {
4463   unsigned op2_0, op2p1_0;
4464   op2p1_0 = *valp;
4465   op2_0 = (op2p1_0 - 0x1) & 0xf;
4466   *valp = op2_0;
4467   return 0;
4468 }
4469
4470 static int
4471 Operand_label8_decode (uint32 *valp)
4472 {
4473   unsigned label8_0, imm8_0;
4474   imm8_0 = *valp & 0xff;
4475   label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
4476   *valp = label8_0;
4477   return 0;
4478 }
4479
4480 static int
4481 Operand_label8_encode (uint32 *valp)
4482 {
4483   unsigned imm8_0, label8_0;
4484   label8_0 = *valp;
4485   imm8_0 = (label8_0 - 0x4) & 0xff;
4486   *valp = imm8_0;
4487   return 0;
4488 }
4489
4490 static int
4491 Operand_label8_ator (uint32 *valp, uint32 pc)
4492 {
4493   *valp -= pc;
4494   return 0;
4495 }
4496
4497 static int
4498 Operand_label8_rtoa (uint32 *valp, uint32 pc)
4499 {
4500   *valp += pc;
4501   return 0;
4502 }
4503
4504 static int
4505 Operand_ulabel8_decode (uint32 *valp)
4506 {
4507   unsigned ulabel8_0, imm8_0;
4508   imm8_0 = *valp & 0xff;
4509   ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
4510   *valp = ulabel8_0;
4511   return 0;
4512 }
4513
4514 static int
4515 Operand_ulabel8_encode (uint32 *valp)
4516 {
4517   unsigned imm8_0, ulabel8_0;
4518   ulabel8_0 = *valp;
4519   imm8_0 = (ulabel8_0 - 0x4) & 0xff;
4520   *valp = imm8_0;
4521   return 0;
4522 }
4523
4524 static int
4525 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
4526 {
4527   *valp -= pc;
4528   return 0;
4529 }
4530
4531 static int
4532 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
4533 {
4534   *valp += pc;
4535   return 0;
4536 }
4537
4538 static int
4539 Operand_label12_decode (uint32 *valp)
4540 {
4541   unsigned label12_0, imm12_0;
4542   imm12_0 = *valp & 0xfff;
4543   label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
4544   *valp = label12_0;
4545   return 0;
4546 }
4547
4548 static int
4549 Operand_label12_encode (uint32 *valp)
4550 {
4551   unsigned imm12_0, label12_0;
4552   label12_0 = *valp;
4553   imm12_0 = (label12_0 - 0x4) & 0xfff;
4554   *valp = imm12_0;
4555   return 0;
4556 }
4557
4558 static int
4559 Operand_label12_ator (uint32 *valp, uint32 pc)
4560 {
4561   *valp -= pc;
4562   return 0;
4563 }
4564
4565 static int
4566 Operand_label12_rtoa (uint32 *valp, uint32 pc)
4567 {
4568   *valp += pc;
4569   return 0;
4570 }
4571
4572 static int
4573 Operand_soffset_decode (uint32 *valp)
4574 {
4575   unsigned soffset_0, offset_0;
4576   offset_0 = *valp & 0x3ffff;
4577   soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
4578   *valp = soffset_0;
4579   return 0;
4580 }
4581
4582 static int
4583 Operand_soffset_encode (uint32 *valp)
4584 {
4585   unsigned offset_0, soffset_0;
4586   soffset_0 = *valp;
4587   offset_0 = (soffset_0 - 0x4) & 0x3ffff;
4588   *valp = offset_0;
4589   return 0;
4590 }
4591
4592 static int
4593 Operand_soffset_ator (uint32 *valp, uint32 pc)
4594 {
4595   *valp -= pc;
4596   return 0;
4597 }
4598
4599 static int
4600 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
4601 {
4602   *valp += pc;
4603   return 0;
4604 }
4605
4606 static int
4607 Operand_uimm16x4_decode (uint32 *valp)
4608 {
4609   unsigned uimm16x4_0, imm16_0;
4610   imm16_0 = *valp & 0xffff;
4611   uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
4612   *valp = uimm16x4_0;
4613   return 0;
4614 }
4615
4616 static int
4617 Operand_uimm16x4_encode (uint32 *valp)
4618 {
4619   unsigned imm16_0, uimm16x4_0;
4620   uimm16x4_0 = *valp;
4621   imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
4622   *valp = imm16_0;
4623   return 0;
4624 }
4625
4626 static int
4627 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
4628 {
4629   *valp -= ((pc + 3) & ~0x3);
4630   return 0;
4631 }
4632
4633 static int
4634 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
4635 {
4636   *valp += ((pc + 3) & ~0x3);
4637   return 0;
4638 }
4639
4640 static int
4641 Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
4642 {
4643   return 0;
4644 }
4645
4646 static int
4647 Operand_mx_encode (uint32 *valp)
4648 {
4649   int error;
4650   error = (*valp & ~0x3) != 0;
4651   return error;
4652 }
4653
4654 static int
4655 Operand_my_decode (uint32 *valp)
4656 {
4657   *valp += 2;
4658   return 0;
4659 }
4660
4661 static int
4662 Operand_my_encode (uint32 *valp)
4663 {
4664   int error;
4665   error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
4666   *valp = *valp & 1;
4667   return error;
4668 }
4669
4670 static int
4671 Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
4672 {
4673   return 0;
4674 }
4675
4676 static int
4677 Operand_mw_encode (uint32 *valp)
4678 {
4679   int error;
4680   error = (*valp & ~0x3) != 0;
4681   return error;
4682 }
4683
4684 static int
4685 Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
4686 {
4687   return 0;
4688 }
4689
4690 static int
4691 Operand_mr0_encode (uint32 *valp)
4692 {
4693   int error;
4694   error = (*valp & ~0x3) != 0;
4695   return error;
4696 }
4697
4698 static int
4699 Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
4700 {
4701   return 0;
4702 }
4703
4704 static int
4705 Operand_mr1_encode (uint32 *valp)
4706 {
4707   int error;
4708   error = (*valp & ~0x3) != 0;
4709   return error;
4710 }
4711
4712 static int
4713 Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
4714 {
4715   return 0;
4716 }
4717
4718 static int
4719 Operand_mr2_encode (uint32 *valp)
4720 {
4721   int error;
4722   error = (*valp & ~0x3) != 0;
4723   return error;
4724 }
4725
4726 static int
4727 Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
4728 {
4729   return 0;
4730 }
4731
4732 static int
4733 Operand_mr3_encode (uint32 *valp)
4734 {
4735   int error;
4736   error = (*valp & ~0x3) != 0;
4737   return error;
4738 }
4739
4740 static int
4741 Operand_immt_decode (uint32 *valp)
4742 {
4743   unsigned immt_0, t_0;
4744   t_0 = *valp & 0xf;
4745   immt_0 = t_0;
4746   *valp = immt_0;
4747   return 0;
4748 }
4749
4750 static int
4751 Operand_immt_encode (uint32 *valp)
4752 {
4753   unsigned t_0, immt_0;
4754   immt_0 = *valp;
4755   t_0 = immt_0 & 0xf;
4756   *valp = t_0;
4757   return 0;
4758 }
4759
4760 static int
4761 Operand_imms_decode (uint32 *valp)
4762 {
4763   unsigned imms_0, s_0;
4764   s_0 = *valp & 0xf;
4765   imms_0 = s_0;
4766   *valp = imms_0;
4767   return 0;
4768 }
4769
4770 static int
4771 Operand_imms_encode (uint32 *valp)
4772 {
4773   unsigned s_0, imms_0;
4774   imms_0 = *valp;
4775   s_0 = imms_0 & 0xf;
4776   *valp = s_0;
4777   return 0;
4778 }
4779
4780 static int
4781 Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED)
4782 {
4783   return 0;
4784 }
4785
4786 static int
4787 Operand_bt_encode (uint32 *valp)
4788 {
4789   int error;
4790   error = (*valp & ~0xf) != 0;
4791   return error;
4792 }
4793
4794 static int
4795 Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED)
4796 {
4797   return 0;
4798 }
4799
4800 static int
4801 Operand_bs_encode (uint32 *valp)
4802 {
4803   int error;
4804   error = (*valp & ~0xf) != 0;
4805   return error;
4806 }
4807
4808 static int
4809 Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED)
4810 {
4811   return 0;
4812 }
4813
4814 static int
4815 Operand_br_encode (uint32 *valp)
4816 {
4817   int error;
4818   error = (*valp & ~0xf) != 0;
4819   return error;
4820 }
4821
4822 static int
4823 Operand_bt2_decode (uint32 *valp)
4824 {
4825   *valp = *valp << 1;
4826   return 0;
4827 }
4828
4829 static int
4830 Operand_bt2_encode (uint32 *valp)
4831 {
4832   int error;
4833   error = (*valp & ~(0x7 << 1)) != 0;
4834   *valp = *valp >> 1;
4835   return error;
4836 }
4837
4838 static int
4839 Operand_bs2_decode (uint32 *valp)
4840 {
4841   *valp = *valp << 1;
4842   return 0;
4843 }
4844
4845 static int
4846 Operand_bs2_encode (uint32 *valp)
4847 {
4848   int error;
4849   error = (*valp & ~(0x7 << 1)) != 0;
4850   *valp = *valp >> 1;
4851   return error;
4852 }
4853
4854 static int
4855 Operand_br2_decode (uint32 *valp)
4856 {
4857   *valp = *valp << 1;
4858   return 0;
4859 }
4860
4861 static int
4862 Operand_br2_encode (uint32 *valp)
4863 {
4864   int error;
4865   error = (*valp & ~(0x7 << 1)) != 0;
4866   *valp = *valp >> 1;
4867   return error;
4868 }
4869
4870 static int
4871 Operand_bt4_decode (uint32 *valp)
4872 {
4873   *valp = *valp << 2;
4874   return 0;
4875 }
4876
4877 static int
4878 Operand_bt4_encode (uint32 *valp)
4879 {
4880   int error;
4881   error = (*valp & ~(0x3 << 2)) != 0;
4882   *valp = *valp >> 2;
4883   return error;
4884 }
4885
4886 static int
4887 Operand_bs4_decode (uint32 *valp)
4888 {
4889   *valp = *valp << 2;
4890   return 0;
4891 }
4892
4893 static int
4894 Operand_bs4_encode (uint32 *valp)
4895 {
4896   int error;
4897   error = (*valp & ~(0x3 << 2)) != 0;
4898   *valp = *valp >> 2;
4899   return error;
4900 }
4901
4902 static int
4903 Operand_br4_decode (uint32 *valp)
4904 {
4905   *valp = *valp << 2;
4906   return 0;
4907 }
4908
4909 static int
4910 Operand_br4_encode (uint32 *valp)
4911 {
4912   int error;
4913   error = (*valp & ~(0x3 << 2)) != 0;
4914   *valp = *valp >> 2;
4915   return error;
4916 }
4917
4918 static int
4919 Operand_bt8_decode (uint32 *valp)
4920 {
4921   *valp = *valp << 3;
4922   return 0;
4923 }
4924
4925 static int
4926 Operand_bt8_encode (uint32 *valp)
4927 {
4928   int error;
4929   error = (*valp & ~(0x1 << 3)) != 0;
4930   *valp = *valp >> 3;
4931   return error;
4932 }
4933
4934 static int
4935 Operand_bs8_decode (uint32 *valp)
4936 {
4937   *valp = *valp << 3;
4938   return 0;
4939 }
4940
4941 static int
4942 Operand_bs8_encode (uint32 *valp)
4943 {
4944   int error;
4945   error = (*valp & ~(0x1 << 3)) != 0;
4946   *valp = *valp >> 3;
4947   return error;
4948 }
4949
4950 static int
4951 Operand_br8_decode (uint32 *valp)
4952 {
4953   *valp = *valp << 3;
4954   return 0;
4955 }
4956
4957 static int
4958 Operand_br8_encode (uint32 *valp)
4959 {
4960   int error;
4961   error = (*valp & ~(0x1 << 3)) != 0;
4962   *valp = *valp >> 3;
4963   return error;
4964 }
4965
4966 static int
4967 Operand_bt16_decode (uint32 *valp)
4968 {
4969   *valp = *valp << 4;
4970   return 0;
4971 }
4972
4973 static int
4974 Operand_bt16_encode (uint32 *valp)
4975 {
4976   int error;
4977   error = (*valp & ~(0 << 4)) != 0;
4978   *valp = *valp >> 4;
4979   return error;
4980 }
4981
4982 static int
4983 Operand_bs16_decode (uint32 *valp)
4984 {
4985   *valp = *valp << 4;
4986   return 0;
4987 }
4988
4989 static int
4990 Operand_bs16_encode (uint32 *valp)
4991 {
4992   int error;
4993   error = (*valp & ~(0 << 4)) != 0;
4994   *valp = *valp >> 4;
4995   return error;
4996 }
4997
4998 static int
4999 Operand_br16_decode (uint32 *valp)
5000 {
5001   *valp = *valp << 4;
5002   return 0;
5003 }
5004
5005 static int
5006 Operand_br16_encode (uint32 *valp)
5007 {
5008   int error;
5009   error = (*valp & ~(0 << 4)) != 0;
5010   *valp = *valp >> 4;
5011   return error;
5012 }
5013
5014 static int
5015 Operand_brall_decode (uint32 *valp)
5016 {
5017   *valp = *valp << 4;
5018   return 0;
5019 }
5020
5021 static int
5022 Operand_brall_encode (uint32 *valp)
5023 {
5024   int error;
5025   error = (*valp & ~(0 << 4)) != 0;
5026   *valp = *valp >> 4;
5027   return error;
5028 }
5029
5030 static int
5031 Operand_tp7_decode (uint32 *valp)
5032 {
5033   unsigned tp7_0, t_0;
5034   t_0 = *valp & 0xf;
5035   tp7_0 = t_0 + 0x7;
5036   *valp = tp7_0;
5037   return 0;
5038 }
5039
5040 static int
5041 Operand_tp7_encode (uint32 *valp)
5042 {
5043   unsigned t_0, tp7_0;
5044   tp7_0 = *valp;
5045   t_0 = (tp7_0 - 0x7) & 0xf;
5046   *valp = t_0;
5047   return 0;
5048 }
5049
5050 static int
5051 Operand_xt_wbr15_label_decode (uint32 *valp)
5052 {
5053   unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
5054   xt_wbr15_imm_0 = *valp & 0x7fff;
5055   xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
5056   *valp = xt_wbr15_label_0;
5057   return 0;
5058 }
5059
5060 static int
5061 Operand_xt_wbr15_label_encode (uint32 *valp)
5062 {
5063   unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
5064   xt_wbr15_label_0 = *valp;
5065   xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
5066   *valp = xt_wbr15_imm_0;
5067   return 0;
5068 }
5069
5070 static int
5071 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
5072 {
5073   *valp -= pc;
5074   return 0;
5075 }
5076
5077 static int
5078 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
5079 {
5080   *valp += pc;
5081   return 0;
5082 }
5083
5084 static int
5085 Operand_xt_wbr18_label_decode (uint32 *valp)
5086 {
5087   unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
5088   xt_wbr18_imm_0 = *valp & 0x3ffff;
5089   xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
5090   *valp = xt_wbr18_label_0;
5091   return 0;
5092 }
5093
5094 static int
5095 Operand_xt_wbr18_label_encode (uint32 *valp)
5096 {
5097   unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
5098   xt_wbr18_label_0 = *valp;
5099   xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
5100   *valp = xt_wbr18_imm_0;
5101   return 0;
5102 }
5103
5104 static int
5105 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
5106 {
5107   *valp -= pc;
5108   return 0;
5109 }
5110
5111 static int
5112 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
5113 {
5114   *valp += pc;
5115   return 0;
5116 }
5117
5118 static int
5119 Operand_cimm8x4_decode (uint32 *valp)
5120 {
5121   unsigned cimm8x4_0, imm8_0;
5122   imm8_0 = *valp & 0xff;
5123   cimm8x4_0 = (imm8_0 << 2) | 0;
5124   *valp = cimm8x4_0;
5125   return 0;
5126 }
5127
5128 static int
5129 Operand_cimm8x4_encode (uint32 *valp)
5130 {
5131   unsigned imm8_0, cimm8x4_0;
5132   cimm8x4_0 = *valp;
5133   imm8_0 = (cimm8x4_0 >> 2) & 0xff;
5134   *valp = imm8_0;
5135   return 0;
5136 }
5137
5138 static int
5139 Operand_frr_decode (uint32 *valp ATTRIBUTE_UNUSED)
5140 {
5141   return 0;
5142 }
5143
5144 static int
5145 Operand_frr_encode (uint32 *valp)
5146 {
5147   int error;
5148   error = (*valp & ~0xf) != 0;
5149   return error;
5150 }
5151
5152 static int
5153 Operand_frs_decode (uint32 *valp ATTRIBUTE_UNUSED)
5154 {
5155   return 0;
5156 }
5157
5158 static int
5159 Operand_frs_encode (uint32 *valp)
5160 {
5161   int error;
5162   error = (*valp & ~0xf) != 0;
5163   return error;
5164 }
5165
5166 static int
5167 Operand_frt_decode (uint32 *valp ATTRIBUTE_UNUSED)
5168 {
5169   return 0;
5170 }
5171
5172 static int
5173 Operand_frt_encode (uint32 *valp)
5174 {
5175   int error;
5176   error = (*valp & ~0xf) != 0;
5177   return error;
5178 }
5179
5180 static xtensa_operand_internal operands[] = {
5181   { "soffsetx4", 10, -1, 0,
5182     XTENSA_OPERAND_IS_PCRELATIVE,
5183     Operand_soffsetx4_encode, Operand_soffsetx4_decode,
5184     Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
5185   { "uimm12x8", 3, -1, 0,
5186     0,
5187     Operand_uimm12x8_encode, Operand_uimm12x8_decode,
5188     0, 0 },
5189   { "simm4", 26, -1, 0,
5190     0,
5191     Operand_simm4_encode, Operand_simm4_decode,
5192     0, 0 },
5193   { "arr", 14, 0, 1,
5194     XTENSA_OPERAND_IS_REGISTER,
5195     Operand_arr_encode, Operand_arr_decode,
5196     0, 0 },
5197   { "ars", 5, 0, 1,
5198     XTENSA_OPERAND_IS_REGISTER,
5199     Operand_ars_encode, Operand_ars_decode,
5200     0, 0 },
5201   { "*ars_invisible", 5, 0, 1,
5202     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5203     Operand_ars_encode, Operand_ars_decode,
5204     0, 0 },
5205   { "art", 0, 0, 1,
5206     XTENSA_OPERAND_IS_REGISTER,
5207     Operand_art_encode, Operand_art_decode,
5208     0, 0 },
5209   { "ar0", 123, 0, 1,
5210     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5211     Operand_ar0_encode, Operand_ar0_decode,
5212     0, 0 },
5213   { "ar4", 124, 0, 1,
5214     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5215     Operand_ar4_encode, Operand_ar4_decode,
5216     0, 0 },
5217   { "ar8", 125, 0, 1,
5218     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5219     Operand_ar8_encode, Operand_ar8_decode,
5220     0, 0 },
5221   { "ar12", 126, 0, 1,
5222     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5223     Operand_ar12_encode, Operand_ar12_decode,
5224     0, 0 },
5225   { "ars_entry", 5, 0, 1,
5226     XTENSA_OPERAND_IS_REGISTER,
5227     Operand_ars_entry_encode, Operand_ars_entry_decode,
5228     0, 0 },
5229   { "immrx4", 14, -1, 0,
5230     0,
5231     Operand_immrx4_encode, Operand_immrx4_decode,
5232     0, 0 },
5233   { "lsi4x4", 14, -1, 0,
5234     0,
5235     Operand_lsi4x4_encode, Operand_lsi4x4_decode,
5236     0, 0 },
5237   { "simm7", 34, -1, 0,
5238     0,
5239     Operand_simm7_encode, Operand_simm7_decode,
5240     0, 0 },
5241   { "uimm6", 33, -1, 0,
5242     XTENSA_OPERAND_IS_PCRELATIVE,
5243     Operand_uimm6_encode, Operand_uimm6_decode,
5244     Operand_uimm6_ator, Operand_uimm6_rtoa },
5245   { "ai4const", 0, -1, 0,
5246     0,
5247     Operand_ai4const_encode, Operand_ai4const_decode,
5248     0, 0 },
5249   { "b4const", 14, -1, 0,
5250     0,
5251     Operand_b4const_encode, Operand_b4const_decode,
5252     0, 0 },
5253   { "b4constu", 14, -1, 0,
5254     0,
5255     Operand_b4constu_encode, Operand_b4constu_decode,
5256     0, 0 },
5257   { "uimm8", 4, -1, 0,
5258     0,
5259     Operand_uimm8_encode, Operand_uimm8_decode,
5260     0, 0 },
5261   { "uimm8x2", 4, -1, 0,
5262     0,
5263     Operand_uimm8x2_encode, Operand_uimm8x2_decode,
5264     0, 0 },
5265   { "uimm8x4", 4, -1, 0,
5266     0,
5267     Operand_uimm8x4_encode, Operand_uimm8x4_decode,
5268     0, 0 },
5269   { "uimm4x16", 13, -1, 0,
5270     0,
5271     Operand_uimm4x16_encode, Operand_uimm4x16_decode,
5272     0, 0 },
5273   { "simm8", 4, -1, 0,
5274     0,
5275     Operand_simm8_encode, Operand_simm8_decode,
5276     0, 0 },
5277   { "simm8x256", 4, -1, 0,
5278     0,
5279     Operand_simm8x256_encode, Operand_simm8x256_decode,
5280     0, 0 },
5281   { "simm12b", 6, -1, 0,
5282     0,
5283     Operand_simm12b_encode, Operand_simm12b_decode,
5284     0, 0 },
5285   { "msalp32", 18, -1, 0,
5286     0,
5287     Operand_msalp32_encode, Operand_msalp32_decode,
5288     0, 0 },
5289   { "op2p1", 13, -1, 0,
5290     0,
5291     Operand_op2p1_encode, Operand_op2p1_decode,
5292     0, 0 },
5293   { "label8", 4, -1, 0,
5294     XTENSA_OPERAND_IS_PCRELATIVE,
5295     Operand_label8_encode, Operand_label8_decode,
5296     Operand_label8_ator, Operand_label8_rtoa },
5297   { "ulabel8", 4, -1, 0,
5298     XTENSA_OPERAND_IS_PCRELATIVE,
5299     Operand_ulabel8_encode, Operand_ulabel8_decode,
5300     Operand_ulabel8_ator, Operand_ulabel8_rtoa },
5301   { "label12", 3, -1, 0,
5302     XTENSA_OPERAND_IS_PCRELATIVE,
5303     Operand_label12_encode, Operand_label12_decode,
5304     Operand_label12_ator, Operand_label12_rtoa },
5305   { "soffset", 10, -1, 0,
5306     XTENSA_OPERAND_IS_PCRELATIVE,
5307     Operand_soffset_encode, Operand_soffset_decode,
5308     Operand_soffset_ator, Operand_soffset_rtoa },
5309   { "uimm16x4", 7, -1, 0,
5310     XTENSA_OPERAND_IS_PCRELATIVE,
5311     Operand_uimm16x4_encode, Operand_uimm16x4_decode,
5312     Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
5313   { "mx", 43, 1, 1,
5314     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
5315     Operand_mx_encode, Operand_mx_decode,
5316     0, 0 },
5317   { "my", 42, 1, 1,
5318     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
5319     Operand_my_encode, Operand_my_decode,
5320     0, 0 },
5321   { "mw", 41, 1, 1,
5322     XTENSA_OPERAND_IS_REGISTER,
5323     Operand_mw_encode, Operand_mw_decode,
5324     0, 0 },
5325   { "mr0", 127, 1, 1,
5326     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5327     Operand_mr0_encode, Operand_mr0_decode,
5328     0, 0 },
5329   { "mr1", 128, 1, 1,
5330     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5331     Operand_mr1_encode, Operand_mr1_decode,
5332     0, 0 },
5333   { "mr2", 129, 1, 1,
5334     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5335     Operand_mr2_encode, Operand_mr2_decode,
5336     0, 0 },
5337   { "mr3", 130, 1, 1,
5338     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5339     Operand_mr3_encode, Operand_mr3_decode,
5340     0, 0 },
5341   { "immt", 0, -1, 0,
5342     0,
5343     Operand_immt_encode, Operand_immt_decode,
5344     0, 0 },
5345   { "imms", 5, -1, 0,
5346     0,
5347     Operand_imms_encode, Operand_imms_decode,
5348     0, 0 },
5349   { "bt", 0, 2, 1,
5350     XTENSA_OPERAND_IS_REGISTER,
5351     Operand_bt_encode, Operand_bt_decode,
5352     0, 0 },
5353   { "bs", 5, 2, 1,
5354     XTENSA_OPERAND_IS_REGISTER,
5355     Operand_bs_encode, Operand_bs_decode,
5356     0, 0 },
5357   { "br", 14, 2, 1,
5358     XTENSA_OPERAND_IS_REGISTER,
5359     Operand_br_encode, Operand_br_decode,
5360     0, 0 },
5361   { "bt2", 44, 2, 2,
5362     XTENSA_OPERAND_IS_REGISTER,
5363     Operand_bt2_encode, Operand_bt2_decode,
5364     0, 0 },
5365   { "bs2", 45, 2, 2,
5366     XTENSA_OPERAND_IS_REGISTER,
5367     Operand_bs2_encode, Operand_bs2_decode,
5368     0, 0 },
5369   { "br2", 46, 2, 2,
5370     XTENSA_OPERAND_IS_REGISTER,
5371     Operand_br2_encode, Operand_br2_decode,
5372     0, 0 },
5373   { "bt4", 47, 2, 4,
5374     XTENSA_OPERAND_IS_REGISTER,
5375     Operand_bt4_encode, Operand_bt4_decode,
5376     0, 0 },
5377   { "bs4", 48, 2, 4,
5378     XTENSA_OPERAND_IS_REGISTER,
5379     Operand_bs4_encode, Operand_bs4_decode,
5380     0, 0 },
5381   { "br4", 49, 2, 4,
5382     XTENSA_OPERAND_IS_REGISTER,
5383     Operand_br4_encode, Operand_br4_decode,
5384     0, 0 },
5385   { "bt8", 50, 2, 8,
5386     XTENSA_OPERAND_IS_REGISTER,
5387     Operand_bt8_encode, Operand_bt8_decode,
5388     0, 0 },
5389   { "bs8", 51, 2, 8,
5390     XTENSA_OPERAND_IS_REGISTER,
5391     Operand_bs8_encode, Operand_bs8_decode,
5392     0, 0 },
5393   { "br8", 52, 2, 8,
5394     XTENSA_OPERAND_IS_REGISTER,
5395     Operand_br8_encode, Operand_br8_decode,
5396     0, 0 },
5397   { "bt16", 131, 2, 16,
5398     XTENSA_OPERAND_IS_REGISTER,
5399     Operand_bt16_encode, Operand_bt16_decode,
5400     0, 0 },
5401   { "bs16", 132, 2, 16,
5402     XTENSA_OPERAND_IS_REGISTER,
5403     Operand_bs16_encode, Operand_bs16_decode,
5404     0, 0 },
5405   { "br16", 133, 2, 16,
5406     XTENSA_OPERAND_IS_REGISTER,
5407     Operand_br16_encode, Operand_br16_decode,
5408     0, 0 },
5409   { "brall", 134, 2, 16,
5410     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5411     Operand_brall_encode, Operand_brall_decode,
5412     0, 0 },
5413   { "tp7", 0, -1, 0,
5414     0,
5415     Operand_tp7_encode, Operand_tp7_decode,
5416     0, 0 },
5417   { "xt_wbr15_label", 53, -1, 0,
5418     XTENSA_OPERAND_IS_PCRELATIVE,
5419     Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
5420     Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
5421   { "xt_wbr18_label", 54, -1, 0,
5422     XTENSA_OPERAND_IS_PCRELATIVE,
5423     Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
5424     Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
5425   { "cimm8x4", 4, -1, 0,
5426     0,
5427     Operand_cimm8x4_encode, Operand_cimm8x4_decode,
5428     0, 0 },
5429   { "frr", 14, 3, 1,
5430     XTENSA_OPERAND_IS_REGISTER,
5431     Operand_frr_encode, Operand_frr_decode,
5432     0, 0 },
5433   { "frs", 5, 3, 1,
5434     XTENSA_OPERAND_IS_REGISTER,
5435     Operand_frs_encode, Operand_frs_decode,
5436     0, 0 },
5437   { "frt", 0, 3, 1,
5438     XTENSA_OPERAND_IS_REGISTER,
5439     Operand_frt_encode, Operand_frt_decode,
5440     0, 0 },
5441   { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
5442   { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
5443   { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
5444   { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
5445   { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
5446   { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
5447   { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
5448   { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
5449   { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
5450   { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
5451   { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
5452   { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
5453   { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
5454   { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
5455   { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
5456   { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
5457   { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
5458   { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
5459   { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
5460   { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
5461   { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
5462   { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
5463   { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
5464   { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
5465   { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
5466   { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
5467   { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
5468   { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
5469   { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
5470   { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
5471   { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
5472   { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
5473   { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
5474   { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
5475   { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
5476   { "r3", 35, -1, 0, 0, 0, 0, 0, 0 },
5477   { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 },
5478   { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 },
5479   { "t3", 38, -1, 0, 0, 0, 0, 0, 0 },
5480   { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 },
5481   { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 },
5482   { "w", 41, -1, 0, 0, 0, 0, 0, 0 },
5483   { "y", 42, -1, 0, 0, 0, 0, 0, 0 },
5484   { "x", 43, -1, 0, 0, 0, 0, 0, 0 },
5485   { "t2", 44, -1, 0, 0, 0, 0, 0, 0 },
5486   { "s2", 45, -1, 0, 0, 0, 0, 0, 0 },
5487   { "r2", 46, -1, 0, 0, 0, 0, 0, 0 },
5488   { "t4", 47, -1, 0, 0, 0, 0, 0, 0 },
5489   { "s4", 48, -1, 0, 0, 0, 0, 0, 0 },
5490   { "r4", 49, -1, 0, 0, 0, 0, 0, 0 },
5491   { "t8", 50, -1, 0, 0, 0, 0, 0, 0 },
5492   { "s8", 51, -1, 0, 0, 0, 0, 0, 0 },
5493   { "r8", 52, -1, 0, 0, 0, 0, 0, 0 },
5494   { "xt_wbr15_imm", 53, -1, 0, 0, 0, 0, 0, 0 },
5495   { "xt_wbr18_imm", 54, -1, 0, 0, 0, 0, 0, 0 },
5496   { "op0_xt_flix64_slot0_s3", 55, -1, 0, 0, 0, 0, 0, 0 },
5497   { "combined3e2c5767_fld7", 56, -1, 0, 0, 0, 0, 0, 0 },
5498   { "combined3e2c5767_fld8", 57, -1, 0, 0, 0, 0, 0, 0 },
5499   { "combined3e2c5767_fld9", 58, -1, 0, 0, 0, 0, 0, 0 },
5500   { "combined3e2c5767_fld11", 59, -1, 0, 0, 0, 0, 0, 0 },
5501   { "combined3e2c5767_fld49xt_flix64_slot0", 60, -1, 0, 0, 0, 0, 0, 0 },
5502   { "op0_s4", 61, -1, 0, 0, 0, 0, 0, 0 },
5503   { "combined3e2c5767_fld16", 62, -1, 0, 0, 0, 0, 0, 0 },
5504   { "combined3e2c5767_fld19xt_flix64_slot1", 63, -1, 0, 0, 0, 0, 0, 0 },
5505   { "combined3e2c5767_fld20xt_flix64_slot1", 64, -1, 0, 0, 0, 0, 0, 0 },
5506   { "combined3e2c5767_fld21xt_flix64_slot1", 65, -1, 0, 0, 0, 0, 0, 0 },
5507   { "combined3e2c5767_fld22xt_flix64_slot1", 66, -1, 0, 0, 0, 0, 0, 0 },
5508   { "combined3e2c5767_fld23xt_flix64_slot1", 67, -1, 0, 0, 0, 0, 0, 0 },
5509   { "combined3e2c5767_fld25xt_flix64_slot1", 68, -1, 0, 0, 0, 0, 0, 0 },
5510   { "combined3e2c5767_fld26xt_flix64_slot1", 69, -1, 0, 0, 0, 0, 0, 0 },
5511   { "combined3e2c5767_fld28xt_flix64_slot1", 70, -1, 0, 0, 0, 0, 0, 0 },
5512   { "combined3e2c5767_fld30xt_flix64_slot1", 71, -1, 0, 0, 0, 0, 0, 0 },
5513   { "combined3e2c5767_fld32xt_flix64_slot1", 72, -1, 0, 0, 0, 0, 0, 0 },
5514   { "combined3e2c5767_fld33xt_flix64_slot1", 73, -1, 0, 0, 0, 0, 0, 0 },
5515   { "combined3e2c5767_fld35xt_flix64_slot1", 74, -1, 0, 0, 0, 0, 0, 0 },
5516   { "combined3e2c5767_fld51xt_flix64_slot1", 75, -1, 0, 0, 0, 0, 0, 0 },
5517   { "combined3e2c5767_fld52xt_flix64_slot1", 76, -1, 0, 0, 0, 0, 0, 0 },
5518   { "combined3e2c5767_fld53xt_flix64_slot1", 77, -1, 0, 0, 0, 0, 0, 0 },
5519   { "combined3e2c5767_fld54xt_flix64_slot1", 78, -1, 0, 0, 0, 0, 0, 0 },
5520   { "combined3e2c5767_fld57xt_flix64_slot1", 79, -1, 0, 0, 0, 0, 0, 0 },
5521   { "combined3e2c5767_fld58xt_flix64_slot1", 80, -1, 0, 0, 0, 0, 0, 0 },
5522   { "combined3e2c5767_fld60xt_flix64_slot1", 81, -1, 0, 0, 0, 0, 0, 0 },
5523   { "combined3e2c5767_fld62xt_flix64_slot1", 82, -1, 0, 0, 0, 0, 0, 0 },
5524   { "op0_s5", 83, -1, 0, 0, 0, 0, 0, 0 },
5525   { "combined3e2c5767_fld36xt_flix64_slot2", 84, -1, 0, 0, 0, 0, 0, 0 },
5526   { "combined3e2c5767_fld37xt_flix64_slot2", 85, -1, 0, 0, 0, 0, 0, 0 },
5527   { "combined3e2c5767_fld39xt_flix64_slot2", 86, -1, 0, 0, 0, 0, 0, 0 },
5528   { "combined3e2c5767_fld41xt_flix64_slot2", 87, -1, 0, 0, 0, 0, 0, 0 },
5529   { "combined3e2c5767_fld42xt_flix64_slot2", 88, -1, 0, 0, 0, 0, 0, 0 },
5530   { "combined3e2c5767_fld44xt_flix64_slot2", 89, -1, 0, 0, 0, 0, 0, 0 },
5531   { "combined3e2c5767_fld45xt_flix64_slot2", 90, -1, 0, 0, 0, 0, 0, 0 },
5532   { "combined3e2c5767_fld47xt_flix64_slot2", 91, -1, 0, 0, 0, 0, 0, 0 },
5533   { "combined3e2c5767_fld63xt_flix64_slot2", 92, -1, 0, 0, 0, 0, 0, 0 },
5534   { "combined3e2c5767_fld64xt_flix64_slot2", 93, -1, 0, 0, 0, 0, 0, 0 },
5535   { "combined3e2c5767_fld65xt_flix64_slot2", 94, -1, 0, 0, 0, 0, 0, 0 },
5536   { "combined3e2c5767_fld66xt_flix64_slot2", 95, -1, 0, 0, 0, 0, 0, 0 },
5537   { "combined3e2c5767_fld68xt_flix64_slot2", 96, -1, 0, 0, 0, 0, 0, 0 },
5538   { "op0_s6", 97, -1, 0, 0, 0, 0, 0, 0 },
5539   { "combined3e2c5767_fld70xt_flix64_slot3", 98, -1, 0, 0, 0, 0, 0, 0 },
5540   { "combined3e2c5767_fld71", 99, -1, 0, 0, 0, 0, 0, 0 },
5541   { "combined3e2c5767_fld72xt_flix64_slot3", 100, -1, 0, 0, 0, 0, 0, 0 },
5542   { "combined3e2c5767_fld73xt_flix64_slot3", 101, -1, 0, 0, 0, 0, 0, 0 },
5543   { "combined3e2c5767_fld74xt_flix64_slot3", 102, -1, 0, 0, 0, 0, 0, 0 },
5544   { "combined3e2c5767_fld75xt_flix64_slot3", 103, -1, 0, 0, 0, 0, 0, 0 },
5545   { "combined3e2c5767_fld76xt_flix64_slot3", 104, -1, 0, 0, 0, 0, 0, 0 },
5546   { "combined3e2c5767_fld77xt_flix64_slot3", 105, -1, 0, 0, 0, 0, 0, 0 },
5547   { "combined3e2c5767_fld78xt_flix64_slot3", 106, -1, 0, 0, 0, 0, 0, 0 },
5548   { "combined3e2c5767_fld79xt_flix64_slot3", 107, -1, 0, 0, 0, 0, 0, 0 },
5549   { "combined3e2c5767_fld80xt_flix64_slot3", 108, -1, 0, 0, 0, 0, 0, 0 },
5550   { "combined3e2c5767_fld81xt_flix64_slot3", 109, -1, 0, 0, 0, 0, 0, 0 },
5551   { "combined3e2c5767_fld82xt_flix64_slot3", 110, -1, 0, 0, 0, 0, 0, 0 },
5552   { "combined3e2c5767_fld83xt_flix64_slot3", 111, -1, 0, 0, 0, 0, 0, 0 },
5553   { "combined3e2c5767_fld84xt_flix64_slot3", 112, -1, 0, 0, 0, 0, 0, 0 },
5554   { "combined3e2c5767_fld85xt_flix64_slot3", 113, -1, 0, 0, 0, 0, 0, 0 },
5555   { "combined3e2c5767_fld86xt_flix64_slot3", 114, -1, 0, 0, 0, 0, 0, 0 },
5556   { "combined3e2c5767_fld87xt_flix64_slot3", 115, -1, 0, 0, 0, 0, 0, 0 },
5557   { "combined3e2c5767_fld88xt_flix64_slot3", 116, -1, 0, 0, 0, 0, 0, 0 },
5558   { "combined3e2c5767_fld89xt_flix64_slot3", 117, -1, 0, 0, 0, 0, 0, 0 },
5559   { "combined3e2c5767_fld90xt_flix64_slot3", 118, -1, 0, 0, 0, 0, 0, 0 },
5560   { "combined3e2c5767_fld91xt_flix64_slot3", 119, -1, 0, 0, 0, 0, 0, 0 },
5561   { "combined3e2c5767_fld92xt_flix64_slot3", 120, -1, 0, 0, 0, 0, 0, 0 },
5562   { "combined3e2c5767_fld93xt_flix64_slot3", 121, -1, 0, 0, 0, 0, 0, 0 },
5563   { "op0_xt_flix64_slot0", 122, -1, 0, 0, 0, 0, 0, 0 }
5564 };
5565
5566 \f
5567 /* Iclass table.  */
5568
5569 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
5570   { { STATE_PSRING }, 'i' },
5571   { { STATE_PSEXCM }, 'm' },
5572   { { STATE_EPC1 }, 'i' }
5573 };
5574
5575 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
5576   { { STATE_PSEXCM }, 'i' },
5577   { { STATE_PSRING }, 'i' },
5578   { { STATE_DEPC }, 'i' }
5579 };
5580
5581 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
5582   { { 0 /* soffsetx4 */ }, 'i' },
5583   { { 10 /* ar12 */ }, 'o' }
5584 };
5585
5586 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
5587   { { STATE_PSCALLINC }, 'o' }
5588 };
5589
5590 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
5591   { { 0 /* soffsetx4 */ }, 'i' },
5592   { { 9 /* ar8 */ }, 'o' }
5593 };
5594
5595 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
5596   { { STATE_PSCALLINC }, 'o' }
5597 };
5598
5599 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
5600   { { 0 /* soffsetx4 */ }, 'i' },
5601   { { 8 /* ar4 */ }, 'o' }
5602 };
5603
5604 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
5605   { { STATE_PSCALLINC }, 'o' }
5606 };
5607
5608 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
5609   { { 4 /* ars */ }, 'i' },
5610   { { 10 /* ar12 */ }, 'o' }
5611 };
5612
5613 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
5614   { { STATE_PSCALLINC }, 'o' }
5615 };
5616
5617 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
5618   { { 4 /* ars */ }, 'i' },
5619   { { 9 /* ar8 */ }, 'o' }
5620 };
5621
5622 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
5623   { { STATE_PSCALLINC }, 'o' }
5624 };
5625
5626 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
5627   { { 4 /* ars */ }, 'i' },
5628   { { 8 /* ar4 */ }, 'o' }
5629 };
5630
5631 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
5632   { { STATE_PSCALLINC }, 'o' }
5633 };
5634
5635 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
5636   { { 11 /* ars_entry */ }, 's' },
5637   { { 4 /* ars */ }, 'i' },
5638   { { 1 /* uimm12x8 */ }, 'i' }
5639 };
5640
5641 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
5642   { { STATE_PSCALLINC }, 'i' },
5643   { { STATE_PSEXCM }, 'i' },
5644   { { STATE_PSWOE }, 'i' },
5645   { { STATE_WindowBase }, 'm' },
5646   { { STATE_WindowStart }, 'm' }
5647 };
5648
5649 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
5650   { { 6 /* art */ }, 'o' },
5651   { { 4 /* ars */ }, 'i' }
5652 };
5653
5654 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
5655   { { STATE_WindowBase }, 'i' },
5656   { { STATE_WindowStart }, 'i' }
5657 };
5658
5659 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
5660   { { 2 /* simm4 */ }, 'i' }
5661 };
5662
5663 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
5664   { { STATE_PSEXCM }, 'i' },
5665   { { STATE_PSRING }, 'i' },
5666   { { STATE_WindowBase }, 'm' }
5667 };
5668
5669 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
5670   { { 5 /* *ars_invisible */ }, 'i' }
5671 };
5672
5673 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
5674   { { STATE_WindowBase }, 'm' },
5675   { { STATE_WindowStart }, 'm' },
5676   { { STATE_PSEXCM }, 'i' },
5677   { { STATE_PSWOE }, 'i' }
5678 };
5679
5680 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
5681   { { STATE_EPC1 }, 'i' },
5682   { { STATE_PSEXCM }, 'm' },
5683   { { STATE_PSRING }, 'i' },
5684   { { STATE_WindowBase }, 'm' },
5685   { { STATE_WindowStart }, 'm' },
5686   { { STATE_PSOWB }, 'i' }
5687 };
5688
5689 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
5690   { { 6 /* art */ }, 'o' },
5691   { { 4 /* ars */ }, 'i' },
5692   { { 12 /* immrx4 */ }, 'i' }
5693 };
5694
5695 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
5696   { { STATE_PSEXCM }, 'i' },
5697   { { STATE_PSRING }, 'i' }
5698 };
5699
5700 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
5701   { { 6 /* art */ }, 'i' },
5702   { { 4 /* ars */ }, 'i' },
5703   { { 12 /* immrx4 */ }, 'i' }
5704 };
5705
5706 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
5707   { { STATE_PSEXCM }, 'i' },
5708   { { STATE_PSRING }, 'i' }
5709 };
5710
5711 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
5712   { { 6 /* art */ }, 'o' }
5713 };
5714
5715 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
5716   { { STATE_PSEXCM }, 'i' },
5717   { { STATE_PSRING }, 'i' },
5718   { { STATE_WindowBase }, 'i' }
5719 };
5720
5721 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
5722   { { 6 /* art */ }, 'i' }
5723 };
5724
5725 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
5726   { { STATE_PSEXCM }, 'i' },
5727   { { STATE_PSRING }, 'i' },
5728   { { STATE_WindowBase }, 'o' }
5729 };
5730
5731 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
5732   { { 6 /* art */ }, 'm' }
5733 };
5734
5735 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
5736   { { STATE_PSEXCM }, 'i' },
5737   { { STATE_PSRING }, 'i' },
5738   { { STATE_WindowBase }, 'm' }
5739 };
5740
5741 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
5742   { { 6 /* art */ }, 'o' }
5743 };
5744
5745 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
5746   { { STATE_PSEXCM }, 'i' },
5747   { { STATE_PSRING }, 'i' },
5748   { { STATE_WindowStart }, 'i' }
5749 };
5750
5751 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
5752   { { 6 /* art */ }, 'i' }
5753 };
5754
5755 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
5756   { { STATE_PSEXCM }, 'i' },
5757   { { STATE_PSRING }, 'i' },
5758   { { STATE_WindowStart }, 'o' }
5759 };
5760
5761 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
5762   { { 6 /* art */ }, 'm' }
5763 };
5764
5765 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
5766   { { STATE_PSEXCM }, 'i' },
5767   { { STATE_PSRING }, 'i' },
5768   { { STATE_WindowStart }, 'm' }
5769 };
5770
5771 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
5772   { { 3 /* arr */ }, 'o' },
5773   { { 4 /* ars */ }, 'i' },
5774   { { 6 /* art */ }, 'i' }
5775 };
5776
5777 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
5778   { { 3 /* arr */ }, 'o' },
5779   { { 4 /* ars */ }, 'i' },
5780   { { 16 /* ai4const */ }, 'i' }
5781 };
5782
5783 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
5784   { { 4 /* ars */ }, 'i' },
5785   { { 15 /* uimm6 */ }, 'i' }
5786 };
5787
5788 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
5789   { { 6 /* art */ }, 'o' },
5790   { { 4 /* ars */ }, 'i' },
5791   { { 13 /* lsi4x4 */ }, 'i' }
5792 };
5793
5794 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
5795   { { 6 /* art */ }, 'o' },
5796   { { 4 /* ars */ }, 'i' }
5797 };
5798
5799 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
5800   { { 4 /* ars */ }, 'o' },
5801   { { 14 /* simm7 */ }, 'i' }
5802 };
5803
5804 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
5805   { { 5 /* *ars_invisible */ }, 'i' }
5806 };
5807
5808 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
5809   { { 6 /* art */ }, 'i' },
5810   { { 4 /* ars */ }, 'i' },
5811   { { 13 /* lsi4x4 */ }, 'i' }
5812 };
5813
5814 static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
5815   { { 3 /* arr */ }, 'o' }
5816 };
5817
5818 static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
5819   { { STATE_THREADPTR }, 'i' }
5820 };
5821
5822 static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
5823   { { 6 /* art */ }, 'i' }
5824 };
5825
5826 static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
5827   { { STATE_THREADPTR }, 'o' }
5828 };
5829
5830 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
5831   { { 6 /* art */ }, 'o' },
5832   { { 4 /* ars */ }, 'i' },
5833   { { 23 /* simm8 */ }, 'i' }
5834 };
5835
5836 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
5837   { { 6 /* art */ }, 'o' },
5838   { { 4 /* ars */ }, 'i' },
5839   { { 24 /* simm8x256 */ }, 'i' }
5840 };
5841
5842 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
5843   { { 3 /* arr */ }, 'o' },
5844   { { 4 /* ars */ }, 'i' },
5845   { { 6 /* art */ }, 'i' }
5846 };
5847
5848 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
5849   { { 3 /* arr */ }, 'o' },
5850   { { 4 /* ars */ }, 'i' },
5851   { { 6 /* art */ }, 'i' }
5852 };
5853
5854 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
5855   { { 4 /* ars */ }, 'i' },
5856   { { 17 /* b4const */ }, 'i' },
5857   { { 28 /* label8 */ }, 'i' }
5858 };
5859
5860 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
5861   { { 4 /* ars */ }, 'i' },
5862   { { 67 /* bbi */ }, 'i' },
5863   { { 28 /* label8 */ }, 'i' }
5864 };
5865
5866 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
5867   { { 4 /* ars */ }, 'i' },
5868   { { 18 /* b4constu */ }, 'i' },
5869   { { 28 /* label8 */ }, 'i' }
5870 };
5871
5872 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
5873   { { 4 /* ars */ }, 'i' },
5874   { { 6 /* art */ }, 'i' },
5875   { { 28 /* label8 */ }, 'i' }
5876 };
5877
5878 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
5879   { { 4 /* ars */ }, 'i' },
5880   { { 30 /* label12 */ }, 'i' }
5881 };
5882
5883 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
5884   { { 0 /* soffsetx4 */ }, 'i' },
5885   { { 7 /* ar0 */ }, 'o' }
5886 };
5887
5888 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
5889   { { 4 /* ars */ }, 'i' },
5890   { { 7 /* ar0 */ }, 'o' }
5891 };
5892
5893 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
5894   { { 3 /* arr */ }, 'o' },
5895   { { 6 /* art */ }, 'i' },
5896   { { 82 /* sae */ }, 'i' },
5897   { { 27 /* op2p1 */ }, 'i' }
5898 };
5899
5900 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
5901   { { 31 /* soffset */ }, 'i' }
5902 };
5903
5904 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
5905   { { 4 /* ars */ }, 'i' }
5906 };
5907
5908 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
5909   { { 6 /* art */ }, 'o' },
5910   { { 4 /* ars */ }, 'i' },
5911   { { 20 /* uimm8x2 */ }, 'i' }
5912 };
5913
5914 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
5915   { { 6 /* art */ }, 'o' },
5916   { { 4 /* ars */ }, 'i' },
5917   { { 20 /* uimm8x2 */ }, 'i' }
5918 };
5919
5920 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
5921   { { 6 /* art */ }, 'o' },
5922   { { 4 /* ars */ }, 'i' },
5923   { { 21 /* uimm8x4 */ }, 'i' }
5924 };
5925
5926 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
5927   { { 6 /* art */ }, 'o' },
5928   { { 32 /* uimm16x4 */ }, 'i' }
5929 };
5930
5931 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
5932   { { STATE_LITBADDR }, 'i' },
5933   { { STATE_LITBEN }, 'i' }
5934 };
5935
5936 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
5937   { { 6 /* art */ }, 'o' },
5938   { { 4 /* ars */ }, 'i' },
5939   { { 19 /* uimm8 */ }, 'i' }
5940 };
5941
5942 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
5943   { { 4 /* ars */ }, 'i' },
5944   { { 29 /* ulabel8 */ }, 'i' }
5945 };
5946
5947 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
5948   { { STATE_LBEG }, 'o' },
5949   { { STATE_LEND }, 'o' },
5950   { { STATE_LCOUNT }, 'o' }
5951 };
5952
5953 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
5954   { { 4 /* ars */ }, 'i' },
5955   { { 29 /* ulabel8 */ }, 'i' }
5956 };
5957
5958 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
5959   { { STATE_LBEG }, 'o' },
5960   { { STATE_LEND }, 'o' },
5961   { { STATE_LCOUNT }, 'o' }
5962 };
5963
5964 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
5965   { { 6 /* art */ }, 'o' },
5966   { { 25 /* simm12b */ }, 'i' }
5967 };
5968
5969 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
5970   { { 3 /* arr */ }, 'm' },
5971   { { 4 /* ars */ }, 'i' },
5972   { { 6 /* art */ }, 'i' }
5973 };
5974
5975 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
5976   { { 3 /* arr */ }, 'o' },
5977   { { 6 /* art */ }, 'i' }
5978 };
5979
5980 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
5981   { { 5 /* *ars_invisible */ }, 'i' }
5982 };
5983
5984 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
5985   { { 6 /* art */ }, 'i' },
5986   { { 4 /* ars */ }, 'i' },
5987   { { 20 /* uimm8x2 */ }, 'i' }
5988 };
5989
5990 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
5991   { { 6 /* art */ }, 'i' },
5992   { { 4 /* ars */ }, 'i' },
5993   { { 21 /* uimm8x4 */ }, 'i' }
5994 };
5995
5996 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
5997   { { 6 /* art */ }, 'i' },
5998   { { 4 /* ars */ }, 'i' },
5999   { { 19 /* uimm8 */ }, 'i' }
6000 };
6001
6002 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
6003   { { 4 /* ars */ }, 'i' }
6004 };
6005
6006 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
6007   { { STATE_SAR }, 'o' }
6008 };
6009
6010 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
6011   { { 86 /* sas */ }, 'i' }
6012 };
6013
6014 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
6015   { { STATE_SAR }, 'o' }
6016 };
6017
6018 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
6019   { { 3 /* arr */ }, 'o' },
6020   { { 4 /* ars */ }, 'i' }
6021 };
6022
6023 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
6024   { { STATE_SAR }, 'i' }
6025 };
6026
6027 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
6028   { { 3 /* arr */ }, 'o' },
6029   { { 4 /* ars */ }, 'i' },
6030   { { 6 /* art */ }, 'i' }
6031 };
6032
6033 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
6034   { { STATE_SAR }, 'i' }
6035 };
6036
6037 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
6038   { { 3 /* arr */ }, 'o' },
6039   { { 6 /* art */ }, 'i' }
6040 };
6041
6042 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
6043   { { STATE_SAR }, 'i' }
6044 };
6045
6046 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
6047   { { 3 /* arr */ }, 'o' },
6048   { { 4 /* ars */ }, 'i' },
6049   { { 26 /* msalp32 */ }, 'i' }
6050 };
6051
6052 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
6053   { { 3 /* arr */ }, 'o' },
6054   { { 6 /* art */ }, 'i' },
6055   { { 84 /* sargt */ }, 'i' }
6056 };
6057
6058 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
6059   { { 3 /* arr */ }, 'o' },
6060   { { 6 /* art */ }, 'i' },
6061   { { 70 /* s */ }, 'i' }
6062 };
6063
6064 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
6065   { { STATE_XTSYNC }, 'i' }
6066 };
6067
6068 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
6069   { { 6 /* art */ }, 'o' },
6070   { { 70 /* s */ }, 'i' }
6071 };
6072
6073 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
6074   { { STATE_PSWOE }, 'i' },
6075   { { STATE_PSCALLINC }, 'i' },
6076   { { STATE_PSOWB }, 'i' },
6077   { { STATE_PSRING }, 'i' },
6078   { { STATE_PSUM }, 'i' },
6079   { { STATE_PSEXCM }, 'i' },
6080   { { STATE_PSINTLEVEL }, 'm' }
6081 };
6082
6083 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
6084   { { 6 /* art */ }, 'o' }
6085 };
6086
6087 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
6088   { { STATE_LEND }, 'i' }
6089 };
6090
6091 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
6092   { { 6 /* art */ }, 'i' }
6093 };
6094
6095 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
6096   { { STATE_LEND }, 'o' }
6097 };
6098
6099 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
6100   { { 6 /* art */ }, 'm' }
6101 };
6102
6103 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
6104   { { STATE_LEND }, 'm' }
6105 };
6106
6107 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
6108   { { 6 /* art */ }, 'o' }
6109 };
6110
6111 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
6112   { { STATE_LCOUNT }, 'i' }
6113 };
6114
6115 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
6116   { { 6 /* art */ }, 'i' }
6117 };
6118
6119 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
6120   { { STATE_XTSYNC }, 'o' },
6121   { { STATE_LCOUNT }, 'o' }
6122 };
6123
6124 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
6125   { { 6 /* art */ }, 'm' }
6126 };
6127
6128 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
6129   { { STATE_XTSYNC }, 'o' },
6130   { { STATE_LCOUNT }, 'm' }
6131 };
6132
6133 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
6134   { { 6 /* art */ }, 'o' }
6135 };
6136
6137 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
6138   { { STATE_LBEG }, 'i' }
6139 };
6140
6141 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
6142   { { 6 /* art */ }, 'i' }
6143 };
6144
6145 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
6146   { { STATE_LBEG }, 'o' }
6147 };
6148
6149 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
6150   { { 6 /* art */ }, 'm' }
6151 };
6152
6153 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
6154   { { STATE_LBEG }, 'm' }
6155 };
6156
6157 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
6158   { { 6 /* art */ }, 'o' }
6159 };
6160
6161 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
6162   { { STATE_SAR }, 'i' }
6163 };
6164
6165 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
6166   { { 6 /* art */ }, 'i' }
6167 };
6168
6169 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
6170   { { STATE_SAR }, 'o' },
6171   { { STATE_XTSYNC }, 'o' }
6172 };
6173
6174 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
6175   { { 6 /* art */ }, 'm' }
6176 };
6177
6178 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
6179   { { STATE_SAR }, 'm' }
6180 };
6181
6182 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
6183   { { 6 /* art */ }, 'o' }
6184 };
6185
6186 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
6187   { { STATE_LITBADDR }, 'i' },
6188   { { STATE_LITBEN }, 'i' }
6189 };
6190
6191 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
6192   { { 6 /* art */ }, 'i' }
6193 };
6194
6195 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
6196   { { STATE_LITBADDR }, 'o' },
6197   { { STATE_LITBEN }, 'o' }
6198 };
6199
6200 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
6201   { { 6 /* art */ }, 'm' }
6202 };
6203
6204 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
6205   { { STATE_LITBADDR }, 'm' },
6206   { { STATE_LITBEN }, 'm' }
6207 };
6208
6209 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
6210   { { 6 /* art */ }, 'o' }
6211 };
6212
6213 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
6214   { { STATE_PSEXCM }, 'i' },
6215   { { STATE_PSRING }, 'i' }
6216 };
6217
6218 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
6219   { { 6 /* art */ }, 'o' }
6220 };
6221
6222 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
6223   { { STATE_PSEXCM }, 'i' },
6224   { { STATE_PSRING }, 'i' }
6225 };
6226
6227 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
6228   { { 6 /* art */ }, 'o' }
6229 };
6230
6231 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
6232   { { STATE_PSWOE }, 'i' },
6233   { { STATE_PSCALLINC }, 'i' },
6234   { { STATE_PSOWB }, 'i' },
6235   { { STATE_PSRING }, 'i' },
6236   { { STATE_PSUM }, 'i' },
6237   { { STATE_PSEXCM }, 'i' },
6238   { { STATE_PSINTLEVEL }, 'i' }
6239 };
6240
6241 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
6242   { { 6 /* art */ }, 'i' }
6243 };
6244
6245 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
6246   { { STATE_PSWOE }, 'o' },
6247   { { STATE_PSCALLINC }, 'o' },
6248   { { STATE_PSOWB }, 'o' },
6249   { { STATE_PSRING }, 'm' },
6250   { { STATE_PSUM }, 'o' },
6251   { { STATE_PSEXCM }, 'm' },
6252   { { STATE_PSINTLEVEL }, 'o' }
6253 };
6254
6255 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
6256   { { 6 /* art */ }, 'm' }
6257 };
6258
6259 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
6260   { { STATE_PSWOE }, 'm' },
6261   { { STATE_PSCALLINC }, 'm' },
6262   { { STATE_PSOWB }, 'm' },
6263   { { STATE_PSRING }, 'm' },
6264   { { STATE_PSUM }, 'm' },
6265   { { STATE_PSEXCM }, 'm' },
6266   { { STATE_PSINTLEVEL }, 'm' }
6267 };
6268
6269 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
6270   { { 6 /* art */ }, 'o' }
6271 };
6272
6273 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
6274   { { STATE_PSEXCM }, 'i' },
6275   { { STATE_PSRING }, 'i' },
6276   { { STATE_EPC1 }, 'i' }
6277 };
6278
6279 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
6280   { { 6 /* art */ }, 'i' }
6281 };
6282
6283 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
6284   { { STATE_PSEXCM }, 'i' },
6285   { { STATE_PSRING }, 'i' },
6286   { { STATE_EPC1 }, 'o' }
6287 };
6288
6289 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
6290   { { 6 /* art */ }, 'm' }
6291 };
6292
6293 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
6294   { { STATE_PSEXCM }, 'i' },
6295   { { STATE_PSRING }, 'i' },
6296   { { STATE_EPC1 }, 'm' }
6297 };
6298
6299 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
6300   { { 6 /* art */ }, 'o' }
6301 };
6302
6303 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
6304   { { STATE_PSEXCM }, 'i' },
6305   { { STATE_PSRING }, 'i' },
6306   { { STATE_EXCSAVE1 }, 'i' }
6307 };
6308
6309 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
6310   { { 6 /* art */ }, 'i' }
6311 };
6312
6313 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
6314   { { STATE_PSEXCM }, 'i' },
6315   { { STATE_PSRING }, 'i' },
6316   { { STATE_EXCSAVE1 }, 'o' }
6317 };
6318
6319 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
6320   { { 6 /* art */ }, 'm' }
6321 };
6322
6323 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
6324   { { STATE_PSEXCM }, 'i' },
6325   { { STATE_PSRING }, 'i' },
6326   { { STATE_EXCSAVE1 }, 'm' }
6327 };
6328
6329 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
6330   { { 6 /* art */ }, 'o' }
6331 };
6332
6333 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
6334   { { STATE_PSEXCM }, 'i' },
6335   { { STATE_PSRING }, 'i' },
6336   { { STATE_EPC2 }, 'i' }
6337 };
6338
6339 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
6340   { { 6 /* art */ }, 'i' }
6341 };
6342
6343 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
6344   { { STATE_PSEXCM }, 'i' },
6345   { { STATE_PSRING }, 'i' },
6346   { { STATE_EPC2 }, 'o' }
6347 };
6348
6349 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
6350   { { 6 /* art */ }, 'm' }
6351 };
6352
6353 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
6354   { { STATE_PSEXCM }, 'i' },
6355   { { STATE_PSRING }, 'i' },
6356   { { STATE_EPC2 }, 'm' }
6357 };
6358
6359 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
6360   { { 6 /* art */ }, 'o' }
6361 };
6362
6363 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
6364   { { STATE_PSEXCM }, 'i' },
6365   { { STATE_PSRING }, 'i' },
6366   { { STATE_EXCSAVE2 }, 'i' }
6367 };
6368
6369 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
6370   { { 6 /* art */ }, 'i' }
6371 };
6372
6373 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
6374   { { STATE_PSEXCM }, 'i' },
6375   { { STATE_PSRING }, 'i' },
6376   { { STATE_EXCSAVE2 }, 'o' }
6377 };
6378
6379 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
6380   { { 6 /* art */ }, 'm' }
6381 };
6382
6383 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
6384   { { STATE_PSEXCM }, 'i' },
6385   { { STATE_PSRING }, 'i' },
6386   { { STATE_EXCSAVE2 }, 'm' }
6387 };
6388
6389 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
6390   { { 6 /* art */ }, 'o' }
6391 };
6392
6393 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
6394   { { STATE_PSEXCM }, 'i' },
6395   { { STATE_PSRING }, 'i' },
6396   { { STATE_EPC3 }, 'i' }
6397 };
6398
6399 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
6400   { { 6 /* art */ }, 'i' }
6401 };
6402
6403 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
6404   { { STATE_PSEXCM }, 'i' },
6405   { { STATE_PSRING }, 'i' },
6406   { { STATE_EPC3 }, 'o' }
6407 };
6408
6409 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
6410   { { 6 /* art */ }, 'm' }
6411 };
6412
6413 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
6414   { { STATE_PSEXCM }, 'i' },
6415   { { STATE_PSRING }, 'i' },
6416   { { STATE_EPC3 }, 'm' }
6417 };
6418
6419 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
6420   { { 6 /* art */ }, 'o' }
6421 };
6422
6423 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
6424   { { STATE_PSEXCM }, 'i' },
6425   { { STATE_PSRING }, 'i' },
6426   { { STATE_EXCSAVE3 }, 'i' }
6427 };
6428
6429 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
6430   { { 6 /* art */ }, 'i' }
6431 };
6432
6433 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
6434   { { STATE_PSEXCM }, 'i' },
6435   { { STATE_PSRING }, 'i' },
6436   { { STATE_EXCSAVE3 }, 'o' }
6437 };
6438
6439 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
6440   { { 6 /* art */ }, 'm' }
6441 };
6442
6443 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
6444   { { STATE_PSEXCM }, 'i' },
6445   { { STATE_PSRING }, 'i' },
6446   { { STATE_EXCSAVE3 }, 'm' }
6447 };
6448
6449 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
6450   { { 6 /* art */ }, 'o' }
6451 };
6452
6453 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
6454   { { STATE_PSEXCM }, 'i' },
6455   { { STATE_PSRING }, 'i' },
6456   { { STATE_EPC4 }, 'i' }
6457 };
6458
6459 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
6460   { { 6 /* art */ }, 'i' }
6461 };
6462
6463 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
6464   { { STATE_PSEXCM }, 'i' },
6465   { { STATE_PSRING }, 'i' },
6466   { { STATE_EPC4 }, 'o' }
6467 };
6468
6469 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
6470   { { 6 /* art */ }, 'm' }
6471 };
6472
6473 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
6474   { { STATE_PSEXCM }, 'i' },
6475   { { STATE_PSRING }, 'i' },
6476   { { STATE_EPC4 }, 'm' }
6477 };
6478
6479 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
6480   { { 6 /* art */ }, 'o' }
6481 };
6482
6483 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
6484   { { STATE_PSEXCM }, 'i' },
6485   { { STATE_PSRING }, 'i' },
6486   { { STATE_EXCSAVE4 }, 'i' }
6487 };
6488
6489 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
6490   { { 6 /* art */ }, 'i' }
6491 };
6492
6493 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
6494   { { STATE_PSEXCM }, 'i' },
6495   { { STATE_PSRING }, 'i' },
6496   { { STATE_EXCSAVE4 }, 'o' }
6497 };
6498
6499 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
6500   { { 6 /* art */ }, 'm' }
6501 };
6502
6503 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
6504   { { STATE_PSEXCM }, 'i' },
6505   { { STATE_PSRING }, 'i' },
6506   { { STATE_EXCSAVE4 }, 'm' }
6507 };
6508
6509 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
6510   { { 6 /* art */ }, 'o' }
6511 };
6512
6513 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
6514   { { STATE_PSEXCM }, 'i' },
6515   { { STATE_PSRING }, 'i' },
6516   { { STATE_EPC5 }, 'i' }
6517 };
6518
6519 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
6520   { { 6 /* art */ }, 'i' }
6521 };
6522
6523 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
6524   { { STATE_PSEXCM }, 'i' },
6525   { { STATE_PSRING }, 'i' },
6526   { { STATE_EPC5 }, 'o' }
6527 };
6528
6529 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
6530   { { 6 /* art */ }, 'm' }
6531 };
6532
6533 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
6534   { { STATE_PSEXCM }, 'i' },
6535   { { STATE_PSRING }, 'i' },
6536   { { STATE_EPC5 }, 'm' }
6537 };
6538
6539 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
6540   { { 6 /* art */ }, 'o' }
6541 };
6542
6543 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
6544   { { STATE_PSEXCM }, 'i' },
6545   { { STATE_PSRING }, 'i' },
6546   { { STATE_EXCSAVE5 }, 'i' }
6547 };
6548
6549 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
6550   { { 6 /* art */ }, 'i' }
6551 };
6552
6553 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
6554   { { STATE_PSEXCM }, 'i' },
6555   { { STATE_PSRING }, 'i' },
6556   { { STATE_EXCSAVE5 }, 'o' }
6557 };
6558
6559 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
6560   { { 6 /* art */ }, 'm' }
6561 };
6562
6563 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
6564   { { STATE_PSEXCM }, 'i' },
6565   { { STATE_PSRING }, 'i' },
6566   { { STATE_EXCSAVE5 }, 'm' }
6567 };
6568
6569 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
6570   { { 6 /* art */ }, 'o' }
6571 };
6572
6573 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
6574   { { STATE_PSEXCM }, 'i' },
6575   { { STATE_PSRING }, 'i' },
6576   { { STATE_EPC6 }, 'i' }
6577 };
6578
6579 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
6580   { { 6 /* art */ }, 'i' }
6581 };
6582
6583 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
6584   { { STATE_PSEXCM }, 'i' },
6585   { { STATE_PSRING }, 'i' },
6586   { { STATE_EPC6 }, 'o' }
6587 };
6588
6589 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
6590   { { 6 /* art */ }, 'm' }
6591 };
6592
6593 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
6594   { { STATE_PSEXCM }, 'i' },
6595   { { STATE_PSRING }, 'i' },
6596   { { STATE_EPC6 }, 'm' }
6597 };
6598
6599 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
6600   { { 6 /* art */ }, 'o' }
6601 };
6602
6603 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
6604   { { STATE_PSEXCM }, 'i' },
6605   { { STATE_PSRING }, 'i' },
6606   { { STATE_EXCSAVE6 }, 'i' }
6607 };
6608
6609 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
6610   { { 6 /* art */ }, 'i' }
6611 };
6612
6613 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
6614   { { STATE_PSEXCM }, 'i' },
6615   { { STATE_PSRING }, 'i' },
6616   { { STATE_EXCSAVE6 }, 'o' }
6617 };
6618
6619 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
6620   { { 6 /* art */ }, 'm' }
6621 };
6622
6623 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
6624   { { STATE_PSEXCM }, 'i' },
6625   { { STATE_PSRING }, 'i' },
6626   { { STATE_EXCSAVE6 }, 'm' }
6627 };
6628
6629 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
6630   { { 6 /* art */ }, 'o' }
6631 };
6632
6633 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
6634   { { STATE_PSEXCM }, 'i' },
6635   { { STATE_PSRING }, 'i' },
6636   { { STATE_EPC7 }, 'i' }
6637 };
6638
6639 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
6640   { { 6 /* art */ }, 'i' }
6641 };
6642
6643 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
6644   { { STATE_PSEXCM }, 'i' },
6645   { { STATE_PSRING }, 'i' },
6646   { { STATE_EPC7 }, 'o' }
6647 };
6648
6649 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
6650   { { 6 /* art */ }, 'm' }
6651 };
6652
6653 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
6654   { { STATE_PSEXCM }, 'i' },
6655   { { STATE_PSRING }, 'i' },
6656   { { STATE_EPC7 }, 'm' }
6657 };
6658
6659 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
6660   { { 6 /* art */ }, 'o' }
6661 };
6662
6663 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
6664   { { STATE_PSEXCM }, 'i' },
6665   { { STATE_PSRING }, 'i' },
6666   { { STATE_EXCSAVE7 }, 'i' }
6667 };
6668
6669 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
6670   { { 6 /* art */ }, 'i' }
6671 };
6672
6673 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
6674   { { STATE_PSEXCM }, 'i' },
6675   { { STATE_PSRING }, 'i' },
6676   { { STATE_EXCSAVE7 }, 'o' }
6677 };
6678
6679 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
6680   { { 6 /* art */ }, 'm' }
6681 };
6682
6683 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
6684   { { STATE_PSEXCM }, 'i' },
6685   { { STATE_PSRING }, 'i' },
6686   { { STATE_EXCSAVE7 }, 'm' }
6687 };
6688
6689 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
6690   { { 6 /* art */ }, 'o' }
6691 };
6692
6693 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
6694   { { STATE_PSEXCM }, 'i' },
6695   { { STATE_PSRING }, 'i' },
6696   { { STATE_EPS2 }, 'i' }
6697 };
6698
6699 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
6700   { { 6 /* art */ }, 'i' }
6701 };
6702
6703 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
6704   { { STATE_PSEXCM }, 'i' },
6705   { { STATE_PSRING }, 'i' },
6706   { { STATE_EPS2 }, 'o' }
6707 };
6708
6709 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
6710   { { 6 /* art */ }, 'm' }
6711 };
6712
6713 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
6714   { { STATE_PSEXCM }, 'i' },
6715   { { STATE_PSRING }, 'i' },
6716   { { STATE_EPS2 }, 'm' }
6717 };
6718
6719 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
6720   { { 6 /* art */ }, 'o' }
6721 };
6722
6723 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
6724   { { STATE_PSEXCM }, 'i' },
6725   { { STATE_PSRING }, 'i' },
6726   { { STATE_EPS3 }, 'i' }
6727 };
6728
6729 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
6730   { { 6 /* art */ }, 'i' }
6731 };
6732
6733 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
6734   { { STATE_PSEXCM }, 'i' },
6735   { { STATE_PSRING }, 'i' },
6736   { { STATE_EPS3 }, 'o' }
6737 };
6738
6739 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
6740   { { 6 /* art */ }, 'm' }
6741 };
6742
6743 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
6744   { { STATE_PSEXCM }, 'i' },
6745   { { STATE_PSRING }, 'i' },
6746   { { STATE_EPS3 }, 'm' }
6747 };
6748
6749 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
6750   { { 6 /* art */ }, 'o' }
6751 };
6752
6753 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
6754   { { STATE_PSEXCM }, 'i' },
6755   { { STATE_PSRING }, 'i' },
6756   { { STATE_EPS4 }, 'i' }
6757 };
6758
6759 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
6760   { { 6 /* art */ }, 'i' }
6761 };
6762
6763 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
6764   { { STATE_PSEXCM }, 'i' },
6765   { { STATE_PSRING }, 'i' },
6766   { { STATE_EPS4 }, 'o' }
6767 };
6768
6769 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
6770   { { 6 /* art */ }, 'm' }
6771 };
6772
6773 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
6774   { { STATE_PSEXCM }, 'i' },
6775   { { STATE_PSRING }, 'i' },
6776   { { STATE_EPS4 }, 'm' }
6777 };
6778
6779 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
6780   { { 6 /* art */ }, 'o' }
6781 };
6782
6783 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
6784   { { STATE_PSEXCM }, 'i' },
6785   { { STATE_PSRING }, 'i' },
6786   { { STATE_EPS5 }, 'i' }
6787 };
6788
6789 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
6790   { { 6 /* art */ }, 'i' }
6791 };
6792
6793 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
6794   { { STATE_PSEXCM }, 'i' },
6795   { { STATE_PSRING }, 'i' },
6796   { { STATE_EPS5 }, 'o' }
6797 };
6798
6799 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
6800   { { 6 /* art */ }, 'm' }
6801 };
6802
6803 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
6804   { { STATE_PSEXCM }, 'i' },
6805   { { STATE_PSRING }, 'i' },
6806   { { STATE_EPS5 }, 'm' }
6807 };
6808
6809 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
6810   { { 6 /* art */ }, 'o' }
6811 };
6812
6813 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
6814   { { STATE_PSEXCM }, 'i' },
6815   { { STATE_PSRING }, 'i' },
6816   { { STATE_EPS6 }, 'i' }
6817 };
6818
6819 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
6820   { { 6 /* art */ }, 'i' }
6821 };
6822
6823 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
6824   { { STATE_PSEXCM }, 'i' },
6825   { { STATE_PSRING }, 'i' },
6826   { { STATE_EPS6 }, 'o' }
6827 };
6828
6829 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
6830   { { 6 /* art */ }, 'm' }
6831 };
6832
6833 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
6834   { { STATE_PSEXCM }, 'i' },
6835   { { STATE_PSRING }, 'i' },
6836   { { STATE_EPS6 }, 'm' }
6837 };
6838
6839 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
6840   { { 6 /* art */ }, 'o' }
6841 };
6842
6843 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
6844   { { STATE_PSEXCM }, 'i' },
6845   { { STATE_PSRING }, 'i' },
6846   { { STATE_EPS7 }, 'i' }
6847 };
6848
6849 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
6850   { { 6 /* art */ }, 'i' }
6851 };
6852
6853 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
6854   { { STATE_PSEXCM }, 'i' },
6855   { { STATE_PSRING }, 'i' },
6856   { { STATE_EPS7 }, 'o' }
6857 };
6858
6859 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
6860   { { 6 /* art */ }, 'm' }
6861 };
6862
6863 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
6864   { { STATE_PSEXCM }, 'i' },
6865   { { STATE_PSRING }, 'i' },
6866   { { STATE_EPS7 }, 'm' }
6867 };
6868
6869 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
6870   { { 6 /* art */ }, 'o' }
6871 };
6872
6873 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
6874   { { STATE_PSEXCM }, 'i' },
6875   { { STATE_PSRING }, 'i' },
6876   { { STATE_EXCVADDR }, 'i' }
6877 };
6878
6879 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
6880   { { 6 /* art */ }, 'i' }
6881 };
6882
6883 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
6884   { { STATE_PSEXCM }, 'i' },
6885   { { STATE_PSRING }, 'i' },
6886   { { STATE_EXCVADDR }, 'o' }
6887 };
6888
6889 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
6890   { { 6 /* art */ }, 'm' }
6891 };
6892
6893 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
6894   { { STATE_PSEXCM }, 'i' },
6895   { { STATE_PSRING }, 'i' },
6896   { { STATE_EXCVADDR }, 'm' }
6897 };
6898
6899 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
6900   { { 6 /* art */ }, 'o' }
6901 };
6902
6903 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
6904   { { STATE_PSEXCM }, 'i' },
6905   { { STATE_PSRING }, 'i' },
6906   { { STATE_DEPC }, 'i' }
6907 };
6908
6909 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
6910   { { 6 /* art */ }, 'i' }
6911 };
6912
6913 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
6914   { { STATE_PSEXCM }, 'i' },
6915   { { STATE_PSRING }, 'i' },
6916   { { STATE_DEPC }, 'o' }
6917 };
6918
6919 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
6920   { { 6 /* art */ }, 'm' }
6921 };
6922
6923 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
6924   { { STATE_PSEXCM }, 'i' },
6925   { { STATE_PSRING }, 'i' },
6926   { { STATE_DEPC }, 'm' }
6927 };
6928
6929 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
6930   { { 6 /* art */ }, 'o' }
6931 };
6932
6933 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
6934   { { STATE_PSEXCM }, 'i' },
6935   { { STATE_PSRING }, 'i' },
6936   { { STATE_EXCCAUSE }, 'i' },
6937   { { STATE_XTSYNC }, 'i' }
6938 };
6939
6940 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
6941   { { 6 /* art */ }, 'i' }
6942 };
6943
6944 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
6945   { { STATE_PSEXCM }, 'i' },
6946   { { STATE_PSRING }, 'i' },
6947   { { STATE_EXCCAUSE }, 'o' }
6948 };
6949
6950 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
6951   { { 6 /* art */ }, 'm' }
6952 };
6953
6954 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
6955   { { STATE_PSEXCM }, 'i' },
6956   { { STATE_PSRING }, 'i' },
6957   { { STATE_EXCCAUSE }, 'm' }
6958 };
6959
6960 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
6961   { { 6 /* art */ }, 'o' }
6962 };
6963
6964 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
6965   { { STATE_PSEXCM }, 'i' },
6966   { { STATE_PSRING }, 'i' },
6967   { { STATE_MISC0 }, 'i' }
6968 };
6969
6970 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
6971   { { 6 /* art */ }, 'i' }
6972 };
6973
6974 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
6975   { { STATE_PSEXCM }, 'i' },
6976   { { STATE_PSRING }, 'i' },
6977   { { STATE_MISC0 }, 'o' }
6978 };
6979
6980 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
6981   { { 6 /* art */ }, 'm' }
6982 };
6983
6984 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
6985   { { STATE_PSEXCM }, 'i' },
6986   { { STATE_PSRING }, 'i' },
6987   { { STATE_MISC0 }, 'm' }
6988 };
6989
6990 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
6991   { { 6 /* art */ }, 'o' }
6992 };
6993
6994 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
6995   { { STATE_PSEXCM }, 'i' },
6996   { { STATE_PSRING }, 'i' },
6997   { { STATE_MISC1 }, 'i' }
6998 };
6999
7000 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
7001   { { 6 /* art */ }, 'i' }
7002 };
7003
7004 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
7005   { { STATE_PSEXCM }, 'i' },
7006   { { STATE_PSRING }, 'i' },
7007   { { STATE_MISC1 }, 'o' }
7008 };
7009
7010 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
7011   { { 6 /* art */ }, 'm' }
7012 };
7013
7014 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
7015   { { STATE_PSEXCM }, 'i' },
7016   { { STATE_PSRING }, 'i' },
7017   { { STATE_MISC1 }, 'm' }
7018 };
7019
7020 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = {
7021   { { 6 /* art */ }, 'o' }
7022 };
7023
7024 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = {
7025   { { STATE_PSEXCM }, 'i' },
7026   { { STATE_PSRING }, 'i' },
7027   { { STATE_MISC2 }, 'i' }
7028 };
7029
7030 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = {
7031   { { 6 /* art */ }, 'i' }
7032 };
7033
7034 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = {
7035   { { STATE_PSEXCM }, 'i' },
7036   { { STATE_PSRING }, 'i' },
7037   { { STATE_MISC2 }, 'o' }
7038 };
7039
7040 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = {
7041   { { 6 /* art */ }, 'm' }
7042 };
7043
7044 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = {
7045   { { STATE_PSEXCM }, 'i' },
7046   { { STATE_PSRING }, 'i' },
7047   { { STATE_MISC2 }, 'm' }
7048 };
7049
7050 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = {
7051   { { 6 /* art */ }, 'o' }
7052 };
7053
7054 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = {
7055   { { STATE_PSEXCM }, 'i' },
7056   { { STATE_PSRING }, 'i' },
7057   { { STATE_MISC3 }, 'i' }
7058 };
7059
7060 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = {
7061   { { 6 /* art */ }, 'i' }
7062 };
7063
7064 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = {
7065   { { STATE_PSEXCM }, 'i' },
7066   { { STATE_PSRING }, 'i' },
7067   { { STATE_MISC3 }, 'o' }
7068 };
7069
7070 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = {
7071   { { 6 /* art */ }, 'm' }
7072 };
7073
7074 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = {
7075   { { STATE_PSEXCM }, 'i' },
7076   { { STATE_PSRING }, 'i' },
7077   { { STATE_MISC3 }, 'm' }
7078 };
7079
7080 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
7081   { { 6 /* art */ }, 'o' }
7082 };
7083
7084 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
7085   { { STATE_PSEXCM }, 'i' },
7086   { { STATE_PSRING }, 'i' }
7087 };
7088
7089 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
7090   { { 6 /* art */ }, 'o' }
7091 };
7092
7093 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
7094   { { STATE_PSEXCM }, 'i' },
7095   { { STATE_PSRING }, 'i' },
7096   { { STATE_VECBASE }, 'i' }
7097 };
7098
7099 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
7100   { { 6 /* art */ }, 'i' }
7101 };
7102
7103 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
7104   { { STATE_PSEXCM }, 'i' },
7105   { { STATE_PSRING }, 'i' },
7106   { { STATE_VECBASE }, 'o' }
7107 };
7108
7109 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
7110   { { 6 /* art */ }, 'm' }
7111 };
7112
7113 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
7114   { { STATE_PSEXCM }, 'i' },
7115   { { STATE_PSRING }, 'i' },
7116   { { STATE_VECBASE }, 'm' }
7117 };
7118
7119 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
7120   { { 4 /* ars */ }, 'i' },
7121   { { 6 /* art */ }, 'i' }
7122 };
7123
7124 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
7125   { { STATE_ACC }, 'o' }
7126 };
7127
7128 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
7129   { { 4 /* ars */ }, 'i' },
7130   { { 34 /* my */ }, 'i' }
7131 };
7132
7133 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
7134   { { STATE_ACC }, 'o' }
7135 };
7136
7137 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
7138   { { 33 /* mx */ }, 'i' },
7139   { { 6 /* art */ }, 'i' }
7140 };
7141
7142 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
7143   { { STATE_ACC }, 'o' }
7144 };
7145
7146 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
7147   { { 33 /* mx */ }, 'i' },
7148   { { 34 /* my */ }, 'i' }
7149 };
7150
7151 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
7152   { { STATE_ACC }, 'o' }
7153 };
7154
7155 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
7156   { { 4 /* ars */ }, 'i' },
7157   { { 6 /* art */ }, 'i' }
7158 };
7159
7160 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
7161   { { STATE_ACC }, 'm' }
7162 };
7163
7164 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
7165   { { 4 /* ars */ }, 'i' },
7166   { { 34 /* my */ }, 'i' }
7167 };
7168
7169 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
7170   { { STATE_ACC }, 'm' }
7171 };
7172
7173 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
7174   { { 33 /* mx */ }, 'i' },
7175   { { 6 /* art */ }, 'i' }
7176 };
7177
7178 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
7179   { { STATE_ACC }, 'm' }
7180 };
7181
7182 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
7183   { { 33 /* mx */ }, 'i' },
7184   { { 34 /* my */ }, 'i' }
7185 };
7186
7187 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
7188   { { STATE_ACC }, 'm' }
7189 };
7190
7191 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
7192   { { 35 /* mw */ }, 'o' },
7193   { { 4 /* ars */ }, 'm' },
7194   { { 33 /* mx */ }, 'i' },
7195   { { 6 /* art */ }, 'i' }
7196 };
7197
7198 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
7199   { { STATE_ACC }, 'm' }
7200 };
7201
7202 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
7203   { { 35 /* mw */ }, 'o' },
7204   { { 4 /* ars */ }, 'm' },
7205   { { 33 /* mx */ }, 'i' },
7206   { { 34 /* my */ }, 'i' }
7207 };
7208
7209 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
7210   { { STATE_ACC }, 'm' }
7211 };
7212
7213 static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
7214   { { 35 /* mw */ }, 'o' },
7215   { { 4 /* ars */ }, 'm' }
7216 };
7217
7218 static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
7219   { { 3 /* arr */ }, 'o' },
7220   { { 4 /* ars */ }, 'i' },
7221   { { 6 /* art */ }, 'i' }
7222 };
7223
7224 static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
7225   { { 6 /* art */ }, 'o' },
7226   { { 36 /* mr0 */ }, 'i' }
7227 };
7228
7229 static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
7230   { { 6 /* art */ }, 'i' },
7231   { { 36 /* mr0 */ }, 'o' }
7232 };
7233
7234 static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
7235   { { 6 /* art */ }, 'm' },
7236   { { 36 /* mr0 */ }, 'm' }
7237 };
7238
7239 static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
7240   { { 6 /* art */ }, 'o' },
7241   { { 37 /* mr1 */ }, 'i' }
7242 };
7243
7244 static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
7245   { { 6 /* art */ }, 'i' },
7246   { { 37 /* mr1 */ }, 'o' }
7247 };
7248
7249 static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
7250   { { 6 /* art */ }, 'm' },
7251   { { 37 /* mr1 */ }, 'm' }
7252 };
7253
7254 static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
7255   { { 6 /* art */ }, 'o' },
7256   { { 38 /* mr2 */ }, 'i' }
7257 };
7258
7259 static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
7260   { { 6 /* art */ }, 'i' },
7261   { { 38 /* mr2 */ }, 'o' }
7262 };
7263
7264 static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
7265   { { 6 /* art */ }, 'm' },
7266   { { 38 /* mr2 */ }, 'm' }
7267 };
7268
7269 static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
7270   { { 6 /* art */ }, 'o' },
7271   { { 39 /* mr3 */ }, 'i' }
7272 };
7273
7274 static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
7275   { { 6 /* art */ }, 'i' },
7276   { { 39 /* mr3 */ }, 'o' }
7277 };
7278
7279 static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
7280   { { 6 /* art */ }, 'm' },
7281   { { 39 /* mr3 */ }, 'm' }
7282 };
7283
7284 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
7285   { { 6 /* art */ }, 'o' }
7286 };
7287
7288 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
7289   { { STATE_ACC }, 'i' }
7290 };
7291
7292 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
7293   { { 6 /* art */ }, 'i' }
7294 };
7295
7296 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
7297   { { STATE_ACC }, 'm' }
7298 };
7299
7300 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
7301   { { 6 /* art */ }, 'm' }
7302 };
7303
7304 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
7305   { { STATE_ACC }, 'm' }
7306 };
7307
7308 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
7309   { { 6 /* art */ }, 'o' }
7310 };
7311
7312 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
7313   { { STATE_ACC }, 'i' }
7314 };
7315
7316 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
7317   { { 6 /* art */ }, 'i' }
7318 };
7319
7320 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
7321   { { STATE_ACC }, 'm' }
7322 };
7323
7324 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
7325   { { 6 /* art */ }, 'm' }
7326 };
7327
7328 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
7329   { { STATE_ACC }, 'm' }
7330 };
7331
7332 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
7333   { { 70 /* s */ }, 'i' }
7334 };
7335
7336 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
7337   { { STATE_PSWOE }, 'o' },
7338   { { STATE_PSCALLINC }, 'o' },
7339   { { STATE_PSOWB }, 'o' },
7340   { { STATE_PSRING }, 'm' },
7341   { { STATE_PSUM }, 'o' },
7342   { { STATE_PSEXCM }, 'm' },
7343   { { STATE_PSINTLEVEL }, 'o' },
7344   { { STATE_EPC1 }, 'i' },
7345   { { STATE_EPC2 }, 'i' },
7346   { { STATE_EPC3 }, 'i' },
7347   { { STATE_EPC4 }, 'i' },
7348   { { STATE_EPC5 }, 'i' },
7349   { { STATE_EPC6 }, 'i' },
7350   { { STATE_EPC7 }, 'i' },
7351   { { STATE_EPS2 }, 'i' },
7352   { { STATE_EPS3 }, 'i' },
7353   { { STATE_EPS4 }, 'i' },
7354   { { STATE_EPS5 }, 'i' },
7355   { { STATE_EPS6 }, 'i' },
7356   { { STATE_EPS7 }, 'i' },
7357   { { STATE_InOCDMode }, 'm' }
7358 };
7359
7360 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
7361   { { 70 /* s */ }, 'i' }
7362 };
7363
7364 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
7365   { { STATE_PSEXCM }, 'i' },
7366   { { STATE_PSRING }, 'i' },
7367   { { STATE_PSINTLEVEL }, 'o' }
7368 };
7369
7370 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
7371   { { 6 /* art */ }, 'o' }
7372 };
7373
7374 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
7375   { { STATE_PSEXCM }, 'i' },
7376   { { STATE_PSRING }, 'i' },
7377   { { STATE_INTERRUPT }, 'i' }
7378 };
7379
7380 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
7381   { { 6 /* art */ }, 'i' }
7382 };
7383
7384 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
7385   { { STATE_PSEXCM }, 'i' },
7386   { { STATE_PSRING }, 'i' },
7387   { { STATE_XTSYNC }, 'o' },
7388   { { STATE_INTERRUPT }, 'm' }
7389 };
7390
7391 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
7392   { { 6 /* art */ }, 'i' }
7393 };
7394
7395 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
7396   { { STATE_PSEXCM }, 'i' },
7397   { { STATE_PSRING }, 'i' },
7398   { { STATE_XTSYNC }, 'o' },
7399   { { STATE_INTERRUPT }, 'm' }
7400 };
7401
7402 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
7403   { { 6 /* art */ }, 'o' }
7404 };
7405
7406 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
7407   { { STATE_PSEXCM }, 'i' },
7408   { { STATE_PSRING }, 'i' },
7409   { { STATE_INTENABLE }, 'i' }
7410 };
7411
7412 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
7413   { { 6 /* art */ }, 'i' }
7414 };
7415
7416 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
7417   { { STATE_PSEXCM }, 'i' },
7418   { { STATE_PSRING }, 'i' },
7419   { { STATE_INTENABLE }, 'o' }
7420 };
7421
7422 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
7423   { { 6 /* art */ }, 'm' }
7424 };
7425
7426 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
7427   { { STATE_PSEXCM }, 'i' },
7428   { { STATE_PSRING }, 'i' },
7429   { { STATE_INTENABLE }, 'm' }
7430 };
7431
7432 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
7433   { { 41 /* imms */ }, 'i' },
7434   { { 40 /* immt */ }, 'i' }
7435 };
7436
7437 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
7438   { { STATE_PSEXCM }, 'i' },
7439   { { STATE_PSINTLEVEL }, 'i' }
7440 };
7441
7442 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
7443   { { 41 /* imms */ }, 'i' }
7444 };
7445
7446 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
7447   { { STATE_PSEXCM }, 'i' },
7448   { { STATE_PSINTLEVEL }, 'i' }
7449 };
7450
7451 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
7452   { { 6 /* art */ }, 'o' }
7453 };
7454
7455 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
7456   { { STATE_PSEXCM }, 'i' },
7457   { { STATE_PSRING }, 'i' },
7458   { { STATE_DBREAKA0 }, 'i' }
7459 };
7460
7461 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
7462   { { 6 /* art */ }, 'i' }
7463 };
7464
7465 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
7466   { { STATE_PSEXCM }, 'i' },
7467   { { STATE_PSRING }, 'i' },
7468   { { STATE_DBREAKA0 }, 'o' },
7469   { { STATE_XTSYNC }, 'o' }
7470 };
7471
7472 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
7473   { { 6 /* art */ }, 'm' }
7474 };
7475
7476 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
7477   { { STATE_PSEXCM }, 'i' },
7478   { { STATE_PSRING }, 'i' },
7479   { { STATE_DBREAKA0 }, 'm' },
7480   { { STATE_XTSYNC }, 'o' }
7481 };
7482
7483 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
7484   { { 6 /* art */ }, 'o' }
7485 };
7486
7487 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
7488   { { STATE_PSEXCM }, 'i' },
7489   { { STATE_PSRING }, 'i' },
7490   { { STATE_DBREAKC0 }, 'i' }
7491 };
7492
7493 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
7494   { { 6 /* art */ }, 'i' }
7495 };
7496
7497 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
7498   { { STATE_PSEXCM }, 'i' },
7499   { { STATE_PSRING }, 'i' },
7500   { { STATE_DBREAKC0 }, 'o' },
7501   { { STATE_XTSYNC }, 'o' }
7502 };
7503
7504 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
7505   { { 6 /* art */ }, 'm' }
7506 };
7507
7508 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
7509   { { STATE_PSEXCM }, 'i' },
7510   { { STATE_PSRING }, 'i' },
7511   { { STATE_DBREAKC0 }, 'm' },
7512   { { STATE_XTSYNC }, 'o' }
7513 };
7514
7515 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
7516   { { 6 /* art */ }, 'o' }
7517 };
7518
7519 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
7520   { { STATE_PSEXCM }, 'i' },
7521   { { STATE_PSRING }, 'i' },
7522   { { STATE_DBREAKA1 }, 'i' }
7523 };
7524
7525 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
7526   { { 6 /* art */ }, 'i' }
7527 };
7528
7529 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
7530   { { STATE_PSEXCM }, 'i' },
7531   { { STATE_PSRING }, 'i' },
7532   { { STATE_DBREAKA1 }, 'o' },
7533   { { STATE_XTSYNC }, 'o' }
7534 };
7535
7536 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
7537   { { 6 /* art */ }, 'm' }
7538 };
7539
7540 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
7541   { { STATE_PSEXCM }, 'i' },
7542   { { STATE_PSRING }, 'i' },
7543   { { STATE_DBREAKA1 }, 'm' },
7544   { { STATE_XTSYNC }, 'o' }
7545 };
7546
7547 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
7548   { { 6 /* art */ }, 'o' }
7549 };
7550
7551 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
7552   { { STATE_PSEXCM }, 'i' },
7553   { { STATE_PSRING }, 'i' },
7554   { { STATE_DBREAKC1 }, 'i' }
7555 };
7556
7557 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
7558   { { 6 /* art */ }, 'i' }
7559 };
7560
7561 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
7562   { { STATE_PSEXCM }, 'i' },
7563   { { STATE_PSRING }, 'i' },
7564   { { STATE_DBREAKC1 }, 'o' },
7565   { { STATE_XTSYNC }, 'o' }
7566 };
7567
7568 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
7569   { { 6 /* art */ }, 'm' }
7570 };
7571
7572 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
7573   { { STATE_PSEXCM }, 'i' },
7574   { { STATE_PSRING }, 'i' },
7575   { { STATE_DBREAKC1 }, 'm' },
7576   { { STATE_XTSYNC }, 'o' }
7577 };
7578
7579 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
7580   { { 6 /* art */ }, 'o' }
7581 };
7582
7583 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
7584   { { STATE_PSEXCM }, 'i' },
7585   { { STATE_PSRING }, 'i' },
7586   { { STATE_IBREAKA0 }, 'i' }
7587 };
7588
7589 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
7590   { { 6 /* art */ }, 'i' }
7591 };
7592
7593 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
7594   { { STATE_PSEXCM }, 'i' },
7595   { { STATE_PSRING }, 'i' },
7596   { { STATE_IBREAKA0 }, 'o' }
7597 };
7598
7599 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
7600   { { 6 /* art */ }, 'm' }
7601 };
7602
7603 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
7604   { { STATE_PSEXCM }, 'i' },
7605   { { STATE_PSRING }, 'i' },
7606   { { STATE_IBREAKA0 }, 'm' }
7607 };
7608
7609 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
7610   { { 6 /* art */ }, 'o' }
7611 };
7612
7613 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
7614   { { STATE_PSEXCM }, 'i' },
7615   { { STATE_PSRING }, 'i' },
7616   { { STATE_IBREAKA1 }, 'i' }
7617 };
7618
7619 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
7620   { { 6 /* art */ }, 'i' }
7621 };
7622
7623 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
7624   { { STATE_PSEXCM }, 'i' },
7625   { { STATE_PSRING }, 'i' },
7626   { { STATE_IBREAKA1 }, 'o' }
7627 };
7628
7629 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
7630   { { 6 /* art */ }, 'm' }
7631 };
7632
7633 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
7634   { { STATE_PSEXCM }, 'i' },
7635   { { STATE_PSRING }, 'i' },
7636   { { STATE_IBREAKA1 }, 'm' }
7637 };
7638
7639 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
7640   { { 6 /* art */ }, 'o' }
7641 };
7642
7643 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
7644   { { STATE_PSEXCM }, 'i' },
7645   { { STATE_PSRING }, 'i' },
7646   { { STATE_IBREAKENABLE }, 'i' }
7647 };
7648
7649 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
7650   { { 6 /* art */ }, 'i' }
7651 };
7652
7653 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
7654   { { STATE_PSEXCM }, 'i' },
7655   { { STATE_PSRING }, 'i' },
7656   { { STATE_IBREAKENABLE }, 'o' }
7657 };
7658
7659 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
7660   { { 6 /* art */ }, 'm' }
7661 };
7662
7663 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
7664   { { STATE_PSEXCM }, 'i' },
7665   { { STATE_PSRING }, 'i' },
7666   { { STATE_IBREAKENABLE }, 'm' }
7667 };
7668
7669 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
7670   { { 6 /* art */ }, 'o' }
7671 };
7672
7673 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
7674   { { STATE_PSEXCM }, 'i' },
7675   { { STATE_PSRING }, 'i' },
7676   { { STATE_DEBUGCAUSE }, 'i' },
7677   { { STATE_DBNUM }, 'i' }
7678 };
7679
7680 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
7681   { { 6 /* art */ }, 'i' }
7682 };
7683
7684 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
7685   { { STATE_PSEXCM }, 'i' },
7686   { { STATE_PSRING }, 'i' },
7687   { { STATE_DEBUGCAUSE }, 'o' },
7688   { { STATE_DBNUM }, 'o' }
7689 };
7690
7691 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
7692   { { 6 /* art */ }, 'm' }
7693 };
7694
7695 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
7696   { { STATE_PSEXCM }, 'i' },
7697   { { STATE_PSRING }, 'i' },
7698   { { STATE_DEBUGCAUSE }, 'm' },
7699   { { STATE_DBNUM }, 'm' }
7700 };
7701
7702 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
7703   { { 6 /* art */ }, 'o' }
7704 };
7705
7706 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
7707   { { STATE_PSEXCM }, 'i' },
7708   { { STATE_PSRING }, 'i' },
7709   { { STATE_ICOUNT }, 'i' }
7710 };
7711
7712 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
7713   { { 6 /* art */ }, 'i' }
7714 };
7715
7716 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
7717   { { STATE_PSEXCM }, 'i' },
7718   { { STATE_PSRING }, 'i' },
7719   { { STATE_XTSYNC }, 'o' },
7720   { { STATE_ICOUNT }, 'o' }
7721 };
7722
7723 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
7724   { { 6 /* art */ }, 'm' }
7725 };
7726
7727 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
7728   { { STATE_PSEXCM }, 'i' },
7729   { { STATE_PSRING }, 'i' },
7730   { { STATE_XTSYNC }, 'o' },
7731   { { STATE_ICOUNT }, 'm' }
7732 };
7733
7734 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
7735   { { 6 /* art */ }, 'o' }
7736 };
7737
7738 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
7739   { { STATE_PSEXCM }, 'i' },
7740   { { STATE_PSRING }, 'i' },
7741   { { STATE_ICOUNTLEVEL }, 'i' }
7742 };
7743
7744 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
7745   { { 6 /* art */ }, 'i' }
7746 };
7747
7748 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
7749   { { STATE_PSEXCM }, 'i' },
7750   { { STATE_PSRING }, 'i' },
7751   { { STATE_ICOUNTLEVEL }, 'o' }
7752 };
7753
7754 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
7755   { { 6 /* art */ }, 'm' }
7756 };
7757
7758 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
7759   { { STATE_PSEXCM }, 'i' },
7760   { { STATE_PSRING }, 'i' },
7761   { { STATE_ICOUNTLEVEL }, 'm' }
7762 };
7763
7764 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
7765   { { 6 /* art */ }, 'o' }
7766 };
7767
7768 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
7769   { { STATE_PSEXCM }, 'i' },
7770   { { STATE_PSRING }, 'i' },
7771   { { STATE_DDR }, 'i' }
7772 };
7773
7774 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
7775   { { 6 /* art */ }, 'i' }
7776 };
7777
7778 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
7779   { { STATE_PSEXCM }, 'i' },
7780   { { STATE_PSRING }, 'i' },
7781   { { STATE_XTSYNC }, 'o' },
7782   { { STATE_DDR }, 'o' }
7783 };
7784
7785 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
7786   { { 6 /* art */ }, 'm' }
7787 };
7788
7789 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
7790   { { STATE_PSEXCM }, 'i' },
7791   { { STATE_PSRING }, 'i' },
7792   { { STATE_XTSYNC }, 'o' },
7793   { { STATE_DDR }, 'm' }
7794 };
7795
7796 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
7797   { { 41 /* imms */ }, 'i' }
7798 };
7799
7800 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
7801   { { STATE_InOCDMode }, 'm' },
7802   { { STATE_EPC6 }, 'i' },
7803   { { STATE_PSWOE }, 'o' },
7804   { { STATE_PSCALLINC }, 'o' },
7805   { { STATE_PSOWB }, 'o' },
7806   { { STATE_PSRING }, 'o' },
7807   { { STATE_PSUM }, 'o' },
7808   { { STATE_PSEXCM }, 'o' },
7809   { { STATE_PSINTLEVEL }, 'o' },
7810   { { STATE_EPS6 }, 'i' }
7811 };
7812
7813 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
7814   { { STATE_InOCDMode }, 'm' }
7815 };
7816
7817 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
7818   { { 6 /* art */ }, 'i' }
7819 };
7820
7821 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
7822   { { STATE_PSEXCM }, 'i' },
7823   { { STATE_PSRING }, 'i' },
7824   { { STATE_XTSYNC }, 'o' }
7825 };
7826
7827 static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
7828   { { 44 /* br */ }, 'o' },
7829   { { 43 /* bs */ }, 'i' },
7830   { { 42 /* bt */ }, 'i' }
7831 };
7832
7833 static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
7834   { { 42 /* bt */ }, 'o' },
7835   { { 49 /* bs4 */ }, 'i' }
7836 };
7837
7838 static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
7839   { { 42 /* bt */ }, 'o' },
7840   { { 52 /* bs8 */ }, 'i' }
7841 };
7842
7843 static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
7844   { { 43 /* bs */ }, 'i' },
7845   { { 28 /* label8 */ }, 'i' }
7846 };
7847
7848 static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
7849   { { 3 /* arr */ }, 'm' },
7850   { { 4 /* ars */ }, 'i' },
7851   { { 42 /* bt */ }, 'i' }
7852 };
7853
7854 static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
7855   { { 6 /* art */ }, 'o' },
7856   { { 57 /* brall */ }, 'i' }
7857 };
7858
7859 static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
7860   { { 6 /* art */ }, 'i' },
7861   { { 57 /* brall */ }, 'o' }
7862 };
7863
7864 static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
7865   { { 6 /* art */ }, 'm' },
7866   { { 57 /* brall */ }, 'm' }
7867 };
7868
7869 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
7870   { { 6 /* art */ }, 'o' }
7871 };
7872
7873 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
7874   { { STATE_PSEXCM }, 'i' },
7875   { { STATE_PSRING }, 'i' },
7876   { { STATE_CCOUNT }, 'i' }
7877 };
7878
7879 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
7880   { { 6 /* art */ }, 'i' }
7881 };
7882
7883 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
7884   { { STATE_PSEXCM }, 'i' },
7885   { { STATE_PSRING }, 'i' },
7886   { { STATE_XTSYNC }, 'o' },
7887   { { STATE_CCOUNT }, 'o' }
7888 };
7889
7890 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
7891   { { 6 /* art */ }, 'm' }
7892 };
7893
7894 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
7895   { { STATE_PSEXCM }, 'i' },
7896   { { STATE_PSRING }, 'i' },
7897   { { STATE_XTSYNC }, 'o' },
7898   { { STATE_CCOUNT }, 'm' }
7899 };
7900
7901 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
7902   { { 6 /* art */ }, 'o' }
7903 };
7904
7905 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
7906   { { STATE_PSEXCM }, 'i' },
7907   { { STATE_PSRING }, 'i' },
7908   { { STATE_CCOMPARE0 }, 'i' }
7909 };
7910
7911 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
7912   { { 6 /* art */ }, 'i' }
7913 };
7914
7915 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
7916   { { STATE_PSEXCM }, 'i' },
7917   { { STATE_PSRING }, 'i' },
7918   { { STATE_CCOMPARE0 }, 'o' },
7919   { { STATE_INTERRUPT }, 'm' }
7920 };
7921
7922 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
7923   { { 6 /* art */ }, 'm' }
7924 };
7925
7926 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
7927   { { STATE_PSEXCM }, 'i' },
7928   { { STATE_PSRING }, 'i' },
7929   { { STATE_CCOMPARE0 }, 'm' },
7930   { { STATE_INTERRUPT }, 'm' }
7931 };
7932
7933 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
7934   { { 6 /* art */ }, 'o' }
7935 };
7936
7937 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
7938   { { STATE_PSEXCM }, 'i' },
7939   { { STATE_PSRING }, 'i' },
7940   { { STATE_CCOMPARE1 }, 'i' }
7941 };
7942
7943 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
7944   { { 6 /* art */ }, 'i' }
7945 };
7946
7947 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
7948   { { STATE_PSEXCM }, 'i' },
7949   { { STATE_PSRING }, 'i' },
7950   { { STATE_CCOMPARE1 }, 'o' },
7951   { { STATE_INTERRUPT }, 'm' }
7952 };
7953
7954 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
7955   { { 6 /* art */ }, 'm' }
7956 };
7957
7958 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
7959   { { STATE_PSEXCM }, 'i' },
7960   { { STATE_PSRING }, 'i' },
7961   { { STATE_CCOMPARE1 }, 'm' },
7962   { { STATE_INTERRUPT }, 'm' }
7963 };
7964
7965 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
7966   { { 6 /* art */ }, 'o' }
7967 };
7968
7969 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
7970   { { STATE_PSEXCM }, 'i' },
7971   { { STATE_PSRING }, 'i' },
7972   { { STATE_CCOMPARE2 }, 'i' }
7973 };
7974
7975 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
7976   { { 6 /* art */ }, 'i' }
7977 };
7978
7979 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
7980   { { STATE_PSEXCM }, 'i' },
7981   { { STATE_PSRING }, 'i' },
7982   { { STATE_CCOMPARE2 }, 'o' },
7983   { { STATE_INTERRUPT }, 'm' }
7984 };
7985
7986 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
7987   { { 6 /* art */ }, 'm' }
7988 };
7989
7990 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
7991   { { STATE_PSEXCM }, 'i' },
7992   { { STATE_PSRING }, 'i' },
7993   { { STATE_CCOMPARE2 }, 'm' },
7994   { { STATE_INTERRUPT }, 'm' }
7995 };
7996
7997 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
7998   { { 4 /* ars */ }, 'i' },
7999   { { 21 /* uimm8x4 */ }, 'i' }
8000 };
8001
8002 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
8003   { { 4 /* ars */ }, 'i' },
8004   { { 22 /* uimm4x16 */ }, 'i' }
8005 };
8006
8007 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
8008   { { STATE_PSEXCM }, 'i' },
8009   { { STATE_PSRING }, 'i' }
8010 };
8011
8012 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
8013   { { 4 /* ars */ }, 'i' },
8014   { { 21 /* uimm8x4 */ }, 'i' }
8015 };
8016
8017 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
8018   { { STATE_PSEXCM }, 'i' },
8019   { { STATE_PSRING }, 'i' }
8020 };
8021
8022 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
8023   { { 6 /* art */ }, 'o' },
8024   { { 4 /* ars */ }, 'i' }
8025 };
8026
8027 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
8028   { { STATE_PSEXCM }, 'i' },
8029   { { STATE_PSRING }, 'i' }
8030 };
8031
8032 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
8033   { { 6 /* art */ }, 'i' },
8034   { { 4 /* ars */ }, 'i' }
8035 };
8036
8037 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
8038   { { STATE_PSEXCM }, 'i' },
8039   { { STATE_PSRING }, 'i' }
8040 };
8041
8042 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
8043   { { 4 /* ars */ }, 'i' },
8044   { { 21 /* uimm8x4 */ }, 'i' }
8045 };
8046
8047 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
8048   { { 4 /* ars */ }, 'i' },
8049   { { 22 /* uimm4x16 */ }, 'i' }
8050 };
8051
8052 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
8053   { { STATE_PSEXCM }, 'i' },
8054   { { STATE_PSRING }, 'i' }
8055 };
8056
8057 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
8058   { { 4 /* ars */ }, 'i' },
8059   { { 21 /* uimm8x4 */ }, 'i' }
8060 };
8061
8062 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
8063   { { STATE_PSEXCM }, 'i' },
8064   { { STATE_PSRING }, 'i' }
8065 };
8066
8067 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
8068   { { 4 /* ars */ }, 'i' },
8069   { { 21 /* uimm8x4 */ }, 'i' }
8070 };
8071
8072 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
8073   { { 4 /* ars */ }, 'i' },
8074   { { 22 /* uimm4x16 */ }, 'i' }
8075 };
8076
8077 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
8078   { { STATE_PSEXCM }, 'i' },
8079   { { STATE_PSRING }, 'i' }
8080 };
8081
8082 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
8083   { { 6 /* art */ }, 'i' },
8084   { { 4 /* ars */ }, 'i' }
8085 };
8086
8087 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
8088   { { STATE_PSEXCM }, 'i' },
8089   { { STATE_PSRING }, 'i' }
8090 };
8091
8092 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
8093   { { 6 /* art */ }, 'o' },
8094   { { 4 /* ars */ }, 'i' }
8095 };
8096
8097 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
8098   { { STATE_PSEXCM }, 'i' },
8099   { { STATE_PSRING }, 'i' }
8100 };
8101
8102 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
8103   { { 6 /* art */ }, 'i' }
8104 };
8105
8106 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
8107   { { STATE_PSEXCM }, 'i' },
8108   { { STATE_PSRING }, 'i' },
8109   { { STATE_PTBASE }, 'o' },
8110   { { STATE_XTSYNC }, 'o' }
8111 };
8112
8113 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
8114   { { 6 /* art */ }, 'o' }
8115 };
8116
8117 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
8118   { { STATE_PSEXCM }, 'i' },
8119   { { STATE_PSRING }, 'i' },
8120   { { STATE_PTBASE }, 'i' },
8121   { { STATE_EXCVADDR }, 'i' }
8122 };
8123
8124 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
8125   { { 6 /* art */ }, 'm' }
8126 };
8127
8128 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
8129   { { STATE_PSEXCM }, 'i' },
8130   { { STATE_PSRING }, 'i' },
8131   { { STATE_PTBASE }, 'm' },
8132   { { STATE_EXCVADDR }, 'i' },
8133   { { STATE_XTSYNC }, 'o' }
8134 };
8135
8136 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
8137   { { 6 /* art */ }, 'o' }
8138 };
8139
8140 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
8141   { { STATE_PSEXCM }, 'i' },
8142   { { STATE_PSRING }, 'i' },
8143   { { STATE_ASID3 }, 'i' },
8144   { { STATE_ASID2 }, 'i' },
8145   { { STATE_ASID1 }, 'i' }
8146 };
8147
8148 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
8149   { { 6 /* art */ }, 'i' }
8150 };
8151
8152 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
8153   { { STATE_XTSYNC }, 'o' },
8154   { { STATE_PSEXCM }, 'i' },
8155   { { STATE_PSRING }, 'i' },
8156   { { STATE_ASID3 }, 'o' },
8157   { { STATE_ASID2 }, 'o' },
8158   { { STATE_ASID1 }, 'o' }
8159 };
8160
8161 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
8162   { { 6 /* art */ }, 'm' }
8163 };
8164
8165 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
8166   { { STATE_XTSYNC }, 'o' },
8167   { { STATE_PSEXCM }, 'i' },
8168   { { STATE_PSRING }, 'i' },
8169   { { STATE_ASID3 }, 'm' },
8170   { { STATE_ASID2 }, 'm' },
8171   { { STATE_ASID1 }, 'm' }
8172 };
8173
8174 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
8175   { { 6 /* art */ }, 'o' }
8176 };
8177
8178 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
8179   { { STATE_PSEXCM }, 'i' },
8180   { { STATE_PSRING }, 'i' },
8181   { { STATE_INSTPGSZID4 }, 'i' }
8182 };
8183
8184 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
8185   { { 6 /* art */ }, 'i' }
8186 };
8187
8188 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
8189   { { STATE_XTSYNC }, 'o' },
8190   { { STATE_PSEXCM }, 'i' },
8191   { { STATE_PSRING }, 'i' },
8192   { { STATE_INSTPGSZID4 }, 'o' }
8193 };
8194
8195 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
8196   { { 6 /* art */ }, 'm' }
8197 };
8198
8199 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
8200   { { STATE_XTSYNC }, 'o' },
8201   { { STATE_PSEXCM }, 'i' },
8202   { { STATE_PSRING }, 'i' },
8203   { { STATE_INSTPGSZID4 }, 'm' }
8204 };
8205
8206 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
8207   { { 6 /* art */ }, 'o' }
8208 };
8209
8210 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
8211   { { STATE_PSEXCM }, 'i' },
8212   { { STATE_PSRING }, 'i' },
8213   { { STATE_DATAPGSZID4 }, 'i' }
8214 };
8215
8216 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
8217   { { 6 /* art */ }, 'i' }
8218 };
8219
8220 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
8221   { { STATE_XTSYNC }, 'o' },
8222   { { STATE_PSEXCM }, 'i' },
8223   { { STATE_PSRING }, 'i' },
8224   { { STATE_DATAPGSZID4 }, 'o' }
8225 };
8226
8227 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
8228   { { 6 /* art */ }, 'm' }
8229 };
8230
8231 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
8232   { { STATE_XTSYNC }, 'o' },
8233   { { STATE_PSEXCM }, 'i' },
8234   { { STATE_PSRING }, 'i' },
8235   { { STATE_DATAPGSZID4 }, 'm' }
8236 };
8237
8238 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
8239   { { 4 /* ars */ }, 'i' }
8240 };
8241
8242 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
8243   { { STATE_PSEXCM }, 'i' },
8244   { { STATE_PSRING }, 'i' },
8245   { { STATE_XTSYNC }, 'o' }
8246 };
8247
8248 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
8249   { { 6 /* art */ }, 'o' },
8250   { { 4 /* ars */ }, 'i' }
8251 };
8252
8253 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
8254   { { STATE_PSEXCM }, 'i' },
8255   { { STATE_PSRING }, 'i' }
8256 };
8257
8258 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
8259   { { 6 /* art */ }, 'i' },
8260   { { 4 /* ars */ }, 'i' }
8261 };
8262
8263 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
8264   { { STATE_PSEXCM }, 'i' },
8265   { { STATE_PSRING }, 'i' },
8266   { { STATE_XTSYNC }, 'o' }
8267 };
8268
8269 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
8270   { { 4 /* ars */ }, 'i' }
8271 };
8272
8273 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
8274   { { STATE_PSEXCM }, 'i' },
8275   { { STATE_PSRING }, 'i' }
8276 };
8277
8278 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
8279   { { 6 /* art */ }, 'o' },
8280   { { 4 /* ars */ }, 'i' }
8281 };
8282
8283 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
8284   { { STATE_PSEXCM }, 'i' },
8285   { { STATE_PSRING }, 'i' }
8286 };
8287
8288 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
8289   { { 6 /* art */ }, 'i' },
8290   { { 4 /* ars */ }, 'i' }
8291 };
8292
8293 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
8294   { { STATE_PSEXCM }, 'i' },
8295   { { STATE_PSRING }, 'i' }
8296 };
8297
8298 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
8299   { { STATE_PTBASE }, 'i' },
8300   { { STATE_EXCVADDR }, 'i' }
8301 };
8302
8303 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
8304   { { STATE_EXCVADDR }, 'i' }
8305 };
8306
8307 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
8308   { { STATE_EXCVADDR }, 'i' }
8309 };
8310
8311 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
8312   { { 6 /* art */ }, 'o' }
8313 };
8314
8315 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
8316   { { STATE_PSEXCM }, 'i' },
8317   { { STATE_PSRING }, 'i' },
8318   { { STATE_CPENABLE }, 'i' }
8319 };
8320
8321 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
8322   { { 6 /* art */ }, 'i' }
8323 };
8324
8325 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
8326   { { STATE_PSEXCM }, 'i' },
8327   { { STATE_PSRING }, 'i' },
8328   { { STATE_CPENABLE }, 'o' }
8329 };
8330
8331 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
8332   { { 6 /* art */ }, 'm' }
8333 };
8334
8335 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
8336   { { STATE_PSEXCM }, 'i' },
8337   { { STATE_PSRING }, 'i' },
8338   { { STATE_CPENABLE }, 'm' }
8339 };
8340
8341 static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
8342   { { 3 /* arr */ }, 'o' },
8343   { { 4 /* ars */ }, 'i' },
8344   { { 58 /* tp7 */ }, 'i' }
8345 };
8346
8347 static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
8348   { { 3 /* arr */ }, 'o' },
8349   { { 4 /* ars */ }, 'i' },
8350   { { 6 /* art */ }, 'i' }
8351 };
8352
8353 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
8354   { { 6 /* art */ }, 'o' },
8355   { { 4 /* ars */ }, 'i' }
8356 };
8357
8358 static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
8359   { { 3 /* arr */ }, 'o' },
8360   { { 4 /* ars */ }, 'i' },
8361   { { 58 /* tp7 */ }, 'i' }
8362 };
8363
8364 static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
8365   { { 6 /* art */ }, 'o' },
8366   { { 4 /* ars */ }, 'i' },
8367   { { 21 /* uimm8x4 */ }, 'i' }
8368 };
8369
8370 static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
8371   { { 6 /* art */ }, 'i' },
8372   { { 4 /* ars */ }, 'i' },
8373   { { 21 /* uimm8x4 */ }, 'i' }
8374 };
8375
8376 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
8377   { { 6 /* art */ }, 'm' },
8378   { { 4 /* ars */ }, 'i' },
8379   { { 21 /* uimm8x4 */ }, 'i' }
8380 };
8381
8382 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
8383   { { STATE_SCOMPARE1 }, 'i' },
8384   { { STATE_SCOMPARE1 }, 'i' }
8385 };
8386
8387 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
8388   { { 6 /* art */ }, 'o' }
8389 };
8390
8391 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
8392   { { STATE_SCOMPARE1 }, 'i' }
8393 };
8394
8395 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
8396   { { 6 /* art */ }, 'i' }
8397 };
8398
8399 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
8400   { { STATE_SCOMPARE1 }, 'o' }
8401 };
8402
8403 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
8404   { { 6 /* art */ }, 'm' }
8405 };
8406
8407 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
8408   { { STATE_SCOMPARE1 }, 'm' }
8409 };
8410
8411 static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
8412   { { 3 /* arr */ }, 'o' },
8413   { { 4 /* ars */ }, 'i' },
8414   { { 6 /* art */ }, 'i' }
8415 };
8416
8417 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
8418   { { 3 /* arr */ }, 'o' },
8419   { { 4 /* ars */ }, 'i' },
8420   { { 6 /* art */ }, 'i' }
8421 };
8422
8423 static xtensa_arg_internal Iclass_rur_fcr_args[] = {
8424   { { 3 /* arr */ }, 'o' }
8425 };
8426
8427 static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = {
8428   { { STATE_RoundMode }, 'i' },
8429   { { STATE_InvalidEnable }, 'i' },
8430   { { STATE_DivZeroEnable }, 'i' },
8431   { { STATE_OverflowEnable }, 'i' },
8432   { { STATE_UnderflowEnable }, 'i' },
8433   { { STATE_InexactEnable }, 'i' },
8434   { { STATE_FPreserved20 }, 'i' },
8435   { { STATE_FPreserved5 }, 'i' },
8436   { { STATE_CPENABLE }, 'i' }
8437 };
8438
8439 static xtensa_arg_internal Iclass_wur_fcr_args[] = {
8440   { { 6 /* art */ }, 'i' }
8441 };
8442
8443 static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = {
8444   { { STATE_RoundMode }, 'o' },
8445   { { STATE_InvalidEnable }, 'o' },
8446   { { STATE_DivZeroEnable }, 'o' },
8447   { { STATE_OverflowEnable }, 'o' },
8448   { { STATE_UnderflowEnable }, 'o' },
8449   { { STATE_InexactEnable }, 'o' },
8450   { { STATE_FPreserved20 }, 'o' },
8451   { { STATE_FPreserved5 }, 'o' },
8452   { { STATE_CPENABLE }, 'i' }
8453 };
8454
8455 static xtensa_arg_internal Iclass_rur_fsr_args[] = {
8456   { { 3 /* arr */ }, 'o' }
8457 };
8458
8459 static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = {
8460   { { STATE_InvalidFlag }, 'i' },
8461   { { STATE_DivZeroFlag }, 'i' },
8462   { { STATE_OverflowFlag }, 'i' },
8463   { { STATE_UnderflowFlag }, 'i' },
8464   { { STATE_InexactFlag }, 'i' },
8465   { { STATE_FPreserved20a }, 'i' },
8466   { { STATE_FPreserved7 }, 'i' },
8467   { { STATE_CPENABLE }, 'i' }
8468 };
8469
8470 static xtensa_arg_internal Iclass_wur_fsr_args[] = {
8471   { { 6 /* art */ }, 'i' }
8472 };
8473
8474 static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = {
8475   { { STATE_InvalidFlag }, 'o' },
8476   { { STATE_DivZeroFlag }, 'o' },
8477   { { STATE_OverflowFlag }, 'o' },
8478   { { STATE_UnderflowFlag }, 'o' },
8479   { { STATE_InexactFlag }, 'o' },
8480   { { STATE_FPreserved20a }, 'o' },
8481   { { STATE_FPreserved7 }, 'o' },
8482   { { STATE_CPENABLE }, 'i' }
8483 };
8484
8485 static xtensa_arg_internal Iclass_fp_args[] = {
8486   { { 62 /* frr */ }, 'o' },
8487   { { 63 /* frs */ }, 'i' },
8488   { { 64 /* frt */ }, 'i' }
8489 };
8490
8491 static xtensa_arg_internal Iclass_fp_stateArgs[] = {
8492   { { STATE_RoundMode }, 'i' },
8493   { { STATE_CPENABLE }, 'i' }
8494 };
8495
8496 static xtensa_arg_internal Iclass_fp_mac_args[] = {
8497   { { 62 /* frr */ }, 'm' },
8498   { { 63 /* frs */ }, 'i' },
8499   { { 64 /* frt */ }, 'i' }
8500 };
8501
8502 static xtensa_arg_internal Iclass_fp_mac_stateArgs[] = {
8503   { { STATE_RoundMode }, 'i' },
8504   { { STATE_CPENABLE }, 'i' }
8505 };
8506
8507 static xtensa_arg_internal Iclass_fp_cmov_args[] = {
8508   { { 62 /* frr */ }, 'm' },
8509   { { 63 /* frs */ }, 'i' },
8510   { { 42 /* bt */ }, 'i' }
8511 };
8512
8513 static xtensa_arg_internal Iclass_fp_cmov_stateArgs[] = {
8514   { { STATE_CPENABLE }, 'i' }
8515 };
8516
8517 static xtensa_arg_internal Iclass_fp_mov_args[] = {
8518   { { 62 /* frr */ }, 'm' },
8519   { { 63 /* frs */ }, 'i' },
8520   { { 6 /* art */ }, 'i' }
8521 };
8522
8523 static xtensa_arg_internal Iclass_fp_mov_stateArgs[] = {
8524   { { STATE_CPENABLE }, 'i' }
8525 };
8526
8527 static xtensa_arg_internal Iclass_fp_mov2_args[] = {
8528   { { 62 /* frr */ }, 'o' },
8529   { { 63 /* frs */ }, 'i' }
8530 };
8531
8532 static xtensa_arg_internal Iclass_fp_mov2_stateArgs[] = {
8533   { { STATE_CPENABLE }, 'i' }
8534 };
8535
8536 static xtensa_arg_internal Iclass_fp_cmp_args[] = {
8537   { { 44 /* br */ }, 'o' },
8538   { { 63 /* frs */ }, 'i' },
8539   { { 64 /* frt */ }, 'i' }
8540 };
8541
8542 static xtensa_arg_internal Iclass_fp_cmp_stateArgs[] = {
8543   { { STATE_CPENABLE }, 'i' }
8544 };
8545
8546 static xtensa_arg_internal Iclass_fp_float_args[] = {
8547   { { 62 /* frr */ }, 'o' },
8548   { { 4 /* ars */ }, 'i' },
8549   { { 65 /* t */ }, 'i' }
8550 };
8551
8552 static xtensa_arg_internal Iclass_fp_float_stateArgs[] = {
8553   { { STATE_RoundMode }, 'i' },
8554   { { STATE_CPENABLE }, 'i' }
8555 };
8556
8557 static xtensa_arg_internal Iclass_fp_int_args[] = {
8558   { { 3 /* arr */ }, 'o' },
8559   { { 63 /* frs */ }, 'i' },
8560   { { 65 /* t */ }, 'i' }
8561 };
8562
8563 static xtensa_arg_internal Iclass_fp_int_stateArgs[] = {
8564   { { STATE_CPENABLE }, 'i' }
8565 };
8566
8567 static xtensa_arg_internal Iclass_fp_rfr_args[] = {
8568   { { 3 /* arr */ }, 'o' },
8569   { { 63 /* frs */ }, 'i' }
8570 };
8571
8572 static xtensa_arg_internal Iclass_fp_rfr_stateArgs[] = {
8573   { { STATE_CPENABLE }, 'i' }
8574 };
8575
8576 static xtensa_arg_internal Iclass_fp_wfr_args[] = {
8577   { { 62 /* frr */ }, 'o' },
8578   { { 4 /* ars */ }, 'i' }
8579 };
8580
8581 static xtensa_arg_internal Iclass_fp_wfr_stateArgs[] = {
8582   { { STATE_CPENABLE }, 'i' }
8583 };
8584
8585 static xtensa_arg_internal Iclass_fp_lsi_args[] = {
8586   { { 64 /* frt */ }, 'o' },
8587   { { 4 /* ars */ }, 'i' },
8588   { { 61 /* cimm8x4 */ }, 'i' }
8589 };
8590
8591 static xtensa_arg_internal Iclass_fp_lsi_stateArgs[] = {
8592   { { STATE_CPENABLE }, 'i' }
8593 };
8594
8595 static xtensa_arg_internal Iclass_fp_lsiu_args[] = {
8596   { { 64 /* frt */ }, 'o' },
8597   { { 4 /* ars */ }, 'm' },
8598   { { 61 /* cimm8x4 */ }, 'i' }
8599 };
8600
8601 static xtensa_arg_internal Iclass_fp_lsiu_stateArgs[] = {
8602   { { STATE_CPENABLE }, 'i' }
8603 };
8604
8605 static xtensa_arg_internal Iclass_fp_lsx_args[] = {
8606   { { 62 /* frr */ }, 'o' },
8607   { { 4 /* ars */ }, 'i' },
8608   { { 6 /* art */ }, 'i' }
8609 };
8610
8611 static xtensa_arg_internal Iclass_fp_lsx_stateArgs[] = {
8612   { { STATE_CPENABLE }, 'i' }
8613 };
8614
8615 static xtensa_arg_internal Iclass_fp_lsxu_args[] = {
8616   { { 62 /* frr */ }, 'o' },
8617   { { 4 /* ars */ }, 'm' },
8618   { { 6 /* art */ }, 'i' }
8619 };
8620
8621 static xtensa_arg_internal Iclass_fp_lsxu_stateArgs[] = {
8622   { { STATE_CPENABLE }, 'i' }
8623 };
8624
8625 static xtensa_arg_internal Iclass_fp_ssi_args[] = {
8626   { { 64 /* frt */ }, 'i' },
8627   { { 4 /* ars */ }, 'i' },
8628   { { 61 /* cimm8x4 */ }, 'i' }
8629 };
8630
8631 static xtensa_arg_internal Iclass_fp_ssi_stateArgs[] = {
8632   { { STATE_CPENABLE }, 'i' }
8633 };
8634
8635 static xtensa_arg_internal Iclass_fp_ssiu_args[] = {
8636   { { 64 /* frt */ }, 'i' },
8637   { { 4 /* ars */ }, 'm' },
8638   { { 61 /* cimm8x4 */ }, 'i' }
8639 };
8640
8641 static xtensa_arg_internal Iclass_fp_ssiu_stateArgs[] = {
8642   { { STATE_CPENABLE }, 'i' }
8643 };
8644
8645 static xtensa_arg_internal Iclass_fp_ssx_args[] = {
8646   { { 62 /* frr */ }, 'i' },
8647   { { 4 /* ars */ }, 'i' },
8648   { { 6 /* art */ }, 'i' }
8649 };
8650
8651 static xtensa_arg_internal Iclass_fp_ssx_stateArgs[] = {
8652   { { STATE_CPENABLE }, 'i' }
8653 };
8654
8655 static xtensa_arg_internal Iclass_fp_ssxu_args[] = {
8656   { { 62 /* frr */ }, 'i' },
8657   { { 4 /* ars */ }, 'm' },
8658   { { 6 /* art */ }, 'i' }
8659 };
8660
8661 static xtensa_arg_internal Iclass_fp_ssxu_stateArgs[] = {
8662   { { STATE_CPENABLE }, 'i' }
8663 };
8664
8665 static xtensa_arg_internal Iclass_xt_iclass_wb18_0_args[] = {
8666   { { 4 /* ars */ }, 'i' },
8667   { { 60 /* xt_wbr18_label */ }, 'i' }
8668 };
8669
8670 static xtensa_arg_internal Iclass_xt_iclass_wb18_1_args[] = {
8671   { { 4 /* ars */ }, 'i' },
8672   { { 17 /* b4const */ }, 'i' },
8673   { { 60 /* xt_wbr18_label */ }, 'i' }
8674 };
8675
8676 static xtensa_arg_internal Iclass_xt_iclass_wb18_2_args[] = {
8677   { { 4 /* ars */ }, 'i' },
8678   { { 18 /* b4constu */ }, 'i' },
8679   { { 60 /* xt_wbr18_label */ }, 'i' }
8680 };
8681
8682 static xtensa_arg_internal Iclass_xt_iclass_wb18_3_args[] = {
8683   { { 4 /* ars */ }, 'i' },
8684   { { 67 /* bbi */ }, 'i' },
8685   { { 60 /* xt_wbr18_label */ }, 'i' }
8686 };
8687
8688 static xtensa_arg_internal Iclass_xt_iclass_wb18_4_args[] = {
8689   { { 4 /* ars */ }, 'i' },
8690   { { 6 /* art */ }, 'i' },
8691   { { 60 /* xt_wbr18_label */ }, 'i' }
8692 };
8693
8694 static xtensa_iclass_internal iclasses[] = {
8695   { 0, 0 /* xt_iclass_excw */,
8696     0, 0, 0, 0 },
8697   { 0, 0 /* xt_iclass_rfe */,
8698     3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
8699   { 0, 0 /* xt_iclass_rfde */,
8700     3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
8701   { 0, 0 /* xt_iclass_syscall */,
8702     0, 0, 0, 0 },
8703   { 0, 0 /* xt_iclass_simcall */,
8704     0, 0, 0, 0 },
8705   { 2, Iclass_xt_iclass_call12_args,
8706     1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
8707   { 2, Iclass_xt_iclass_call8_args,
8708     1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
8709   { 2, Iclass_xt_iclass_call4_args,
8710     1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
8711   { 2, Iclass_xt_iclass_callx12_args,
8712     1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
8713   { 2, Iclass_xt_iclass_callx8_args,
8714     1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
8715   { 2, Iclass_xt_iclass_callx4_args,
8716     1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
8717   { 3, Iclass_xt_iclass_entry_args,
8718     5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
8719   { 2, Iclass_xt_iclass_movsp_args,
8720     2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
8721   { 1, Iclass_xt_iclass_rotw_args,
8722     3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
8723   { 1, Iclass_xt_iclass_retw_args,
8724     4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
8725   { 0, 0 /* xt_iclass_rfwou */,
8726     6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
8727   { 3, Iclass_xt_iclass_l32e_args,
8728     2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
8729   { 3, Iclass_xt_iclass_s32e_args,
8730     2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
8731   { 1, Iclass_xt_iclass_rsr_windowbase_args,
8732     3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
8733   { 1, Iclass_xt_iclass_wsr_windowbase_args,
8734     3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
8735   { 1, Iclass_xt_iclass_xsr_windowbase_args,
8736     3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
8737   { 1, Iclass_xt_iclass_rsr_windowstart_args,
8738     3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
8739   { 1, Iclass_xt_iclass_wsr_windowstart_args,
8740     3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
8741   { 1, Iclass_xt_iclass_xsr_windowstart_args,
8742     3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
8743   { 3, Iclass_xt_iclass_add_n_args,
8744     0, 0, 0, 0 },
8745   { 3, Iclass_xt_iclass_addi_n_args,
8746     0, 0, 0, 0 },
8747   { 2, Iclass_xt_iclass_bz6_args,
8748     0, 0, 0, 0 },
8749   { 0, 0 /* xt_iclass_ill_n */,
8750     0, 0, 0, 0 },
8751   { 3, Iclass_xt_iclass_loadi4_args,
8752     0, 0, 0, 0 },
8753   { 2, Iclass_xt_iclass_mov_n_args,
8754     0, 0, 0, 0 },
8755   { 2, Iclass_xt_iclass_movi_n_args,
8756     0, 0, 0, 0 },
8757   { 0, 0 /* xt_iclass_nopn */,
8758     0, 0, 0, 0 },
8759   { 1, Iclass_xt_iclass_retn_args,
8760     0, 0, 0, 0 },
8761   { 3, Iclass_xt_iclass_storei4_args,
8762     0, 0, 0, 0 },
8763   { 1, Iclass_rur_threadptr_args,
8764     1, Iclass_rur_threadptr_stateArgs, 0, 0 },
8765   { 1, Iclass_wur_threadptr_args,
8766     1, Iclass_wur_threadptr_stateArgs, 0, 0 },
8767   { 3, Iclass_xt_iclass_addi_args,
8768     0, 0, 0, 0 },
8769   { 3, Iclass_xt_iclass_addmi_args,
8770     0, 0, 0, 0 },
8771   { 3, Iclass_xt_iclass_addsub_args,
8772     0, 0, 0, 0 },
8773   { 3, Iclass_xt_iclass_bit_args,
8774     0, 0, 0, 0 },
8775   { 3, Iclass_xt_iclass_bsi8_args,
8776     0, 0, 0, 0 },
8777   { 3, Iclass_xt_iclass_bsi8b_args,
8778     0, 0, 0, 0 },
8779   { 3, Iclass_xt_iclass_bsi8u_args,
8780     0, 0, 0, 0 },
8781   { 3, Iclass_xt_iclass_bst8_args,
8782     0, 0, 0, 0 },
8783   { 2, Iclass_xt_iclass_bsz12_args,
8784     0, 0, 0, 0 },
8785   { 2, Iclass_xt_iclass_call0_args,
8786     0, 0, 0, 0 },
8787   { 2, Iclass_xt_iclass_callx0_args,
8788     0, 0, 0, 0 },
8789   { 4, Iclass_xt_iclass_exti_args,
8790     0, 0, 0, 0 },
8791   { 0, 0 /* xt_iclass_ill */,
8792     0, 0, 0, 0 },
8793   { 1, Iclass_xt_iclass_jump_args,
8794     0, 0, 0, 0 },
8795   { 1, Iclass_xt_iclass_jumpx_args,
8796     0, 0, 0, 0 },
8797   { 3, Iclass_xt_iclass_l16ui_args,
8798     0, 0, 0, 0 },
8799   { 3, Iclass_xt_iclass_l16si_args,
8800     0, 0, 0, 0 },
8801   { 3, Iclass_xt_iclass_l32i_args,
8802     0, 0, 0, 0 },
8803   { 2, Iclass_xt_iclass_l32r_args,
8804     2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
8805   { 3, Iclass_xt_iclass_l8i_args,
8806     0, 0, 0, 0 },
8807   { 2, Iclass_xt_iclass_loop_args,
8808     3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
8809   { 2, Iclass_xt_iclass_loopz_args,
8810     3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
8811   { 2, Iclass_xt_iclass_movi_args,
8812     0, 0, 0, 0 },
8813   { 3, Iclass_xt_iclass_movz_args,
8814     0, 0, 0, 0 },
8815   { 2, Iclass_xt_iclass_neg_args,
8816     0, 0, 0, 0 },
8817   { 0, 0 /* xt_iclass_nop */,
8818     0, 0, 0, 0 },
8819   { 1, Iclass_xt_iclass_return_args,
8820     0, 0, 0, 0 },
8821   { 3, Iclass_xt_iclass_s16i_args,
8822     0, 0, 0, 0 },
8823   { 3, Iclass_xt_iclass_s32i_args,
8824     0, 0, 0, 0 },
8825   { 3, Iclass_xt_iclass_s8i_args,
8826     0, 0, 0, 0 },
8827   { 1, Iclass_xt_iclass_sar_args,
8828     1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
8829   { 1, Iclass_xt_iclass_sari_args,
8830     1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
8831   { 2, Iclass_xt_iclass_shifts_args,
8832     1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
8833   { 3, Iclass_xt_iclass_shiftst_args,
8834     1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
8835   { 2, Iclass_xt_iclass_shiftt_args,
8836     1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
8837   { 3, Iclass_xt_iclass_slli_args,
8838     0, 0, 0, 0 },
8839   { 3, Iclass_xt_iclass_srai_args,
8840     0, 0, 0, 0 },
8841   { 3, Iclass_xt_iclass_srli_args,
8842     0, 0, 0, 0 },
8843   { 0, 0 /* xt_iclass_memw */,
8844     0, 0, 0, 0 },
8845   { 0, 0 /* xt_iclass_extw */,
8846     0, 0, 0, 0 },
8847   { 0, 0 /* xt_iclass_isync */,
8848     0, 0, 0, 0 },
8849   { 0, 0 /* xt_iclass_sync */,
8850     1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
8851   { 2, Iclass_xt_iclass_rsil_args,
8852     7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
8853   { 1, Iclass_xt_iclass_rsr_lend_args,
8854     1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
8855   { 1, Iclass_xt_iclass_wsr_lend_args,
8856     1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
8857   { 1, Iclass_xt_iclass_xsr_lend_args,
8858     1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
8859   { 1, Iclass_xt_iclass_rsr_lcount_args,
8860     1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
8861   { 1, Iclass_xt_iclass_wsr_lcount_args,
8862     2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
8863   { 1, Iclass_xt_iclass_xsr_lcount_args,
8864     2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
8865   { 1, Iclass_xt_iclass_rsr_lbeg_args,
8866     1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
8867   { 1, Iclass_xt_iclass_wsr_lbeg_args,
8868     1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
8869   { 1, Iclass_xt_iclass_xsr_lbeg_args,
8870     1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
8871   { 1, Iclass_xt_iclass_rsr_sar_args,
8872     1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
8873   { 1, Iclass_xt_iclass_wsr_sar_args,
8874     2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
8875   { 1, Iclass_xt_iclass_xsr_sar_args,
8876     1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
8877   { 1, Iclass_xt_iclass_rsr_litbase_args,
8878     2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
8879   { 1, Iclass_xt_iclass_wsr_litbase_args,
8880     2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
8881   { 1, Iclass_xt_iclass_xsr_litbase_args,
8882     2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
8883   { 1, Iclass_xt_iclass_rsr_176_args,
8884     2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
8885   { 1, Iclass_xt_iclass_rsr_208_args,
8886     2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
8887   { 1, Iclass_xt_iclass_rsr_ps_args,
8888     7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
8889   { 1, Iclass_xt_iclass_wsr_ps_args,
8890     7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
8891   { 1, Iclass_xt_iclass_xsr_ps_args,
8892     7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
8893   { 1, Iclass_xt_iclass_rsr_epc1_args,
8894     3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
8895   { 1, Iclass_xt_iclass_wsr_epc1_args,
8896     3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
8897   { 1, Iclass_xt_iclass_xsr_epc1_args,
8898     3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
8899   { 1, Iclass_xt_iclass_rsr_excsave1_args,
8900     3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
8901   { 1, Iclass_xt_iclass_wsr_excsave1_args,
8902     3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
8903   { 1, Iclass_xt_iclass_xsr_excsave1_args,
8904     3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
8905   { 1, Iclass_xt_iclass_rsr_epc2_args,
8906     3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
8907   { 1, Iclass_xt_iclass_wsr_epc2_args,
8908     3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
8909   { 1, Iclass_xt_iclass_xsr_epc2_args,
8910     3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
8911   { 1, Iclass_xt_iclass_rsr_excsave2_args,
8912     3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
8913   { 1, Iclass_xt_iclass_wsr_excsave2_args,
8914     3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
8915   { 1, Iclass_xt_iclass_xsr_excsave2_args,
8916     3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
8917   { 1, Iclass_xt_iclass_rsr_epc3_args,
8918     3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
8919   { 1, Iclass_xt_iclass_wsr_epc3_args,
8920     3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
8921   { 1, Iclass_xt_iclass_xsr_epc3_args,
8922     3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
8923   { 1, Iclass_xt_iclass_rsr_excsave3_args,
8924     3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
8925   { 1, Iclass_xt_iclass_wsr_excsave3_args,
8926     3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
8927   { 1, Iclass_xt_iclass_xsr_excsave3_args,
8928     3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
8929   { 1, Iclass_xt_iclass_rsr_epc4_args,
8930     3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
8931   { 1, Iclass_xt_iclass_wsr_epc4_args,
8932     3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
8933   { 1, Iclass_xt_iclass_xsr_epc4_args,
8934     3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
8935   { 1, Iclass_xt_iclass_rsr_excsave4_args,
8936     3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
8937   { 1, Iclass_xt_iclass_wsr_excsave4_args,
8938     3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
8939   { 1, Iclass_xt_iclass_xsr_excsave4_args,
8940     3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
8941   { 1, Iclass_xt_iclass_rsr_epc5_args,
8942     3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
8943   { 1, Iclass_xt_iclass_wsr_epc5_args,
8944     3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
8945   { 1, Iclass_xt_iclass_xsr_epc5_args,
8946     3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
8947   { 1, Iclass_xt_iclass_rsr_excsave5_args,
8948     3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
8949   { 1, Iclass_xt_iclass_wsr_excsave5_args,
8950     3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
8951   { 1, Iclass_xt_iclass_xsr_excsave5_args,
8952     3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
8953   { 1, Iclass_xt_iclass_rsr_epc6_args,
8954     3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
8955   { 1, Iclass_xt_iclass_wsr_epc6_args,
8956     3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
8957   { 1, Iclass_xt_iclass_xsr_epc6_args,
8958     3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
8959   { 1, Iclass_xt_iclass_rsr_excsave6_args,
8960     3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
8961   { 1, Iclass_xt_iclass_wsr_excsave6_args,
8962     3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
8963   { 1, Iclass_xt_iclass_xsr_excsave6_args,
8964     3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
8965   { 1, Iclass_xt_iclass_rsr_epc7_args,
8966     3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
8967   { 1, Iclass_xt_iclass_wsr_epc7_args,
8968     3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
8969   { 1, Iclass_xt_iclass_xsr_epc7_args,
8970     3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
8971   { 1, Iclass_xt_iclass_rsr_excsave7_args,
8972     3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
8973   { 1, Iclass_xt_iclass_wsr_excsave7_args,
8974     3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
8975   { 1, Iclass_xt_iclass_xsr_excsave7_args,
8976     3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
8977   { 1, Iclass_xt_iclass_rsr_eps2_args,
8978     3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
8979   { 1, Iclass_xt_iclass_wsr_eps2_args,
8980     3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
8981   { 1, Iclass_xt_iclass_xsr_eps2_args,
8982     3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
8983   { 1, Iclass_xt_iclass_rsr_eps3_args,
8984     3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
8985   { 1, Iclass_xt_iclass_wsr_eps3_args,
8986     3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
8987   { 1, Iclass_xt_iclass_xsr_eps3_args,
8988     3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
8989   { 1, Iclass_xt_iclass_rsr_eps4_args,
8990     3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
8991   { 1, Iclass_xt_iclass_wsr_eps4_args,
8992     3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
8993   { 1, Iclass_xt_iclass_xsr_eps4_args,
8994     3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
8995   { 1, Iclass_xt_iclass_rsr_eps5_args,
8996     3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
8997   { 1, Iclass_xt_iclass_wsr_eps5_args,
8998     3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
8999   { 1, Iclass_xt_iclass_xsr_eps5_args,
9000     3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
9001   { 1, Iclass_xt_iclass_rsr_eps6_args,
9002     3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
9003   { 1, Iclass_xt_iclass_wsr_eps6_args,
9004     3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
9005   { 1, Iclass_xt_iclass_xsr_eps6_args,
9006     3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
9007   { 1, Iclass_xt_iclass_rsr_eps7_args,
9008     3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
9009   { 1, Iclass_xt_iclass_wsr_eps7_args,
9010     3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
9011   { 1, Iclass_xt_iclass_xsr_eps7_args,
9012     3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
9013   { 1, Iclass_xt_iclass_rsr_excvaddr_args,
9014     3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
9015   { 1, Iclass_xt_iclass_wsr_excvaddr_args,
9016     3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
9017   { 1, Iclass_xt_iclass_xsr_excvaddr_args,
9018     3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
9019   { 1, Iclass_xt_iclass_rsr_depc_args,
9020     3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
9021   { 1, Iclass_xt_iclass_wsr_depc_args,
9022     3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
9023   { 1, Iclass_xt_iclass_xsr_depc_args,
9024     3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
9025   { 1, Iclass_xt_iclass_rsr_exccause_args,
9026     4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
9027   { 1, Iclass_xt_iclass_wsr_exccause_args,
9028     3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
9029   { 1, Iclass_xt_iclass_xsr_exccause_args,
9030     3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
9031   { 1, Iclass_xt_iclass_rsr_misc0_args,
9032     3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
9033   { 1, Iclass_xt_iclass_wsr_misc0_args,
9034     3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
9035   { 1, Iclass_xt_iclass_xsr_misc0_args,
9036     3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
9037   { 1, Iclass_xt_iclass_rsr_misc1_args,
9038     3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
9039   { 1, Iclass_xt_iclass_wsr_misc1_args,
9040     3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
9041   { 1, Iclass_xt_iclass_xsr_misc1_args,
9042     3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
9043   { 1, Iclass_xt_iclass_rsr_misc2_args,
9044     3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 },
9045   { 1, Iclass_xt_iclass_wsr_misc2_args,
9046     3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 },
9047   { 1, Iclass_xt_iclass_xsr_misc2_args,
9048     3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 },
9049   { 1, Iclass_xt_iclass_rsr_misc3_args,
9050     3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 },
9051   { 1, Iclass_xt_iclass_wsr_misc3_args,
9052     3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 },
9053   { 1, Iclass_xt_iclass_xsr_misc3_args,
9054     3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 },
9055   { 1, Iclass_xt_iclass_rsr_prid_args,
9056     2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
9057   { 1, Iclass_xt_iclass_rsr_vecbase_args,
9058     3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
9059   { 1, Iclass_xt_iclass_wsr_vecbase_args,
9060     3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
9061   { 1, Iclass_xt_iclass_xsr_vecbase_args,
9062     3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
9063   { 2, Iclass_xt_iclass_mac16_aa_args,
9064     1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
9065   { 2, Iclass_xt_iclass_mac16_ad_args,
9066     1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
9067   { 2, Iclass_xt_iclass_mac16_da_args,
9068     1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
9069   { 2, Iclass_xt_iclass_mac16_dd_args,
9070     1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
9071   { 2, Iclass_xt_iclass_mac16a_aa_args,
9072     1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
9073   { 2, Iclass_xt_iclass_mac16a_ad_args,
9074     1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
9075   { 2, Iclass_xt_iclass_mac16a_da_args,
9076     1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
9077   { 2, Iclass_xt_iclass_mac16a_dd_args,
9078     1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
9079   { 4, Iclass_xt_iclass_mac16al_da_args,
9080     1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
9081   { 4, Iclass_xt_iclass_mac16al_dd_args,
9082     1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
9083   { 2, Iclass_xt_iclass_mac16_l_args,
9084     0, 0, 0, 0 },
9085   { 3, Iclass_xt_iclass_mul16_args,
9086     0, 0, 0, 0 },
9087   { 2, Iclass_xt_iclass_rsr_m0_args,
9088     0, 0, 0, 0 },
9089   { 2, Iclass_xt_iclass_wsr_m0_args,
9090     0, 0, 0, 0 },
9091   { 2, Iclass_xt_iclass_xsr_m0_args,
9092     0, 0, 0, 0 },
9093   { 2, Iclass_xt_iclass_rsr_m1_args,
9094     0, 0, 0, 0 },
9095   { 2, Iclass_xt_iclass_wsr_m1_args,
9096     0, 0, 0, 0 },
9097   { 2, Iclass_xt_iclass_xsr_m1_args,
9098     0, 0, 0, 0 },
9099   { 2, Iclass_xt_iclass_rsr_m2_args,
9100     0, 0, 0, 0 },
9101   { 2, Iclass_xt_iclass_wsr_m2_args,
9102     0, 0, 0, 0 },
9103   { 2, Iclass_xt_iclass_xsr_m2_args,
9104     0, 0, 0, 0 },
9105   { 2, Iclass_xt_iclass_rsr_m3_args,
9106     0, 0, 0, 0 },
9107   { 2, Iclass_xt_iclass_wsr_m3_args,
9108     0, 0, 0, 0 },
9109   { 2, Iclass_xt_iclass_xsr_m3_args,
9110     0, 0, 0, 0 },
9111   { 1, Iclass_xt_iclass_rsr_acclo_args,
9112     1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
9113   { 1, Iclass_xt_iclass_wsr_acclo_args,
9114     1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
9115   { 1, Iclass_xt_iclass_xsr_acclo_args,
9116     1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
9117   { 1, Iclass_xt_iclass_rsr_acchi_args,
9118     1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
9119   { 1, Iclass_xt_iclass_wsr_acchi_args,
9120     1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
9121   { 1, Iclass_xt_iclass_xsr_acchi_args,
9122     1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
9123   { 1, Iclass_xt_iclass_rfi_args,
9124     21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
9125   { 1, Iclass_xt_iclass_wait_args,
9126     3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
9127   { 1, Iclass_xt_iclass_rsr_interrupt_args,
9128     3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
9129   { 1, Iclass_xt_iclass_wsr_intset_args,
9130     4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
9131   { 1, Iclass_xt_iclass_wsr_intclear_args,
9132     4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
9133   { 1, Iclass_xt_iclass_rsr_intenable_args,
9134     3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
9135   { 1, Iclass_xt_iclass_wsr_intenable_args,
9136     3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
9137   { 1, Iclass_xt_iclass_xsr_intenable_args,
9138     3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
9139   { 2, Iclass_xt_iclass_break_args,
9140     2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
9141   { 1, Iclass_xt_iclass_break_n_args,
9142     2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
9143   { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
9144     3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
9145   { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
9146     4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
9147   { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
9148     4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
9149   { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
9150     3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
9151   { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
9152     4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
9153   { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
9154     4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
9155   { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
9156     3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
9157   { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
9158     4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
9159   { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
9160     4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
9161   { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
9162     3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
9163   { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
9164     4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
9165   { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
9166     4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
9167   { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
9168     3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
9169   { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
9170     3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
9171   { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
9172     3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
9173   { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
9174     3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
9175   { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
9176     3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
9177   { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
9178     3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
9179   { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
9180     3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
9181   { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
9182     3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
9183   { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
9184     3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
9185   { 1, Iclass_xt_iclass_rsr_debugcause_args,
9186     4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
9187   { 1, Iclass_xt_iclass_wsr_debugcause_args,
9188     4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
9189   { 1, Iclass_xt_iclass_xsr_debugcause_args,
9190     4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
9191   { 1, Iclass_xt_iclass_rsr_icount_args,
9192     3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
9193   { 1, Iclass_xt_iclass_wsr_icount_args,
9194     4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
9195   { 1, Iclass_xt_iclass_xsr_icount_args,
9196     4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
9197   { 1, Iclass_xt_iclass_rsr_icountlevel_args,
9198     3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
9199   { 1, Iclass_xt_iclass_wsr_icountlevel_args,
9200     3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
9201   { 1, Iclass_xt_iclass_xsr_icountlevel_args,
9202     3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
9203   { 1, Iclass_xt_iclass_rsr_ddr_args,
9204     3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
9205   { 1, Iclass_xt_iclass_wsr_ddr_args,
9206     4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
9207   { 1, Iclass_xt_iclass_xsr_ddr_args,
9208     4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
9209   { 1, Iclass_xt_iclass_rfdo_args,
9210     10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
9211   { 0, 0 /* xt_iclass_rfdd */,
9212     1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
9213   { 1, Iclass_xt_iclass_wsr_mmid_args,
9214     3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
9215   { 3, Iclass_xt_iclass_bbool1_args,
9216     0, 0, 0, 0 },
9217   { 2, Iclass_xt_iclass_bbool4_args,
9218     0, 0, 0, 0 },
9219   { 2, Iclass_xt_iclass_bbool8_args,
9220     0, 0, 0, 0 },
9221   { 2, Iclass_xt_iclass_bbranch_args,
9222     0, 0, 0, 0 },
9223   { 3, Iclass_xt_iclass_bmove_args,
9224     0, 0, 0, 0 },
9225   { 2, Iclass_xt_iclass_RSR_BR_args,
9226     0, 0, 0, 0 },
9227   { 2, Iclass_xt_iclass_WSR_BR_args,
9228     0, 0, 0, 0 },
9229   { 2, Iclass_xt_iclass_XSR_BR_args,
9230     0, 0, 0, 0 },
9231   { 1, Iclass_xt_iclass_rsr_ccount_args,
9232     3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
9233   { 1, Iclass_xt_iclass_wsr_ccount_args,
9234     4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
9235   { 1, Iclass_xt_iclass_xsr_ccount_args,
9236     4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
9237   { 1, Iclass_xt_iclass_rsr_ccompare0_args,
9238     3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
9239   { 1, Iclass_xt_iclass_wsr_ccompare0_args,
9240     4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
9241   { 1, Iclass_xt_iclass_xsr_ccompare0_args,
9242     4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
9243   { 1, Iclass_xt_iclass_rsr_ccompare1_args,
9244     3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
9245   { 1, Iclass_xt_iclass_wsr_ccompare1_args,
9246     4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
9247   { 1, Iclass_xt_iclass_xsr_ccompare1_args,
9248     4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
9249   { 1, Iclass_xt_iclass_rsr_ccompare2_args,
9250     3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
9251   { 1, Iclass_xt_iclass_wsr_ccompare2_args,
9252     4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
9253   { 1, Iclass_xt_iclass_xsr_ccompare2_args,
9254     4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
9255   { 2, Iclass_xt_iclass_icache_args,
9256     0, 0, 0, 0 },
9257   { 2, Iclass_xt_iclass_icache_lock_args,
9258     2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
9259   { 2, Iclass_xt_iclass_icache_inv_args,
9260     2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
9261   { 2, Iclass_xt_iclass_licx_args,
9262     2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
9263   { 2, Iclass_xt_iclass_sicx_args,
9264     2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
9265   { 2, Iclass_xt_iclass_dcache_args,
9266     0, 0, 0, 0 },
9267   { 2, Iclass_xt_iclass_dcache_ind_args,
9268     2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
9269   { 2, Iclass_xt_iclass_dcache_inv_args,
9270     2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
9271   { 2, Iclass_xt_iclass_dpf_args,
9272     0, 0, 0, 0 },
9273   { 2, Iclass_xt_iclass_dcache_lock_args,
9274     2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
9275   { 2, Iclass_xt_iclass_sdct_args,
9276     2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
9277   { 2, Iclass_xt_iclass_ldct_args,
9278     2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
9279   { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
9280     4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
9281   { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
9282     4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
9283   { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
9284     5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
9285   { 1, Iclass_xt_iclass_rsr_rasid_args,
9286     5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
9287   { 1, Iclass_xt_iclass_wsr_rasid_args,
9288     6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
9289   { 1, Iclass_xt_iclass_xsr_rasid_args,
9290     6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
9291   { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
9292     3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
9293   { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
9294     4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
9295   { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
9296     4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
9297   { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
9298     3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
9299   { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
9300     4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
9301   { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
9302     4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
9303   { 1, Iclass_xt_iclass_idtlb_args,
9304     3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
9305   { 2, Iclass_xt_iclass_rdtlb_args,
9306     2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
9307   { 2, Iclass_xt_iclass_wdtlb_args,
9308     3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
9309   { 1, Iclass_xt_iclass_iitlb_args,
9310     2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
9311   { 2, Iclass_xt_iclass_ritlb_args,
9312     2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
9313   { 2, Iclass_xt_iclass_witlb_args,
9314     2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
9315   { 0, 0 /* xt_iclass_ldpte */,
9316     2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
9317   { 0, 0 /* xt_iclass_hwwitlba */,
9318     1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
9319   { 0, 0 /* xt_iclass_hwwdtlba */,
9320     1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
9321   { 1, Iclass_xt_iclass_rsr_cpenable_args,
9322     3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
9323   { 1, Iclass_xt_iclass_wsr_cpenable_args,
9324     3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
9325   { 1, Iclass_xt_iclass_xsr_cpenable_args,
9326     3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
9327   { 3, Iclass_xt_iclass_clamp_args,
9328     0, 0, 0, 0 },
9329   { 3, Iclass_xt_iclass_minmax_args,
9330     0, 0, 0, 0 },
9331   { 2, Iclass_xt_iclass_nsa_args,
9332     0, 0, 0, 0 },
9333   { 3, Iclass_xt_iclass_sx_args,
9334     0, 0, 0, 0 },
9335   { 3, Iclass_xt_iclass_l32ai_args,
9336     0, 0, 0, 0 },
9337   { 3, Iclass_xt_iclass_s32ri_args,
9338     0, 0, 0, 0 },
9339   { 3, Iclass_xt_iclass_s32c1i_args,
9340     2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
9341   { 1, Iclass_xt_iclass_rsr_scompare1_args,
9342     1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
9343   { 1, Iclass_xt_iclass_wsr_scompare1_args,
9344     1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
9345   { 1, Iclass_xt_iclass_xsr_scompare1_args,
9346     1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
9347   { 3, Iclass_xt_iclass_div_args,
9348     0, 0, 0, 0 },
9349   { 3, Iclass_xt_mul32_args,
9350     0, 0, 0, 0 },
9351   { 1, Iclass_rur_fcr_args,
9352     9, Iclass_rur_fcr_stateArgs, 0, 0 },
9353   { 1, Iclass_wur_fcr_args,
9354     9, Iclass_wur_fcr_stateArgs, 0, 0 },
9355   { 1, Iclass_rur_fsr_args,
9356     8, Iclass_rur_fsr_stateArgs, 0, 0 },
9357   { 1, Iclass_wur_fsr_args,
9358     8, Iclass_wur_fsr_stateArgs, 0, 0 },
9359   { 3, Iclass_fp_args,
9360     2, Iclass_fp_stateArgs, 0, 0 },
9361   { 3, Iclass_fp_mac_args,
9362     2, Iclass_fp_mac_stateArgs, 0, 0 },
9363   { 3, Iclass_fp_cmov_args,
9364     1, Iclass_fp_cmov_stateArgs, 0, 0 },
9365   { 3, Iclass_fp_mov_args,
9366     1, Iclass_fp_mov_stateArgs, 0, 0 },
9367   { 2, Iclass_fp_mov2_args,
9368     1, Iclass_fp_mov2_stateArgs, 0, 0 },
9369   { 3, Iclass_fp_cmp_args,
9370     1, Iclass_fp_cmp_stateArgs, 0, 0 },
9371   { 3, Iclass_fp_float_args,
9372     2, Iclass_fp_float_stateArgs, 0, 0 },
9373   { 3, Iclass_fp_int_args,
9374     1, Iclass_fp_int_stateArgs, 0, 0 },
9375   { 2, Iclass_fp_rfr_args,
9376     1, Iclass_fp_rfr_stateArgs, 0, 0 },
9377   { 2, Iclass_fp_wfr_args,
9378     1, Iclass_fp_wfr_stateArgs, 0, 0 },
9379   { 3, Iclass_fp_lsi_args,
9380     1, Iclass_fp_lsi_stateArgs, 0, 0 },
9381   { 3, Iclass_fp_lsiu_args,
9382     1, Iclass_fp_lsiu_stateArgs, 0, 0 },
9383   { 3, Iclass_fp_lsx_args,
9384     1, Iclass_fp_lsx_stateArgs, 0, 0 },
9385   { 3, Iclass_fp_lsxu_args,
9386     1, Iclass_fp_lsxu_stateArgs, 0, 0 },
9387   { 3, Iclass_fp_ssi_args,
9388     1, Iclass_fp_ssi_stateArgs, 0, 0 },
9389   { 3, Iclass_fp_ssiu_args,
9390     1, Iclass_fp_ssiu_stateArgs, 0, 0 },
9391   { 3, Iclass_fp_ssx_args,
9392     1, Iclass_fp_ssx_stateArgs, 0, 0 },
9393   { 3, Iclass_fp_ssxu_args,
9394     1, Iclass_fp_ssxu_stateArgs, 0, 0 },
9395   { 2, Iclass_xt_iclass_wb18_0_args,
9396     0, 0, 0, 0 },
9397   { 3, Iclass_xt_iclass_wb18_1_args,
9398     0, 0, 0, 0 },
9399   { 3, Iclass_xt_iclass_wb18_2_args,
9400     0, 0, 0, 0 },
9401   { 3, Iclass_xt_iclass_wb18_3_args,
9402     0, 0, 0, 0 },
9403   { 3, Iclass_xt_iclass_wb18_4_args,
9404     0, 0, 0, 0 }
9405 };
9406
9407 \f
9408 /*  Opcode encodings.  */
9409
9410 static void
9411 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
9412 {
9413   slotbuf[0] = 0x2080;
9414 }
9415
9416 static void
9417 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
9418 {
9419   slotbuf[0] = 0x3000;
9420 }
9421
9422 static void
9423 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
9424 {
9425   slotbuf[0] = 0x3200;
9426 }
9427
9428 static void
9429 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
9430 {
9431   slotbuf[0] = 0x5000;
9432 }
9433
9434 static void
9435 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
9436 {
9437   slotbuf[0] = 0x5100;
9438 }
9439
9440 static void
9441 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
9442 {
9443   slotbuf[0] = 0x35;
9444 }
9445
9446 static void
9447 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9448 {
9449   slotbuf[0] = 0x25;
9450 }
9451
9452 static void
9453 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9454 {
9455   slotbuf[0] = 0x15;
9456 }
9457
9458 static void
9459 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
9460 {
9461   slotbuf[0] = 0xf0;
9462 }
9463
9464 static void
9465 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9466 {
9467   slotbuf[0] = 0xe0;
9468 }
9469
9470 static void
9471 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9472 {
9473   slotbuf[0] = 0xd0;
9474 }
9475
9476 static void
9477 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
9478 {
9479   slotbuf[0] = 0x36;
9480 }
9481
9482 static void
9483 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
9484 {
9485   slotbuf[0] = 0x1000;
9486 }
9487
9488 static void
9489 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
9490 {
9491   slotbuf[0] = 0x408000;
9492 }
9493
9494 static void
9495 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
9496 {
9497   slotbuf[0] = 0x90;
9498 }
9499
9500 static void
9501 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9502 {
9503   slotbuf[0] = 0xf01d;
9504 }
9505
9506 static void
9507 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
9508 {
9509   slotbuf[0] = 0x3400;
9510 }
9511
9512 static void
9513 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
9514 {
9515   slotbuf[0] = 0x3500;
9516 }
9517
9518 static void
9519 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
9520 {
9521   slotbuf[0] = 0x90000;
9522 }
9523
9524 static void
9525 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
9526 {
9527   slotbuf[0] = 0x490000;
9528 }
9529
9530 static void
9531 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
9532 {
9533   slotbuf[0] = 0x34800;
9534 }
9535
9536 static void
9537 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
9538 {
9539   slotbuf[0] = 0x134800;
9540 }
9541
9542 static void
9543 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
9544 {
9545   slotbuf[0] = 0x614800;
9546 }
9547
9548 static void
9549 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
9550 {
9551   slotbuf[0] = 0x34900;
9552 }
9553
9554 static void
9555 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
9556 {
9557   slotbuf[0] = 0x134900;
9558 }
9559
9560 static void
9561 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
9562 {
9563   slotbuf[0] = 0x614900;
9564 }
9565
9566 static void
9567 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9568 {
9569   slotbuf[0] = 0xa;
9570 }
9571
9572 static void
9573 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9574 {
9575   slotbuf[0] = 0xb;
9576 }
9577
9578 static void
9579 Opcode_addi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9580 {
9581   slotbuf[0] = 0x3000;
9582 }
9583
9584 static void
9585 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9586 {
9587   slotbuf[0] = 0x8c;
9588 }
9589
9590 static void
9591 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9592 {
9593   slotbuf[0] = 0xcc;
9594 }
9595
9596 static void
9597 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9598 {
9599   slotbuf[0] = 0xf06d;
9600 }
9601
9602 static void
9603 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9604 {
9605   slotbuf[0] = 0x8;
9606 }
9607
9608 static void
9609 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9610 {
9611   slotbuf[0] = 0xd;
9612 }
9613
9614 static void
9615 Opcode_mov_n_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9616 {
9617   slotbuf[0] = 0x6000;
9618 }
9619
9620 static void
9621 Opcode_mov_n_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9622 {
9623   slotbuf[0] = 0xa3000;
9624 }
9625
9626 static void
9627 Opcode_mov_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9628 {
9629   slotbuf[0] = 0xc080;
9630 }
9631
9632 static void
9633 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9634 {
9635   slotbuf[0] = 0xc;
9636 }
9637
9638 static void
9639 Opcode_movi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9640 {
9641   slotbuf[0] = 0xc000;
9642 }
9643
9644 static void
9645 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9646 {
9647   slotbuf[0] = 0xf03d;
9648 }
9649
9650 static void
9651 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9652 {
9653   slotbuf[0] = 0xf00d;
9654 }
9655
9656 static void
9657 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9658 {
9659   slotbuf[0] = 0x9;
9660 }
9661
9662 static void
9663 Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
9664 {
9665   slotbuf[0] = 0xe30e70;
9666 }
9667
9668 static void
9669 Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
9670 {
9671   slotbuf[0] = 0xf3e700;
9672 }
9673
9674 static void
9675 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9676 {
9677   slotbuf[0] = 0xc002;
9678 }
9679
9680 static void
9681 Opcode_addi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9682 {
9683   slotbuf[0] = 0x60000;
9684 }
9685
9686 static void
9687 Opcode_addi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9688 {
9689   slotbuf[0] = 0x200c00;
9690 }
9691
9692 static void
9693 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9694 {
9695   slotbuf[0] = 0xd002;
9696 }
9697
9698 static void
9699 Opcode_addmi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9700 {
9701   slotbuf[0] = 0x70000;
9702 }
9703
9704 static void
9705 Opcode_addmi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9706 {
9707   slotbuf[0] = 0x200d00;
9708 }
9709
9710 static void
9711 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
9712 {
9713   slotbuf[0] = 0x800000;
9714 }
9715
9716 static void
9717 Opcode_add_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9718 {
9719   slotbuf[0] = 0x92000;
9720 }
9721
9722 static void
9723 Opcode_add_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9724 {
9725   slotbuf[0] = 0x2000;
9726 }
9727
9728 static void
9729 Opcode_add_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9730 {
9731   slotbuf[0] = 0x80000;
9732 }
9733
9734 static void
9735 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
9736 {
9737   slotbuf[0] = 0xc00000;
9738 }
9739
9740 static void
9741 Opcode_sub_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9742 {
9743   slotbuf[0] = 0xa8000;
9744 }
9745
9746 static void
9747 Opcode_sub_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9748 {
9749   slotbuf[0] = 0xa000;
9750 }
9751
9752 static void
9753 Opcode_sub_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9754 {
9755   slotbuf[0] = 0xc0000;
9756 }
9757
9758 static void
9759 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
9760 {
9761   slotbuf[0] = 0x900000;
9762 }
9763
9764 static void
9765 Opcode_addx2_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9766 {
9767   slotbuf[0] = 0x94000;
9768 }
9769
9770 static void
9771 Opcode_addx2_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9772 {
9773   slotbuf[0] = 0x4000;
9774 }
9775
9776 static void
9777 Opcode_addx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9778 {
9779   slotbuf[0] = 0x90000;
9780 }
9781
9782 static void
9783 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9784 {
9785   slotbuf[0] = 0xa00000;
9786 }
9787
9788 static void
9789 Opcode_addx4_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9790 {
9791   slotbuf[0] = 0x98000;
9792 }
9793
9794 static void
9795 Opcode_addx4_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9796 {
9797   slotbuf[0] = 0x5000;
9798 }
9799
9800 static void
9801 Opcode_addx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9802 {
9803   slotbuf[0] = 0xa0000;
9804 }
9805
9806 static void
9807 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9808 {
9809   slotbuf[0] = 0xb00000;
9810 }
9811
9812 static void
9813 Opcode_addx8_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9814 {
9815   slotbuf[0] = 0x93000;
9816 }
9817
9818 static void
9819 Opcode_addx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9820 {
9821   slotbuf[0] = 0xb0000;
9822 }
9823
9824 static void
9825 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
9826 {
9827   slotbuf[0] = 0xd00000;
9828 }
9829
9830 static void
9831 Opcode_subx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9832 {
9833   slotbuf[0] = 0xd0000;
9834 }
9835
9836 static void
9837 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9838 {
9839   slotbuf[0] = 0xe00000;
9840 }
9841
9842 static void
9843 Opcode_subx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9844 {
9845   slotbuf[0] = 0xe0000;
9846 }
9847
9848 static void
9849 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9850 {
9851   slotbuf[0] = 0xf00000;
9852 }
9853
9854 static void
9855 Opcode_subx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9856 {
9857   slotbuf[0] = 0xf0000;
9858 }
9859
9860 static void
9861 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
9862 {
9863   slotbuf[0] = 0x100000;
9864 }
9865
9866 static void
9867 Opcode_and_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9868 {
9869   slotbuf[0] = 0x95000;
9870 }
9871
9872 static void
9873 Opcode_and_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9874 {
9875   slotbuf[0] = 0x6000;
9876 }
9877
9878 static void
9879 Opcode_and_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9880 {
9881   slotbuf[0] = 0x10000;
9882 }
9883
9884 static void
9885 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
9886 {
9887   slotbuf[0] = 0x200000;
9888 }
9889
9890 static void
9891 Opcode_or_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9892 {
9893   slotbuf[0] = 0x9e000;
9894 }
9895
9896 static void
9897 Opcode_or_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9898 {
9899   slotbuf[0] = 0x7000;
9900 }
9901
9902 static void
9903 Opcode_or_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9904 {
9905   slotbuf[0] = 0x20000;
9906 }
9907
9908 static void
9909 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
9910 {
9911   slotbuf[0] = 0x300000;
9912 }
9913
9914 static void
9915 Opcode_xor_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9916 {
9917   slotbuf[0] = 0xb0000;
9918 }
9919
9920 static void
9921 Opcode_xor_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9922 {
9923   slotbuf[0] = 0xb000;
9924 }
9925
9926 static void
9927 Opcode_xor_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9928 {
9929   slotbuf[0] = 0x30000;
9930 }
9931
9932 static void
9933 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9934 {
9935   slotbuf[0] = 0x26;
9936 }
9937
9938 static void
9939 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
9940 {
9941   slotbuf[0] = 0x66;
9942 }
9943
9944 static void
9945 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
9946 {
9947   slotbuf[0] = 0xe6;
9948 }
9949
9950 static void
9951 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
9952 {
9953   slotbuf[0] = 0xa6;
9954 }
9955
9956 static void
9957 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
9958 {
9959   slotbuf[0] = 0x6007;
9960 }
9961
9962 static void
9963 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9964 {
9965   slotbuf[0] = 0xe007;
9966 }
9967
9968 static void
9969 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
9970 {
9971   slotbuf[0] = 0xf6;
9972 }
9973
9974 static void
9975 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
9976 {
9977   slotbuf[0] = 0xb6;
9978 }
9979
9980 static void
9981 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
9982 {
9983   slotbuf[0] = 0x1007;
9984 }
9985
9986 static void
9987 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
9988 {
9989   slotbuf[0] = 0x9007;
9990 }
9991
9992 static void
9993 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
9994 {
9995   slotbuf[0] = 0xa007;
9996 }
9997
9998 static void
9999 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
10000 {
10001   slotbuf[0] = 0x2007;
10002 }
10003
10004 static void
10005 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
10006 {
10007   slotbuf[0] = 0xb007;
10008 }
10009
10010 static void
10011 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
10012 {
10013   slotbuf[0] = 0x3007;
10014 }
10015
10016 static void
10017 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
10018 {
10019   slotbuf[0] = 0x8007;
10020 }
10021
10022 static void
10023 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
10024 {
10025   slotbuf[0] = 0x7;
10026 }
10027
10028 static void
10029 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
10030 {
10031   slotbuf[0] = 0x4007;
10032 }
10033
10034 static void
10035 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
10036 {
10037   slotbuf[0] = 0xc007;
10038 }
10039
10040 static void
10041 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
10042 {
10043   slotbuf[0] = 0x5007;
10044 }
10045
10046 static void
10047 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
10048 {
10049   slotbuf[0] = 0xd007;
10050 }
10051
10052 static void
10053 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
10054 {
10055   slotbuf[0] = 0x16;
10056 }
10057
10058 static void
10059 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
10060 {
10061   slotbuf[0] = 0x56;
10062 }
10063
10064 static void
10065 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
10066 {
10067   slotbuf[0] = 0xd6;
10068 }
10069
10070 static void
10071 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
10072 {
10073   slotbuf[0] = 0x96;
10074 }
10075
10076 static void
10077 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
10078 {
10079   slotbuf[0] = 0x5;
10080 }
10081
10082 static void
10083 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
10084 {
10085   slotbuf[0] = 0xc0;
10086 }
10087
10088 static void
10089 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
10090 {
10091   slotbuf[0] = 0x40000;
10092 }
10093
10094 static void
10095 Opcode_extui_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10096 {
10097   slotbuf[0] = 0x40000;
10098 }
10099
10100 static void
10101 Opcode_extui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10102 {
10103   slotbuf[0] = 0x4000;
10104 }
10105
10106 static void
10107 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
10108 {
10109   slotbuf[0] = 0;
10110 }
10111
10112 static void
10113 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
10114 {
10115   slotbuf[0] = 0x6;
10116 }
10117
10118 static void
10119 Opcode_j_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10120 {
10121   slotbuf[0] = 0xc0000;
10122 }
10123
10124 static void
10125 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
10126 {
10127   slotbuf[0] = 0xa0;
10128 }
10129
10130 static void
10131 Opcode_jx_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10132 {
10133   slotbuf[0] = 0xa3010;
10134 }
10135
10136 static void
10137 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
10138 {
10139   slotbuf[0] = 0x1002;
10140 }
10141
10142 static void
10143 Opcode_l16ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10144 {
10145   slotbuf[0] = 0x200100;
10146 }
10147
10148 static void
10149 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
10150 {
10151   slotbuf[0] = 0x9002;
10152 }
10153
10154 static void
10155 Opcode_l16si_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10156 {
10157   slotbuf[0] = 0x200900;
10158 }
10159
10160 static void
10161 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
10162 {
10163   slotbuf[0] = 0x2002;
10164 }
10165
10166 static void
10167 Opcode_l32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10168 {
10169   slotbuf[0] = 0x200200;
10170 }
10171
10172 static void
10173 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
10174 {
10175   slotbuf[0] = 0x1;
10176 }
10177
10178 static void
10179 Opcode_l32r_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10180 {
10181   slotbuf[0] = 0x100000;
10182 }
10183
10184 static void
10185 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
10186 {
10187   slotbuf[0] = 0x2;
10188 }
10189
10190 static void
10191 Opcode_l8ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10192 {
10193   slotbuf[0] = 0x200000;
10194 }
10195
10196 static void
10197 Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
10198 {
10199   slotbuf[0] = 0x8076;
10200 }
10201
10202 static void
10203 Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
10204 {
10205   slotbuf[0] = 0x9076;
10206 }
10207
10208 static void
10209 Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
10210 {
10211   slotbuf[0] = 0xa076;
10212 }
10213
10214 static void
10215 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
10216 {
10217   slotbuf[0] = 0xa002;
10218 }
10219
10220 static void
10221 Opcode_movi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10222 {
10223   slotbuf[0] = 0x80000;
10224 }
10225
10226 static void
10227 Opcode_movi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10228 {
10229   slotbuf[0] = 0x200a00;
10230 }
10231
10232 static void
10233 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
10234 {
10235   slotbuf[0] = 0x830000;
10236 }
10237
10238 static void
10239 Opcode_moveqz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10240 {
10241   slotbuf[0] = 0x96000;
10242 }
10243
10244 static void
10245 Opcode_moveqz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10246 {
10247   slotbuf[0] = 0x83000;
10248 }
10249
10250 static void
10251 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
10252 {
10253   slotbuf[0] = 0x930000;
10254 }
10255
10256 static void
10257 Opcode_movnez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10258 {
10259   slotbuf[0] = 0x9a000;
10260 }
10261
10262 static void
10263 Opcode_movnez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10264 {
10265   slotbuf[0] = 0x93000;
10266 }
10267
10268 static void
10269 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
10270 {
10271   slotbuf[0] = 0xa30000;
10272 }
10273
10274 static void
10275 Opcode_movltz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10276 {
10277   slotbuf[0] = 0x99000;
10278 }
10279
10280 static void
10281 Opcode_movltz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10282 {
10283   slotbuf[0] = 0xa3000;
10284 }
10285
10286 static void
10287 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
10288 {
10289   slotbuf[0] = 0xb30000;
10290 }
10291
10292 static void
10293 Opcode_movgez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10294 {
10295   slotbuf[0] = 0x97000;
10296 }
10297
10298 static void
10299 Opcode_movgez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10300 {
10301   slotbuf[0] = 0xb3000;
10302 }
10303
10304 static void
10305 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
10306 {
10307   slotbuf[0] = 0x600000;
10308 }
10309
10310 static void
10311 Opcode_neg_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10312 {
10313   slotbuf[0] = 0xa5000;
10314 }
10315
10316 static void
10317 Opcode_neg_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10318 {
10319   slotbuf[0] = 0xd100;
10320 }
10321
10322 static void
10323 Opcode_neg_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10324 {
10325   slotbuf[0] = 0x60000;
10326 }
10327
10328 static void
10329 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
10330 {
10331   slotbuf[0] = 0x600100;
10332 }
10333
10334 static void
10335 Opcode_abs_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10336 {
10337   slotbuf[0] = 0xd000;
10338 }
10339
10340 static void
10341 Opcode_abs_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10342 {
10343   slotbuf[0] = 0x60010;
10344 }
10345
10346 static void
10347 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
10348 {
10349   slotbuf[0] = 0x20f0;
10350 }
10351
10352 static void
10353 Opcode_nop_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10354 {
10355   slotbuf[0] = 0xa3040;
10356 }
10357
10358 static void
10359 Opcode_nop_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10360 {
10361   slotbuf[0] = 0xc090;
10362 }
10363
10364 static void
10365 Opcode_nop_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
10366 {
10367   slotbuf[0] = 0xc8000000;
10368   slotbuf[1] = 0;
10369 }
10370
10371 static void
10372 Opcode_nop_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10373 {
10374   slotbuf[0] = 0x20f;
10375 }
10376
10377 static void
10378 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
10379 {
10380   slotbuf[0] = 0x80;
10381 }
10382
10383 static void
10384 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
10385 {
10386   slotbuf[0] = 0x5002;
10387 }
10388
10389 static void
10390 Opcode_s16i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10391 {
10392   slotbuf[0] = 0x200500;
10393 }
10394
10395 static void
10396 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
10397 {
10398   slotbuf[0] = 0x6002;
10399 }
10400
10401 static void
10402 Opcode_s32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10403 {
10404   slotbuf[0] = 0x200600;
10405 }
10406
10407 static void
10408 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
10409 {
10410   slotbuf[0] = 0x4002;
10411 }
10412
10413 static void
10414 Opcode_s8i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10415 {
10416   slotbuf[0] = 0x200400;
10417 }
10418
10419 static void
10420 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
10421 {
10422   slotbuf[0] = 0x400000;
10423 }
10424
10425 static void
10426 Opcode_ssr_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10427 {
10428   slotbuf[0] = 0x40000;
10429 }
10430
10431 static void
10432 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
10433 {
10434   slotbuf[0] = 0x401000;
10435 }
10436
10437 static void
10438 Opcode_ssl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10439 {
10440   slotbuf[0] = 0xa3020;
10441 }
10442
10443 static void
10444 Opcode_ssl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10445 {
10446   slotbuf[0] = 0x40100;
10447 }
10448
10449 static void
10450 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
10451 {
10452   slotbuf[0] = 0x402000;
10453 }
10454
10455 static void
10456 Opcode_ssa8l_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10457 {
10458   slotbuf[0] = 0x40200;
10459 }
10460
10461 static void
10462 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
10463 {
10464   slotbuf[0] = 0x403000;
10465 }
10466
10467 static void
10468 Opcode_ssa8b_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10469 {
10470   slotbuf[0] = 0x40300;
10471 }
10472
10473 static void
10474 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
10475 {
10476   slotbuf[0] = 0x404000;
10477 }
10478
10479 static void
10480 Opcode_ssai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10481 {
10482   slotbuf[0] = 0x40400;
10483 }
10484
10485 static void
10486 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
10487 {
10488   slotbuf[0] = 0xa10000;
10489 }
10490
10491 static void
10492 Opcode_sll_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10493 {
10494   slotbuf[0] = 0xa6000;
10495 }
10496
10497 static void
10498 Opcode_sll_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10499 {
10500   slotbuf[0] = 0xa1000;
10501 }
10502
10503 static void
10504 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
10505 {
10506   slotbuf[0] = 0x810000;
10507 }
10508
10509 static void
10510 Opcode_src_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10511 {
10512   slotbuf[0] = 0xa2000;
10513 }
10514
10515 static void
10516 Opcode_src_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10517 {
10518   slotbuf[0] = 0x81000;
10519 }
10520
10521 static void
10522 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
10523 {
10524   slotbuf[0] = 0x910000;
10525 }
10526
10527 static void
10528 Opcode_srl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10529 {
10530   slotbuf[0] = 0xa5200;
10531 }
10532
10533 static void
10534 Opcode_srl_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10535 {
10536   slotbuf[0] = 0xd400;
10537 }
10538
10539 static void
10540 Opcode_srl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10541 {
10542   slotbuf[0] = 0x91000;
10543 }
10544
10545 static void
10546 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
10547 {
10548   slotbuf[0] = 0xb10000;
10549 }
10550
10551 static void
10552 Opcode_sra_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10553 {
10554   slotbuf[0] = 0xa5100;
10555 }
10556
10557 static void
10558 Opcode_sra_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10559 {
10560   slotbuf[0] = 0xd200;
10561 }
10562
10563 static void
10564 Opcode_sra_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10565 {
10566   slotbuf[0] = 0xb1000;
10567 }
10568
10569 static void
10570 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
10571 {
10572   slotbuf[0] = 0x10000;
10573 }
10574
10575 static void
10576 Opcode_slli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10577 {
10578   slotbuf[0] = 0x90000;
10579 }
10580
10581 static void
10582 Opcode_slli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10583 {
10584   slotbuf[0] = 0x1000;
10585 }
10586
10587 static void
10588 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
10589 {
10590   slotbuf[0] = 0x210000;
10591 }
10592
10593 static void
10594 Opcode_srai_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10595 {
10596   slotbuf[0] = 0xa0000;
10597 }
10598
10599 static void
10600 Opcode_srai_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10601 {
10602   slotbuf[0] = 0xe000;
10603 }
10604
10605 static void
10606 Opcode_srai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10607 {
10608   slotbuf[0] = 0x21000;
10609 }
10610
10611 static void
10612 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
10613 {
10614   slotbuf[0] = 0x410000;
10615 }
10616
10617 static void
10618 Opcode_srli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10619 {
10620   slotbuf[0] = 0xa4000;
10621 }
10622
10623 static void
10624 Opcode_srli_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10625 {
10626   slotbuf[0] = 0x9000;
10627 }
10628
10629 static void
10630 Opcode_srli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10631 {
10632   slotbuf[0] = 0x41000;
10633 }
10634
10635 static void
10636 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
10637 {
10638   slotbuf[0] = 0x20c0;
10639 }
10640
10641 static void
10642 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
10643 {
10644   slotbuf[0] = 0x20d0;
10645 }
10646
10647 static void
10648 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10649 {
10650   slotbuf[0] = 0x2000;
10651 }
10652
10653 static void
10654 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10655 {
10656   slotbuf[0] = 0x2010;
10657 }
10658
10659 static void
10660 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10661 {
10662   slotbuf[0] = 0x2020;
10663 }
10664
10665 static void
10666 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10667 {
10668   slotbuf[0] = 0x2030;
10669 }
10670
10671 static void
10672 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
10673 {
10674   slotbuf[0] = 0x6000;
10675 }
10676
10677 static void
10678 Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
10679 {
10680   slotbuf[0] = 0x30100;
10681 }
10682
10683 static void
10684 Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
10685 {
10686   slotbuf[0] = 0x130100;
10687 }
10688
10689 static void
10690 Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
10691 {
10692   slotbuf[0] = 0x610100;
10693 }
10694
10695 static void
10696 Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
10697 {
10698   slotbuf[0] = 0x30200;
10699 }
10700
10701 static void
10702 Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
10703 {
10704   slotbuf[0] = 0x130200;
10705 }
10706
10707 static void
10708 Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
10709 {
10710   slotbuf[0] = 0x610200;
10711 }
10712
10713 static void
10714 Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
10715 {
10716   slotbuf[0] = 0x30000;
10717 }
10718
10719 static void
10720 Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
10721 {
10722   slotbuf[0] = 0x130000;
10723 }
10724
10725 static void
10726 Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
10727 {
10728   slotbuf[0] = 0x610000;
10729 }
10730
10731 static void
10732 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
10733 {
10734   slotbuf[0] = 0x30300;
10735 }
10736
10737 static void
10738 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
10739 {
10740   slotbuf[0] = 0x130300;
10741 }
10742
10743 static void
10744 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
10745 {
10746   slotbuf[0] = 0x610300;
10747 }
10748
10749 static void
10750 Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
10751 {
10752   slotbuf[0] = 0x30500;
10753 }
10754
10755 static void
10756 Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
10757 {
10758   slotbuf[0] = 0x130500;
10759 }
10760
10761 static void
10762 Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
10763 {
10764   slotbuf[0] = 0x610500;
10765 }
10766
10767 static void
10768 Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
10769 {
10770   slotbuf[0] = 0x3b000;
10771 }
10772
10773 static void
10774 Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
10775 {
10776   slotbuf[0] = 0x3d000;
10777 }
10778
10779 static void
10780 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
10781 {
10782   slotbuf[0] = 0x3e600;
10783 }
10784
10785 static void
10786 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
10787 {
10788   slotbuf[0] = 0x13e600;
10789 }
10790
10791 static void
10792 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
10793 {
10794   slotbuf[0] = 0x61e600;
10795 }
10796
10797 static void
10798 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10799 {
10800   slotbuf[0] = 0x3b100;
10801 }
10802
10803 static void
10804 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10805 {
10806   slotbuf[0] = 0x13b100;
10807 }
10808
10809 static void
10810 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10811 {
10812   slotbuf[0] = 0x61b100;
10813 }
10814
10815 static void
10816 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10817 {
10818   slotbuf[0] = 0x3d100;
10819 }
10820
10821 static void
10822 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10823 {
10824   slotbuf[0] = 0x13d100;
10825 }
10826
10827 static void
10828 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10829 {
10830   slotbuf[0] = 0x61d100;
10831 }
10832
10833 static void
10834 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10835 {
10836   slotbuf[0] = 0x3b200;
10837 }
10838
10839 static void
10840 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10841 {
10842   slotbuf[0] = 0x13b200;
10843 }
10844
10845 static void
10846 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10847 {
10848   slotbuf[0] = 0x61b200;
10849 }
10850
10851 static void
10852 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10853 {
10854   slotbuf[0] = 0x3d200;
10855 }
10856
10857 static void
10858 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10859 {
10860   slotbuf[0] = 0x13d200;
10861 }
10862
10863 static void
10864 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10865 {
10866   slotbuf[0] = 0x61d200;
10867 }
10868
10869 static void
10870 Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10871 {
10872   slotbuf[0] = 0x3b300;
10873 }
10874
10875 static void
10876 Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10877 {
10878   slotbuf[0] = 0x13b300;
10879 }
10880
10881 static void
10882 Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10883 {
10884   slotbuf[0] = 0x61b300;
10885 }
10886
10887 static void
10888 Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10889 {
10890   slotbuf[0] = 0x3d300;
10891 }
10892
10893 static void
10894 Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10895 {
10896   slotbuf[0] = 0x13d300;
10897 }
10898
10899 static void
10900 Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10901 {
10902   slotbuf[0] = 0x61d300;
10903 }
10904
10905 static void
10906 Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10907 {
10908   slotbuf[0] = 0x3b400;
10909 }
10910
10911 static void
10912 Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10913 {
10914   slotbuf[0] = 0x13b400;
10915 }
10916
10917 static void
10918 Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10919 {
10920   slotbuf[0] = 0x61b400;
10921 }
10922
10923 static void
10924 Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10925 {
10926   slotbuf[0] = 0x3d400;
10927 }
10928
10929 static void
10930 Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10931 {
10932   slotbuf[0] = 0x13d400;
10933 }
10934
10935 static void
10936 Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10937 {
10938   slotbuf[0] = 0x61d400;
10939 }
10940
10941 static void
10942 Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10943 {
10944   slotbuf[0] = 0x3b500;
10945 }
10946
10947 static void
10948 Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10949 {
10950   slotbuf[0] = 0x13b500;
10951 }
10952
10953 static void
10954 Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10955 {
10956   slotbuf[0] = 0x61b500;
10957 }
10958
10959 static void
10960 Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10961 {
10962   slotbuf[0] = 0x3d500;
10963 }
10964
10965 static void
10966 Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10967 {
10968   slotbuf[0] = 0x13d500;
10969 }
10970
10971 static void
10972 Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10973 {
10974   slotbuf[0] = 0x61d500;
10975 }
10976
10977 static void
10978 Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10979 {
10980   slotbuf[0] = 0x3b600;
10981 }
10982
10983 static void
10984 Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10985 {
10986   slotbuf[0] = 0x13b600;
10987 }
10988
10989 static void
10990 Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10991 {
10992   slotbuf[0] = 0x61b600;
10993 }
10994
10995 static void
10996 Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10997 {
10998   slotbuf[0] = 0x3d600;
10999 }
11000
11001 static void
11002 Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
11003 {
11004   slotbuf[0] = 0x13d600;
11005 }
11006
11007 static void
11008 Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
11009 {
11010   slotbuf[0] = 0x61d600;
11011 }
11012
11013 static void
11014 Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11015 {
11016   slotbuf[0] = 0x3b700;
11017 }
11018
11019 static void
11020 Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11021 {
11022   slotbuf[0] = 0x13b700;
11023 }
11024
11025 static void
11026 Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11027 {
11028   slotbuf[0] = 0x61b700;
11029 }
11030
11031 static void
11032 Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11033 {
11034   slotbuf[0] = 0x3d700;
11035 }
11036
11037 static void
11038 Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11039 {
11040   slotbuf[0] = 0x13d700;
11041 }
11042
11043 static void
11044 Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11045 {
11046   slotbuf[0] = 0x61d700;
11047 }
11048
11049 static void
11050 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11051 {
11052   slotbuf[0] = 0x3c200;
11053 }
11054
11055 static void
11056 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11057 {
11058   slotbuf[0] = 0x13c200;
11059 }
11060
11061 static void
11062 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11063 {
11064   slotbuf[0] = 0x61c200;
11065 }
11066
11067 static void
11068 Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11069 {
11070   slotbuf[0] = 0x3c300;
11071 }
11072
11073 static void
11074 Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11075 {
11076   slotbuf[0] = 0x13c300;
11077 }
11078
11079 static void
11080 Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11081 {
11082   slotbuf[0] = 0x61c300;
11083 }
11084
11085 static void
11086 Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11087 {
11088   slotbuf[0] = 0x3c400;
11089 }
11090
11091 static void
11092 Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11093 {
11094   slotbuf[0] = 0x13c400;
11095 }
11096
11097 static void
11098 Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11099 {
11100   slotbuf[0] = 0x61c400;
11101 }
11102
11103 static void
11104 Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
11105 {
11106   slotbuf[0] = 0x3c500;
11107 }
11108
11109 static void
11110 Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
11111 {
11112   slotbuf[0] = 0x13c500;
11113 }
11114
11115 static void
11116 Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
11117 {
11118   slotbuf[0] = 0x61c500;
11119 }
11120
11121 static void
11122 Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
11123 {
11124   slotbuf[0] = 0x3c600;
11125 }
11126
11127 static void
11128 Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
11129 {
11130   slotbuf[0] = 0x13c600;
11131 }
11132
11133 static void
11134 Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
11135 {
11136   slotbuf[0] = 0x61c600;
11137 }
11138
11139 static void
11140 Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11141 {
11142   slotbuf[0] = 0x3c700;
11143 }
11144
11145 static void
11146 Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11147 {
11148   slotbuf[0] = 0x13c700;
11149 }
11150
11151 static void
11152 Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11153 {
11154   slotbuf[0] = 0x61c700;
11155 }
11156
11157 static void
11158 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
11159 {
11160   slotbuf[0] = 0x3ee00;
11161 }
11162
11163 static void
11164 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
11165 {
11166   slotbuf[0] = 0x13ee00;
11167 }
11168
11169 static void
11170 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
11171 {
11172   slotbuf[0] = 0x61ee00;
11173 }
11174
11175 static void
11176 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11177 {
11178   slotbuf[0] = 0x3c000;
11179 }
11180
11181 static void
11182 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11183 {
11184   slotbuf[0] = 0x13c000;
11185 }
11186
11187 static void
11188 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11189 {
11190   slotbuf[0] = 0x61c000;
11191 }
11192
11193 static void
11194 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
11195 {
11196   slotbuf[0] = 0x3e800;
11197 }
11198
11199 static void
11200 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
11201 {
11202   slotbuf[0] = 0x13e800;
11203 }
11204
11205 static void
11206 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
11207 {
11208   slotbuf[0] = 0x61e800;
11209 }
11210
11211 static void
11212 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11213 {
11214   slotbuf[0] = 0x3f400;
11215 }
11216
11217 static void
11218 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11219 {
11220   slotbuf[0] = 0x13f400;
11221 }
11222
11223 static void
11224 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11225 {
11226   slotbuf[0] = 0x61f400;
11227 }
11228
11229 static void
11230 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11231 {
11232   slotbuf[0] = 0x3f500;
11233 }
11234
11235 static void
11236 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11237 {
11238   slotbuf[0] = 0x13f500;
11239 }
11240
11241 static void
11242 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11243 {
11244   slotbuf[0] = 0x61f500;
11245 }
11246
11247 static void
11248 Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11249 {
11250   slotbuf[0] = 0x3f600;
11251 }
11252
11253 static void
11254 Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11255 {
11256   slotbuf[0] = 0x13f600;
11257 }
11258
11259 static void
11260 Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11261 {
11262   slotbuf[0] = 0x61f600;
11263 }
11264
11265 static void
11266 Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11267 {
11268   slotbuf[0] = 0x3f700;
11269 }
11270
11271 static void
11272 Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11273 {
11274   slotbuf[0] = 0x13f700;
11275 }
11276
11277 static void
11278 Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11279 {
11280   slotbuf[0] = 0x61f700;
11281 }
11282
11283 static void
11284 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
11285 {
11286   slotbuf[0] = 0x3eb00;
11287 }
11288
11289 static void
11290 Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
11291 {
11292   slotbuf[0] = 0x3e700;
11293 }
11294
11295 static void
11296 Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
11297 {
11298   slotbuf[0] = 0x13e700;
11299 }
11300
11301 static void
11302 Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
11303 {
11304   slotbuf[0] = 0x61e700;
11305 }
11306
11307 static void
11308 Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11309 {
11310   slotbuf[0] = 0x740004;
11311 }
11312
11313 static void
11314 Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11315 {
11316   slotbuf[0] = 0x750004;
11317 }
11318
11319 static void
11320 Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11321 {
11322   slotbuf[0] = 0x760004;
11323 }
11324
11325 static void
11326 Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11327 {
11328   slotbuf[0] = 0x770004;
11329 }
11330
11331 static void
11332 Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11333 {
11334   slotbuf[0] = 0x700004;
11335 }
11336
11337 static void
11338 Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11339 {
11340   slotbuf[0] = 0x710004;
11341 }
11342
11343 static void
11344 Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11345 {
11346   slotbuf[0] = 0x720004;
11347 }
11348
11349 static void
11350 Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11351 {
11352   slotbuf[0] = 0x730004;
11353 }
11354
11355 static void
11356 Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11357 {
11358   slotbuf[0] = 0x340004;
11359 }
11360
11361 static void
11362 Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11363 {
11364   slotbuf[0] = 0x350004;
11365 }
11366
11367 static void
11368 Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11369 {
11370   slotbuf[0] = 0x360004;
11371 }
11372
11373 static void
11374 Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11375 {
11376   slotbuf[0] = 0x370004;
11377 }
11378
11379 static void
11380 Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11381 {
11382   slotbuf[0] = 0x640004;
11383 }
11384
11385 static void
11386 Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11387 {
11388   slotbuf[0] = 0x650004;
11389 }
11390
11391 static void
11392 Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11393 {
11394   slotbuf[0] = 0x660004;
11395 }
11396
11397 static void
11398 Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11399 {
11400   slotbuf[0] = 0x670004;
11401 }
11402
11403 static void
11404 Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11405 {
11406   slotbuf[0] = 0x240004;
11407 }
11408
11409 static void
11410 Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11411 {
11412   slotbuf[0] = 0x250004;
11413 }
11414
11415 static void
11416 Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11417 {
11418   slotbuf[0] = 0x260004;
11419 }
11420
11421 static void
11422 Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11423 {
11424   slotbuf[0] = 0x270004;
11425 }
11426
11427 static void
11428 Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11429 {
11430   slotbuf[0] = 0x780004;
11431 }
11432
11433 static void
11434 Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11435 {
11436   slotbuf[0] = 0x790004;
11437 }
11438
11439 static void
11440 Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11441 {
11442   slotbuf[0] = 0x7a0004;
11443 }
11444
11445 static void
11446 Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11447 {
11448   slotbuf[0] = 0x7b0004;
11449 }
11450
11451 static void
11452 Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11453 {
11454   slotbuf[0] = 0x7c0004;
11455 }
11456
11457 static void
11458 Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11459 {
11460   slotbuf[0] = 0x7d0004;
11461 }
11462
11463 static void
11464 Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11465 {
11466   slotbuf[0] = 0x7e0004;
11467 }
11468
11469 static void
11470 Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11471 {
11472   slotbuf[0] = 0x7f0004;
11473 }
11474
11475 static void
11476 Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11477 {
11478   slotbuf[0] = 0x380004;
11479 }
11480
11481 static void
11482 Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11483 {
11484   slotbuf[0] = 0x390004;
11485 }
11486
11487 static void
11488 Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11489 {
11490   slotbuf[0] = 0x3a0004;
11491 }
11492
11493 static void
11494 Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11495 {
11496   slotbuf[0] = 0x3b0004;
11497 }
11498
11499 static void
11500 Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11501 {
11502   slotbuf[0] = 0x3c0004;
11503 }
11504
11505 static void
11506 Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11507 {
11508   slotbuf[0] = 0x3d0004;
11509 }
11510
11511 static void
11512 Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11513 {
11514   slotbuf[0] = 0x3e0004;
11515 }
11516
11517 static void
11518 Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11519 {
11520   slotbuf[0] = 0x3f0004;
11521 }
11522
11523 static void
11524 Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11525 {
11526   slotbuf[0] = 0x680004;
11527 }
11528
11529 static void
11530 Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11531 {
11532   slotbuf[0] = 0x690004;
11533 }
11534
11535 static void
11536 Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11537 {
11538   slotbuf[0] = 0x6a0004;
11539 }
11540
11541 static void
11542 Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11543 {
11544   slotbuf[0] = 0x6b0004;
11545 }
11546
11547 static void
11548 Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11549 {
11550   slotbuf[0] = 0x6c0004;
11551 }
11552
11553 static void
11554 Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11555 {
11556   slotbuf[0] = 0x6d0004;
11557 }
11558
11559 static void
11560 Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11561 {
11562   slotbuf[0] = 0x6e0004;
11563 }
11564
11565 static void
11566 Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11567 {
11568   slotbuf[0] = 0x6f0004;
11569 }
11570
11571 static void
11572 Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11573 {
11574   slotbuf[0] = 0x280004;
11575 }
11576
11577 static void
11578 Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11579 {
11580   slotbuf[0] = 0x290004;
11581 }
11582
11583 static void
11584 Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11585 {
11586   slotbuf[0] = 0x2a0004;
11587 }
11588
11589 static void
11590 Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11591 {
11592   slotbuf[0] = 0x2b0004;
11593 }
11594
11595 static void
11596 Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11597 {
11598   slotbuf[0] = 0x2c0004;
11599 }
11600
11601 static void
11602 Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11603 {
11604   slotbuf[0] = 0x2d0004;
11605 }
11606
11607 static void
11608 Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11609 {
11610   slotbuf[0] = 0x2e0004;
11611 }
11612
11613 static void
11614 Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11615 {
11616   slotbuf[0] = 0x2f0004;
11617 }
11618
11619 static void
11620 Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11621 {
11622   slotbuf[0] = 0x580004;
11623 }
11624
11625 static void
11626 Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11627 {
11628   slotbuf[0] = 0x480004;
11629 }
11630
11631 static void
11632 Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11633 {
11634   slotbuf[0] = 0x590004;
11635 }
11636
11637 static void
11638 Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11639 {
11640   slotbuf[0] = 0x490004;
11641 }
11642
11643 static void
11644 Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11645 {
11646   slotbuf[0] = 0x5a0004;
11647 }
11648
11649 static void
11650 Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11651 {
11652   slotbuf[0] = 0x4a0004;
11653 }
11654
11655 static void
11656 Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11657 {
11658   slotbuf[0] = 0x5b0004;
11659 }
11660
11661 static void
11662 Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11663 {
11664   slotbuf[0] = 0x4b0004;
11665 }
11666
11667 static void
11668 Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11669 {
11670   slotbuf[0] = 0x180004;
11671 }
11672
11673 static void
11674 Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11675 {
11676   slotbuf[0] = 0x80004;
11677 }
11678
11679 static void
11680 Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11681 {
11682   slotbuf[0] = 0x190004;
11683 }
11684
11685 static void
11686 Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11687 {
11688   slotbuf[0] = 0x90004;
11689 }
11690
11691 static void
11692 Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11693 {
11694   slotbuf[0] = 0x1a0004;
11695 }
11696
11697 static void
11698 Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11699 {
11700   slotbuf[0] = 0xa0004;
11701 }
11702
11703 static void
11704 Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11705 {
11706   slotbuf[0] = 0x1b0004;
11707 }
11708
11709 static void
11710 Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11711 {
11712   slotbuf[0] = 0xb0004;
11713 }
11714
11715 static void
11716 Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11717 {
11718   slotbuf[0] = 0x900004;
11719 }
11720
11721 static void
11722 Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11723 {
11724   slotbuf[0] = 0x800004;
11725 }
11726
11727 static void
11728 Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
11729 {
11730   slotbuf[0] = 0xc10000;
11731 }
11732
11733 static void
11734 Opcode_mul16u_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
11735 {
11736   slotbuf[0] = 0x9b000;
11737 }
11738
11739 static void
11740 Opcode_mul16u_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
11741 {
11742   slotbuf[0] = 0xc1000;
11743 }
11744
11745 static void
11746 Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
11747 {
11748   slotbuf[0] = 0xd10000;
11749 }
11750
11751 static void
11752 Opcode_mul16s_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
11753 {
11754   slotbuf[0] = 0x9c000;
11755 }
11756
11757 static void
11758 Opcode_mul16s_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
11759 {
11760   slotbuf[0] = 0xd1000;
11761 }
11762
11763 static void
11764 Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11765 {
11766   slotbuf[0] = 0x32000;
11767 }
11768
11769 static void
11770 Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11771 {
11772   slotbuf[0] = 0x132000;
11773 }
11774
11775 static void
11776 Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11777 {
11778   slotbuf[0] = 0x612000;
11779 }
11780
11781 static void
11782 Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11783 {
11784   slotbuf[0] = 0x32100;
11785 }
11786
11787 static void
11788 Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11789 {
11790   slotbuf[0] = 0x132100;
11791 }
11792
11793 static void
11794 Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11795 {
11796   slotbuf[0] = 0x612100;
11797 }
11798
11799 static void
11800 Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11801 {
11802   slotbuf[0] = 0x32200;
11803 }
11804
11805 static void
11806 Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11807 {
11808   slotbuf[0] = 0x132200;
11809 }
11810
11811 static void
11812 Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11813 {
11814   slotbuf[0] = 0x612200;
11815 }
11816
11817 static void
11818 Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11819 {
11820   slotbuf[0] = 0x32300;
11821 }
11822
11823 static void
11824 Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11825 {
11826   slotbuf[0] = 0x132300;
11827 }
11828
11829 static void
11830 Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11831 {
11832   slotbuf[0] = 0x612300;
11833 }
11834
11835 static void
11836 Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
11837 {
11838   slotbuf[0] = 0x31000;
11839 }
11840
11841 static void
11842 Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
11843 {
11844   slotbuf[0] = 0x131000;
11845 }
11846
11847 static void
11848 Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
11849 {
11850   slotbuf[0] = 0x611000;
11851 }
11852
11853 static void
11854 Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
11855 {
11856   slotbuf[0] = 0x31100;
11857 }
11858
11859 static void
11860 Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
11861 {
11862   slotbuf[0] = 0x131100;
11863 }
11864
11865 static void
11866 Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
11867 {
11868   slotbuf[0] = 0x611100;
11869 }
11870
11871 static void
11872 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
11873 {
11874   slotbuf[0] = 0x3010;
11875 }
11876
11877 static void
11878 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
11879 {
11880   slotbuf[0] = 0x7000;
11881 }
11882
11883 static void
11884 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
11885 {
11886   slotbuf[0] = 0x3e200;
11887 }
11888
11889 static void
11890 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
11891 {
11892   slotbuf[0] = 0x13e200;
11893 }
11894
11895 static void
11896 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
11897 {
11898   slotbuf[0] = 0x13e300;
11899 }
11900
11901 static void
11902 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
11903 {
11904   slotbuf[0] = 0x3e400;
11905 }
11906
11907 static void
11908 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
11909 {
11910   slotbuf[0] = 0x13e400;
11911 }
11912
11913 static void
11914 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
11915 {
11916   slotbuf[0] = 0x61e400;
11917 }
11918
11919 static void
11920 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
11921 {
11922   slotbuf[0] = 0x4000;
11923 }
11924
11925 static void
11926 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
11927 {
11928   slotbuf[0] = 0xf02d;
11929 }
11930
11931 static void
11932 Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11933 {
11934   slotbuf[0] = 0x39000;
11935 }
11936
11937 static void
11938 Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11939 {
11940   slotbuf[0] = 0x139000;
11941 }
11942
11943 static void
11944 Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11945 {
11946   slotbuf[0] = 0x619000;
11947 }
11948
11949 static void
11950 Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11951 {
11952   slotbuf[0] = 0x3a000;
11953 }
11954
11955 static void
11956 Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11957 {
11958   slotbuf[0] = 0x13a000;
11959 }
11960
11961 static void
11962 Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11963 {
11964   slotbuf[0] = 0x61a000;
11965 }
11966
11967 static void
11968 Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11969 {
11970   slotbuf[0] = 0x39100;
11971 }
11972
11973 static void
11974 Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11975 {
11976   slotbuf[0] = 0x139100;
11977 }
11978
11979 static void
11980 Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11981 {
11982   slotbuf[0] = 0x619100;
11983 }
11984
11985 static void
11986 Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11987 {
11988   slotbuf[0] = 0x3a100;
11989 }
11990
11991 static void
11992 Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11993 {
11994   slotbuf[0] = 0x13a100;
11995 }
11996
11997 static void
11998 Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11999 {
12000   slotbuf[0] = 0x61a100;
12001 }
12002
12003 static void
12004 Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12005 {
12006   slotbuf[0] = 0x38000;
12007 }
12008
12009 static void
12010 Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12011 {
12012   slotbuf[0] = 0x138000;
12013 }
12014
12015 static void
12016 Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12017 {
12018   slotbuf[0] = 0x618000;
12019 }
12020
12021 static void
12022 Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12023 {
12024   slotbuf[0] = 0x38100;
12025 }
12026
12027 static void
12028 Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12029 {
12030   slotbuf[0] = 0x138100;
12031 }
12032
12033 static void
12034 Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12035 {
12036   slotbuf[0] = 0x618100;
12037 }
12038
12039 static void
12040 Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
12041 {
12042   slotbuf[0] = 0x36000;
12043 }
12044
12045 static void
12046 Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
12047 {
12048   slotbuf[0] = 0x136000;
12049 }
12050
12051 static void
12052 Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
12053 {
12054   slotbuf[0] = 0x616000;
12055 }
12056
12057 static void
12058 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
12059 {
12060   slotbuf[0] = 0x3e900;
12061 }
12062
12063 static void
12064 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
12065 {
12066   slotbuf[0] = 0x13e900;
12067 }
12068
12069 static void
12070 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
12071 {
12072   slotbuf[0] = 0x61e900;
12073 }
12074
12075 static void
12076 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
12077 {
12078   slotbuf[0] = 0x3ec00;
12079 }
12080
12081 static void
12082 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
12083 {
12084   slotbuf[0] = 0x13ec00;
12085 }
12086
12087 static void
12088 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
12089 {
12090   slotbuf[0] = 0x61ec00;
12091 }
12092
12093 static void
12094 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
12095 {
12096   slotbuf[0] = 0x3ed00;
12097 }
12098
12099 static void
12100 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
12101 {
12102   slotbuf[0] = 0x13ed00;
12103 }
12104
12105 static void
12106 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
12107 {
12108   slotbuf[0] = 0x61ed00;
12109 }
12110
12111 static void
12112 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12113 {
12114   slotbuf[0] = 0x36800;
12115 }
12116
12117 static void
12118 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12119 {
12120   slotbuf[0] = 0x136800;
12121 }
12122
12123 static void
12124 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12125 {
12126   slotbuf[0] = 0x616800;
12127 }
12128
12129 static void
12130 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
12131 {
12132   slotbuf[0] = 0xf1e000;
12133 }
12134
12135 static void
12136 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
12137 {
12138   slotbuf[0] = 0xf1e010;
12139 }
12140
12141 static void
12142 Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
12143 {
12144   slotbuf[0] = 0x135900;
12145 }
12146
12147 static void
12148 Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12149 {
12150   slotbuf[0] = 0x20000;
12151 }
12152
12153 static void
12154 Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
12155 {
12156   slotbuf[0] = 0x120000;
12157 }
12158
12159 static void
12160 Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12161 {
12162   slotbuf[0] = 0x220000;
12163 }
12164
12165 static void
12166 Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
12167 {
12168   slotbuf[0] = 0x320000;
12169 }
12170
12171 static void
12172 Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12173 {
12174   slotbuf[0] = 0x420000;
12175 }
12176
12177 static void
12178 Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
12179 {
12180   slotbuf[0] = 0x8000;
12181 }
12182
12183 static void
12184 Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
12185 {
12186   slotbuf[0] = 0x9000;
12187 }
12188
12189 static void
12190 Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
12191 {
12192   slotbuf[0] = 0xa000;
12193 }
12194
12195 static void
12196 Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
12197 {
12198   slotbuf[0] = 0xb000;
12199 }
12200
12201 static void
12202 Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
12203 {
12204   slotbuf[0] = 0x76;
12205 }
12206
12207 static void
12208 Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
12209 {
12210   slotbuf[0] = 0x1076;
12211 }
12212
12213 static void
12214 Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
12215 {
12216   slotbuf[0] = 0xc30000;
12217 }
12218
12219 static void
12220 Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
12221 {
12222   slotbuf[0] = 0xd30000;
12223 }
12224
12225 static void
12226 Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
12227 {
12228   slotbuf[0] = 0x30400;
12229 }
12230
12231 static void
12232 Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
12233 {
12234   slotbuf[0] = 0x130400;
12235 }
12236
12237 static void
12238 Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
12239 {
12240   slotbuf[0] = 0x610400;
12241 }
12242
12243 static void
12244 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
12245 {
12246   slotbuf[0] = 0x3ea00;
12247 }
12248
12249 static void
12250 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
12251 {
12252   slotbuf[0] = 0x13ea00;
12253 }
12254
12255 static void
12256 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
12257 {
12258   slotbuf[0] = 0x61ea00;
12259 }
12260
12261 static void
12262 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12263 {
12264   slotbuf[0] = 0x3f000;
12265 }
12266
12267 static void
12268 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12269 {
12270   slotbuf[0] = 0x13f000;
12271 }
12272
12273 static void
12274 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12275 {
12276   slotbuf[0] = 0x61f000;
12277 }
12278
12279 static void
12280 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12281 {
12282   slotbuf[0] = 0x3f100;
12283 }
12284
12285 static void
12286 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12287 {
12288   slotbuf[0] = 0x13f100;
12289 }
12290
12291 static void
12292 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12293 {
12294   slotbuf[0] = 0x61f100;
12295 }
12296
12297 static void
12298 Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
12299 {
12300   slotbuf[0] = 0x3f200;
12301 }
12302
12303 static void
12304 Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
12305 {
12306   slotbuf[0] = 0x13f200;
12307 }
12308
12309 static void
12310 Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
12311 {
12312   slotbuf[0] = 0x61f200;
12313 }
12314
12315 static void
12316 Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
12317 {
12318   slotbuf[0] = 0x70c2;
12319 }
12320
12321 static void
12322 Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12323 {
12324   slotbuf[0] = 0x70e2;
12325 }
12326
12327 static void
12328 Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
12329 {
12330   slotbuf[0] = 0x70d2;
12331 }
12332
12333 static void
12334 Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12335 {
12336   slotbuf[0] = 0x270d2;
12337 }
12338
12339 static void
12340 Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12341 {
12342   slotbuf[0] = 0x370d2;
12343 }
12344
12345 static void
12346 Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
12347 {
12348   slotbuf[0] = 0x70f2;
12349 }
12350
12351 static void
12352 Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
12353 {
12354   slotbuf[0] = 0xf10000;
12355 }
12356
12357 static void
12358 Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
12359 {
12360   slotbuf[0] = 0xf12000;
12361 }
12362
12363 static void
12364 Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
12365 {
12366   slotbuf[0] = 0xf11000;
12367 }
12368
12369 static void
12370 Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
12371 {
12372   slotbuf[0] = 0xf13000;
12373 }
12374
12375 static void
12376 Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12377 {
12378   slotbuf[0] = 0x7042;
12379 }
12380
12381 static void
12382 Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12383 {
12384   slotbuf[0] = 0x7052;
12385 }
12386
12387 static void
12388 Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12389 {
12390   slotbuf[0] = 0x47082;
12391 }
12392
12393 static void
12394 Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12395 {
12396   slotbuf[0] = 0x57082;
12397 }
12398
12399 static void
12400 Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12401 {
12402   slotbuf[0] = 0x7062;
12403 }
12404
12405 static void
12406 Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
12407 {
12408   slotbuf[0] = 0x7072;
12409 }
12410
12411 static void
12412 Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12413 {
12414   slotbuf[0] = 0x7002;
12415 }
12416
12417 static void
12418 Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
12419 {
12420   slotbuf[0] = 0x7012;
12421 }
12422
12423 static void
12424 Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
12425 {
12426   slotbuf[0] = 0x7022;
12427 }
12428
12429 static void
12430 Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
12431 {
12432   slotbuf[0] = 0x7032;
12433 }
12434
12435 static void
12436 Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
12437 {
12438   slotbuf[0] = 0x7082;
12439 }
12440
12441 static void
12442 Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12443 {
12444   slotbuf[0] = 0x27082;
12445 }
12446
12447 static void
12448 Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12449 {
12450   slotbuf[0] = 0x37082;
12451 }
12452
12453 static void
12454 Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
12455 {
12456   slotbuf[0] = 0xf19000;
12457 }
12458
12459 static void
12460 Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
12461 {
12462   slotbuf[0] = 0xf18000;
12463 }
12464
12465 static void
12466 Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12467 {
12468   slotbuf[0] = 0x135300;
12469 }
12470
12471 static void
12472 Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12473 {
12474   slotbuf[0] = 0x35300;
12475 }
12476
12477 static void
12478 Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12479 {
12480   slotbuf[0] = 0x615300;
12481 }
12482
12483 static void
12484 Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
12485 {
12486   slotbuf[0] = 0x35a00;
12487 }
12488
12489 static void
12490 Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
12491 {
12492   slotbuf[0] = 0x135a00;
12493 }
12494
12495 static void
12496 Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
12497 {
12498   slotbuf[0] = 0x615a00;
12499 }
12500
12501 static void
12502 Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12503 {
12504   slotbuf[0] = 0x35b00;
12505 }
12506
12507 static void
12508 Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12509 {
12510   slotbuf[0] = 0x135b00;
12511 }
12512
12513 static void
12514 Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12515 {
12516   slotbuf[0] = 0x615b00;
12517 }
12518
12519 static void
12520 Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12521 {
12522   slotbuf[0] = 0x35c00;
12523 }
12524
12525 static void
12526 Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12527 {
12528   slotbuf[0] = 0x135c00;
12529 }
12530
12531 static void
12532 Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12533 {
12534   slotbuf[0] = 0x615c00;
12535 }
12536
12537 static void
12538 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12539 {
12540   slotbuf[0] = 0x50c000;
12541 }
12542
12543 static void
12544 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12545 {
12546   slotbuf[0] = 0x50d000;
12547 }
12548
12549 static void
12550 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12551 {
12552   slotbuf[0] = 0x50b000;
12553 }
12554
12555 static void
12556 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12557 {
12558   slotbuf[0] = 0x50f000;
12559 }
12560
12561 static void
12562 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12563 {
12564   slotbuf[0] = 0x50e000;
12565 }
12566
12567 static void
12568 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12569 {
12570   slotbuf[0] = 0x504000;
12571 }
12572
12573 static void
12574 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12575 {
12576   slotbuf[0] = 0x505000;
12577 }
12578
12579 static void
12580 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12581 {
12582   slotbuf[0] = 0x503000;
12583 }
12584
12585 static void
12586 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12587 {
12588   slotbuf[0] = 0x507000;
12589 }
12590
12591 static void
12592 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12593 {
12594   slotbuf[0] = 0x506000;
12595 }
12596
12597 static void
12598 Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
12599 {
12600   slotbuf[0] = 0xf1f000;
12601 }
12602
12603 static void
12604 Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
12605 {
12606   slotbuf[0] = 0x501000;
12607 }
12608
12609 static void
12610 Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
12611 {
12612   slotbuf[0] = 0x509000;
12613 }
12614
12615 static void
12616 Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
12617 {
12618   slotbuf[0] = 0x3e000;
12619 }
12620
12621 static void
12622 Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
12623 {
12624   slotbuf[0] = 0x13e000;
12625 }
12626
12627 static void
12628 Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
12629 {
12630   slotbuf[0] = 0x61e000;
12631 }
12632
12633 static void
12634 Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
12635 {
12636   slotbuf[0] = 0x330000;
12637 }
12638
12639 static void
12640 Opcode_clamps_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12641 {
12642   slotbuf[0] = 0x33000;
12643 }
12644
12645 static void
12646 Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
12647 {
12648   slotbuf[0] = 0x430000;
12649 }
12650
12651 static void
12652 Opcode_min_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12653 {
12654   slotbuf[0] = 0x43000;
12655 }
12656
12657 static void
12658 Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
12659 {
12660   slotbuf[0] = 0x530000;
12661 }
12662
12663 static void
12664 Opcode_max_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12665 {
12666   slotbuf[0] = 0x53000;
12667 }
12668
12669 static void
12670 Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12671 {
12672   slotbuf[0] = 0x630000;
12673 }
12674
12675 static void
12676 Opcode_minu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12677 {
12678   slotbuf[0] = 0x63000;
12679 }
12680
12681 static void
12682 Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12683 {
12684   slotbuf[0] = 0x730000;
12685 }
12686
12687 static void
12688 Opcode_maxu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12689 {
12690   slotbuf[0] = 0x73000;
12691 }
12692
12693 static void
12694 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
12695 {
12696   slotbuf[0] = 0x40e000;
12697 }
12698
12699 static void
12700 Opcode_nsa_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12701 {
12702   slotbuf[0] = 0x40e00;
12703 }
12704
12705 static void
12706 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
12707 {
12708   slotbuf[0] = 0x40f000;
12709 }
12710
12711 static void
12712 Opcode_nsau_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12713 {
12714   slotbuf[0] = 0x40f00;
12715 }
12716
12717 static void
12718 Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
12719 {
12720   slotbuf[0] = 0x230000;
12721 }
12722
12723 static void
12724 Opcode_sext_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12725 {
12726   slotbuf[0] = 0x9f000;
12727 }
12728
12729 static void
12730 Opcode_sext_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12731 {
12732   slotbuf[0] = 0x8000;
12733 }
12734
12735 static void
12736 Opcode_sext_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12737 {
12738   slotbuf[0] = 0x23000;
12739 }
12740
12741 static void
12742 Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
12743 {
12744   slotbuf[0] = 0xb002;
12745 }
12746
12747 static void
12748 Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
12749 {
12750   slotbuf[0] = 0xf002;
12751 }
12752
12753 static void
12754 Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
12755 {
12756   slotbuf[0] = 0xe002;
12757 }
12758
12759 static void
12760 Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12761 {
12762   slotbuf[0] = 0x30c00;
12763 }
12764
12765 static void
12766 Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12767 {
12768   slotbuf[0] = 0x130c00;
12769 }
12770
12771 static void
12772 Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12773 {
12774   slotbuf[0] = 0x610c00;
12775 }
12776
12777 static void
12778 Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
12779 {
12780   slotbuf[0] = 0xc20000;
12781 }
12782
12783 static void
12784 Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
12785 {
12786   slotbuf[0] = 0xd20000;
12787 }
12788
12789 static void
12790 Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12791 {
12792   slotbuf[0] = 0xe20000;
12793 }
12794
12795 static void
12796 Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
12797 {
12798   slotbuf[0] = 0xf20000;
12799 }
12800
12801 static void
12802 Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
12803 {
12804   slotbuf[0] = 0x820000;
12805 }
12806
12807 static void
12808 Opcode_mull_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12809 {
12810   slotbuf[0] = 0x9d000;
12811 }
12812
12813 static void
12814 Opcode_mull_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12815 {
12816   slotbuf[0] = 0x82000;
12817 }
12818
12819 static void
12820 Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
12821 {
12822   slotbuf[0] = 0xa20000;
12823 }
12824
12825 static void
12826 Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
12827 {
12828   slotbuf[0] = 0xb20000;
12829 }
12830
12831 static void
12832 Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12833 {
12834   slotbuf[0] = 0xe30e80;
12835 }
12836
12837 static void
12838 Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12839 {
12840   slotbuf[0] = 0xf3e800;
12841 }
12842
12843 static void
12844 Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12845 {
12846   slotbuf[0] = 0xe30e90;
12847 }
12848
12849 static void
12850 Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12851 {
12852   slotbuf[0] = 0xf3e900;
12853 }
12854
12855 static void
12856 Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12857 {
12858   slotbuf[0] = 0xa0000;
12859 }
12860
12861 static void
12862 Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12863 {
12864   slotbuf[0] = 0x1a0000;
12865 }
12866
12867 static void
12868 Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12869 {
12870   slotbuf[0] = 0x2a0000;
12871 }
12872
12873 static void
12874 Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12875 {
12876   slotbuf[0] = 0x4a0000;
12877 }
12878
12879 static void
12880 Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12881 {
12882   slotbuf[0] = 0x5a0000;
12883 }
12884
12885 static void
12886 Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12887 {
12888   slotbuf[0] = 0xcb0000;
12889 }
12890
12891 static void
12892 Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12893 {
12894   slotbuf[0] = 0xdb0000;
12895 }
12896
12897 static void
12898 Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12899 {
12900   slotbuf[0] = 0x8b0000;
12901 }
12902
12903 static void
12904 Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12905 {
12906   slotbuf[0] = 0x9b0000;
12907 }
12908
12909 static void
12910 Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12911 {
12912   slotbuf[0] = 0xab0000;
12913 }
12914
12915 static void
12916 Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12917 {
12918   slotbuf[0] = 0xbb0000;
12919 }
12920
12921 static void
12922 Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12923 {
12924   slotbuf[0] = 0xfa0010;
12925 }
12926
12927 static void
12928 Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12929 {
12930   slotbuf[0] = 0xfa0000;
12931 }
12932
12933 static void
12934 Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12935 {
12936   slotbuf[0] = 0xfa0060;
12937 }
12938
12939 static void
12940 Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12941 {
12942   slotbuf[0] = 0x1b0000;
12943 }
12944
12945 static void
12946 Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12947 {
12948   slotbuf[0] = 0x2b0000;
12949 }
12950
12951 static void
12952 Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12953 {
12954   slotbuf[0] = 0x3b0000;
12955 }
12956
12957 static void
12958 Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12959 {
12960   slotbuf[0] = 0x4b0000;
12961 }
12962
12963 static void
12964 Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12965 {
12966   slotbuf[0] = 0x5b0000;
12967 }
12968
12969 static void
12970 Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12971 {
12972   slotbuf[0] = 0x6b0000;
12973 }
12974
12975 static void
12976 Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12977 {
12978   slotbuf[0] = 0x7b0000;
12979 }
12980
12981 static void
12982 Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12983 {
12984   slotbuf[0] = 0xca0000;
12985 }
12986
12987 static void
12988 Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12989 {
12990   slotbuf[0] = 0xda0000;
12991 }
12992
12993 static void
12994 Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12995 {
12996   slotbuf[0] = 0x8a0000;
12997 }
12998
12999 static void
13000 Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
13001 {
13002   slotbuf[0] = 0xba0000;
13003 }
13004
13005 static void
13006 Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
13007 {
13008   slotbuf[0] = 0xaa0000;
13009 }
13010
13011 static void
13012 Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
13013 {
13014   slotbuf[0] = 0x9a0000;
13015 }
13016
13017 static void
13018 Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
13019 {
13020   slotbuf[0] = 0xea0000;
13021 }
13022
13023 static void
13024 Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
13025 {
13026   slotbuf[0] = 0xfa0040;
13027 }
13028
13029 static void
13030 Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
13031 {
13032   slotbuf[0] = 0xfa0050;
13033 }
13034
13035 static void
13036 Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
13037 {
13038   slotbuf[0] = 0x3;
13039 }
13040
13041 static void
13042 Opcode_lsiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
13043 {
13044   slotbuf[0] = 0x8003;
13045 }
13046
13047 static void
13048 Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf)
13049 {
13050   slotbuf[0] = 0x80000;
13051 }
13052
13053 static void
13054 Opcode_lsxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
13055 {
13056   slotbuf[0] = 0x180000;
13057 }
13058
13059 static void
13060 Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf)
13061 {
13062   slotbuf[0] = 0x4003;
13063 }
13064
13065 static void
13066 Opcode_ssiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
13067 {
13068   slotbuf[0] = 0xc003;
13069 }
13070
13071 static void
13072 Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf)
13073 {
13074   slotbuf[0] = 0x480000;
13075 }
13076
13077 static void
13078 Opcode_ssxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
13079 {
13080   slotbuf[0] = 0x580000;
13081 }
13082
13083 static void
13084 Opcode_beqz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13085 {
13086   slotbuf[0] = 0xa8000000;
13087   slotbuf[1] = 0;
13088 }
13089
13090 static void
13091 Opcode_bnez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13092 {
13093   slotbuf[0] = 0xc0000000;
13094   slotbuf[1] = 0;
13095 }
13096
13097 static void
13098 Opcode_bgez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13099 {
13100   slotbuf[0] = 0xb0000000;
13101   slotbuf[1] = 0;
13102 }
13103
13104 static void
13105 Opcode_bltz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13106 {
13107   slotbuf[0] = 0xb8000000;
13108   slotbuf[1] = 0;
13109 }
13110
13111 static void
13112 Opcode_beqi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13113 {
13114   slotbuf[0] = 0x40000000;
13115   slotbuf[1] = 0;
13116 }
13117
13118 static void
13119 Opcode_bnei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13120 {
13121   slotbuf[0] = 0x98000000;
13122   slotbuf[1] = 0;
13123 }
13124
13125 static void
13126 Opcode_bgei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13127 {
13128   slotbuf[0] = 0x50000000;
13129   slotbuf[1] = 0;
13130 }
13131
13132 static void
13133 Opcode_blti_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13134 {
13135   slotbuf[0] = 0x70000000;
13136   slotbuf[1] = 0;
13137 }
13138
13139 static void
13140 Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13141 {
13142   slotbuf[0] = 0x60000000;
13143   slotbuf[1] = 0;
13144 }
13145
13146 static void
13147 Opcode_bltui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13148 {
13149   slotbuf[0] = 0x80000000;
13150   slotbuf[1] = 0;
13151 }
13152
13153 static void
13154 Opcode_bbci_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13155 {
13156   slotbuf[0] = 0x8000000;
13157   slotbuf[1] = 0;
13158 }
13159
13160 static void
13161 Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13162 {
13163   slotbuf[0] = 0x10000000;
13164   slotbuf[1] = 0;
13165 }
13166
13167 static void
13168 Opcode_beq_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13169 {
13170   slotbuf[0] = 0x38000000;
13171   slotbuf[1] = 0;
13172 }
13173
13174 static void
13175 Opcode_bne_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13176 {
13177   slotbuf[0] = 0x90000000;
13178   slotbuf[1] = 0;
13179 }
13180
13181 static void
13182 Opcode_bge_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13183 {
13184   slotbuf[0] = 0x48000000;
13185   slotbuf[1] = 0;
13186 }
13187
13188 static void
13189 Opcode_blt_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13190 {
13191   slotbuf[0] = 0x68000000;
13192   slotbuf[1] = 0;
13193 }
13194
13195 static void
13196 Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13197 {
13198   slotbuf[0] = 0x58000000;
13199   slotbuf[1] = 0;
13200 }
13201
13202 static void
13203 Opcode_bltu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13204 {
13205   slotbuf[0] = 0x78000000;
13206   slotbuf[1] = 0;
13207 }
13208
13209 static void
13210 Opcode_bany_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13211 {
13212   slotbuf[0] = 0x20000000;
13213   slotbuf[1] = 0;
13214 }
13215
13216 static void
13217 Opcode_bnone_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13218 {
13219   slotbuf[0] = 0xa0000000;
13220   slotbuf[1] = 0;
13221 }
13222
13223 static void
13224 Opcode_ball_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13225 {
13226   slotbuf[0] = 0x18000000;
13227   slotbuf[1] = 0;
13228 }
13229
13230 static void
13231 Opcode_bnall_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13232 {
13233   slotbuf[0] = 0x88000000;
13234   slotbuf[1] = 0;
13235 }
13236
13237 static void
13238 Opcode_bbc_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13239 {
13240   slotbuf[0] = 0x28000000;
13241   slotbuf[1] = 0;
13242 }
13243
13244 static void
13245 Opcode_bbs_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13246 {
13247   slotbuf[0] = 0x30000000;
13248   slotbuf[1] = 0;
13249 }
13250
13251 xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
13252   Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13253 };
13254
13255 xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
13256   Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13257 };
13258
13259 xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
13260   Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13261 };
13262
13263 xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
13264   Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13265 };
13266
13267 xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
13268   Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13269 };
13270
13271 xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
13272   Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13273 };
13274
13275 xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
13276   Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13277 };
13278
13279 xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
13280   Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13281 };
13282
13283 xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
13284   Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13285 };
13286
13287 xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
13288   Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13289 };
13290
13291 xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
13292   Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13293 };
13294
13295 xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
13296   Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13297 };
13298
13299 xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
13300   Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13301 };
13302
13303 xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
13304   Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13305 };
13306
13307 xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
13308   Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13309 };
13310
13311 xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
13312   0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13313 };
13314
13315 xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
13316   Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13317 };
13318
13319 xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
13320   Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13321 };
13322
13323 xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
13324   Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13325 };
13326
13327 xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
13328   Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13329 };
13330
13331 xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
13332   Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13333 };
13334
13335 xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
13336   Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13337 };
13338
13339 xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
13340   Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13341 };
13342
13343 xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
13344   Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13345 };
13346
13347 xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
13348   Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13349 };
13350
13351 xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
13352   Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13353 };
13354
13355 xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
13356   0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
13357 };
13358
13359 xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
13360   0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, Opcode_addi_n_Slot_xt_flix64_slot2_encode, 0
13361 };
13362
13363 xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
13364   0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13365 };
13366
13367 xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
13368   0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13369 };
13370
13371 xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
13372   0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13373 };
13374
13375 xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
13376   0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
13377 };
13378
13379 xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
13380   0, 0, Opcode_mov_n_Slot_inst16b_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot1_encode, Opcode_mov_n_Slot_xt_flix64_slot2_encode, 0
13381 };
13382
13383 xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
13384   0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, Opcode_movi_n_Slot_xt_flix64_slot2_encode, 0
13385 };
13386
13387 xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
13388   0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13389 };
13390
13391 xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
13392   0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13393 };
13394
13395 xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
13396   0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
13397 };
13398
13399 xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
13400   Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13401 };
13402
13403 xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
13404   Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13405 };
13406
13407 xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
13408   Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot1_encode, 0, 0
13409 };
13410
13411 xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
13412   Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot1_encode, 0, 0
13413 };
13414
13415 xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
13416   Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot1_encode, Opcode_add_Slot_xt_flix64_slot2_encode, 0
13417 };
13418
13419 xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
13420   Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot1_encode, Opcode_sub_Slot_xt_flix64_slot2_encode, 0
13421 };
13422
13423 xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
13424   Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot1_encode, Opcode_addx2_Slot_xt_flix64_slot2_encode, 0
13425 };
13426
13427 xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
13428   Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot1_encode, Opcode_addx4_Slot_xt_flix64_slot2_encode, 0
13429 };
13430
13431 xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
13432   Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot1_encode, 0, 0
13433 };
13434
13435 xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
13436   Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_xt_flix64_slot0_encode, Opcode_subx2_Slot_xt_flix64_slot0_encode, 0, 0, 0
13437 };
13438
13439 xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
13440   Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_xt_flix64_slot0_encode, Opcode_subx4_Slot_xt_flix64_slot0_encode, 0, 0, 0
13441 };
13442
13443 xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
13444   Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_xt_flix64_slot0_encode, Opcode_subx8_Slot_xt_flix64_slot0_encode, 0, 0, 0
13445 };
13446
13447 xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
13448   Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot1_encode, Opcode_and_Slot_xt_flix64_slot2_encode, 0
13449 };
13450
13451 xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
13452   Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot1_encode, Opcode_or_Slot_xt_flix64_slot2_encode, 0
13453 };
13454
13455 xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
13456   Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot1_encode, Opcode_xor_Slot_xt_flix64_slot2_encode, 0
13457 };
13458
13459 xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
13460   Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13461 };
13462
13463 xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
13464   Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13465 };
13466
13467 xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
13468   Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13469 };
13470
13471 xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
13472   Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13473 };
13474
13475 xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
13476   Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13477 };
13478
13479 xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
13480   Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13481 };
13482
13483 xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
13484   Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13485 };
13486
13487 xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
13488   Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13489 };
13490
13491 xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
13492   Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13493 };
13494
13495 xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
13496   Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13497 };
13498
13499 xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
13500   Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13501 };
13502
13503 xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
13504   Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13505 };
13506
13507 xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
13508   Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13509 };
13510
13511 xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
13512   Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13513 };
13514
13515 xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
13516   Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13517 };
13518
13519 xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
13520   Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13521 };
13522
13523 xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
13524   Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13525 };
13526
13527 xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
13528   Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13529 };
13530
13531 xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
13532   Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13533 };
13534
13535 xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
13536   Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13537 };
13538
13539 xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
13540   Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13541 };
13542
13543 xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
13544   Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13545 };
13546
13547 xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
13548   Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13549 };
13550
13551 xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
13552   Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13553 };
13554
13555 xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
13556   Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13557 };
13558
13559 xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
13560   Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13561 };
13562
13563 xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
13564   Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot1_encode, 0, 0
13565 };
13566
13567 xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
13568   Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13569 };
13570
13571 xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
13572   Opcode_j_Slot_inst_encode, 0, 0, 0, 0, Opcode_j_Slot_xt_flix64_slot1_encode, 0, 0
13573 };
13574
13575 xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
13576   Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, Opcode_jx_Slot_xt_flix64_slot1_encode, 0, 0
13577 };
13578
13579 xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
13580   Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_xt_flix64_slot0_encode, Opcode_l16ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
13581 };
13582
13583 xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
13584   Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_xt_flix64_slot0_encode, Opcode_l16si_Slot_xt_flix64_slot0_encode, 0, 0, 0
13585 };
13586
13587 xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
13588   Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_xt_flix64_slot0_encode, Opcode_l32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13589 };
13590
13591 xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
13592   Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_xt_flix64_slot0_encode, Opcode_l32r_Slot_xt_flix64_slot0_encode, 0, 0, 0
13593 };
13594
13595 xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
13596   Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_xt_flix64_slot0_encode, Opcode_l8ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
13597 };
13598
13599 xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
13600   Opcode_loop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13601 };
13602
13603 xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
13604   Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13605 };
13606
13607 xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
13608   Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13609 };
13610
13611 xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
13612   Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot1_encode, 0, 0
13613 };
13614
13615 xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
13616   Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot1_encode, 0, 0
13617 };
13618
13619 xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
13620   Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot1_encode, 0, 0
13621 };
13622
13623 xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
13624   Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot1_encode, 0, 0
13625 };
13626
13627 xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
13628   Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot1_encode, 0, 0
13629 };
13630
13631 xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
13632   Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot1_encode, Opcode_neg_Slot_xt_flix64_slot2_encode, 0
13633 };
13634
13635 xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
13636   Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_xt_flix64_slot0_encode, Opcode_abs_Slot_xt_flix64_slot0_encode, 0, Opcode_abs_Slot_xt_flix64_slot2_encode, 0
13637 };
13638
13639 xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
13640   Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot1_encode, Opcode_nop_Slot_xt_flix64_slot2_encode, Opcode_nop_Slot_xt_flix64_slot3_encode
13641 };
13642
13643 xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
13644   Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13645 };
13646
13647 xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
13648   Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_xt_flix64_slot0_encode, Opcode_s16i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13649 };
13650
13651 xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
13652   Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_xt_flix64_slot0_encode, Opcode_s32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13653 };
13654
13655 xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
13656   Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_xt_flix64_slot0_encode, Opcode_s8i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13657 };
13658
13659 xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
13660   Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_xt_flix64_slot0_encode, Opcode_ssr_Slot_xt_flix64_slot0_encode, 0, 0, 0
13661 };
13662
13663 xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
13664   Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot1_encode, 0, 0
13665 };
13666
13667 xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
13668   Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, 0, 0, 0
13669 };
13670
13671 xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
13672   Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, 0, 0, 0
13673 };
13674
13675 xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
13676   Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_xt_flix64_slot0_encode, Opcode_ssai_Slot_xt_flix64_slot0_encode, 0, 0, 0
13677 };
13678
13679 xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
13680   Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot1_encode, 0, 0
13681 };
13682
13683 xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
13684   Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot1_encode, 0, 0
13685 };
13686
13687 xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
13688   Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot1_encode, Opcode_srl_Slot_xt_flix64_slot2_encode, 0
13689 };
13690
13691 xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
13692   Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot1_encode, Opcode_sra_Slot_xt_flix64_slot2_encode, 0
13693 };
13694
13695 xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
13696   Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot1_encode, 0, 0
13697 };
13698
13699 xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
13700   Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot1_encode, Opcode_srai_Slot_xt_flix64_slot2_encode, 0
13701 };
13702
13703 xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
13704   Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot1_encode, Opcode_srli_Slot_xt_flix64_slot2_encode, 0
13705 };
13706
13707 xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
13708   Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13709 };
13710
13711 xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
13712   Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13713 };
13714
13715 xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
13716   Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13717 };
13718
13719 xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
13720   Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13721 };
13722
13723 xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
13724   Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13725 };
13726
13727 xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
13728   Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13729 };
13730
13731 xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
13732   Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13733 };
13734
13735 xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
13736   Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13737 };
13738
13739 xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
13740   Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13741 };
13742
13743 xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
13744   Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13745 };
13746
13747 xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
13748   Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13749 };
13750
13751 xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
13752   Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13753 };
13754
13755 xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
13756   Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13757 };
13758
13759 xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
13760   Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13761 };
13762
13763 xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
13764   Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13765 };
13766
13767 xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
13768   Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13769 };
13770
13771 xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
13772   Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13773 };
13774
13775 xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
13776   Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13777 };
13778
13779 xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
13780   Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13781 };
13782
13783 xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
13784   Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13785 };
13786
13787 xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
13788   Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13789 };
13790
13791 xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
13792   Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13793 };
13794
13795 xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
13796   Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13797 };
13798
13799 xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
13800   Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13801 };
13802
13803 xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
13804   Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13805 };
13806
13807 xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
13808   Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13809 };
13810
13811 xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
13812   Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13813 };
13814
13815 xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
13816   Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13817 };
13818
13819 xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
13820   Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13821 };
13822
13823 xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
13824   Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13825 };
13826
13827 xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
13828   Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13829 };
13830
13831 xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
13832   Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13833 };
13834
13835 xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
13836   Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13837 };
13838
13839 xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
13840   Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13841 };
13842
13843 xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
13844   Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13845 };
13846
13847 xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
13848   Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13849 };
13850
13851 xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
13852   Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13853 };
13854
13855 xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
13856   Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13857 };
13858
13859 xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
13860   Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13861 };
13862
13863 xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
13864   Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13865 };
13866
13867 xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
13868   Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13869 };
13870
13871 xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
13872   Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13873 };
13874
13875 xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
13876   Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13877 };
13878
13879 xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
13880   Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13881 };
13882
13883 xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
13884   Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13885 };
13886
13887 xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
13888   Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13889 };
13890
13891 xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
13892   Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13893 };
13894
13895 xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
13896   Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13897 };
13898
13899 xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
13900   Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13901 };
13902
13903 xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
13904   Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13905 };
13906
13907 xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
13908   Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13909 };
13910
13911 xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
13912   Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13913 };
13914
13915 xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
13916   Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13917 };
13918
13919 xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
13920   Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13921 };
13922
13923 xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
13924   Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13925 };
13926
13927 xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
13928   Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13929 };
13930
13931 xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
13932   Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13933 };
13934
13935 xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
13936   Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13937 };
13938
13939 xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
13940   Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13941 };
13942
13943 xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
13944   Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13945 };
13946
13947 xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
13948   Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13949 };
13950
13951 xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
13952   Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13953 };
13954
13955 xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
13956   Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13957 };
13958
13959 xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
13960   Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13961 };
13962
13963 xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
13964   Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13965 };
13966
13967 xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
13968   Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13969 };
13970
13971 xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
13972   Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13973 };
13974
13975 xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
13976   Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13977 };
13978
13979 xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
13980   Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13981 };
13982
13983 xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
13984   Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13985 };
13986
13987 xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
13988   Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13989 };
13990
13991 xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
13992   Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13993 };
13994
13995 xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
13996   Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13997 };
13998
13999 xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
14000   Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14001 };
14002
14003 xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
14004   Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14005 };
14006
14007 xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
14008   Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14009 };
14010
14011 xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
14012   Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14013 };
14014
14015 xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
14016   Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14017 };
14018
14019 xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
14020   Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14021 };
14022
14023 xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
14024   Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14025 };
14026
14027 xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
14028   Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14029 };
14030
14031 xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
14032   Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14033 };
14034
14035 xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
14036   Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14037 };
14038
14039 xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
14040   Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14041 };
14042
14043 xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
14044   Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14045 };
14046
14047 xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
14048   Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14049 };
14050
14051 xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
14052   Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14053 };
14054
14055 xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
14056   Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14057 };
14058
14059 xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
14060   Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14061 };
14062
14063 xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
14064   Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14065 };
14066
14067 xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
14068   Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14069 };
14070
14071 xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
14072   Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14073 };
14074
14075 xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
14076   Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14077 };
14078
14079 xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
14080   Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14081 };
14082
14083 xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
14084   Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14085 };
14086
14087 xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
14088   Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14089 };
14090
14091 xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
14092   Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14093 };
14094
14095 xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
14096   Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14097 };
14098
14099 xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
14100   Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14101 };
14102
14103 xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
14104   Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14105 };
14106
14107 xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
14108   Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14109 };
14110
14111 xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
14112   Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14113 };
14114
14115 xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = {
14116   Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14117 };
14118
14119 xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = {
14120   Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14121 };
14122
14123 xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = {
14124   Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14125 };
14126
14127 xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = {
14128   Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14129 };
14130
14131 xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = {
14132   Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14133 };
14134
14135 xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = {
14136   Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14137 };
14138
14139 xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
14140   Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14141 };
14142
14143 xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
14144   Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14145 };
14146
14147 xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
14148   Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14149 };
14150
14151 xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
14152   Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14153 };
14154
14155 xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
14156   Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14157 };
14158
14159 xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
14160   Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14161 };
14162
14163 xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
14164   Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14165 };
14166
14167 xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
14168   Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14169 };
14170
14171 xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
14172   Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14173 };
14174
14175 xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
14176   Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14177 };
14178
14179 xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
14180   Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14181 };
14182
14183 xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
14184   Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14185 };
14186
14187 xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
14188   Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14189 };
14190
14191 xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
14192   Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14193 };
14194
14195 xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
14196   Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14197 };
14198
14199 xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
14200   Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14201 };
14202
14203 xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
14204   Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14205 };
14206
14207 xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
14208   Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14209 };
14210
14211 xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
14212   Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14213 };
14214
14215 xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
14216   Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14217 };
14218
14219 xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
14220   Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14221 };
14222
14223 xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
14224   Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14225 };
14226
14227 xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
14228   Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14229 };
14230
14231 xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
14232   Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14233 };
14234
14235 xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
14236   Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14237 };
14238
14239 xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
14240   Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14241 };
14242
14243 xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
14244   Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14245 };
14246
14247 xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
14248   Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14249 };
14250
14251 xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
14252   Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14253 };
14254
14255 xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
14256   Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14257 };
14258
14259 xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
14260   Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14261 };
14262
14263 xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
14264   Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14265 };
14266
14267 xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
14268   Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14269 };
14270
14271 xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
14272   Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14273 };
14274
14275 xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
14276   Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14277 };
14278
14279 xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
14280   Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14281 };
14282
14283 xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
14284   Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14285 };
14286
14287 xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
14288   Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14289 };
14290
14291 xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
14292   Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14293 };
14294
14295 xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
14296   Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14297 };
14298
14299 xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
14300   Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14301 };
14302
14303 xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
14304   Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14305 };
14306
14307 xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
14308   Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14309 };
14310
14311 xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
14312   Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14313 };
14314
14315 xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
14316   Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14317 };
14318
14319 xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
14320   Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14321 };
14322
14323 xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
14324   Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14325 };
14326
14327 xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
14328   Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14329 };
14330
14331 xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
14332   Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14333 };
14334
14335 xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
14336   Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14337 };
14338
14339 xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
14340   Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14341 };
14342
14343 xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
14344   Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14345 };
14346
14347 xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
14348   Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14349 };
14350
14351 xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
14352   Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14353 };
14354
14355 xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
14356   Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14357 };
14358
14359 xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
14360   Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14361 };
14362
14363 xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
14364   Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14365 };
14366
14367 xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
14368   Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14369 };
14370
14371 xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
14372   Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14373 };
14374
14375 xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
14376   Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14377 };
14378
14379 xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
14380   Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14381 };
14382
14383 xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
14384   Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14385 };
14386
14387 xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
14388   Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14389 };
14390
14391 xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
14392   Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14393 };
14394
14395 xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
14396   Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14397 };
14398
14399 xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
14400   Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14401 };
14402
14403 xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
14404   Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14405 };
14406
14407 xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
14408   Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14409 };
14410
14411 xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
14412   Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14413 };
14414
14415 xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
14416   Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14417 };
14418
14419 xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
14420   Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14421 };
14422
14423 xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
14424   Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14425 };
14426
14427 xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
14428   Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14429 };
14430
14431 xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
14432   Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14433 };
14434
14435 xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
14436   Opcode_mul16u_Slot_inst_encode, 0, 0, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot1_encode, 0, 0
14437 };
14438
14439 xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
14440   Opcode_mul16s_Slot_inst_encode, 0, 0, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot1_encode, 0, 0
14441 };
14442
14443 xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
14444   Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14445 };
14446
14447 xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
14448   Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14449 };
14450
14451 xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
14452   Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14453 };
14454
14455 xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
14456   Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14457 };
14458
14459 xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
14460   Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14461 };
14462
14463 xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
14464   Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14465 };
14466
14467 xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
14468   Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14469 };
14470
14471 xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
14472   Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14473 };
14474
14475 xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
14476   Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14477 };
14478
14479 xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
14480   Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14481 };
14482
14483 xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
14484   Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14485 };
14486
14487 xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
14488   Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14489 };
14490
14491 xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
14492   Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14493 };
14494
14495 xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
14496   Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14497 };
14498
14499 xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
14500   Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14501 };
14502
14503 xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
14504   Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14505 };
14506
14507 xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
14508   Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14509 };
14510
14511 xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
14512   Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14513 };
14514
14515 xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
14516   Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14517 };
14518
14519 xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
14520   Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14521 };
14522
14523 xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
14524   Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14525 };
14526
14527 xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
14528   Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14529 };
14530
14531 xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
14532   Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14533 };
14534
14535 xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
14536   Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14537 };
14538
14539 xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
14540   Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14541 };
14542
14543 xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
14544   Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14545 };
14546
14547 xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
14548   Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14549 };
14550
14551 xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
14552   0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
14553 };
14554
14555 xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
14556   Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14557 };
14558
14559 xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
14560   Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14561 };
14562
14563 xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
14564   Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14565 };
14566
14567 xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
14568   Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14569 };
14570
14571 xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
14572   Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14573 };
14574
14575 xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
14576   Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14577 };
14578
14579 xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
14580   Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14581 };
14582
14583 xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
14584   Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14585 };
14586
14587 xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
14588   Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14589 };
14590
14591 xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
14592   Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14593 };
14594
14595 xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
14596   Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14597 };
14598
14599 xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
14600   Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14601 };
14602
14603 xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
14604   Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14605 };
14606
14607 xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
14608   Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14609 };
14610
14611 xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
14612   Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14613 };
14614
14615 xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
14616   Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14617 };
14618
14619 xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
14620   Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14621 };
14622
14623 xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
14624   Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14625 };
14626
14627 xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
14628   Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14629 };
14630
14631 xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
14632   Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14633 };
14634
14635 xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
14636   Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14637 };
14638
14639 xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
14640   Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14641 };
14642
14643 xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
14644   Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14645 };
14646
14647 xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
14648   Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14649 };
14650
14651 xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
14652   Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14653 };
14654
14655 xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
14656   Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14657 };
14658
14659 xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
14660   Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14661 };
14662
14663 xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
14664   Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14665 };
14666
14667 xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
14668   Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14669 };
14670
14671 xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
14672   Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14673 };
14674
14675 xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
14676   Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14677 };
14678
14679 xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
14680   Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14681 };
14682
14683 xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
14684   Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14685 };
14686
14687 xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
14688   Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14689 };
14690
14691 xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
14692   Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14693 };
14694
14695 xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
14696   Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14697 };
14698
14699 xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
14700   Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14701 };
14702
14703 xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
14704   Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14705 };
14706
14707 xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
14708   Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14709 };
14710
14711 xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
14712   Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14713 };
14714
14715 xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
14716   Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14717 };
14718
14719 xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
14720   Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14721 };
14722
14723 xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
14724   Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14725 };
14726
14727 xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
14728   Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14729 };
14730
14731 xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
14732   Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14733 };
14734
14735 xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
14736   Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14737 };
14738
14739 xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
14740   Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14741 };
14742
14743 xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
14744   Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14745 };
14746
14747 xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
14748   Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14749 };
14750
14751 xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
14752   Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14753 };
14754
14755 xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
14756   Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14757 };
14758
14759 xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
14760   Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14761 };
14762
14763 xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
14764   Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14765 };
14766
14767 xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
14768   Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14769 };
14770
14771 xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
14772   Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14773 };
14774
14775 xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
14776   Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14777 };
14778
14779 xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
14780   Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14781 };
14782
14783 xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
14784   Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14785 };
14786
14787 xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
14788   Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14789 };
14790
14791 xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
14792   Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14793 };
14794
14795 xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
14796   Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14797 };
14798
14799 xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
14800   Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14801 };
14802
14803 xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
14804   Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14805 };
14806
14807 xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
14808   Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14809 };
14810
14811 xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
14812   Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14813 };
14814
14815 xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
14816   Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14817 };
14818
14819 xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
14820   Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14821 };
14822
14823 xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
14824   Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14825 };
14826
14827 xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
14828   Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14829 };
14830
14831 xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
14832   Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14833 };
14834
14835 xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
14836   Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14837 };
14838
14839 xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
14840   Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14841 };
14842
14843 xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
14844   Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14845 };
14846
14847 xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
14848   Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14849 };
14850
14851 xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
14852   Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14853 };
14854
14855 xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
14856   Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14857 };
14858
14859 xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
14860   Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14861 };
14862
14863 xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
14864   Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14865 };
14866
14867 xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
14868   Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14869 };
14870
14871 xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
14872   Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14873 };
14874
14875 xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
14876   Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14877 };
14878
14879 xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
14880   Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14881 };
14882
14883 xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
14884   Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14885 };
14886
14887 xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
14888   Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14889 };
14890
14891 xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
14892   Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14893 };
14894
14895 xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
14896   Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14897 };
14898
14899 xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
14900   Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14901 };
14902
14903 xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
14904   Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14905 };
14906
14907 xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
14908   Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14909 };
14910
14911 xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
14912   Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14913 };
14914
14915 xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
14916   Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14917 };
14918
14919 xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
14920   Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14921 };
14922
14923 xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
14924   Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14925 };
14926
14927 xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
14928   Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14929 };
14930
14931 xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
14932   Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14933 };
14934
14935 xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
14936   Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14937 };
14938
14939 xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
14940   Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14941 };
14942
14943 xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
14944   Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14945 };
14946
14947 xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
14948   Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14949 };
14950
14951 xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
14952   Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14953 };
14954
14955 xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
14956   Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14957 };
14958
14959 xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
14960   Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14961 };
14962
14963 xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
14964   Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14965 };
14966
14967 xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
14968   Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14969 };
14970
14971 xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
14972   Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14973 };
14974
14975 xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
14976   Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14977 };
14978
14979 xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
14980   Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14981 };
14982
14983 xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
14984   Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14985 };
14986
14987 xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
14988   Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14989 };
14990
14991 xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
14992   Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14993 };
14994
14995 xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
14996   Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14997 };
14998
14999 xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
15000   Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15001 };
15002
15003 xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
15004   Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15005 };
15006
15007 xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
15008   Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15009 };
15010
15011 xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
15012   Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15013 };
15014
15015 xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
15016   Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15017 };
15018
15019 xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
15020   Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15021 };
15022
15023 xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
15024   Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_xt_flix64_slot0_encode, Opcode_clamps_Slot_xt_flix64_slot0_encode, 0, 0, 0
15025 };
15026
15027 xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
15028   Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_xt_flix64_slot0_encode, Opcode_min_Slot_xt_flix64_slot0_encode, 0, 0, 0
15029 };
15030
15031 xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
15032   Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_xt_flix64_slot0_encode, Opcode_max_Slot_xt_flix64_slot0_encode, 0, 0, 0
15033 };
15034
15035 xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
15036   Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_xt_flix64_slot0_encode, Opcode_minu_Slot_xt_flix64_slot0_encode, 0, 0, 0
15037 };
15038
15039 xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
15040   Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_xt_flix64_slot0_encode, Opcode_maxu_Slot_xt_flix64_slot0_encode, 0, 0, 0
15041 };
15042
15043 xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
15044   Opcode_nsa_Slot_inst_encode, 0, 0, Opcode_nsa_Slot_xt_flix64_slot0_encode, Opcode_nsa_Slot_xt_flix64_slot0_encode, 0, 0, 0
15045 };
15046
15047 xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
15048   Opcode_nsau_Slot_inst_encode, 0, 0, Opcode_nsau_Slot_xt_flix64_slot0_encode, Opcode_nsau_Slot_xt_flix64_slot0_encode, 0, 0, 0
15049 };
15050
15051 xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
15052   Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot1_encode, Opcode_sext_Slot_xt_flix64_slot2_encode, 0
15053 };
15054
15055 xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
15056   Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15057 };
15058
15059 xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
15060   Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15061 };
15062
15063 xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
15064   Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15065 };
15066
15067 xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
15068   Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15069 };
15070
15071 xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
15072   Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15073 };
15074
15075 xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
15076   Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15077 };
15078
15079 xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
15080   Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15081 };
15082
15083 xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
15084   Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15085 };
15086
15087 xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
15088   Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15089 };
15090
15091 xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
15092   Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15093 };
15094
15095 xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
15096   Opcode_mull_Slot_inst_encode, 0, 0, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot1_encode, 0, 0
15097 };
15098
15099 xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
15100   Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15101 };
15102
15103 xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
15104   Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15105 };
15106
15107 xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = {
15108   Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15109 };
15110
15111 xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = {
15112   Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15113 };
15114
15115 xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = {
15116   Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15117 };
15118
15119 xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = {
15120   Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15121 };
15122
15123 xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = {
15124   Opcode_add_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15125 };
15126
15127 xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = {
15128   Opcode_sub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15129 };
15130
15131 xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = {
15132   Opcode_mul_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15133 };
15134
15135 xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = {
15136   Opcode_madd_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15137 };
15138
15139 xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = {
15140   Opcode_msub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15141 };
15142
15143 xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = {
15144   Opcode_movf_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15145 };
15146
15147 xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = {
15148   Opcode_movt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15149 };
15150
15151 xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = {
15152   Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15153 };
15154
15155 xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = {
15156   Opcode_movnez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15157 };
15158
15159 xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = {
15160   Opcode_movltz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15161 };
15162
15163 xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = {
15164   Opcode_movgez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15165 };
15166
15167 xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = {
15168   Opcode_abs_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15169 };
15170
15171 xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = {
15172   Opcode_mov_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15173 };
15174
15175 xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = {
15176   Opcode_neg_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15177 };
15178
15179 xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = {
15180   Opcode_un_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15181 };
15182
15183 xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = {
15184   Opcode_oeq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15185 };
15186
15187 xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = {
15188   Opcode_ueq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15189 };
15190
15191 xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = {
15192   Opcode_olt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15193 };
15194
15195 xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = {
15196   Opcode_ult_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15197 };
15198
15199 xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = {
15200   Opcode_ole_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15201 };
15202
15203 xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = {
15204   Opcode_ule_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15205 };
15206
15207 xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = {
15208   Opcode_float_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15209 };
15210
15211 xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = {
15212   Opcode_ufloat_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15213 };
15214
15215 xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = {
15216   Opcode_round_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15217 };
15218
15219 xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = {
15220   Opcode_ceil_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15221 };
15222
15223 xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = {
15224   Opcode_floor_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15225 };
15226
15227 xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = {
15228   Opcode_trunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15229 };
15230
15231 xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = {
15232   Opcode_utrunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15233 };
15234
15235 xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = {
15236   Opcode_rfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15237 };
15238
15239 xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = {
15240   Opcode_wfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15241 };
15242
15243 xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = {
15244   Opcode_lsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15245 };
15246
15247 xtensa_opcode_encode_fn Opcode_lsiu_encode_fns[] = {
15248   Opcode_lsiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15249 };
15250
15251 xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = {
15252   Opcode_lsx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15253 };
15254
15255 xtensa_opcode_encode_fn Opcode_lsxu_encode_fns[] = {
15256   Opcode_lsxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15257 };
15258
15259 xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = {
15260   Opcode_ssi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15261 };
15262
15263 xtensa_opcode_encode_fn Opcode_ssiu_encode_fns[] = {
15264   Opcode_ssiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15265 };
15266
15267 xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = {
15268   Opcode_ssx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15269 };
15270
15271 xtensa_opcode_encode_fn Opcode_ssxu_encode_fns[] = {
15272   Opcode_ssxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15273 };
15274
15275 xtensa_opcode_encode_fn Opcode_beqz_w18_encode_fns[] = {
15276   0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w18_Slot_xt_flix64_slot3_encode
15277 };
15278
15279 xtensa_opcode_encode_fn Opcode_bnez_w18_encode_fns[] = {
15280   0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w18_Slot_xt_flix64_slot3_encode
15281 };
15282
15283 xtensa_opcode_encode_fn Opcode_bgez_w18_encode_fns[] = {
15284   0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w18_Slot_xt_flix64_slot3_encode
15285 };
15286
15287 xtensa_opcode_encode_fn Opcode_bltz_w18_encode_fns[] = {
15288   0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w18_Slot_xt_flix64_slot3_encode
15289 };
15290
15291 xtensa_opcode_encode_fn Opcode_beqi_w18_encode_fns[] = {
15292   0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w18_Slot_xt_flix64_slot3_encode
15293 };
15294
15295 xtensa_opcode_encode_fn Opcode_bnei_w18_encode_fns[] = {
15296   0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w18_Slot_xt_flix64_slot3_encode
15297 };
15298
15299 xtensa_opcode_encode_fn Opcode_bgei_w18_encode_fns[] = {
15300   0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w18_Slot_xt_flix64_slot3_encode
15301 };
15302
15303 xtensa_opcode_encode_fn Opcode_blti_w18_encode_fns[] = {
15304   0, 0, 0, 0, 0, 0, 0, Opcode_blti_w18_Slot_xt_flix64_slot3_encode
15305 };
15306
15307 xtensa_opcode_encode_fn Opcode_bgeui_w18_encode_fns[] = {
15308   0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode
15309 };
15310
15311 xtensa_opcode_encode_fn Opcode_bltui_w18_encode_fns[] = {
15312   0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w18_Slot_xt_flix64_slot3_encode
15313 };
15314
15315 xtensa_opcode_encode_fn Opcode_bbci_w18_encode_fns[] = {
15316   0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w18_Slot_xt_flix64_slot3_encode
15317 };
15318
15319 xtensa_opcode_encode_fn Opcode_bbsi_w18_encode_fns[] = {
15320   0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode
15321 };
15322
15323 xtensa_opcode_encode_fn Opcode_beq_w18_encode_fns[] = {
15324   0, 0, 0, 0, 0, 0, 0, Opcode_beq_w18_Slot_xt_flix64_slot3_encode
15325 };
15326
15327 xtensa_opcode_encode_fn Opcode_bne_w18_encode_fns[] = {
15328   0, 0, 0, 0, 0, 0, 0, Opcode_bne_w18_Slot_xt_flix64_slot3_encode
15329 };
15330
15331 xtensa_opcode_encode_fn Opcode_bge_w18_encode_fns[] = {
15332   0, 0, 0, 0, 0, 0, 0, Opcode_bge_w18_Slot_xt_flix64_slot3_encode
15333 };
15334
15335 xtensa_opcode_encode_fn Opcode_blt_w18_encode_fns[] = {
15336   0, 0, 0, 0, 0, 0, 0, Opcode_blt_w18_Slot_xt_flix64_slot3_encode
15337 };
15338
15339 xtensa_opcode_encode_fn Opcode_bgeu_w18_encode_fns[] = {
15340   0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode
15341 };
15342
15343 xtensa_opcode_encode_fn Opcode_bltu_w18_encode_fns[] = {
15344   0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w18_Slot_xt_flix64_slot3_encode
15345 };
15346
15347 xtensa_opcode_encode_fn Opcode_bany_w18_encode_fns[] = {
15348   0, 0, 0, 0, 0, 0, 0, Opcode_bany_w18_Slot_xt_flix64_slot3_encode
15349 };
15350
15351 xtensa_opcode_encode_fn Opcode_bnone_w18_encode_fns[] = {
15352   0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w18_Slot_xt_flix64_slot3_encode
15353 };
15354
15355 xtensa_opcode_encode_fn Opcode_ball_w18_encode_fns[] = {
15356   0, 0, 0, 0, 0, 0, 0, Opcode_ball_w18_Slot_xt_flix64_slot3_encode
15357 };
15358
15359 xtensa_opcode_encode_fn Opcode_bnall_w18_encode_fns[] = {
15360   0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w18_Slot_xt_flix64_slot3_encode
15361 };
15362
15363 xtensa_opcode_encode_fn Opcode_bbc_w18_encode_fns[] = {
15364   0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w18_Slot_xt_flix64_slot3_encode
15365 };
15366
15367 xtensa_opcode_encode_fn Opcode_bbs_w18_encode_fns[] = {
15368   0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w18_Slot_xt_flix64_slot3_encode
15369 };
15370
15371 \f
15372 /* Opcode table.  */
15373
15374 static xtensa_opcode_internal opcodes[] = {
15375   { "excw", 0 /* xt_iclass_excw */,
15376     0,
15377     Opcode_excw_encode_fns, 0, 0 },
15378   { "rfe", 1 /* xt_iclass_rfe */,
15379     XTENSA_OPCODE_IS_JUMP,
15380     Opcode_rfe_encode_fns, 0, 0 },
15381   { "rfde", 2 /* xt_iclass_rfde */,
15382     XTENSA_OPCODE_IS_JUMP,
15383     Opcode_rfde_encode_fns, 0, 0 },
15384   { "syscall", 3 /* xt_iclass_syscall */,
15385     0,
15386     Opcode_syscall_encode_fns, 0, 0 },
15387   { "simcall", 4 /* xt_iclass_simcall */,
15388     0,
15389     Opcode_simcall_encode_fns, 0, 0 },
15390   { "call12", 5 /* xt_iclass_call12 */,
15391     XTENSA_OPCODE_IS_CALL,
15392     Opcode_call12_encode_fns, 0, 0 },
15393   { "call8", 6 /* xt_iclass_call8 */,
15394     XTENSA_OPCODE_IS_CALL,
15395     Opcode_call8_encode_fns, 0, 0 },
15396   { "call4", 7 /* xt_iclass_call4 */,
15397     XTENSA_OPCODE_IS_CALL,
15398     Opcode_call4_encode_fns, 0, 0 },
15399   { "callx12", 8 /* xt_iclass_callx12 */,
15400     XTENSA_OPCODE_IS_CALL,
15401     Opcode_callx12_encode_fns, 0, 0 },
15402   { "callx8", 9 /* xt_iclass_callx8 */,
15403     XTENSA_OPCODE_IS_CALL,
15404     Opcode_callx8_encode_fns, 0, 0 },
15405   { "callx4", 10 /* xt_iclass_callx4 */,
15406     XTENSA_OPCODE_IS_CALL,
15407     Opcode_callx4_encode_fns, 0, 0 },
15408   { "entry", 11 /* xt_iclass_entry */,
15409     0,
15410     Opcode_entry_encode_fns, 0, 0 },
15411   { "movsp", 12 /* xt_iclass_movsp */,
15412     0,
15413     Opcode_movsp_encode_fns, 0, 0 },
15414   { "rotw", 13 /* xt_iclass_rotw */,
15415     0,
15416     Opcode_rotw_encode_fns, 0, 0 },
15417   { "retw", 14 /* xt_iclass_retw */,
15418     XTENSA_OPCODE_IS_JUMP,
15419     Opcode_retw_encode_fns, 0, 0 },
15420   { "retw.n", 14 /* xt_iclass_retw */,
15421     XTENSA_OPCODE_IS_JUMP,
15422     Opcode_retw_n_encode_fns, 0, 0 },
15423   { "rfwo", 15 /* xt_iclass_rfwou */,
15424     XTENSA_OPCODE_IS_JUMP,
15425     Opcode_rfwo_encode_fns, 0, 0 },
15426   { "rfwu", 15 /* xt_iclass_rfwou */,
15427     XTENSA_OPCODE_IS_JUMP,
15428     Opcode_rfwu_encode_fns, 0, 0 },
15429   { "l32e", 16 /* xt_iclass_l32e */,
15430     0,
15431     Opcode_l32e_encode_fns, 0, 0 },
15432   { "s32e", 17 /* xt_iclass_s32e */,
15433     0,
15434     Opcode_s32e_encode_fns, 0, 0 },
15435   { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
15436     0,
15437     Opcode_rsr_windowbase_encode_fns, 0, 0 },
15438   { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
15439     0,
15440     Opcode_wsr_windowbase_encode_fns, 0, 0 },
15441   { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
15442     0,
15443     Opcode_xsr_windowbase_encode_fns, 0, 0 },
15444   { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
15445     0,
15446     Opcode_rsr_windowstart_encode_fns, 0, 0 },
15447   { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
15448     0,
15449     Opcode_wsr_windowstart_encode_fns, 0, 0 },
15450   { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
15451     0,
15452     Opcode_xsr_windowstart_encode_fns, 0, 0 },
15453   { "add.n", 24 /* xt_iclass_add.n */,
15454     0,
15455     Opcode_add_n_encode_fns, 0, 0 },
15456   { "addi.n", 25 /* xt_iclass_addi.n */,
15457     0,
15458     Opcode_addi_n_encode_fns, 0, 0 },
15459   { "beqz.n", 26 /* xt_iclass_bz6 */,
15460     XTENSA_OPCODE_IS_BRANCH,
15461     Opcode_beqz_n_encode_fns, 0, 0 },
15462   { "bnez.n", 26 /* xt_iclass_bz6 */,
15463     XTENSA_OPCODE_IS_BRANCH,
15464     Opcode_bnez_n_encode_fns, 0, 0 },
15465   { "ill.n", 27 /* xt_iclass_ill.n */,
15466     0,
15467     Opcode_ill_n_encode_fns, 0, 0 },
15468   { "l32i.n", 28 /* xt_iclass_loadi4 */,
15469     0,
15470     Opcode_l32i_n_encode_fns, 0, 0 },
15471   { "mov.n", 29 /* xt_iclass_mov.n */,
15472     0,
15473     Opcode_mov_n_encode_fns, 0, 0 },
15474   { "movi.n", 30 /* xt_iclass_movi.n */,
15475     0,
15476     Opcode_movi_n_encode_fns, 0, 0 },
15477   { "nop.n", 31 /* xt_iclass_nopn */,
15478     0,
15479     Opcode_nop_n_encode_fns, 0, 0 },
15480   { "ret.n", 32 /* xt_iclass_retn */,
15481     XTENSA_OPCODE_IS_JUMP,
15482     Opcode_ret_n_encode_fns, 0, 0 },
15483   { "s32i.n", 33 /* xt_iclass_storei4 */,
15484     0,
15485     Opcode_s32i_n_encode_fns, 0, 0 },
15486   { "rur.threadptr", 34 /* rur_threadptr */,
15487     0,
15488     Opcode_rur_threadptr_encode_fns, 0, 0 },
15489   { "wur.threadptr", 35 /* wur_threadptr */,
15490     0,
15491     Opcode_wur_threadptr_encode_fns, 0, 0 },
15492   { "addi", 36 /* xt_iclass_addi */,
15493     0,
15494     Opcode_addi_encode_fns, 0, 0 },
15495   { "addmi", 37 /* xt_iclass_addmi */,
15496     0,
15497     Opcode_addmi_encode_fns, 0, 0 },
15498   { "add", 38 /* xt_iclass_addsub */,
15499     0,
15500     Opcode_add_encode_fns, 0, 0 },
15501   { "sub", 38 /* xt_iclass_addsub */,
15502     0,
15503     Opcode_sub_encode_fns, 0, 0 },
15504   { "addx2", 38 /* xt_iclass_addsub */,
15505     0,
15506     Opcode_addx2_encode_fns, 0, 0 },
15507   { "addx4", 38 /* xt_iclass_addsub */,
15508     0,
15509     Opcode_addx4_encode_fns, 0, 0 },
15510   { "addx8", 38 /* xt_iclass_addsub */,
15511     0,
15512     Opcode_addx8_encode_fns, 0, 0 },
15513   { "subx2", 38 /* xt_iclass_addsub */,
15514     0,
15515     Opcode_subx2_encode_fns, 0, 0 },
15516   { "subx4", 38 /* xt_iclass_addsub */,
15517     0,
15518     Opcode_subx4_encode_fns, 0, 0 },
15519   { "subx8", 38 /* xt_iclass_addsub */,
15520     0,
15521     Opcode_subx8_encode_fns, 0, 0 },
15522   { "and", 39 /* xt_iclass_bit */,
15523     0,
15524     Opcode_and_encode_fns, 0, 0 },
15525   { "or", 39 /* xt_iclass_bit */,
15526     0,
15527     Opcode_or_encode_fns, 0, 0 },
15528   { "xor", 39 /* xt_iclass_bit */,
15529     0,
15530     Opcode_xor_encode_fns, 0, 0 },
15531   { "beqi", 40 /* xt_iclass_bsi8 */,
15532     XTENSA_OPCODE_IS_BRANCH,
15533     Opcode_beqi_encode_fns, 0, 0 },
15534   { "bnei", 40 /* xt_iclass_bsi8 */,
15535     XTENSA_OPCODE_IS_BRANCH,
15536     Opcode_bnei_encode_fns, 0, 0 },
15537   { "bgei", 40 /* xt_iclass_bsi8 */,
15538     XTENSA_OPCODE_IS_BRANCH,
15539     Opcode_bgei_encode_fns, 0, 0 },
15540   { "blti", 40 /* xt_iclass_bsi8 */,
15541     XTENSA_OPCODE_IS_BRANCH,
15542     Opcode_blti_encode_fns, 0, 0 },
15543   { "bbci", 41 /* xt_iclass_bsi8b */,
15544     XTENSA_OPCODE_IS_BRANCH,
15545     Opcode_bbci_encode_fns, 0, 0 },
15546   { "bbsi", 41 /* xt_iclass_bsi8b */,
15547     XTENSA_OPCODE_IS_BRANCH,
15548     Opcode_bbsi_encode_fns, 0, 0 },
15549   { "bgeui", 42 /* xt_iclass_bsi8u */,
15550     XTENSA_OPCODE_IS_BRANCH,
15551     Opcode_bgeui_encode_fns, 0, 0 },
15552   { "bltui", 42 /* xt_iclass_bsi8u */,
15553     XTENSA_OPCODE_IS_BRANCH,
15554     Opcode_bltui_encode_fns, 0, 0 },
15555   { "beq", 43 /* xt_iclass_bst8 */,
15556     XTENSA_OPCODE_IS_BRANCH,
15557     Opcode_beq_encode_fns, 0, 0 },
15558   { "bne", 43 /* xt_iclass_bst8 */,
15559     XTENSA_OPCODE_IS_BRANCH,
15560     Opcode_bne_encode_fns, 0, 0 },
15561   { "bge", 43 /* xt_iclass_bst8 */,
15562     XTENSA_OPCODE_IS_BRANCH,
15563     Opcode_bge_encode_fns, 0, 0 },
15564   { "blt", 43 /* xt_iclass_bst8 */,
15565     XTENSA_OPCODE_IS_BRANCH,
15566     Opcode_blt_encode_fns, 0, 0 },
15567   { "bgeu", 43 /* xt_iclass_bst8 */,
15568     XTENSA_OPCODE_IS_BRANCH,
15569     Opcode_bgeu_encode_fns, 0, 0 },
15570   { "bltu", 43 /* xt_iclass_bst8 */,
15571     XTENSA_OPCODE_IS_BRANCH,
15572     Opcode_bltu_encode_fns, 0, 0 },
15573   { "bany", 43 /* xt_iclass_bst8 */,
15574     XTENSA_OPCODE_IS_BRANCH,
15575     Opcode_bany_encode_fns, 0, 0 },
15576   { "bnone", 43 /* xt_iclass_bst8 */,
15577     XTENSA_OPCODE_IS_BRANCH,
15578     Opcode_bnone_encode_fns, 0, 0 },
15579   { "ball", 43 /* xt_iclass_bst8 */,
15580     XTENSA_OPCODE_IS_BRANCH,
15581     Opcode_ball_encode_fns, 0, 0 },
15582   { "bnall", 43 /* xt_iclass_bst8 */,
15583     XTENSA_OPCODE_IS_BRANCH,
15584     Opcode_bnall_encode_fns, 0, 0 },
15585   { "bbc", 43 /* xt_iclass_bst8 */,
15586     XTENSA_OPCODE_IS_BRANCH,
15587     Opcode_bbc_encode_fns, 0, 0 },
15588   { "bbs", 43 /* xt_iclass_bst8 */,
15589     XTENSA_OPCODE_IS_BRANCH,
15590     Opcode_bbs_encode_fns, 0, 0 },
15591   { "beqz", 44 /* xt_iclass_bsz12 */,
15592     XTENSA_OPCODE_IS_BRANCH,
15593     Opcode_beqz_encode_fns, 0, 0 },
15594   { "bnez", 44 /* xt_iclass_bsz12 */,
15595     XTENSA_OPCODE_IS_BRANCH,
15596     Opcode_bnez_encode_fns, 0, 0 },
15597   { "bgez", 44 /* xt_iclass_bsz12 */,
15598     XTENSA_OPCODE_IS_BRANCH,
15599     Opcode_bgez_encode_fns, 0, 0 },
15600   { "bltz", 44 /* xt_iclass_bsz12 */,
15601     XTENSA_OPCODE_IS_BRANCH,
15602     Opcode_bltz_encode_fns, 0, 0 },
15603   { "call0", 45 /* xt_iclass_call0 */,
15604     XTENSA_OPCODE_IS_CALL,
15605     Opcode_call0_encode_fns, 0, 0 },
15606   { "callx0", 46 /* xt_iclass_callx0 */,
15607     XTENSA_OPCODE_IS_CALL,
15608     Opcode_callx0_encode_fns, 0, 0 },
15609   { "extui", 47 /* xt_iclass_exti */,
15610     0,
15611     Opcode_extui_encode_fns, 0, 0 },
15612   { "ill", 48 /* xt_iclass_ill */,
15613     0,
15614     Opcode_ill_encode_fns, 0, 0 },
15615   { "j", 49 /* xt_iclass_jump */,
15616     XTENSA_OPCODE_IS_JUMP,
15617     Opcode_j_encode_fns, 0, 0 },
15618   { "jx", 50 /* xt_iclass_jumpx */,
15619     XTENSA_OPCODE_IS_JUMP,
15620     Opcode_jx_encode_fns, 0, 0 },
15621   { "l16ui", 51 /* xt_iclass_l16ui */,
15622     0,
15623     Opcode_l16ui_encode_fns, 0, 0 },
15624   { "l16si", 52 /* xt_iclass_l16si */,
15625     0,
15626     Opcode_l16si_encode_fns, 0, 0 },
15627   { "l32i", 53 /* xt_iclass_l32i */,
15628     0,
15629     Opcode_l32i_encode_fns, 0, 0 },
15630   { "l32r", 54 /* xt_iclass_l32r */,
15631     0,
15632     Opcode_l32r_encode_fns, 0, 0 },
15633   { "l8ui", 55 /* xt_iclass_l8i */,
15634     0,
15635     Opcode_l8ui_encode_fns, 0, 0 },
15636   { "loop", 56 /* xt_iclass_loop */,
15637     XTENSA_OPCODE_IS_LOOP,
15638     Opcode_loop_encode_fns, 0, 0 },
15639   { "loopnez", 57 /* xt_iclass_loopz */,
15640     XTENSA_OPCODE_IS_LOOP,
15641     Opcode_loopnez_encode_fns, 0, 0 },
15642   { "loopgtz", 57 /* xt_iclass_loopz */,
15643     XTENSA_OPCODE_IS_LOOP,
15644     Opcode_loopgtz_encode_fns, 0, 0 },
15645   { "movi", 58 /* xt_iclass_movi */,
15646     0,
15647     Opcode_movi_encode_fns, 0, 0 },
15648   { "moveqz", 59 /* xt_iclass_movz */,
15649     0,
15650     Opcode_moveqz_encode_fns, 0, 0 },
15651   { "movnez", 59 /* xt_iclass_movz */,
15652     0,
15653     Opcode_movnez_encode_fns, 0, 0 },
15654   { "movltz", 59 /* xt_iclass_movz */,
15655     0,
15656     Opcode_movltz_encode_fns, 0, 0 },
15657   { "movgez", 59 /* xt_iclass_movz */,
15658     0,
15659     Opcode_movgez_encode_fns, 0, 0 },
15660   { "neg", 60 /* xt_iclass_neg */,
15661     0,
15662     Opcode_neg_encode_fns, 0, 0 },
15663   { "abs", 60 /* xt_iclass_neg */,
15664     0,
15665     Opcode_abs_encode_fns, 0, 0 },
15666   { "nop", 61 /* xt_iclass_nop */,
15667     0,
15668     Opcode_nop_encode_fns, 0, 0 },
15669   { "ret", 62 /* xt_iclass_return */,
15670     XTENSA_OPCODE_IS_JUMP,
15671     Opcode_ret_encode_fns, 0, 0 },
15672   { "s16i", 63 /* xt_iclass_s16i */,
15673     0,
15674     Opcode_s16i_encode_fns, 0, 0 },
15675   { "s32i", 64 /* xt_iclass_s32i */,
15676     0,
15677     Opcode_s32i_encode_fns, 0, 0 },
15678   { "s8i", 65 /* xt_iclass_s8i */,
15679     0,
15680     Opcode_s8i_encode_fns, 0, 0 },
15681   { "ssr", 66 /* xt_iclass_sar */,
15682     0,
15683     Opcode_ssr_encode_fns, 0, 0 },
15684   { "ssl", 66 /* xt_iclass_sar */,
15685     0,
15686     Opcode_ssl_encode_fns, 0, 0 },
15687   { "ssa8l", 66 /* xt_iclass_sar */,
15688     0,
15689     Opcode_ssa8l_encode_fns, 0, 0 },
15690   { "ssa8b", 66 /* xt_iclass_sar */,
15691     0,
15692     Opcode_ssa8b_encode_fns, 0, 0 },
15693   { "ssai", 67 /* xt_iclass_sari */,
15694     0,
15695     Opcode_ssai_encode_fns, 0, 0 },
15696   { "sll", 68 /* xt_iclass_shifts */,
15697     0,
15698     Opcode_sll_encode_fns, 0, 0 },
15699   { "src", 69 /* xt_iclass_shiftst */,
15700     0,
15701     Opcode_src_encode_fns, 0, 0 },
15702   { "srl", 70 /* xt_iclass_shiftt */,
15703     0,
15704     Opcode_srl_encode_fns, 0, 0 },
15705   { "sra", 70 /* xt_iclass_shiftt */,
15706     0,
15707     Opcode_sra_encode_fns, 0, 0 },
15708   { "slli", 71 /* xt_iclass_slli */,
15709     0,
15710     Opcode_slli_encode_fns, 0, 0 },
15711   { "srai", 72 /* xt_iclass_srai */,
15712     0,
15713     Opcode_srai_encode_fns, 0, 0 },
15714   { "srli", 73 /* xt_iclass_srli */,
15715     0,
15716     Opcode_srli_encode_fns, 0, 0 },
15717   { "memw", 74 /* xt_iclass_memw */,
15718     0,
15719     Opcode_memw_encode_fns, 0, 0 },
15720   { "extw", 75 /* xt_iclass_extw */,
15721     0,
15722     Opcode_extw_encode_fns, 0, 0 },
15723   { "isync", 76 /* xt_iclass_isync */,
15724     0,
15725     Opcode_isync_encode_fns, 0, 0 },
15726   { "rsync", 77 /* xt_iclass_sync */,
15727     0,
15728     Opcode_rsync_encode_fns, 0, 0 },
15729   { "esync", 77 /* xt_iclass_sync */,
15730     0,
15731     Opcode_esync_encode_fns, 0, 0 },
15732   { "dsync", 77 /* xt_iclass_sync */,
15733     0,
15734     Opcode_dsync_encode_fns, 0, 0 },
15735   { "rsil", 78 /* xt_iclass_rsil */,
15736     0,
15737     Opcode_rsil_encode_fns, 0, 0 },
15738   { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
15739     0,
15740     Opcode_rsr_lend_encode_fns, 0, 0 },
15741   { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
15742     0,
15743     Opcode_wsr_lend_encode_fns, 0, 0 },
15744   { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
15745     0,
15746     Opcode_xsr_lend_encode_fns, 0, 0 },
15747   { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
15748     0,
15749     Opcode_rsr_lcount_encode_fns, 0, 0 },
15750   { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
15751     0,
15752     Opcode_wsr_lcount_encode_fns, 0, 0 },
15753   { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
15754     0,
15755     Opcode_xsr_lcount_encode_fns, 0, 0 },
15756   { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
15757     0,
15758     Opcode_rsr_lbeg_encode_fns, 0, 0 },
15759   { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
15760     0,
15761     Opcode_wsr_lbeg_encode_fns, 0, 0 },
15762   { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
15763     0,
15764     Opcode_xsr_lbeg_encode_fns, 0, 0 },
15765   { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
15766     0,
15767     Opcode_rsr_sar_encode_fns, 0, 0 },
15768   { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
15769     0,
15770     Opcode_wsr_sar_encode_fns, 0, 0 },
15771   { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
15772     0,
15773     Opcode_xsr_sar_encode_fns, 0, 0 },
15774   { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
15775     0,
15776     Opcode_rsr_litbase_encode_fns, 0, 0 },
15777   { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
15778     0,
15779     Opcode_wsr_litbase_encode_fns, 0, 0 },
15780   { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
15781     0,
15782     Opcode_xsr_litbase_encode_fns, 0, 0 },
15783   { "rsr.176", 94 /* xt_iclass_rsr.176 */,
15784     0,
15785     Opcode_rsr_176_encode_fns, 0, 0 },
15786   { "rsr.208", 95 /* xt_iclass_rsr.208 */,
15787     0,
15788     Opcode_rsr_208_encode_fns, 0, 0 },
15789   { "rsr.ps", 96 /* xt_iclass_rsr.ps */,
15790     0,
15791     Opcode_rsr_ps_encode_fns, 0, 0 },
15792   { "wsr.ps", 97 /* xt_iclass_wsr.ps */,
15793     0,
15794     Opcode_wsr_ps_encode_fns, 0, 0 },
15795   { "xsr.ps", 98 /* xt_iclass_xsr.ps */,
15796     0,
15797     Opcode_xsr_ps_encode_fns, 0, 0 },
15798   { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */,
15799     0,
15800     Opcode_rsr_epc1_encode_fns, 0, 0 },
15801   { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */,
15802     0,
15803     Opcode_wsr_epc1_encode_fns, 0, 0 },
15804   { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */,
15805     0,
15806     Opcode_xsr_epc1_encode_fns, 0, 0 },
15807   { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */,
15808     0,
15809     Opcode_rsr_excsave1_encode_fns, 0, 0 },
15810   { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */,
15811     0,
15812     Opcode_wsr_excsave1_encode_fns, 0, 0 },
15813   { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */,
15814     0,
15815     Opcode_xsr_excsave1_encode_fns, 0, 0 },
15816   { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */,
15817     0,
15818     Opcode_rsr_epc2_encode_fns, 0, 0 },
15819   { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */,
15820     0,
15821     Opcode_wsr_epc2_encode_fns, 0, 0 },
15822   { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */,
15823     0,
15824     Opcode_xsr_epc2_encode_fns, 0, 0 },
15825   { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */,
15826     0,
15827     Opcode_rsr_excsave2_encode_fns, 0, 0 },
15828   { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */,
15829     0,
15830     Opcode_wsr_excsave2_encode_fns, 0, 0 },
15831   { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */,
15832     0,
15833     Opcode_xsr_excsave2_encode_fns, 0, 0 },
15834   { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */,
15835     0,
15836     Opcode_rsr_epc3_encode_fns, 0, 0 },
15837   { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */,
15838     0,
15839     Opcode_wsr_epc3_encode_fns, 0, 0 },
15840   { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */,
15841     0,
15842     Opcode_xsr_epc3_encode_fns, 0, 0 },
15843   { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */,
15844     0,
15845     Opcode_rsr_excsave3_encode_fns, 0, 0 },
15846   { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */,
15847     0,
15848     Opcode_wsr_excsave3_encode_fns, 0, 0 },
15849   { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */,
15850     0,
15851     Opcode_xsr_excsave3_encode_fns, 0, 0 },
15852   { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */,
15853     0,
15854     Opcode_rsr_epc4_encode_fns, 0, 0 },
15855   { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */,
15856     0,
15857     Opcode_wsr_epc4_encode_fns, 0, 0 },
15858   { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */,
15859     0,
15860     Opcode_xsr_epc4_encode_fns, 0, 0 },
15861   { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */,
15862     0,
15863     Opcode_rsr_excsave4_encode_fns, 0, 0 },
15864   { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */,
15865     0,
15866     Opcode_wsr_excsave4_encode_fns, 0, 0 },
15867   { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */,
15868     0,
15869     Opcode_xsr_excsave4_encode_fns, 0, 0 },
15870   { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
15871     0,
15872     Opcode_rsr_epc5_encode_fns, 0, 0 },
15873   { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
15874     0,
15875     Opcode_wsr_epc5_encode_fns, 0, 0 },
15876   { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
15877     0,
15878     Opcode_xsr_epc5_encode_fns, 0, 0 },
15879   { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */,
15880     0,
15881     Opcode_rsr_excsave5_encode_fns, 0, 0 },
15882   { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */,
15883     0,
15884     Opcode_wsr_excsave5_encode_fns, 0, 0 },
15885   { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */,
15886     0,
15887     Opcode_xsr_excsave5_encode_fns, 0, 0 },
15888   { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */,
15889     0,
15890     Opcode_rsr_epc6_encode_fns, 0, 0 },
15891   { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */,
15892     0,
15893     Opcode_wsr_epc6_encode_fns, 0, 0 },
15894   { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */,
15895     0,
15896     Opcode_xsr_epc6_encode_fns, 0, 0 },
15897   { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */,
15898     0,
15899     Opcode_rsr_excsave6_encode_fns, 0, 0 },
15900   { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */,
15901     0,
15902     Opcode_wsr_excsave6_encode_fns, 0, 0 },
15903   { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */,
15904     0,
15905     Opcode_xsr_excsave6_encode_fns, 0, 0 },
15906   { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */,
15907     0,
15908     Opcode_rsr_epc7_encode_fns, 0, 0 },
15909   { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */,
15910     0,
15911     Opcode_wsr_epc7_encode_fns, 0, 0 },
15912   { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */,
15913     0,
15914     Opcode_xsr_epc7_encode_fns, 0, 0 },
15915   { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */,
15916     0,
15917     Opcode_rsr_excsave7_encode_fns, 0, 0 },
15918   { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */,
15919     0,
15920     Opcode_wsr_excsave7_encode_fns, 0, 0 },
15921   { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */,
15922     0,
15923     Opcode_xsr_excsave7_encode_fns, 0, 0 },
15924   { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */,
15925     0,
15926     Opcode_rsr_eps2_encode_fns, 0, 0 },
15927   { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */,
15928     0,
15929     Opcode_wsr_eps2_encode_fns, 0, 0 },
15930   { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */,
15931     0,
15932     Opcode_xsr_eps2_encode_fns, 0, 0 },
15933   { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */,
15934     0,
15935     Opcode_rsr_eps3_encode_fns, 0, 0 },
15936   { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */,
15937     0,
15938     Opcode_wsr_eps3_encode_fns, 0, 0 },
15939   { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */,
15940     0,
15941     Opcode_xsr_eps3_encode_fns, 0, 0 },
15942   { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */,
15943     0,
15944     Opcode_rsr_eps4_encode_fns, 0, 0 },
15945   { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */,
15946     0,
15947     Opcode_wsr_eps4_encode_fns, 0, 0 },
15948   { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */,
15949     0,
15950     Opcode_xsr_eps4_encode_fns, 0, 0 },
15951   { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */,
15952     0,
15953     Opcode_rsr_eps5_encode_fns, 0, 0 },
15954   { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */,
15955     0,
15956     Opcode_wsr_eps5_encode_fns, 0, 0 },
15957   { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */,
15958     0,
15959     Opcode_xsr_eps5_encode_fns, 0, 0 },
15960   { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */,
15961     0,
15962     Opcode_rsr_eps6_encode_fns, 0, 0 },
15963   { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */,
15964     0,
15965     Opcode_wsr_eps6_encode_fns, 0, 0 },
15966   { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */,
15967     0,
15968     Opcode_xsr_eps6_encode_fns, 0, 0 },
15969   { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */,
15970     0,
15971     Opcode_rsr_eps7_encode_fns, 0, 0 },
15972   { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */,
15973     0,
15974     Opcode_wsr_eps7_encode_fns, 0, 0 },
15975   { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */,
15976     0,
15977     Opcode_xsr_eps7_encode_fns, 0, 0 },
15978   { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */,
15979     0,
15980     Opcode_rsr_excvaddr_encode_fns, 0, 0 },
15981   { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */,
15982     0,
15983     Opcode_wsr_excvaddr_encode_fns, 0, 0 },
15984   { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */,
15985     0,
15986     Opcode_xsr_excvaddr_encode_fns, 0, 0 },
15987   { "rsr.depc", 162 /* xt_iclass_rsr.depc */,
15988     0,
15989     Opcode_rsr_depc_encode_fns, 0, 0 },
15990   { "wsr.depc", 163 /* xt_iclass_wsr.depc */,
15991     0,
15992     Opcode_wsr_depc_encode_fns, 0, 0 },
15993   { "xsr.depc", 164 /* xt_iclass_xsr.depc */,
15994     0,
15995     Opcode_xsr_depc_encode_fns, 0, 0 },
15996   { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */,
15997     0,
15998     Opcode_rsr_exccause_encode_fns, 0, 0 },
15999   { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */,
16000     0,
16001     Opcode_wsr_exccause_encode_fns, 0, 0 },
16002   { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */,
16003     0,
16004     Opcode_xsr_exccause_encode_fns, 0, 0 },
16005   { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */,
16006     0,
16007     Opcode_rsr_misc0_encode_fns, 0, 0 },
16008   { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */,
16009     0,
16010     Opcode_wsr_misc0_encode_fns, 0, 0 },
16011   { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */,
16012     0,
16013     Opcode_xsr_misc0_encode_fns, 0, 0 },
16014   { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */,
16015     0,
16016     Opcode_rsr_misc1_encode_fns, 0, 0 },
16017   { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */,
16018     0,
16019     Opcode_wsr_misc1_encode_fns, 0, 0 },
16020   { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */,
16021     0,
16022     Opcode_xsr_misc1_encode_fns, 0, 0 },
16023   { "rsr.misc2", 174 /* xt_iclass_rsr.misc2 */,
16024     0,
16025     Opcode_rsr_misc2_encode_fns, 0, 0 },
16026   { "wsr.misc2", 175 /* xt_iclass_wsr.misc2 */,
16027     0,
16028     Opcode_wsr_misc2_encode_fns, 0, 0 },
16029   { "xsr.misc2", 176 /* xt_iclass_xsr.misc2 */,
16030     0,
16031     Opcode_xsr_misc2_encode_fns, 0, 0 },
16032   { "rsr.misc3", 177 /* xt_iclass_rsr.misc3 */,
16033     0,
16034     Opcode_rsr_misc3_encode_fns, 0, 0 },
16035   { "wsr.misc3", 178 /* xt_iclass_wsr.misc3 */,
16036     0,
16037     Opcode_wsr_misc3_encode_fns, 0, 0 },
16038   { "xsr.misc3", 179 /* xt_iclass_xsr.misc3 */,
16039     0,
16040     Opcode_xsr_misc3_encode_fns, 0, 0 },
16041   { "rsr.prid", 180 /* xt_iclass_rsr.prid */,
16042     0,
16043     Opcode_rsr_prid_encode_fns, 0, 0 },
16044   { "rsr.vecbase", 181 /* xt_iclass_rsr.vecbase */,
16045     0,
16046     Opcode_rsr_vecbase_encode_fns, 0, 0 },
16047   { "wsr.vecbase", 182 /* xt_iclass_wsr.vecbase */,
16048     0,
16049     Opcode_wsr_vecbase_encode_fns, 0, 0 },
16050   { "xsr.vecbase", 183 /* xt_iclass_xsr.vecbase */,
16051     0,
16052     Opcode_xsr_vecbase_encode_fns, 0, 0 },
16053   { "mul.aa.ll", 184 /* xt_iclass_mac16_aa */,
16054     0,
16055     Opcode_mul_aa_ll_encode_fns, 0, 0 },
16056   { "mul.aa.hl", 184 /* xt_iclass_mac16_aa */,
16057     0,
16058     Opcode_mul_aa_hl_encode_fns, 0, 0 },
16059   { "mul.aa.lh", 184 /* xt_iclass_mac16_aa */,
16060     0,
16061     Opcode_mul_aa_lh_encode_fns, 0, 0 },
16062   { "mul.aa.hh", 184 /* xt_iclass_mac16_aa */,
16063     0,
16064     Opcode_mul_aa_hh_encode_fns, 0, 0 },
16065   { "umul.aa.ll", 184 /* xt_iclass_mac16_aa */,
16066     0,
16067     Opcode_umul_aa_ll_encode_fns, 0, 0 },
16068   { "umul.aa.hl", 184 /* xt_iclass_mac16_aa */,
16069     0,
16070     Opcode_umul_aa_hl_encode_fns, 0, 0 },
16071   { "umul.aa.lh", 184 /* xt_iclass_mac16_aa */,
16072     0,
16073     Opcode_umul_aa_lh_encode_fns, 0, 0 },
16074   { "umul.aa.hh", 184 /* xt_iclass_mac16_aa */,
16075     0,
16076     Opcode_umul_aa_hh_encode_fns, 0, 0 },
16077   { "mul.ad.ll", 185 /* xt_iclass_mac16_ad */,
16078     0,
16079     Opcode_mul_ad_ll_encode_fns, 0, 0 },
16080   { "mul.ad.hl", 185 /* xt_iclass_mac16_ad */,
16081     0,
16082     Opcode_mul_ad_hl_encode_fns, 0, 0 },
16083   { "mul.ad.lh", 185 /* xt_iclass_mac16_ad */,
16084     0,
16085     Opcode_mul_ad_lh_encode_fns, 0, 0 },
16086   { "mul.ad.hh", 185 /* xt_iclass_mac16_ad */,
16087     0,
16088     Opcode_mul_ad_hh_encode_fns, 0, 0 },
16089   { "mul.da.ll", 186 /* xt_iclass_mac16_da */,
16090     0,
16091     Opcode_mul_da_ll_encode_fns, 0, 0 },
16092   { "mul.da.hl", 186 /* xt_iclass_mac16_da */,
16093     0,
16094     Opcode_mul_da_hl_encode_fns, 0, 0 },
16095   { "mul.da.lh", 186 /* xt_iclass_mac16_da */,
16096     0,
16097     Opcode_mul_da_lh_encode_fns, 0, 0 },
16098   { "mul.da.hh", 186 /* xt_iclass_mac16_da */,
16099     0,
16100     Opcode_mul_da_hh_encode_fns, 0, 0 },
16101   { "mul.dd.ll", 187 /* xt_iclass_mac16_dd */,
16102     0,
16103     Opcode_mul_dd_ll_encode_fns, 0, 0 },
16104   { "mul.dd.hl", 187 /* xt_iclass_mac16_dd */,
16105     0,
16106     Opcode_mul_dd_hl_encode_fns, 0, 0 },
16107   { "mul.dd.lh", 187 /* xt_iclass_mac16_dd */,
16108     0,
16109     Opcode_mul_dd_lh_encode_fns, 0, 0 },
16110   { "mul.dd.hh", 187 /* xt_iclass_mac16_dd */,
16111     0,
16112     Opcode_mul_dd_hh_encode_fns, 0, 0 },
16113   { "mula.aa.ll", 188 /* xt_iclass_mac16a_aa */,
16114     0,
16115     Opcode_mula_aa_ll_encode_fns, 0, 0 },
16116   { "mula.aa.hl", 188 /* xt_iclass_mac16a_aa */,
16117     0,
16118     Opcode_mula_aa_hl_encode_fns, 0, 0 },
16119   { "mula.aa.lh", 188 /* xt_iclass_mac16a_aa */,
16120     0,
16121     Opcode_mula_aa_lh_encode_fns, 0, 0 },
16122   { "mula.aa.hh", 188 /* xt_iclass_mac16a_aa */,
16123     0,
16124     Opcode_mula_aa_hh_encode_fns, 0, 0 },
16125   { "muls.aa.ll", 188 /* xt_iclass_mac16a_aa */,
16126     0,
16127     Opcode_muls_aa_ll_encode_fns, 0, 0 },
16128   { "muls.aa.hl", 188 /* xt_iclass_mac16a_aa */,
16129     0,
16130     Opcode_muls_aa_hl_encode_fns, 0, 0 },
16131   { "muls.aa.lh", 188 /* xt_iclass_mac16a_aa */,
16132     0,
16133     Opcode_muls_aa_lh_encode_fns, 0, 0 },
16134   { "muls.aa.hh", 188 /* xt_iclass_mac16a_aa */,
16135     0,
16136     Opcode_muls_aa_hh_encode_fns, 0, 0 },
16137   { "mula.ad.ll", 189 /* xt_iclass_mac16a_ad */,
16138     0,
16139     Opcode_mula_ad_ll_encode_fns, 0, 0 },
16140   { "mula.ad.hl", 189 /* xt_iclass_mac16a_ad */,
16141     0,
16142     Opcode_mula_ad_hl_encode_fns, 0, 0 },
16143   { "mula.ad.lh", 189 /* xt_iclass_mac16a_ad */,
16144     0,
16145     Opcode_mula_ad_lh_encode_fns, 0, 0 },
16146   { "mula.ad.hh", 189 /* xt_iclass_mac16a_ad */,
16147     0,
16148     Opcode_mula_ad_hh_encode_fns, 0, 0 },
16149   { "muls.ad.ll", 189 /* xt_iclass_mac16a_ad */,
16150     0,
16151     Opcode_muls_ad_ll_encode_fns, 0, 0 },
16152   { "muls.ad.hl", 189 /* xt_iclass_mac16a_ad */,
16153     0,
16154     Opcode_muls_ad_hl_encode_fns, 0, 0 },
16155   { "muls.ad.lh", 189 /* xt_iclass_mac16a_ad */,
16156     0,
16157     Opcode_muls_ad_lh_encode_fns, 0, 0 },
16158   { "muls.ad.hh", 189 /* xt_iclass_mac16a_ad */,
16159     0,
16160     Opcode_muls_ad_hh_encode_fns, 0, 0 },
16161   { "mula.da.ll", 190 /* xt_iclass_mac16a_da */,
16162     0,
16163     Opcode_mula_da_ll_encode_fns, 0, 0 },
16164   { "mula.da.hl", 190 /* xt_iclass_mac16a_da */,
16165     0,
16166     Opcode_mula_da_hl_encode_fns, 0, 0 },
16167   { "mula.da.lh", 190 /* xt_iclass_mac16a_da */,
16168     0,
16169     Opcode_mula_da_lh_encode_fns, 0, 0 },
16170   { "mula.da.hh", 190 /* xt_iclass_mac16a_da */,
16171     0,
16172     Opcode_mula_da_hh_encode_fns, 0, 0 },
16173   { "muls.da.ll", 190 /* xt_iclass_mac16a_da */,
16174     0,
16175     Opcode_muls_da_ll_encode_fns, 0, 0 },
16176   { "muls.da.hl", 190 /* xt_iclass_mac16a_da */,
16177     0,
16178     Opcode_muls_da_hl_encode_fns, 0, 0 },
16179   { "muls.da.lh", 190 /* xt_iclass_mac16a_da */,
16180     0,
16181     Opcode_muls_da_lh_encode_fns, 0, 0 },
16182   { "muls.da.hh", 190 /* xt_iclass_mac16a_da */,
16183     0,
16184     Opcode_muls_da_hh_encode_fns, 0, 0 },
16185   { "mula.dd.ll", 191 /* xt_iclass_mac16a_dd */,
16186     0,
16187     Opcode_mula_dd_ll_encode_fns, 0, 0 },
16188   { "mula.dd.hl", 191 /* xt_iclass_mac16a_dd */,
16189     0,
16190     Opcode_mula_dd_hl_encode_fns, 0, 0 },
16191   { "mula.dd.lh", 191 /* xt_iclass_mac16a_dd */,
16192     0,
16193     Opcode_mula_dd_lh_encode_fns, 0, 0 },
16194   { "mula.dd.hh", 191 /* xt_iclass_mac16a_dd */,
16195     0,
16196     Opcode_mula_dd_hh_encode_fns, 0, 0 },
16197   { "muls.dd.ll", 191 /* xt_iclass_mac16a_dd */,
16198     0,
16199     Opcode_muls_dd_ll_encode_fns, 0, 0 },
16200   { "muls.dd.hl", 191 /* xt_iclass_mac16a_dd */,
16201     0,
16202     Opcode_muls_dd_hl_encode_fns, 0, 0 },
16203   { "muls.dd.lh", 191 /* xt_iclass_mac16a_dd */,
16204     0,
16205     Opcode_muls_dd_lh_encode_fns, 0, 0 },
16206   { "muls.dd.hh", 191 /* xt_iclass_mac16a_dd */,
16207     0,
16208     Opcode_muls_dd_hh_encode_fns, 0, 0 },
16209   { "mula.da.ll.lddec", 192 /* xt_iclass_mac16al_da */,
16210     0,
16211     Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
16212   { "mula.da.ll.ldinc", 192 /* xt_iclass_mac16al_da */,
16213     0,
16214     Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
16215   { "mula.da.hl.lddec", 192 /* xt_iclass_mac16al_da */,
16216     0,
16217     Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
16218   { "mula.da.hl.ldinc", 192 /* xt_iclass_mac16al_da */,
16219     0,
16220     Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
16221   { "mula.da.lh.lddec", 192 /* xt_iclass_mac16al_da */,
16222     0,
16223     Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
16224   { "mula.da.lh.ldinc", 192 /* xt_iclass_mac16al_da */,
16225     0,
16226     Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
16227   { "mula.da.hh.lddec", 192 /* xt_iclass_mac16al_da */,
16228     0,
16229     Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
16230   { "mula.da.hh.ldinc", 192 /* xt_iclass_mac16al_da */,
16231     0,
16232     Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
16233   { "mula.dd.ll.lddec", 193 /* xt_iclass_mac16al_dd */,
16234     0,
16235     Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
16236   { "mula.dd.ll.ldinc", 193 /* xt_iclass_mac16al_dd */,
16237     0,
16238     Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
16239   { "mula.dd.hl.lddec", 193 /* xt_iclass_mac16al_dd */,
16240     0,
16241     Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
16242   { "mula.dd.hl.ldinc", 193 /* xt_iclass_mac16al_dd */,
16243     0,
16244     Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
16245   { "mula.dd.lh.lddec", 193 /* xt_iclass_mac16al_dd */,
16246     0,
16247     Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
16248   { "mula.dd.lh.ldinc", 193 /* xt_iclass_mac16al_dd */,
16249     0,
16250     Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
16251   { "mula.dd.hh.lddec", 193 /* xt_iclass_mac16al_dd */,
16252     0,
16253     Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
16254   { "mula.dd.hh.ldinc", 193 /* xt_iclass_mac16al_dd */,
16255     0,
16256     Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
16257   { "lddec", 194 /* xt_iclass_mac16_l */,
16258     0,
16259     Opcode_lddec_encode_fns, 0, 0 },
16260   { "ldinc", 194 /* xt_iclass_mac16_l */,
16261     0,
16262     Opcode_ldinc_encode_fns, 0, 0 },
16263   { "mul16u", 195 /* xt_iclass_mul16 */,
16264     0,
16265     Opcode_mul16u_encode_fns, 0, 0 },
16266   { "mul16s", 195 /* xt_iclass_mul16 */,
16267     0,
16268     Opcode_mul16s_encode_fns, 0, 0 },
16269   { "rsr.m0", 196 /* xt_iclass_rsr.m0 */,
16270     0,
16271     Opcode_rsr_m0_encode_fns, 0, 0 },
16272   { "wsr.m0", 197 /* xt_iclass_wsr.m0 */,
16273     0,
16274     Opcode_wsr_m0_encode_fns, 0, 0 },
16275   { "xsr.m0", 198 /* xt_iclass_xsr.m0 */,
16276     0,
16277     Opcode_xsr_m0_encode_fns, 0, 0 },
16278   { "rsr.m1", 199 /* xt_iclass_rsr.m1 */,
16279     0,
16280     Opcode_rsr_m1_encode_fns, 0, 0 },
16281   { "wsr.m1", 200 /* xt_iclass_wsr.m1 */,
16282     0,
16283     Opcode_wsr_m1_encode_fns, 0, 0 },
16284   { "xsr.m1", 201 /* xt_iclass_xsr.m1 */,
16285     0,
16286     Opcode_xsr_m1_encode_fns, 0, 0 },
16287   { "rsr.m2", 202 /* xt_iclass_rsr.m2 */,
16288     0,
16289     Opcode_rsr_m2_encode_fns, 0, 0 },
16290   { "wsr.m2", 203 /* xt_iclass_wsr.m2 */,
16291     0,
16292     Opcode_wsr_m2_encode_fns, 0, 0 },
16293   { "xsr.m2", 204 /* xt_iclass_xsr.m2 */,
16294     0,
16295     Opcode_xsr_m2_encode_fns, 0, 0 },
16296   { "rsr.m3", 205 /* xt_iclass_rsr.m3 */,
16297     0,
16298     Opcode_rsr_m3_encode_fns, 0, 0 },
16299   { "wsr.m3", 206 /* xt_iclass_wsr.m3 */,
16300     0,
16301     Opcode_wsr_m3_encode_fns, 0, 0 },
16302   { "xsr.m3", 207 /* xt_iclass_xsr.m3 */,
16303     0,
16304     Opcode_xsr_m3_encode_fns, 0, 0 },
16305   { "rsr.acclo", 208 /* xt_iclass_rsr.acclo */,
16306     0,
16307     Opcode_rsr_acclo_encode_fns, 0, 0 },
16308   { "wsr.acclo", 209 /* xt_iclass_wsr.acclo */,
16309     0,
16310     Opcode_wsr_acclo_encode_fns, 0, 0 },
16311   { "xsr.acclo", 210 /* xt_iclass_xsr.acclo */,
16312     0,
16313     Opcode_xsr_acclo_encode_fns, 0, 0 },
16314   { "rsr.acchi", 211 /* xt_iclass_rsr.acchi */,
16315     0,
16316     Opcode_rsr_acchi_encode_fns, 0, 0 },
16317   { "wsr.acchi", 212 /* xt_iclass_wsr.acchi */,
16318     0,
16319     Opcode_wsr_acchi_encode_fns, 0, 0 },
16320   { "xsr.acchi", 213 /* xt_iclass_xsr.acchi */,
16321     0,
16322     Opcode_xsr_acchi_encode_fns, 0, 0 },
16323   { "rfi", 214 /* xt_iclass_rfi */,
16324     XTENSA_OPCODE_IS_JUMP,
16325     Opcode_rfi_encode_fns, 0, 0 },
16326   { "waiti", 215 /* xt_iclass_wait */,
16327     0,
16328     Opcode_waiti_encode_fns, 0, 0 },
16329   { "rsr.interrupt", 216 /* xt_iclass_rsr.interrupt */,
16330     0,
16331     Opcode_rsr_interrupt_encode_fns, 0, 0 },
16332   { "wsr.intset", 217 /* xt_iclass_wsr.intset */,
16333     0,
16334     Opcode_wsr_intset_encode_fns, 0, 0 },
16335   { "wsr.intclear", 218 /* xt_iclass_wsr.intclear */,
16336     0,
16337     Opcode_wsr_intclear_encode_fns, 0, 0 },
16338   { "rsr.intenable", 219 /* xt_iclass_rsr.intenable */,
16339     0,
16340     Opcode_rsr_intenable_encode_fns, 0, 0 },
16341   { "wsr.intenable", 220 /* xt_iclass_wsr.intenable */,
16342     0,
16343     Opcode_wsr_intenable_encode_fns, 0, 0 },
16344   { "xsr.intenable", 221 /* xt_iclass_xsr.intenable */,
16345     0,
16346     Opcode_xsr_intenable_encode_fns, 0, 0 },
16347   { "break", 222 /* xt_iclass_break */,
16348     0,
16349     Opcode_break_encode_fns, 0, 0 },
16350   { "break.n", 223 /* xt_iclass_break.n */,
16351     0,
16352     Opcode_break_n_encode_fns, 0, 0 },
16353   { "rsr.dbreaka0", 224 /* xt_iclass_rsr.dbreaka0 */,
16354     0,
16355     Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
16356   { "wsr.dbreaka0", 225 /* xt_iclass_wsr.dbreaka0 */,
16357     0,
16358     Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
16359   { "xsr.dbreaka0", 226 /* xt_iclass_xsr.dbreaka0 */,
16360     0,
16361     Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
16362   { "rsr.dbreakc0", 227 /* xt_iclass_rsr.dbreakc0 */,
16363     0,
16364     Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
16365   { "wsr.dbreakc0", 228 /* xt_iclass_wsr.dbreakc0 */,
16366     0,
16367     Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
16368   { "xsr.dbreakc0", 229 /* xt_iclass_xsr.dbreakc0 */,
16369     0,
16370     Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
16371   { "rsr.dbreaka1", 230 /* xt_iclass_rsr.dbreaka1 */,
16372     0,
16373     Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
16374   { "wsr.dbreaka1", 231 /* xt_iclass_wsr.dbreaka1 */,
16375     0,
16376     Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
16377   { "xsr.dbreaka1", 232 /* xt_iclass_xsr.dbreaka1 */,
16378     0,
16379     Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
16380   { "rsr.dbreakc1", 233 /* xt_iclass_rsr.dbreakc1 */,
16381     0,
16382     Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
16383   { "wsr.dbreakc1", 234 /* xt_iclass_wsr.dbreakc1 */,
16384     0,
16385     Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
16386   { "xsr.dbreakc1", 235 /* xt_iclass_xsr.dbreakc1 */,
16387     0,
16388     Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
16389   { "rsr.ibreaka0", 236 /* xt_iclass_rsr.ibreaka0 */,
16390     0,
16391     Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
16392   { "wsr.ibreaka0", 237 /* xt_iclass_wsr.ibreaka0 */,
16393     0,
16394     Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
16395   { "xsr.ibreaka0", 238 /* xt_iclass_xsr.ibreaka0 */,
16396     0,
16397     Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
16398   { "rsr.ibreaka1", 239 /* xt_iclass_rsr.ibreaka1 */,
16399     0,
16400     Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
16401   { "wsr.ibreaka1", 240 /* xt_iclass_wsr.ibreaka1 */,
16402     0,
16403     Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
16404   { "xsr.ibreaka1", 241 /* xt_iclass_xsr.ibreaka1 */,
16405     0,
16406     Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
16407   { "rsr.ibreakenable", 242 /* xt_iclass_rsr.ibreakenable */,
16408     0,
16409     Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
16410   { "wsr.ibreakenable", 243 /* xt_iclass_wsr.ibreakenable */,
16411     0,
16412     Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
16413   { "xsr.ibreakenable", 244 /* xt_iclass_xsr.ibreakenable */,
16414     0,
16415     Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
16416   { "rsr.debugcause", 245 /* xt_iclass_rsr.debugcause */,
16417     0,
16418     Opcode_rsr_debugcause_encode_fns, 0, 0 },
16419   { "wsr.debugcause", 246 /* xt_iclass_wsr.debugcause */,
16420     0,
16421     Opcode_wsr_debugcause_encode_fns, 0, 0 },
16422   { "xsr.debugcause", 247 /* xt_iclass_xsr.debugcause */,
16423     0,
16424     Opcode_xsr_debugcause_encode_fns, 0, 0 },
16425   { "rsr.icount", 248 /* xt_iclass_rsr.icount */,
16426     0,
16427     Opcode_rsr_icount_encode_fns, 0, 0 },
16428   { "wsr.icount", 249 /* xt_iclass_wsr.icount */,
16429     0,
16430     Opcode_wsr_icount_encode_fns, 0, 0 },
16431   { "xsr.icount", 250 /* xt_iclass_xsr.icount */,
16432     0,
16433     Opcode_xsr_icount_encode_fns, 0, 0 },
16434   { "rsr.icountlevel", 251 /* xt_iclass_rsr.icountlevel */,
16435     0,
16436     Opcode_rsr_icountlevel_encode_fns, 0, 0 },
16437   { "wsr.icountlevel", 252 /* xt_iclass_wsr.icountlevel */,
16438     0,
16439     Opcode_wsr_icountlevel_encode_fns, 0, 0 },
16440   { "xsr.icountlevel", 253 /* xt_iclass_xsr.icountlevel */,
16441     0,
16442     Opcode_xsr_icountlevel_encode_fns, 0, 0 },
16443   { "rsr.ddr", 254 /* xt_iclass_rsr.ddr */,
16444     0,
16445     Opcode_rsr_ddr_encode_fns, 0, 0 },
16446   { "wsr.ddr", 255 /* xt_iclass_wsr.ddr */,
16447     0,
16448     Opcode_wsr_ddr_encode_fns, 0, 0 },
16449   { "xsr.ddr", 256 /* xt_iclass_xsr.ddr */,
16450     0,
16451     Opcode_xsr_ddr_encode_fns, 0, 0 },
16452   { "rfdo", 257 /* xt_iclass_rfdo */,
16453     XTENSA_OPCODE_IS_JUMP,
16454     Opcode_rfdo_encode_fns, 0, 0 },
16455   { "rfdd", 258 /* xt_iclass_rfdd */,
16456     XTENSA_OPCODE_IS_JUMP,
16457     Opcode_rfdd_encode_fns, 0, 0 },
16458   { "wsr.mmid", 259 /* xt_iclass_wsr.mmid */,
16459     0,
16460     Opcode_wsr_mmid_encode_fns, 0, 0 },
16461   { "andb", 260 /* xt_iclass_bbool1 */,
16462     0,
16463     Opcode_andb_encode_fns, 0, 0 },
16464   { "andbc", 260 /* xt_iclass_bbool1 */,
16465     0,
16466     Opcode_andbc_encode_fns, 0, 0 },
16467   { "orb", 260 /* xt_iclass_bbool1 */,
16468     0,
16469     Opcode_orb_encode_fns, 0, 0 },
16470   { "orbc", 260 /* xt_iclass_bbool1 */,
16471     0,
16472     Opcode_orbc_encode_fns, 0, 0 },
16473   { "xorb", 260 /* xt_iclass_bbool1 */,
16474     0,
16475     Opcode_xorb_encode_fns, 0, 0 },
16476   { "any4", 261 /* xt_iclass_bbool4 */,
16477     0,
16478     Opcode_any4_encode_fns, 0, 0 },
16479   { "all4", 261 /* xt_iclass_bbool4 */,
16480     0,
16481     Opcode_all4_encode_fns, 0, 0 },
16482   { "any8", 262 /* xt_iclass_bbool8 */,
16483     0,
16484     Opcode_any8_encode_fns, 0, 0 },
16485   { "all8", 262 /* xt_iclass_bbool8 */,
16486     0,
16487     Opcode_all8_encode_fns, 0, 0 },
16488   { "bf", 263 /* xt_iclass_bbranch */,
16489     XTENSA_OPCODE_IS_BRANCH,
16490     Opcode_bf_encode_fns, 0, 0 },
16491   { "bt", 263 /* xt_iclass_bbranch */,
16492     XTENSA_OPCODE_IS_BRANCH,
16493     Opcode_bt_encode_fns, 0, 0 },
16494   { "movf", 264 /* xt_iclass_bmove */,
16495     0,
16496     Opcode_movf_encode_fns, 0, 0 },
16497   { "movt", 264 /* xt_iclass_bmove */,
16498     0,
16499     Opcode_movt_encode_fns, 0, 0 },
16500   { "rsr.br", 265 /* xt_iclass_RSR.BR */,
16501     0,
16502     Opcode_rsr_br_encode_fns, 0, 0 },
16503   { "wsr.br", 266 /* xt_iclass_WSR.BR */,
16504     0,
16505     Opcode_wsr_br_encode_fns, 0, 0 },
16506   { "xsr.br", 267 /* xt_iclass_XSR.BR */,
16507     0,
16508     Opcode_xsr_br_encode_fns, 0, 0 },
16509   { "rsr.ccount", 268 /* xt_iclass_rsr.ccount */,
16510     0,
16511     Opcode_rsr_ccount_encode_fns, 0, 0 },
16512   { "wsr.ccount", 269 /* xt_iclass_wsr.ccount */,
16513     0,
16514     Opcode_wsr_ccount_encode_fns, 0, 0 },
16515   { "xsr.ccount", 270 /* xt_iclass_xsr.ccount */,
16516     0,
16517     Opcode_xsr_ccount_encode_fns, 0, 0 },
16518   { "rsr.ccompare0", 271 /* xt_iclass_rsr.ccompare0 */,
16519     0,
16520     Opcode_rsr_ccompare0_encode_fns, 0, 0 },
16521   { "wsr.ccompare0", 272 /* xt_iclass_wsr.ccompare0 */,
16522     0,
16523     Opcode_wsr_ccompare0_encode_fns, 0, 0 },
16524   { "xsr.ccompare0", 273 /* xt_iclass_xsr.ccompare0 */,
16525     0,
16526     Opcode_xsr_ccompare0_encode_fns, 0, 0 },
16527   { "rsr.ccompare1", 274 /* xt_iclass_rsr.ccompare1 */,
16528     0,
16529     Opcode_rsr_ccompare1_encode_fns, 0, 0 },
16530   { "wsr.ccompare1", 275 /* xt_iclass_wsr.ccompare1 */,
16531     0,
16532     Opcode_wsr_ccompare1_encode_fns, 0, 0 },
16533   { "xsr.ccompare1", 276 /* xt_iclass_xsr.ccompare1 */,
16534     0,
16535     Opcode_xsr_ccompare1_encode_fns, 0, 0 },
16536   { "rsr.ccompare2", 277 /* xt_iclass_rsr.ccompare2 */,
16537     0,
16538     Opcode_rsr_ccompare2_encode_fns, 0, 0 },
16539   { "wsr.ccompare2", 278 /* xt_iclass_wsr.ccompare2 */,
16540     0,
16541     Opcode_wsr_ccompare2_encode_fns, 0, 0 },
16542   { "xsr.ccompare2", 279 /* xt_iclass_xsr.ccompare2 */,
16543     0,
16544     Opcode_xsr_ccompare2_encode_fns, 0, 0 },
16545   { "ipf", 280 /* xt_iclass_icache */,
16546     0,
16547     Opcode_ipf_encode_fns, 0, 0 },
16548   { "ihi", 280 /* xt_iclass_icache */,
16549     0,
16550     Opcode_ihi_encode_fns, 0, 0 },
16551   { "ipfl", 281 /* xt_iclass_icache_lock */,
16552     0,
16553     Opcode_ipfl_encode_fns, 0, 0 },
16554   { "ihu", 281 /* xt_iclass_icache_lock */,
16555     0,
16556     Opcode_ihu_encode_fns, 0, 0 },
16557   { "iiu", 281 /* xt_iclass_icache_lock */,
16558     0,
16559     Opcode_iiu_encode_fns, 0, 0 },
16560   { "iii", 282 /* xt_iclass_icache_inv */,
16561     0,
16562     Opcode_iii_encode_fns, 0, 0 },
16563   { "lict", 283 /* xt_iclass_licx */,
16564     0,
16565     Opcode_lict_encode_fns, 0, 0 },
16566   { "licw", 283 /* xt_iclass_licx */,
16567     0,
16568     Opcode_licw_encode_fns, 0, 0 },
16569   { "sict", 284 /* xt_iclass_sicx */,
16570     0,
16571     Opcode_sict_encode_fns, 0, 0 },
16572   { "sicw", 284 /* xt_iclass_sicx */,
16573     0,
16574     Opcode_sicw_encode_fns, 0, 0 },
16575   { "dhwb", 285 /* xt_iclass_dcache */,
16576     0,
16577     Opcode_dhwb_encode_fns, 0, 0 },
16578   { "dhwbi", 285 /* xt_iclass_dcache */,
16579     0,
16580     Opcode_dhwbi_encode_fns, 0, 0 },
16581   { "diwb", 286 /* xt_iclass_dcache_ind */,
16582     0,
16583     Opcode_diwb_encode_fns, 0, 0 },
16584   { "diwbi", 286 /* xt_iclass_dcache_ind */,
16585     0,
16586     Opcode_diwbi_encode_fns, 0, 0 },
16587   { "dhi", 287 /* xt_iclass_dcache_inv */,
16588     0,
16589     Opcode_dhi_encode_fns, 0, 0 },
16590   { "dii", 287 /* xt_iclass_dcache_inv */,
16591     0,
16592     Opcode_dii_encode_fns, 0, 0 },
16593   { "dpfr", 288 /* xt_iclass_dpf */,
16594     0,
16595     Opcode_dpfr_encode_fns, 0, 0 },
16596   { "dpfw", 288 /* xt_iclass_dpf */,
16597     0,
16598     Opcode_dpfw_encode_fns, 0, 0 },
16599   { "dpfro", 288 /* xt_iclass_dpf */,
16600     0,
16601     Opcode_dpfro_encode_fns, 0, 0 },
16602   { "dpfwo", 288 /* xt_iclass_dpf */,
16603     0,
16604     Opcode_dpfwo_encode_fns, 0, 0 },
16605   { "dpfl", 289 /* xt_iclass_dcache_lock */,
16606     0,
16607     Opcode_dpfl_encode_fns, 0, 0 },
16608   { "dhu", 289 /* xt_iclass_dcache_lock */,
16609     0,
16610     Opcode_dhu_encode_fns, 0, 0 },
16611   { "diu", 289 /* xt_iclass_dcache_lock */,
16612     0,
16613     Opcode_diu_encode_fns, 0, 0 },
16614   { "sdct", 290 /* xt_iclass_sdct */,
16615     0,
16616     Opcode_sdct_encode_fns, 0, 0 },
16617   { "ldct", 291 /* xt_iclass_ldct */,
16618     0,
16619     Opcode_ldct_encode_fns, 0, 0 },
16620   { "wsr.ptevaddr", 292 /* xt_iclass_wsr.ptevaddr */,
16621     0,
16622     Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
16623   { "rsr.ptevaddr", 293 /* xt_iclass_rsr.ptevaddr */,
16624     0,
16625     Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
16626   { "xsr.ptevaddr", 294 /* xt_iclass_xsr.ptevaddr */,
16627     0,
16628     Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
16629   { "rsr.rasid", 295 /* xt_iclass_rsr.rasid */,
16630     0,
16631     Opcode_rsr_rasid_encode_fns, 0, 0 },
16632   { "wsr.rasid", 296 /* xt_iclass_wsr.rasid */,
16633     0,
16634     Opcode_wsr_rasid_encode_fns, 0, 0 },
16635   { "xsr.rasid", 297 /* xt_iclass_xsr.rasid */,
16636     0,
16637     Opcode_xsr_rasid_encode_fns, 0, 0 },
16638   { "rsr.itlbcfg", 298 /* xt_iclass_rsr.itlbcfg */,
16639     0,
16640     Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
16641   { "wsr.itlbcfg", 299 /* xt_iclass_wsr.itlbcfg */,
16642     0,
16643     Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
16644   { "xsr.itlbcfg", 300 /* xt_iclass_xsr.itlbcfg */,
16645     0,
16646     Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
16647   { "rsr.dtlbcfg", 301 /* xt_iclass_rsr.dtlbcfg */,
16648     0,
16649     Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
16650   { "wsr.dtlbcfg", 302 /* xt_iclass_wsr.dtlbcfg */,
16651     0,
16652     Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
16653   { "xsr.dtlbcfg", 303 /* xt_iclass_xsr.dtlbcfg */,
16654     0,
16655     Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
16656   { "idtlb", 304 /* xt_iclass_idtlb */,
16657     0,
16658     Opcode_idtlb_encode_fns, 0, 0 },
16659   { "pdtlb", 305 /* xt_iclass_rdtlb */,
16660     0,
16661     Opcode_pdtlb_encode_fns, 0, 0 },
16662   { "rdtlb0", 305 /* xt_iclass_rdtlb */,
16663     0,
16664     Opcode_rdtlb0_encode_fns, 0, 0 },
16665   { "rdtlb1", 305 /* xt_iclass_rdtlb */,
16666     0,
16667     Opcode_rdtlb1_encode_fns, 0, 0 },
16668   { "wdtlb", 306 /* xt_iclass_wdtlb */,
16669     0,
16670     Opcode_wdtlb_encode_fns, 0, 0 },
16671   { "iitlb", 307 /* xt_iclass_iitlb */,
16672     0,
16673     Opcode_iitlb_encode_fns, 0, 0 },
16674   { "pitlb", 308 /* xt_iclass_ritlb */,
16675     0,
16676     Opcode_pitlb_encode_fns, 0, 0 },
16677   { "ritlb0", 308 /* xt_iclass_ritlb */,
16678     0,
16679     Opcode_ritlb0_encode_fns, 0, 0 },
16680   { "ritlb1", 308 /* xt_iclass_ritlb */,
16681     0,
16682     Opcode_ritlb1_encode_fns, 0, 0 },
16683   { "witlb", 309 /* xt_iclass_witlb */,
16684     0,
16685     Opcode_witlb_encode_fns, 0, 0 },
16686   { "ldpte", 310 /* xt_iclass_ldpte */,
16687     0,
16688     Opcode_ldpte_encode_fns, 0, 0 },
16689   { "hwwitlba", 311 /* xt_iclass_hwwitlba */,
16690     XTENSA_OPCODE_IS_BRANCH,
16691     Opcode_hwwitlba_encode_fns, 0, 0 },
16692   { "hwwdtlba", 312 /* xt_iclass_hwwdtlba */,
16693     0,
16694     Opcode_hwwdtlba_encode_fns, 0, 0 },
16695   { "rsr.cpenable", 313 /* xt_iclass_rsr.cpenable */,
16696     0,
16697     Opcode_rsr_cpenable_encode_fns, 0, 0 },
16698   { "wsr.cpenable", 314 /* xt_iclass_wsr.cpenable */,
16699     0,
16700     Opcode_wsr_cpenable_encode_fns, 0, 0 },
16701   { "xsr.cpenable", 315 /* xt_iclass_xsr.cpenable */,
16702     0,
16703     Opcode_xsr_cpenable_encode_fns, 0, 0 },
16704   { "clamps", 316 /* xt_iclass_clamp */,
16705     0,
16706     Opcode_clamps_encode_fns, 0, 0 },
16707   { "min", 317 /* xt_iclass_minmax */,
16708     0,
16709     Opcode_min_encode_fns, 0, 0 },
16710   { "max", 317 /* xt_iclass_minmax */,
16711     0,
16712     Opcode_max_encode_fns, 0, 0 },
16713   { "minu", 317 /* xt_iclass_minmax */,
16714     0,
16715     Opcode_minu_encode_fns, 0, 0 },
16716   { "maxu", 317 /* xt_iclass_minmax */,
16717     0,
16718     Opcode_maxu_encode_fns, 0, 0 },
16719   { "nsa", 318 /* xt_iclass_nsa */,
16720     0,
16721     Opcode_nsa_encode_fns, 0, 0 },
16722   { "nsau", 318 /* xt_iclass_nsa */,
16723     0,
16724     Opcode_nsau_encode_fns, 0, 0 },
16725   { "sext", 319 /* xt_iclass_sx */,
16726     0,
16727     Opcode_sext_encode_fns, 0, 0 },
16728   { "l32ai", 320 /* xt_iclass_l32ai */,
16729     0,
16730     Opcode_l32ai_encode_fns, 0, 0 },
16731   { "s32ri", 321 /* xt_iclass_s32ri */,
16732     0,
16733     Opcode_s32ri_encode_fns, 0, 0 },
16734   { "s32c1i", 322 /* xt_iclass_s32c1i */,
16735     0,
16736     Opcode_s32c1i_encode_fns, 0, 0 },
16737   { "rsr.scompare1", 323 /* xt_iclass_rsr.scompare1 */,
16738     0,
16739     Opcode_rsr_scompare1_encode_fns, 0, 0 },
16740   { "wsr.scompare1", 324 /* xt_iclass_wsr.scompare1 */,
16741     0,
16742     Opcode_wsr_scompare1_encode_fns, 0, 0 },
16743   { "xsr.scompare1", 325 /* xt_iclass_xsr.scompare1 */,
16744     0,
16745     Opcode_xsr_scompare1_encode_fns, 0, 0 },
16746   { "quou", 326 /* xt_iclass_div */,
16747     0,
16748     Opcode_quou_encode_fns, 0, 0 },
16749   { "quos", 326 /* xt_iclass_div */,
16750     0,
16751     Opcode_quos_encode_fns, 0, 0 },
16752   { "remu", 326 /* xt_iclass_div */,
16753     0,
16754     Opcode_remu_encode_fns, 0, 0 },
16755   { "rems", 326 /* xt_iclass_div */,
16756     0,
16757     Opcode_rems_encode_fns, 0, 0 },
16758   { "mull", 327 /* xt_mul32 */,
16759     0,
16760     Opcode_mull_encode_fns, 0, 0 },
16761   { "muluh", 327 /* xt_mul32 */,
16762     0,
16763     Opcode_muluh_encode_fns, 0, 0 },
16764   { "mulsh", 327 /* xt_mul32 */,
16765     0,
16766     Opcode_mulsh_encode_fns, 0, 0 },
16767   { "rur.fcr", 328 /* rur_fcr */,
16768     0,
16769     Opcode_rur_fcr_encode_fns, 0, 0 },
16770   { "wur.fcr", 329 /* wur_fcr */,
16771     0,
16772     Opcode_wur_fcr_encode_fns, 0, 0 },
16773   { "rur.fsr", 330 /* rur_fsr */,
16774     0,
16775     Opcode_rur_fsr_encode_fns, 0, 0 },
16776   { "wur.fsr", 331 /* wur_fsr */,
16777     0,
16778     Opcode_wur_fsr_encode_fns, 0, 0 },
16779   { "add.s", 332 /* fp */,
16780     0,
16781     Opcode_add_s_encode_fns, 0, 0 },
16782   { "sub.s", 332 /* fp */,
16783     0,
16784     Opcode_sub_s_encode_fns, 0, 0 },
16785   { "mul.s", 332 /* fp */,
16786     0,
16787     Opcode_mul_s_encode_fns, 0, 0 },
16788   { "madd.s", 333 /* fp_mac */,
16789     0,
16790     Opcode_madd_s_encode_fns, 0, 0 },
16791   { "msub.s", 333 /* fp_mac */,
16792     0,
16793     Opcode_msub_s_encode_fns, 0, 0 },
16794   { "movf.s", 334 /* fp_cmov */,
16795     0,
16796     Opcode_movf_s_encode_fns, 0, 0 },
16797   { "movt.s", 334 /* fp_cmov */,
16798     0,
16799     Opcode_movt_s_encode_fns, 0, 0 },
16800   { "moveqz.s", 335 /* fp_mov */,
16801     0,
16802     Opcode_moveqz_s_encode_fns, 0, 0 },
16803   { "movnez.s", 335 /* fp_mov */,
16804     0,
16805     Opcode_movnez_s_encode_fns, 0, 0 },
16806   { "movltz.s", 335 /* fp_mov */,
16807     0,
16808     Opcode_movltz_s_encode_fns, 0, 0 },
16809   { "movgez.s", 335 /* fp_mov */,
16810     0,
16811     Opcode_movgez_s_encode_fns, 0, 0 },
16812   { "abs.s", 336 /* fp_mov2 */,
16813     0,
16814     Opcode_abs_s_encode_fns, 0, 0 },
16815   { "mov.s", 336 /* fp_mov2 */,
16816     0,
16817     Opcode_mov_s_encode_fns, 0, 0 },
16818   { "neg.s", 336 /* fp_mov2 */,
16819     0,
16820     Opcode_neg_s_encode_fns, 0, 0 },
16821   { "un.s", 337 /* fp_cmp */,
16822     0,
16823     Opcode_un_s_encode_fns, 0, 0 },
16824   { "oeq.s", 337 /* fp_cmp */,
16825     0,
16826     Opcode_oeq_s_encode_fns, 0, 0 },
16827   { "ueq.s", 337 /* fp_cmp */,
16828     0,
16829     Opcode_ueq_s_encode_fns, 0, 0 },
16830   { "olt.s", 337 /* fp_cmp */,
16831     0,
16832     Opcode_olt_s_encode_fns, 0, 0 },
16833   { "ult.s", 337 /* fp_cmp */,
16834     0,
16835     Opcode_ult_s_encode_fns, 0, 0 },
16836   { "ole.s", 337 /* fp_cmp */,
16837     0,
16838     Opcode_ole_s_encode_fns, 0, 0 },
16839   { "ule.s", 337 /* fp_cmp */,
16840     0,
16841     Opcode_ule_s_encode_fns, 0, 0 },
16842   { "float.s", 338 /* fp_float */,
16843     0,
16844     Opcode_float_s_encode_fns, 0, 0 },
16845   { "ufloat.s", 338 /* fp_float */,
16846     0,
16847     Opcode_ufloat_s_encode_fns, 0, 0 },
16848   { "round.s", 339 /* fp_int */,
16849     0,
16850     Opcode_round_s_encode_fns, 0, 0 },
16851   { "ceil.s", 339 /* fp_int */,
16852     0,
16853     Opcode_ceil_s_encode_fns, 0, 0 },
16854   { "floor.s", 339 /* fp_int */,
16855     0,
16856     Opcode_floor_s_encode_fns, 0, 0 },
16857   { "trunc.s", 339 /* fp_int */,
16858     0,
16859     Opcode_trunc_s_encode_fns, 0, 0 },
16860   { "utrunc.s", 339 /* fp_int */,
16861     0,
16862     Opcode_utrunc_s_encode_fns, 0, 0 },
16863   { "rfr", 340 /* fp_rfr */,
16864     0,
16865     Opcode_rfr_encode_fns, 0, 0 },
16866   { "wfr", 341 /* fp_wfr */,
16867     0,
16868     Opcode_wfr_encode_fns, 0, 0 },
16869   { "lsi", 342 /* fp_lsi */,
16870     0,
16871     Opcode_lsi_encode_fns, 0, 0 },
16872   { "lsiu", 343 /* fp_lsiu */,
16873     0,
16874     Opcode_lsiu_encode_fns, 0, 0 },
16875   { "lsx", 344 /* fp_lsx */,
16876     0,
16877     Opcode_lsx_encode_fns, 0, 0 },
16878   { "lsxu", 345 /* fp_lsxu */,
16879     0,
16880     Opcode_lsxu_encode_fns, 0, 0 },
16881   { "ssi", 346 /* fp_ssi */,
16882     0,
16883     Opcode_ssi_encode_fns, 0, 0 },
16884   { "ssiu", 347 /* fp_ssiu */,
16885     0,
16886     Opcode_ssiu_encode_fns, 0, 0 },
16887   { "ssx", 348 /* fp_ssx */,
16888     0,
16889     Opcode_ssx_encode_fns, 0, 0 },
16890   { "ssxu", 349 /* fp_ssxu */,
16891     0,
16892     Opcode_ssxu_encode_fns, 0, 0 },
16893   { "beqz.w18", 350 /* xt_iclass_wb18_0 */,
16894     XTENSA_OPCODE_IS_BRANCH,
16895     Opcode_beqz_w18_encode_fns, 0, 0 },
16896   { "bnez.w18", 350 /* xt_iclass_wb18_0 */,
16897     XTENSA_OPCODE_IS_BRANCH,
16898     Opcode_bnez_w18_encode_fns, 0, 0 },
16899   { "bgez.w18", 350 /* xt_iclass_wb18_0 */,
16900     XTENSA_OPCODE_IS_BRANCH,
16901     Opcode_bgez_w18_encode_fns, 0, 0 },
16902   { "bltz.w18", 350 /* xt_iclass_wb18_0 */,
16903     XTENSA_OPCODE_IS_BRANCH,
16904     Opcode_bltz_w18_encode_fns, 0, 0 },
16905   { "beqi.w18", 351 /* xt_iclass_wb18_1 */,
16906     XTENSA_OPCODE_IS_BRANCH,
16907     Opcode_beqi_w18_encode_fns, 0, 0 },
16908   { "bnei.w18", 351 /* xt_iclass_wb18_1 */,
16909     XTENSA_OPCODE_IS_BRANCH,
16910     Opcode_bnei_w18_encode_fns, 0, 0 },
16911   { "bgei.w18", 351 /* xt_iclass_wb18_1 */,
16912     XTENSA_OPCODE_IS_BRANCH,
16913     Opcode_bgei_w18_encode_fns, 0, 0 },
16914   { "blti.w18", 351 /* xt_iclass_wb18_1 */,
16915     XTENSA_OPCODE_IS_BRANCH,
16916     Opcode_blti_w18_encode_fns, 0, 0 },
16917   { "bgeui.w18", 352 /* xt_iclass_wb18_2 */,
16918     XTENSA_OPCODE_IS_BRANCH,
16919     Opcode_bgeui_w18_encode_fns, 0, 0 },
16920   { "bltui.w18", 352 /* xt_iclass_wb18_2 */,
16921     XTENSA_OPCODE_IS_BRANCH,
16922     Opcode_bltui_w18_encode_fns, 0, 0 },
16923   { "bbci.w18", 353 /* xt_iclass_wb18_3 */,
16924     XTENSA_OPCODE_IS_BRANCH,
16925     Opcode_bbci_w18_encode_fns, 0, 0 },
16926   { "bbsi.w18", 353 /* xt_iclass_wb18_3 */,
16927     XTENSA_OPCODE_IS_BRANCH,
16928     Opcode_bbsi_w18_encode_fns, 0, 0 },
16929   { "beq.w18", 354 /* xt_iclass_wb18_4 */,
16930     XTENSA_OPCODE_IS_BRANCH,
16931     Opcode_beq_w18_encode_fns, 0, 0 },
16932   { "bne.w18", 354 /* xt_iclass_wb18_4 */,
16933     XTENSA_OPCODE_IS_BRANCH,
16934     Opcode_bne_w18_encode_fns, 0, 0 },
16935   { "bge.w18", 354 /* xt_iclass_wb18_4 */,
16936     XTENSA_OPCODE_IS_BRANCH,
16937     Opcode_bge_w18_encode_fns, 0, 0 },
16938   { "blt.w18", 354 /* xt_iclass_wb18_4 */,
16939     XTENSA_OPCODE_IS_BRANCH,
16940     Opcode_blt_w18_encode_fns, 0, 0 },
16941   { "bgeu.w18", 354 /* xt_iclass_wb18_4 */,
16942     XTENSA_OPCODE_IS_BRANCH,
16943     Opcode_bgeu_w18_encode_fns, 0, 0 },
16944   { "bltu.w18", 354 /* xt_iclass_wb18_4 */,
16945     XTENSA_OPCODE_IS_BRANCH,
16946     Opcode_bltu_w18_encode_fns, 0, 0 },
16947   { "bany.w18", 354 /* xt_iclass_wb18_4 */,
16948     XTENSA_OPCODE_IS_BRANCH,
16949     Opcode_bany_w18_encode_fns, 0, 0 },
16950   { "bnone.w18", 354 /* xt_iclass_wb18_4 */,
16951     XTENSA_OPCODE_IS_BRANCH,
16952     Opcode_bnone_w18_encode_fns, 0, 0 },
16953   { "ball.w18", 354 /* xt_iclass_wb18_4 */,
16954     XTENSA_OPCODE_IS_BRANCH,
16955     Opcode_ball_w18_encode_fns, 0, 0 },
16956   { "bnall.w18", 354 /* xt_iclass_wb18_4 */,
16957     XTENSA_OPCODE_IS_BRANCH,
16958     Opcode_bnall_w18_encode_fns, 0, 0 },
16959   { "bbc.w18", 354 /* xt_iclass_wb18_4 */,
16960     XTENSA_OPCODE_IS_BRANCH,
16961     Opcode_bbc_w18_encode_fns, 0, 0 },
16962   { "bbs.w18", 354 /* xt_iclass_wb18_4 */,
16963     XTENSA_OPCODE_IS_BRANCH,
16964     Opcode_bbs_w18_encode_fns, 0, 0 }
16965 };
16966
16967 \f
16968 /* Slot-specific opcode decode functions.  */
16969
16970 static int
16971 Slot_inst_decode (const xtensa_insnbuf insn)
16972 {
16973   switch (Field_op0_Slot_inst_get (insn))
16974     {
16975     case 0:
16976       switch (Field_op1_Slot_inst_get (insn))
16977         {
16978         case 0:
16979           switch (Field_op2_Slot_inst_get (insn))
16980             {
16981             case 0:
16982               switch (Field_r_Slot_inst_get (insn))
16983                 {
16984                 case 0:
16985                   switch (Field_m_Slot_inst_get (insn))
16986                     {
16987                     case 0:
16988                       if (Field_s_Slot_inst_get (insn) == 0 &&
16989                           Field_n_Slot_inst_get (insn) == 0)
16990                         return 79; /* ill */
16991                       break;
16992                     case 2:
16993                       switch (Field_n_Slot_inst_get (insn))
16994                         {
16995                         case 0:
16996                           return 98; /* ret */
16997                         case 1:
16998                           return 14; /* retw */
16999                         case 2:
17000                           return 81; /* jx */
17001                         }
17002                       break;
17003                     case 3:
17004                       switch (Field_n_Slot_inst_get (insn))
17005                         {
17006                         case 0:
17007                           return 77; /* callx0 */
17008                         case 1:
17009                           return 10; /* callx4 */
17010                         case 2:
17011                           return 9; /* callx8 */
17012                         case 3:
17013                           return 8; /* callx12 */
17014                         }
17015                       break;
17016                     }
17017                   break;
17018                 case 1:
17019                   return 12; /* movsp */
17020                 case 2:
17021                   if (Field_s_Slot_inst_get (insn) == 0)
17022                     {
17023                       switch (Field_t_Slot_inst_get (insn))
17024                         {
17025                         case 0:
17026                           return 116; /* isync */
17027                         case 1:
17028                           return 117; /* rsync */
17029                         case 2:
17030                           return 118; /* esync */
17031                         case 3:
17032                           return 119; /* dsync */
17033                         case 8:
17034                           return 0; /* excw */
17035                         case 12:
17036                           return 114; /* memw */
17037                         case 13:
17038                           return 115; /* extw */
17039                         case 15:
17040                           return 97; /* nop */
17041                         }
17042                     }
17043                   break;
17044                 case 3:
17045                   switch (Field_t_Slot_inst_get (insn))
17046                     {
17047                     case 0:
17048                       switch (Field_s_Slot_inst_get (insn))
17049                         {
17050                         case 0:
17051                           return 1; /* rfe */
17052                         case 2:
17053                           return 2; /* rfde */
17054                         case 4:
17055                           return 16; /* rfwo */
17056                         case 5:
17057                           return 17; /* rfwu */
17058                         }
17059                       break;
17060                     case 1:
17061                       return 316; /* rfi */
17062                     }
17063                   break;
17064                 case 4:
17065                   return 324; /* break */
17066                 case 5:
17067                   switch (Field_s_Slot_inst_get (insn))
17068                     {
17069                     case 0:
17070                       if (Field_t_Slot_inst_get (insn) == 0)
17071                         return 3; /* syscall */
17072                       break;
17073                     case 1:
17074                       if (Field_t_Slot_inst_get (insn) == 0)
17075                         return 4; /* simcall */
17076                       break;
17077                     }
17078                   break;
17079                 case 6:
17080                   return 120; /* rsil */
17081                 case 7:
17082                   if (Field_t_Slot_inst_get (insn) == 0)
17083                     return 317; /* waiti */
17084                   break;
17085                 case 8:
17086                   return 367; /* any4 */
17087                 case 9:
17088                   return 368; /* all4 */
17089                 case 10:
17090                   return 369; /* any8 */
17091                 case 11:
17092                   return 370; /* all8 */
17093                 }
17094               break;
17095             case 1:
17096               return 49; /* and */
17097             case 2:
17098               return 50; /* or */
17099             case 3:
17100               return 51; /* xor */
17101             case 4:
17102               switch (Field_r_Slot_inst_get (insn))
17103                 {
17104                 case 0:
17105                   if (Field_t_Slot_inst_get (insn) == 0)
17106                     return 102; /* ssr */
17107                   break;
17108                 case 1:
17109                   if (Field_t_Slot_inst_get (insn) == 0)
17110                     return 103; /* ssl */
17111                   break;
17112                 case 2:
17113                   if (Field_t_Slot_inst_get (insn) == 0)
17114                     return 104; /* ssa8l */
17115                   break;
17116                 case 3:
17117                   if (Field_t_Slot_inst_get (insn) == 0)
17118                     return 105; /* ssa8b */
17119                   break;
17120                 case 4:
17121                   if (Field_thi3_Slot_inst_get (insn) == 0)
17122                     return 106; /* ssai */
17123                   break;
17124                 case 8:
17125                   if (Field_s_Slot_inst_get (insn) == 0)
17126                     return 13; /* rotw */
17127                   break;
17128                 case 14:
17129                   return 448; /* nsa */
17130                 case 15:
17131                   return 449; /* nsau */
17132                 }
17133               break;
17134             case 5:
17135               switch (Field_r_Slot_inst_get (insn))
17136                 {
17137                 case 1:
17138                   return 438; /* hwwitlba */
17139                 case 3:
17140                   return 434; /* ritlb0 */
17141                 case 4:
17142                   if (Field_t_Slot_inst_get (insn) == 0)
17143                     return 432; /* iitlb */
17144                   break;
17145                 case 5:
17146                   return 433; /* pitlb */
17147                 case 6:
17148                   return 436; /* witlb */
17149                 case 7:
17150                   return 435; /* ritlb1 */
17151                 case 9:
17152                   return 439; /* hwwdtlba */
17153                 case 11:
17154                   return 429; /* rdtlb0 */
17155                 case 12:
17156                   if (Field_t_Slot_inst_get (insn) == 0)
17157                     return 427; /* idtlb */
17158                   break;
17159                 case 13:
17160                   return 428; /* pdtlb */
17161                 case 14:
17162                   return 431; /* wdtlb */
17163                 case 15:
17164                   return 430; /* rdtlb1 */
17165                 }
17166               break;
17167             case 6:
17168               switch (Field_s_Slot_inst_get (insn))
17169                 {
17170                 case 0:
17171                   return 95; /* neg */
17172                 case 1:
17173                   return 96; /* abs */
17174                 }
17175               break;
17176             case 8:
17177               return 41; /* add */
17178             case 9:
17179               return 43; /* addx2 */
17180             case 10:
17181               return 44; /* addx4 */
17182             case 11:
17183               return 45; /* addx8 */
17184             case 12:
17185               return 42; /* sub */
17186             case 13:
17187               return 46; /* subx2 */
17188             case 14:
17189               return 47; /* subx4 */
17190             case 15:
17191               return 48; /* subx8 */
17192             }
17193           break;
17194         case 1:
17195           switch (Field_op2_Slot_inst_get (insn))
17196             {
17197             case 0:
17198             case 1:
17199               return 111; /* slli */
17200             case 2:
17201             case 3:
17202               return 112; /* srai */
17203             case 4:
17204               return 113; /* srli */
17205             case 6:
17206               switch (Field_sr_Slot_inst_get (insn))
17207                 {
17208                 case 0:
17209                   return 129; /* xsr.lbeg */
17210                 case 1:
17211                   return 123; /* xsr.lend */
17212                 case 2:
17213                   return 126; /* xsr.lcount */
17214                 case 3:
17215                   return 132; /* xsr.sar */
17216                 case 4:
17217                   return 377; /* xsr.br */
17218                 case 5:
17219                   return 135; /* xsr.litbase */
17220                 case 12:
17221                   return 456; /* xsr.scompare1 */
17222                 case 16:
17223                   return 312; /* xsr.acclo */
17224                 case 17:
17225                   return 315; /* xsr.acchi */
17226                 case 32:
17227                   return 300; /* xsr.m0 */
17228                 case 33:
17229                   return 303; /* xsr.m1 */
17230                 case 34:
17231                   return 306; /* xsr.m2 */
17232                 case 35:
17233                   return 309; /* xsr.m3 */
17234                 case 72:
17235                   return 22; /* xsr.windowbase */
17236                 case 73:
17237                   return 25; /* xsr.windowstart */
17238                 case 83:
17239                   return 417; /* xsr.ptevaddr */
17240                 case 90:
17241                   return 420; /* xsr.rasid */
17242                 case 91:
17243                   return 423; /* xsr.itlbcfg */
17244                 case 92:
17245                   return 426; /* xsr.dtlbcfg */
17246                 case 96:
17247                   return 346; /* xsr.ibreakenable */
17248                 case 104:
17249                   return 358; /* xsr.ddr */
17250                 case 128:
17251                   return 340; /* xsr.ibreaka0 */
17252                 case 129:
17253                   return 343; /* xsr.ibreaka1 */
17254                 case 144:
17255                   return 328; /* xsr.dbreaka0 */
17256                 case 145:
17257                   return 334; /* xsr.dbreaka1 */
17258                 case 160:
17259                   return 331; /* xsr.dbreakc0 */
17260                 case 161:
17261                   return 337; /* xsr.dbreakc1 */
17262                 case 177:
17263                   return 143; /* xsr.epc1 */
17264                 case 178:
17265                   return 149; /* xsr.epc2 */
17266                 case 179:
17267                   return 155; /* xsr.epc3 */
17268                 case 180:
17269                   return 161; /* xsr.epc4 */
17270                 case 181:
17271                   return 167; /* xsr.epc5 */
17272                 case 182:
17273                   return 173; /* xsr.epc6 */
17274                 case 183:
17275                   return 179; /* xsr.epc7 */
17276                 case 192:
17277                   return 206; /* xsr.depc */
17278                 case 194:
17279                   return 185; /* xsr.eps2 */
17280                 case 195:
17281                   return 188; /* xsr.eps3 */
17282                 case 196:
17283                   return 191; /* xsr.eps4 */
17284                 case 197:
17285                   return 194; /* xsr.eps5 */
17286                 case 198:
17287                   return 197; /* xsr.eps6 */
17288                 case 199:
17289                   return 200; /* xsr.eps7 */
17290                 case 209:
17291                   return 146; /* xsr.excsave1 */
17292                 case 210:
17293                   return 152; /* xsr.excsave2 */
17294                 case 211:
17295                   return 158; /* xsr.excsave3 */
17296                 case 212:
17297                   return 164; /* xsr.excsave4 */
17298                 case 213:
17299                   return 170; /* xsr.excsave5 */
17300                 case 214:
17301                   return 176; /* xsr.excsave6 */
17302                 case 215:
17303                   return 182; /* xsr.excsave7 */
17304                 case 224:
17305                   return 442; /* xsr.cpenable */
17306                 case 228:
17307                   return 323; /* xsr.intenable */
17308                 case 230:
17309                   return 140; /* xsr.ps */
17310                 case 231:
17311                   return 225; /* xsr.vecbase */
17312                 case 232:
17313                   return 209; /* xsr.exccause */
17314                 case 233:
17315                   return 349; /* xsr.debugcause */
17316                 case 234:
17317                   return 380; /* xsr.ccount */
17318                 case 236:
17319                   return 352; /* xsr.icount */
17320                 case 237:
17321                   return 355; /* xsr.icountlevel */
17322                 case 238:
17323                   return 203; /* xsr.excvaddr */
17324                 case 240:
17325                   return 383; /* xsr.ccompare0 */
17326                 case 241:
17327                   return 386; /* xsr.ccompare1 */
17328                 case 242:
17329                   return 389; /* xsr.ccompare2 */
17330                 case 244:
17331                   return 212; /* xsr.misc0 */
17332                 case 245:
17333                   return 215; /* xsr.misc1 */
17334                 case 246:
17335                   return 218; /* xsr.misc2 */
17336                 case 247:
17337                   return 221; /* xsr.misc3 */
17338                 }
17339               break;
17340             case 8:
17341               return 108; /* src */
17342             case 9:
17343               if (Field_s_Slot_inst_get (insn) == 0)
17344                 return 109; /* srl */
17345               break;
17346             case 10:
17347               if (Field_t_Slot_inst_get (insn) == 0)
17348                 return 107; /* sll */
17349               break;
17350             case 11:
17351               if (Field_s_Slot_inst_get (insn) == 0)
17352                 return 110; /* sra */
17353               break;
17354             case 12:
17355               return 296; /* mul16u */
17356             case 13:
17357               return 297; /* mul16s */
17358             case 15:
17359               switch (Field_r_Slot_inst_get (insn))
17360                 {
17361                 case 0:
17362                   return 396; /* lict */
17363                 case 1:
17364                   return 398; /* sict */
17365                 case 2:
17366                   return 397; /* licw */
17367                 case 3:
17368                   return 399; /* sicw */
17369                 case 8:
17370                   return 414; /* ldct */
17371                 case 9:
17372                   return 413; /* sdct */
17373                 case 14:
17374                   if (Field_t_Slot_inst_get (insn) == 0)
17375                     return 359; /* rfdo */
17376                   if (Field_t_Slot_inst_get (insn) == 1)
17377                     return 360; /* rfdd */
17378                   break;
17379                 case 15:
17380                   return 437; /* ldpte */
17381                 }
17382               break;
17383             }
17384           break;
17385         case 2:
17386           switch (Field_op2_Slot_inst_get (insn))
17387             {
17388             case 0:
17389               return 362; /* andb */
17390             case 1:
17391               return 363; /* andbc */
17392             case 2:
17393               return 364; /* orb */
17394             case 3:
17395               return 365; /* orbc */
17396             case 4:
17397               return 366; /* xorb */
17398             case 8:
17399               return 461; /* mull */
17400             case 10:
17401               return 462; /* muluh */
17402             case 11:
17403               return 463; /* mulsh */
17404             case 12:
17405               return 457; /* quou */
17406             case 13:
17407               return 458; /* quos */
17408             case 14:
17409               return 459; /* remu */
17410             case 15:
17411               return 460; /* rems */
17412             }
17413           break;
17414         case 3:
17415           switch (Field_op2_Slot_inst_get (insn))
17416             {
17417             case 0:
17418               switch (Field_sr_Slot_inst_get (insn))
17419                 {
17420                 case 0:
17421                   return 127; /* rsr.lbeg */
17422                 case 1:
17423                   return 121; /* rsr.lend */
17424                 case 2:
17425                   return 124; /* rsr.lcount */
17426                 case 3:
17427                   return 130; /* rsr.sar */
17428                 case 4:
17429                   return 375; /* rsr.br */
17430                 case 5:
17431                   return 133; /* rsr.litbase */
17432                 case 12:
17433                   return 454; /* rsr.scompare1 */
17434                 case 16:
17435                   return 310; /* rsr.acclo */
17436                 case 17:
17437                   return 313; /* rsr.acchi */
17438                 case 32:
17439                   return 298; /* rsr.m0 */
17440                 case 33:
17441                   return 301; /* rsr.m1 */
17442                 case 34:
17443                   return 304; /* rsr.m2 */
17444                 case 35:
17445                   return 307; /* rsr.m3 */
17446                 case 72:
17447                   return 20; /* rsr.windowbase */
17448                 case 73:
17449                   return 23; /* rsr.windowstart */
17450                 case 83:
17451                   return 416; /* rsr.ptevaddr */
17452                 case 90:
17453                   return 418; /* rsr.rasid */
17454                 case 91:
17455                   return 421; /* rsr.itlbcfg */
17456                 case 92:
17457                   return 424; /* rsr.dtlbcfg */
17458                 case 96:
17459                   return 344; /* rsr.ibreakenable */
17460                 case 104:
17461                   return 356; /* rsr.ddr */
17462                 case 128:
17463                   return 338; /* rsr.ibreaka0 */
17464                 case 129:
17465                   return 341; /* rsr.ibreaka1 */
17466                 case 144:
17467                   return 326; /* rsr.dbreaka0 */
17468                 case 145:
17469                   return 332; /* rsr.dbreaka1 */
17470                 case 160:
17471                   return 329; /* rsr.dbreakc0 */
17472                 case 161:
17473                   return 335; /* rsr.dbreakc1 */
17474                 case 176:
17475                   return 136; /* rsr.176 */
17476                 case 177:
17477                   return 141; /* rsr.epc1 */
17478                 case 178:
17479                   return 147; /* rsr.epc2 */
17480                 case 179:
17481                   return 153; /* rsr.epc3 */
17482                 case 180:
17483                   return 159; /* rsr.epc4 */
17484                 case 181:
17485                   return 165; /* rsr.epc5 */
17486                 case 182:
17487                   return 171; /* rsr.epc6 */
17488                 case 183:
17489                   return 177; /* rsr.epc7 */
17490                 case 192:
17491                   return 204; /* rsr.depc */
17492                 case 194:
17493                   return 183; /* rsr.eps2 */
17494                 case 195:
17495                   return 186; /* rsr.eps3 */
17496                 case 196:
17497                   return 189; /* rsr.eps4 */
17498                 case 197:
17499                   return 192; /* rsr.eps5 */
17500                 case 198:
17501                   return 195; /* rsr.eps6 */
17502                 case 199:
17503                   return 198; /* rsr.eps7 */
17504                 case 208:
17505                   return 137; /* rsr.208 */
17506                 case 209:
17507                   return 144; /* rsr.excsave1 */
17508                 case 210:
17509                   return 150; /* rsr.excsave2 */
17510                 case 211:
17511                   return 156; /* rsr.excsave3 */
17512                 case 212:
17513                   return 162; /* rsr.excsave4 */
17514                 case 213:
17515                   return 168; /* rsr.excsave5 */
17516                 case 214:
17517                   return 174; /* rsr.excsave6 */
17518                 case 215:
17519                   return 180; /* rsr.excsave7 */
17520                 case 224:
17521                   return 440; /* rsr.cpenable */
17522                 case 226:
17523                   return 318; /* rsr.interrupt */
17524                 case 228:
17525                   return 321; /* rsr.intenable */
17526                 case 230:
17527                   return 138; /* rsr.ps */
17528                 case 231:
17529                   return 223; /* rsr.vecbase */
17530                 case 232:
17531                   return 207; /* rsr.exccause */
17532                 case 233:
17533                   return 347; /* rsr.debugcause */
17534                 case 234:
17535                   return 378; /* rsr.ccount */
17536                 case 235:
17537                   return 222; /* rsr.prid */
17538                 case 236:
17539                   return 350; /* rsr.icount */
17540                 case 237:
17541                   return 353; /* rsr.icountlevel */
17542                 case 238:
17543                   return 201; /* rsr.excvaddr */
17544                 case 240:
17545                   return 381; /* rsr.ccompare0 */
17546                 case 241:
17547                   return 384; /* rsr.ccompare1 */
17548                 case 242:
17549                   return 387; /* rsr.ccompare2 */
17550                 case 244:
17551                   return 210; /* rsr.misc0 */
17552                 case 245:
17553                   return 213; /* rsr.misc1 */
17554                 case 246:
17555                   return 216; /* rsr.misc2 */
17556                 case 247:
17557                   return 219; /* rsr.misc3 */
17558                 }
17559               break;
17560             case 1:
17561               switch (Field_sr_Slot_inst_get (insn))
17562                 {
17563                 case 0:
17564                   return 128; /* wsr.lbeg */
17565                 case 1:
17566                   return 122; /* wsr.lend */
17567                 case 2:
17568                   return 125; /* wsr.lcount */
17569                 case 3:
17570                   return 131; /* wsr.sar */
17571                 case 4:
17572                   return 376; /* wsr.br */
17573                 case 5:
17574                   return 134; /* wsr.litbase */
17575                 case 12:
17576                   return 455; /* wsr.scompare1 */
17577                 case 16:
17578                   return 311; /* wsr.acclo */
17579                 case 17:
17580                   return 314; /* wsr.acchi */
17581                 case 32:
17582                   return 299; /* wsr.m0 */
17583                 case 33:
17584                   return 302; /* wsr.m1 */
17585                 case 34:
17586                   return 305; /* wsr.m2 */
17587                 case 35:
17588                   return 308; /* wsr.m3 */
17589                 case 72:
17590                   return 21; /* wsr.windowbase */
17591                 case 73:
17592                   return 24; /* wsr.windowstart */
17593                 case 83:
17594                   return 415; /* wsr.ptevaddr */
17595                 case 89:
17596                   return 361; /* wsr.mmid */
17597                 case 90:
17598                   return 419; /* wsr.rasid */
17599                 case 91:
17600                   return 422; /* wsr.itlbcfg */
17601                 case 92:
17602                   return 425; /* wsr.dtlbcfg */
17603                 case 96:
17604                   return 345; /* wsr.ibreakenable */
17605                 case 104:
17606                   return 357; /* wsr.ddr */
17607                 case 128:
17608                   return 339; /* wsr.ibreaka0 */
17609                 case 129:
17610                   return 342; /* wsr.ibreaka1 */
17611                 case 144:
17612                   return 327; /* wsr.dbreaka0 */
17613                 case 145:
17614                   return 333; /* wsr.dbreaka1 */
17615                 case 160:
17616                   return 330; /* wsr.dbreakc0 */
17617                 case 161:
17618                   return 336; /* wsr.dbreakc1 */
17619                 case 177:
17620                   return 142; /* wsr.epc1 */
17621                 case 178:
17622                   return 148; /* wsr.epc2 */
17623                 case 179:
17624                   return 154; /* wsr.epc3 */
17625                 case 180:
17626                   return 160; /* wsr.epc4 */
17627                 case 181:
17628                   return 166; /* wsr.epc5 */
17629                 case 182:
17630                   return 172; /* wsr.epc6 */
17631                 case 183:
17632                   return 178; /* wsr.epc7 */
17633                 case 192:
17634                   return 205; /* wsr.depc */
17635                 case 194:
17636                   return 184; /* wsr.eps2 */
17637                 case 195:
17638                   return 187; /* wsr.eps3 */
17639                 case 196:
17640                   return 190; /* wsr.eps4 */
17641                 case 197:
17642                   return 193; /* wsr.eps5 */
17643                 case 198:
17644                   return 196; /* wsr.eps6 */
17645                 case 199:
17646                   return 199; /* wsr.eps7 */
17647                 case 209:
17648                   return 145; /* wsr.excsave1 */
17649                 case 210:
17650                   return 151; /* wsr.excsave2 */
17651                 case 211:
17652                   return 157; /* wsr.excsave3 */
17653                 case 212:
17654                   return 163; /* wsr.excsave4 */
17655                 case 213:
17656                   return 169; /* wsr.excsave5 */
17657                 case 214:
17658                   return 175; /* wsr.excsave6 */
17659                 case 215:
17660                   return 181; /* wsr.excsave7 */
17661                 case 224:
17662                   return 441; /* wsr.cpenable */
17663                 case 226:
17664                   return 319; /* wsr.intset */
17665                 case 227:
17666                   return 320; /* wsr.intclear */
17667                 case 228:
17668                   return 322; /* wsr.intenable */
17669                 case 230:
17670                   return 139; /* wsr.ps */
17671                 case 231:
17672                   return 224; /* wsr.vecbase */
17673                 case 232:
17674                   return 208; /* wsr.exccause */
17675                 case 233:
17676                   return 348; /* wsr.debugcause */
17677                 case 234:
17678                   return 379; /* wsr.ccount */
17679                 case 236:
17680                   return 351; /* wsr.icount */
17681                 case 237:
17682                   return 354; /* wsr.icountlevel */
17683                 case 238:
17684                   return 202; /* wsr.excvaddr */
17685                 case 240:
17686                   return 382; /* wsr.ccompare0 */
17687                 case 241:
17688                   return 385; /* wsr.ccompare1 */
17689                 case 242:
17690                   return 388; /* wsr.ccompare2 */
17691                 case 244:
17692                   return 211; /* wsr.misc0 */
17693                 case 245:
17694                   return 214; /* wsr.misc1 */
17695                 case 246:
17696                   return 217; /* wsr.misc2 */
17697                 case 247:
17698                   return 220; /* wsr.misc3 */
17699                 }
17700               break;
17701             case 2:
17702               return 450; /* sext */
17703             case 3:
17704               return 443; /* clamps */
17705             case 4:
17706               return 444; /* min */
17707             case 5:
17708               return 445; /* max */
17709             case 6:
17710               return 446; /* minu */
17711             case 7:
17712               return 447; /* maxu */
17713             case 8:
17714               return 91; /* moveqz */
17715             case 9:
17716               return 92; /* movnez */
17717             case 10:
17718               return 93; /* movltz */
17719             case 11:
17720               return 94; /* movgez */
17721             case 12:
17722               return 373; /* movf */
17723             case 13:
17724               return 374; /* movt */
17725             case 14:
17726               switch (Field_st_Slot_inst_get (insn))
17727                 {
17728                 case 231:
17729                   return 37; /* rur.threadptr */
17730                 case 232:
17731                   return 464; /* rur.fcr */
17732                 case 233:
17733                   return 466; /* rur.fsr */
17734                 }
17735               break;
17736             case 15:
17737               switch (Field_sr_Slot_inst_get (insn))
17738                 {
17739                 case 231:
17740                   return 38; /* wur.threadptr */
17741                 case 232:
17742                   return 465; /* wur.fcr */
17743                 case 233:
17744                   return 467; /* wur.fsr */
17745                 }
17746               break;
17747             }
17748           break;
17749         case 4:
17750         case 5:
17751           return 78; /* extui */
17752         case 8:
17753           switch (Field_op2_Slot_inst_get (insn))
17754             {
17755             case 0:
17756               return 500; /* lsx */
17757             case 1:
17758               return 501; /* lsxu */
17759             case 4:
17760               return 504; /* ssx */
17761             case 5:
17762               return 505; /* ssxu */
17763             }
17764           break;
17765         case 9:
17766           switch (Field_op2_Slot_inst_get (insn))
17767             {
17768             case 0:
17769               return 18; /* l32e */
17770             case 4:
17771               return 19; /* s32e */
17772             }
17773           break;
17774         case 10:
17775           switch (Field_op2_Slot_inst_get (insn))
17776             {
17777             case 0:
17778               return 468; /* add.s */
17779             case 1:
17780               return 469; /* sub.s */
17781             case 2:
17782               return 470; /* mul.s */
17783             case 4:
17784               return 471; /* madd.s */
17785             case 5:
17786               return 472; /* msub.s */
17787             case 8:
17788               return 491; /* round.s */
17789             case 9:
17790               return 494; /* trunc.s */
17791             case 10:
17792               return 493; /* floor.s */
17793             case 11:
17794               return 492; /* ceil.s */
17795             case 12:
17796               return 489; /* float.s */
17797             case 13:
17798               return 490; /* ufloat.s */
17799             case 14:
17800               return 495; /* utrunc.s */
17801             case 15:
17802               switch (Field_t_Slot_inst_get (insn))
17803                 {
17804                 case 0:
17805                   return 480; /* mov.s */
17806                 case 1:
17807                   return 479; /* abs.s */
17808                 case 4:
17809                   return 496; /* rfr */
17810                 case 5:
17811                   return 497; /* wfr */
17812                 case 6:
17813                   return 481; /* neg.s */
17814                 }
17815               break;
17816             }
17817           break;
17818         case 11:
17819           switch (Field_op2_Slot_inst_get (insn))
17820             {
17821             case 1:
17822               return 482; /* un.s */
17823             case 2:
17824               return 483; /* oeq.s */
17825             case 3:
17826               return 484; /* ueq.s */
17827             case 4:
17828               return 485; /* olt.s */
17829             case 5:
17830               return 486; /* ult.s */
17831             case 6:
17832               return 487; /* ole.s */
17833             case 7:
17834               return 488; /* ule.s */
17835             case 8:
17836               return 475; /* moveqz.s */
17837             case 9:
17838               return 476; /* movnez.s */
17839             case 10:
17840               return 477; /* movltz.s */
17841             case 11:
17842               return 478; /* movgez.s */
17843             case 12:
17844               return 473; /* movf.s */
17845             case 13:
17846               return 474; /* movt.s */
17847             }
17848           break;
17849         }
17850       break;
17851     case 1:
17852       return 85; /* l32r */
17853     case 2:
17854       switch (Field_r_Slot_inst_get (insn))
17855         {
17856         case 0:
17857           return 86; /* l8ui */
17858         case 1:
17859           return 82; /* l16ui */
17860         case 2:
17861           return 84; /* l32i */
17862         case 4:
17863           return 101; /* s8i */
17864         case 5:
17865           return 99; /* s16i */
17866         case 6:
17867           return 100; /* s32i */
17868         case 7:
17869           switch (Field_t_Slot_inst_get (insn))
17870             {
17871             case 0:
17872               return 406; /* dpfr */
17873             case 1:
17874               return 407; /* dpfw */
17875             case 2:
17876               return 408; /* dpfro */
17877             case 3:
17878               return 409; /* dpfwo */
17879             case 4:
17880               return 400; /* dhwb */
17881             case 5:
17882               return 401; /* dhwbi */
17883             case 6:
17884               return 404; /* dhi */
17885             case 7:
17886               return 405; /* dii */
17887             case 8:
17888               switch (Field_op1_Slot_inst_get (insn))
17889                 {
17890                 case 0:
17891                   return 410; /* dpfl */
17892                 case 2:
17893                   return 411; /* dhu */
17894                 case 3:
17895                   return 412; /* diu */
17896                 case 4:
17897                   return 402; /* diwb */
17898                 case 5:
17899                   return 403; /* diwbi */
17900                 }
17901               break;
17902             case 12:
17903               return 390; /* ipf */
17904             case 13:
17905               switch (Field_op1_Slot_inst_get (insn))
17906                 {
17907                 case 0:
17908                   return 392; /* ipfl */
17909                 case 2:
17910                   return 393; /* ihu */
17911                 case 3:
17912                   return 394; /* iiu */
17913                 }
17914               break;
17915             case 14:
17916               return 391; /* ihi */
17917             case 15:
17918               return 395; /* iii */
17919             }
17920           break;
17921         case 9:
17922           return 83; /* l16si */
17923         case 10:
17924           return 90; /* movi */
17925         case 11:
17926           return 451; /* l32ai */
17927         case 12:
17928           return 39; /* addi */
17929         case 13:
17930           return 40; /* addmi */
17931         case 14:
17932           return 453; /* s32c1i */
17933         case 15:
17934           return 452; /* s32ri */
17935         }
17936       break;
17937     case 3:
17938       switch (Field_r_Slot_inst_get (insn))
17939         {
17940         case 0:
17941           return 498; /* lsi */
17942         case 4:
17943           return 502; /* ssi */
17944         case 8:
17945           return 499; /* lsiu */
17946         case 12:
17947           return 503; /* ssiu */
17948         }
17949       break;
17950     case 4:
17951       switch (Field_op2_Slot_inst_get (insn))
17952         {
17953         case 0:
17954           switch (Field_op1_Slot_inst_get (insn))
17955             {
17956             case 8:
17957               if (Field_t3_Slot_inst_get (insn) == 0 &&
17958                   Field_tlo_Slot_inst_get (insn) == 0 &&
17959                   Field_r3_Slot_inst_get (insn) == 0)
17960                 return 287; /* mula.dd.ll.ldinc */
17961               break;
17962             case 9:
17963               if (Field_t3_Slot_inst_get (insn) == 0 &&
17964                   Field_tlo_Slot_inst_get (insn) == 0 &&
17965                   Field_r3_Slot_inst_get (insn) == 0)
17966                 return 289; /* mula.dd.hl.ldinc */
17967               break;
17968             case 10:
17969               if (Field_t3_Slot_inst_get (insn) == 0 &&
17970                   Field_tlo_Slot_inst_get (insn) == 0 &&
17971                   Field_r3_Slot_inst_get (insn) == 0)
17972                 return 291; /* mula.dd.lh.ldinc */
17973               break;
17974             case 11:
17975               if (Field_t3_Slot_inst_get (insn) == 0 &&
17976                   Field_tlo_Slot_inst_get (insn) == 0 &&
17977                   Field_r3_Slot_inst_get (insn) == 0)
17978                 return 293; /* mula.dd.hh.ldinc */
17979               break;
17980             }
17981           break;
17982         case 1:
17983           switch (Field_op1_Slot_inst_get (insn))
17984             {
17985             case 8:
17986               if (Field_t3_Slot_inst_get (insn) == 0 &&
17987                   Field_tlo_Slot_inst_get (insn) == 0 &&
17988                   Field_r3_Slot_inst_get (insn) == 0)
17989                 return 286; /* mula.dd.ll.lddec */
17990               break;
17991             case 9:
17992               if (Field_t3_Slot_inst_get (insn) == 0 &&
17993                   Field_tlo_Slot_inst_get (insn) == 0 &&
17994                   Field_r3_Slot_inst_get (insn) == 0)
17995                 return 288; /* mula.dd.hl.lddec */
17996               break;
17997             case 10:
17998               if (Field_t3_Slot_inst_get (insn) == 0 &&
17999                   Field_tlo_Slot_inst_get (insn) == 0 &&
18000                   Field_r3_Slot_inst_get (insn) == 0)
18001                 return 290; /* mula.dd.lh.lddec */
18002               break;
18003             case 11:
18004               if (Field_t3_Slot_inst_get (insn) == 0 &&
18005                   Field_tlo_Slot_inst_get (insn) == 0 &&
18006                   Field_r3_Slot_inst_get (insn) == 0)
18007                 return 292; /* mula.dd.hh.lddec */
18008               break;
18009             }
18010           break;
18011         case 2:
18012           switch (Field_op1_Slot_inst_get (insn))
18013             {
18014             case 4:
18015               if (Field_s_Slot_inst_get (insn) == 0 &&
18016                   Field_w_Slot_inst_get (insn) == 0 &&
18017                   Field_r3_Slot_inst_get (insn) == 0 &&
18018                   Field_t3_Slot_inst_get (insn) == 0 &&
18019                   Field_tlo_Slot_inst_get (insn) == 0)
18020                 return 242; /* mul.dd.ll */
18021               break;
18022             case 5:
18023               if (Field_s_Slot_inst_get (insn) == 0 &&
18024                   Field_w_Slot_inst_get (insn) == 0 &&
18025                   Field_r3_Slot_inst_get (insn) == 0 &&
18026                   Field_t3_Slot_inst_get (insn) == 0 &&
18027                   Field_tlo_Slot_inst_get (insn) == 0)
18028                 return 243; /* mul.dd.hl */
18029               break;
18030             case 6:
18031               if (Field_s_Slot_inst_get (insn) == 0 &&
18032                   Field_w_Slot_inst_get (insn) == 0 &&
18033                   Field_r3_Slot_inst_get (insn) == 0 &&
18034                   Field_t3_Slot_inst_get (insn) == 0 &&
18035                   Field_tlo_Slot_inst_get (insn) == 0)
18036                 return 244; /* mul.dd.lh */
18037               break;
18038             case 7:
18039               if (Field_s_Slot_inst_get (insn) == 0 &&
18040                   Field_w_Slot_inst_get (insn) == 0 &&
18041                   Field_r3_Slot_inst_get (insn) == 0 &&
18042                   Field_t3_Slot_inst_get (insn) == 0 &&
18043                   Field_tlo_Slot_inst_get (insn) == 0)
18044                 return 245; /* mul.dd.hh */
18045               break;
18046             case 8:
18047               if (Field_s_Slot_inst_get (insn) == 0 &&
18048                   Field_w_Slot_inst_get (insn) == 0 &&
18049                   Field_r3_Slot_inst_get (insn) == 0 &&
18050                   Field_t3_Slot_inst_get (insn) == 0 &&
18051                   Field_tlo_Slot_inst_get (insn) == 0)
18052                 return 270; /* mula.dd.ll */
18053               break;
18054             case 9:
18055               if (Field_s_Slot_inst_get (insn) == 0 &&
18056                   Field_w_Slot_inst_get (insn) == 0 &&
18057                   Field_r3_Slot_inst_get (insn) == 0 &&
18058                   Field_t3_Slot_inst_get (insn) == 0 &&
18059                   Field_tlo_Slot_inst_get (insn) == 0)
18060                 return 271; /* mula.dd.hl */
18061               break;
18062             case 10:
18063               if (Field_s_Slot_inst_get (insn) == 0 &&
18064                   Field_w_Slot_inst_get (insn) == 0 &&
18065                   Field_r3_Slot_inst_get (insn) == 0 &&
18066                   Field_t3_Slot_inst_get (insn) == 0 &&
18067                   Field_tlo_Slot_inst_get (insn) == 0)
18068                 return 272; /* mula.dd.lh */
18069               break;
18070             case 11:
18071               if (Field_s_Slot_inst_get (insn) == 0 &&
18072                   Field_w_Slot_inst_get (insn) == 0 &&
18073                   Field_r3_Slot_inst_get (insn) == 0 &&
18074                   Field_t3_Slot_inst_get (insn) == 0 &&
18075                   Field_tlo_Slot_inst_get (insn) == 0)
18076                 return 273; /* mula.dd.hh */
18077               break;
18078             case 12:
18079               if (Field_s_Slot_inst_get (insn) == 0 &&
18080                   Field_w_Slot_inst_get (insn) == 0 &&
18081                   Field_r3_Slot_inst_get (insn) == 0 &&
18082                   Field_t3_Slot_inst_get (insn) == 0 &&
18083                   Field_tlo_Slot_inst_get (insn) == 0)
18084                 return 274; /* muls.dd.ll */
18085               break;
18086             case 13:
18087               if (Field_s_Slot_inst_get (insn) == 0 &&
18088                   Field_w_Slot_inst_get (insn) == 0 &&
18089                   Field_r3_Slot_inst_get (insn) == 0 &&
18090                   Field_t3_Slot_inst_get (insn) == 0 &&
18091                   Field_tlo_Slot_inst_get (insn) == 0)
18092                 return 275; /* muls.dd.hl */
18093               break;
18094             case 14:
18095               if (Field_s_Slot_inst_get (insn) == 0 &&
18096                   Field_w_Slot_inst_get (insn) == 0 &&
18097                   Field_r3_Slot_inst_get (insn) == 0 &&
18098                   Field_t3_Slot_inst_get (insn) == 0 &&
18099                   Field_tlo_Slot_inst_get (insn) == 0)
18100                 return 276; /* muls.dd.lh */
18101               break;
18102             case 15:
18103               if (Field_s_Slot_inst_get (insn) == 0 &&
18104                   Field_w_Slot_inst_get (insn) == 0 &&
18105                   Field_r3_Slot_inst_get (insn) == 0 &&
18106                   Field_t3_Slot_inst_get (insn) == 0 &&
18107                   Field_tlo_Slot_inst_get (insn) == 0)
18108                 return 277; /* muls.dd.hh */
18109               break;
18110             }
18111           break;
18112         case 3:
18113           switch (Field_op1_Slot_inst_get (insn))
18114             {
18115             case 4:
18116               if (Field_r_Slot_inst_get (insn) == 0 &&
18117                   Field_t3_Slot_inst_get (insn) == 0 &&
18118                   Field_tlo_Slot_inst_get (insn) == 0)
18119                 return 234; /* mul.ad.ll */
18120               break;
18121             case 5:
18122               if (Field_r_Slot_inst_get (insn) == 0 &&
18123                   Field_t3_Slot_inst_get (insn) == 0 &&
18124                   Field_tlo_Slot_inst_get (insn) == 0)
18125                 return 235; /* mul.ad.hl */
18126               break;
18127             case 6:
18128               if (Field_r_Slot_inst_get (insn) == 0 &&
18129                   Field_t3_Slot_inst_get (insn) == 0 &&
18130                   Field_tlo_Slot_inst_get (insn) == 0)
18131                 return 236; /* mul.ad.lh */
18132               break;
18133             case 7:
18134               if (Field_r_Slot_inst_get (insn) == 0 &&
18135                   Field_t3_Slot_inst_get (insn) == 0 &&
18136                   Field_tlo_Slot_inst_get (insn) == 0)
18137                 return 237; /* mul.ad.hh */
18138               break;
18139             case 8:
18140               if (Field_r_Slot_inst_get (insn) == 0 &&
18141                   Field_t3_Slot_inst_get (insn) == 0 &&
18142                   Field_tlo_Slot_inst_get (insn) == 0)
18143                 return 254; /* mula.ad.ll */
18144               break;
18145             case 9:
18146               if (Field_r_Slot_inst_get (insn) == 0 &&
18147                   Field_t3_Slot_inst_get (insn) == 0 &&
18148                   Field_tlo_Slot_inst_get (insn) == 0)
18149                 return 255; /* mula.ad.hl */
18150               break;
18151             case 10:
18152               if (Field_r_Slot_inst_get (insn) == 0 &&
18153                   Field_t3_Slot_inst_get (insn) == 0 &&
18154                   Field_tlo_Slot_inst_get (insn) == 0)
18155                 return 256; /* mula.ad.lh */
18156               break;
18157             case 11:
18158               if (Field_r_Slot_inst_get (insn) == 0 &&
18159                   Field_t3_Slot_inst_get (insn) == 0 &&
18160                   Field_tlo_Slot_inst_get (insn) == 0)
18161                 return 257; /* mula.ad.hh */
18162               break;
18163             case 12:
18164               if (Field_r_Slot_inst_get (insn) == 0 &&
18165                   Field_t3_Slot_inst_get (insn) == 0 &&
18166                   Field_tlo_Slot_inst_get (insn) == 0)
18167                 return 258; /* muls.ad.ll */
18168               break;
18169             case 13:
18170               if (Field_r_Slot_inst_get (insn) == 0 &&
18171                   Field_t3_Slot_inst_get (insn) == 0 &&
18172                   Field_tlo_Slot_inst_get (insn) == 0)
18173                 return 259; /* muls.ad.hl */
18174               break;
18175             case 14:
18176               if (Field_r_Slot_inst_get (insn) == 0 &&
18177                   Field_t3_Slot_inst_get (insn) == 0 &&
18178                   Field_tlo_Slot_inst_get (insn) == 0)
18179                 return 260; /* muls.ad.lh */
18180               break;
18181             case 15:
18182               if (Field_r_Slot_inst_get (insn) == 0 &&
18183                   Field_t3_Slot_inst_get (insn) == 0 &&
18184                   Field_tlo_Slot_inst_get (insn) == 0)
18185                 return 261; /* muls.ad.hh */
18186               break;
18187             }
18188           break;
18189         case 4:
18190           switch (Field_op1_Slot_inst_get (insn))
18191             {
18192             case 8:
18193               if (Field_r3_Slot_inst_get (insn) == 0)
18194                 return 279; /* mula.da.ll.ldinc */
18195               break;
18196             case 9:
18197               if (Field_r3_Slot_inst_get (insn) == 0)
18198                 return 281; /* mula.da.hl.ldinc */
18199               break;
18200             case 10:
18201               if (Field_r3_Slot_inst_get (insn) == 0)
18202                 return 283; /* mula.da.lh.ldinc */
18203               break;
18204             case 11:
18205               if (Field_r3_Slot_inst_get (insn) == 0)
18206                 return 285; /* mula.da.hh.ldinc */
18207               break;
18208             }
18209           break;
18210         case 5:
18211           switch (Field_op1_Slot_inst_get (insn))
18212             {
18213             case 8:
18214               if (Field_r3_Slot_inst_get (insn) == 0)
18215                 return 278; /* mula.da.ll.lddec */
18216               break;
18217             case 9:
18218               if (Field_r3_Slot_inst_get (insn) == 0)
18219                 return 280; /* mula.da.hl.lddec */
18220               break;
18221             case 10:
18222               if (Field_r3_Slot_inst_get (insn) == 0)
18223                 return 282; /* mula.da.lh.lddec */
18224               break;
18225             case 11:
18226               if (Field_r3_Slot_inst_get (insn) == 0)
18227                 return 284; /* mula.da.hh.lddec */
18228               break;
18229             }
18230           break;
18231         case 6:
18232           switch (Field_op1_Slot_inst_get (insn))
18233             {
18234             case 4:
18235               if (Field_s_Slot_inst_get (insn) == 0 &&
18236                   Field_w_Slot_inst_get (insn) == 0 &&
18237                   Field_r3_Slot_inst_get (insn) == 0)
18238                 return 238; /* mul.da.ll */
18239               break;
18240             case 5:
18241               if (Field_s_Slot_inst_get (insn) == 0 &&
18242                   Field_w_Slot_inst_get (insn) == 0 &&
18243                   Field_r3_Slot_inst_get (insn) == 0)
18244                 return 239; /* mul.da.hl */
18245               break;
18246             case 6:
18247               if (Field_s_Slot_inst_get (insn) == 0 &&
18248                   Field_w_Slot_inst_get (insn) == 0 &&
18249                   Field_r3_Slot_inst_get (insn) == 0)
18250                 return 240; /* mul.da.lh */
18251               break;
18252             case 7:
18253               if (Field_s_Slot_inst_get (insn) == 0 &&
18254                   Field_w_Slot_inst_get (insn) == 0 &&
18255                   Field_r3_Slot_inst_get (insn) == 0)
18256                 return 241; /* mul.da.hh */
18257               break;
18258             case 8:
18259               if (Field_s_Slot_inst_get (insn) == 0 &&
18260                   Field_w_Slot_inst_get (insn) == 0 &&
18261                   Field_r3_Slot_inst_get (insn) == 0)
18262                 return 262; /* mula.da.ll */
18263               break;
18264             case 9:
18265               if (Field_s_Slot_inst_get (insn) == 0 &&
18266                   Field_w_Slot_inst_get (insn) == 0 &&
18267                   Field_r3_Slot_inst_get (insn) == 0)
18268                 return 263; /* mula.da.hl */
18269               break;
18270             case 10:
18271               if (Field_s_Slot_inst_get (insn) == 0 &&
18272                   Field_w_Slot_inst_get (insn) == 0 &&
18273                   Field_r3_Slot_inst_get (insn) == 0)
18274                 return 264; /* mula.da.lh */
18275               break;
18276             case 11:
18277               if (Field_s_Slot_inst_get (insn) == 0 &&
18278                   Field_w_Slot_inst_get (insn) == 0 &&
18279                   Field_r3_Slot_inst_get (insn) == 0)
18280                 return 265; /* mula.da.hh */
18281               break;
18282             case 12:
18283               if (Field_s_Slot_inst_get (insn) == 0 &&
18284                   Field_w_Slot_inst_get (insn) == 0 &&
18285                   Field_r3_Slot_inst_get (insn) == 0)
18286                 return 266; /* muls.da.ll */
18287               break;
18288             case 13:
18289               if (Field_s_Slot_inst_get (insn) == 0 &&
18290                   Field_w_Slot_inst_get (insn) == 0 &&
18291                   Field_r3_Slot_inst_get (insn) == 0)
18292                 return 267; /* muls.da.hl */
18293               break;
18294             case 14:
18295               if (Field_s_Slot_inst_get (insn) == 0 &&
18296                   Field_w_Slot_inst_get (insn) == 0 &&
18297                   Field_r3_Slot_inst_get (insn) == 0)
18298                 return 268; /* muls.da.lh */
18299               break;
18300             case 15:
18301               if (Field_s_Slot_inst_get (insn) == 0 &&
18302                   Field_w_Slot_inst_get (insn) == 0 &&
18303                   Field_r3_Slot_inst_get (insn) == 0)
18304                 return 269; /* muls.da.hh */
18305               break;
18306             }
18307           break;
18308         case 7:
18309           switch (Field_op1_Slot_inst_get (insn))
18310             {
18311             case 0:
18312               if (Field_r_Slot_inst_get (insn) == 0)
18313                 return 230; /* umul.aa.ll */
18314               break;
18315             case 1:
18316               if (Field_r_Slot_inst_get (insn) == 0)
18317                 return 231; /* umul.aa.hl */
18318               break;
18319             case 2:
18320               if (Field_r_Slot_inst_get (insn) == 0)
18321                 return 232; /* umul.aa.lh */
18322               break;
18323             case 3:
18324               if (Field_r_Slot_inst_get (insn) == 0)
18325                 return 233; /* umul.aa.hh */
18326               break;
18327             case 4:
18328               if (Field_r_Slot_inst_get (insn) == 0)
18329                 return 226; /* mul.aa.ll */
18330               break;
18331             case 5:
18332               if (Field_r_Slot_inst_get (insn) == 0)
18333                 return 227; /* mul.aa.hl */
18334               break;
18335             case 6:
18336               if (Field_r_Slot_inst_get (insn) == 0)
18337                 return 228; /* mul.aa.lh */
18338               break;
18339             case 7:
18340               if (Field_r_Slot_inst_get (insn) == 0)
18341                 return 229; /* mul.aa.hh */
18342               break;
18343             case 8:
18344               if (Field_r_Slot_inst_get (insn) == 0)
18345                 return 246; /* mula.aa.ll */
18346               break;
18347             case 9:
18348               if (Field_r_Slot_inst_get (insn) == 0)
18349                 return 247; /* mula.aa.hl */
18350               break;
18351             case 10:
18352               if (Field_r_Slot_inst_get (insn) == 0)
18353                 return 248; /* mula.aa.lh */
18354               break;
18355             case 11:
18356               if (Field_r_Slot_inst_get (insn) == 0)
18357                 return 249; /* mula.aa.hh */
18358               break;
18359             case 12:
18360               if (Field_r_Slot_inst_get (insn) == 0)
18361                 return 250; /* muls.aa.ll */
18362               break;
18363             case 13:
18364               if (Field_r_Slot_inst_get (insn) == 0)
18365                 return 251; /* muls.aa.hl */
18366               break;
18367             case 14:
18368               if (Field_r_Slot_inst_get (insn) == 0)
18369                 return 252; /* muls.aa.lh */
18370               break;
18371             case 15:
18372               if (Field_r_Slot_inst_get (insn) == 0)
18373                 return 253; /* muls.aa.hh */
18374               break;
18375             }
18376           break;
18377         case 8:
18378           if (Field_op1_Slot_inst_get (insn) == 0 &&
18379               Field_t_Slot_inst_get (insn) == 0 &&
18380               Field_rhi_Slot_inst_get (insn) == 0)
18381             return 295; /* ldinc */
18382           break;
18383         case 9:
18384           if (Field_op1_Slot_inst_get (insn) == 0 &&
18385               Field_t_Slot_inst_get (insn) == 0 &&
18386               Field_rhi_Slot_inst_get (insn) == 0)
18387             return 294; /* lddec */
18388           break;
18389         }
18390       break;
18391     case 5:
18392       switch (Field_n_Slot_inst_get (insn))
18393         {
18394         case 0:
18395           return 76; /* call0 */
18396         case 1:
18397           return 7; /* call4 */
18398         case 2:
18399           return 6; /* call8 */
18400         case 3:
18401           return 5; /* call12 */
18402         }
18403       break;
18404     case 6:
18405       switch (Field_n_Slot_inst_get (insn))
18406         {
18407         case 0:
18408           return 80; /* j */
18409         case 1:
18410           switch (Field_m_Slot_inst_get (insn))
18411             {
18412             case 0:
18413               return 72; /* beqz */
18414             case 1:
18415               return 73; /* bnez */
18416             case 2:
18417               return 75; /* bltz */
18418             case 3:
18419               return 74; /* bgez */
18420             }
18421           break;
18422         case 2:
18423           switch (Field_m_Slot_inst_get (insn))
18424             {
18425             case 0:
18426               return 52; /* beqi */
18427             case 1:
18428               return 53; /* bnei */
18429             case 2:
18430               return 55; /* blti */
18431             case 3:
18432               return 54; /* bgei */
18433             }
18434           break;
18435         case 3:
18436           switch (Field_m_Slot_inst_get (insn))
18437             {
18438             case 0:
18439               return 11; /* entry */
18440             case 1:
18441               switch (Field_r_Slot_inst_get (insn))
18442                 {
18443                 case 0:
18444                   return 371; /* bf */
18445                 case 1:
18446                   return 372; /* bt */
18447                 case 8:
18448                   return 87; /* loop */
18449                 case 9:
18450                   return 88; /* loopnez */
18451                 case 10:
18452                   return 89; /* loopgtz */
18453                 }
18454               break;
18455             case 2:
18456               return 59; /* bltui */
18457             case 3:
18458               return 58; /* bgeui */
18459             }
18460           break;
18461         }
18462       break;
18463     case 7:
18464       switch (Field_r_Slot_inst_get (insn))
18465         {
18466         case 0:
18467           return 67; /* bnone */
18468         case 1:
18469           return 60; /* beq */
18470         case 2:
18471           return 63; /* blt */
18472         case 3:
18473           return 65; /* bltu */
18474         case 4:
18475           return 68; /* ball */
18476         case 5:
18477           return 70; /* bbc */
18478         case 6:
18479         case 7:
18480           return 56; /* bbci */
18481         case 8:
18482           return 66; /* bany */
18483         case 9:
18484           return 61; /* bne */
18485         case 10:
18486           return 62; /* bge */
18487         case 11:
18488           return 64; /* bgeu */
18489         case 12:
18490           return 69; /* bnall */
18491         case 13:
18492           return 71; /* bbs */
18493         case 14:
18494         case 15:
18495           return 57; /* bbsi */
18496         }
18497       break;
18498     }
18499   return 0;
18500 }
18501
18502 static int
18503 Slot_inst16b_decode (const xtensa_insnbuf insn)
18504 {
18505   switch (Field_op0_Slot_inst16b_get (insn))
18506     {
18507     case 12:
18508       switch (Field_i_Slot_inst16b_get (insn))
18509         {
18510         case 0:
18511           return 33; /* movi.n */
18512         case 1:
18513           switch (Field_z_Slot_inst16b_get (insn))
18514             {
18515             case 0:
18516               return 28; /* beqz.n */
18517             case 1:
18518               return 29; /* bnez.n */
18519             }
18520           break;
18521         }
18522       break;
18523     case 13:
18524       switch (Field_r_Slot_inst16b_get (insn))
18525         {
18526         case 0:
18527           return 32; /* mov.n */
18528         case 15:
18529           switch (Field_t_Slot_inst16b_get (insn))
18530             {
18531             case 0:
18532               return 35; /* ret.n */
18533             case 1:
18534               return 15; /* retw.n */
18535             case 2:
18536               return 325; /* break.n */
18537             case 3:
18538               if (Field_s_Slot_inst16b_get (insn) == 0)
18539                 return 34; /* nop.n */
18540               break;
18541             case 6:
18542               if (Field_s_Slot_inst16b_get (insn) == 0)
18543                 return 30; /* ill.n */
18544               break;
18545             }
18546           break;
18547         }
18548       break;
18549     }
18550   return 0;
18551 }
18552
18553 static int
18554 Slot_inst16a_decode (const xtensa_insnbuf insn)
18555 {
18556   switch (Field_op0_Slot_inst16a_get (insn))
18557     {
18558     case 8:
18559       return 31; /* l32i.n */
18560     case 9:
18561       return 36; /* s32i.n */
18562     case 10:
18563       return 26; /* add.n */
18564     case 11:
18565       return 27; /* addi.n */
18566     }
18567   return 0;
18568 }
18569
18570 static int
18571 Slot_xt_flix64_slot2_decode (const xtensa_insnbuf insn)
18572 {
18573   switch (Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn))
18574     {
18575     case 0:
18576       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
18577         return 41; /* add */
18578       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
18579         return 42; /* sub */
18580       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
18581         return 43; /* addx2 */
18582       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
18583         return 49; /* and */
18584       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
18585         return 450; /* sext */
18586       break;
18587     case 1:
18588       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
18589         return 27; /* addi.n */
18590       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
18591         return 44; /* addx4 */
18592       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
18593         return 50; /* or */
18594       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
18595         return 51; /* xor */
18596       if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
18597         return 113; /* srli */
18598       break;
18599     }
18600   if (Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0 &&
18601       Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6)
18602     return 33; /* movi.n */
18603   if (Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 2 &&
18604       Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18605       Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18606     return 32; /* mov.n */
18607   if (Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
18608       Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18609       Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18610     return 97; /* nop */
18611   if (Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 8 &&
18612       Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18613       Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18614     return 96; /* abs */
18615   if (Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 9 &&
18616       Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18617       Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18618     return 95; /* neg */
18619   if (Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 5 &&
18620       Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18621       Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18622     return 110; /* sra */
18623   if (Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
18624       Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18625       Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18626     return 109; /* srl */
18627   if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 7)
18628     return 112; /* srai */
18629   return 0;
18630 }
18631
18632 static int
18633 Slot_xt_flix64_slot0_decode (const xtensa_insnbuf insn)
18634 {
18635   switch (Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn))
18636     {
18637     case 0:
18638       if (Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (insn) == 2)
18639         return 78; /* extui */
18640       switch (Field_op1_Slot_xt_flix64_slot0_get (insn))
18641         {
18642         case 0:
18643           switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
18644             {
18645             case 0:
18646               if (Field_r_Slot_xt_flix64_slot0_get (insn) == 2)
18647                 {
18648                   if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
18649                     {
18650                       if (Field_t_Slot_xt_flix64_slot0_get (insn) == 15)
18651                         return 97; /* nop */
18652                     }
18653                 }
18654               break;
18655             case 1:
18656               return 49; /* and */
18657             case 2:
18658               return 50; /* or */
18659             case 3:
18660               return 51; /* xor */
18661             case 4:
18662               switch (Field_r_Slot_xt_flix64_slot0_get (insn))
18663                 {
18664                 case 0:
18665                   if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18666                     return 102; /* ssr */
18667                   break;
18668                 case 1:
18669                   if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18670                     return 103; /* ssl */
18671                   break;
18672                 case 2:
18673                   if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18674                     return 104; /* ssa8l */
18675                   break;
18676                 case 3:
18677                   if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18678                     return 105; /* ssa8b */
18679                   break;
18680                 case 4:
18681                   if (Field_thi3_Slot_xt_flix64_slot0_get (insn) == 0)
18682                     return 106; /* ssai */
18683                   break;
18684                 case 14:
18685                   return 448; /* nsa */
18686                 case 15:
18687                   return 449; /* nsau */
18688                 }
18689               break;
18690             case 6:
18691               switch (Field_s_Slot_xt_flix64_slot0_get (insn))
18692                 {
18693                 case 0:
18694                   return 95; /* neg */
18695                 case 1:
18696                   return 96; /* abs */
18697                 }
18698               break;
18699             case 8:
18700               return 41; /* add */
18701             case 9:
18702               return 43; /* addx2 */
18703             case 10:
18704               return 44; /* addx4 */
18705             case 11:
18706               return 45; /* addx8 */
18707             case 12:
18708               return 42; /* sub */
18709             case 13:
18710               return 46; /* subx2 */
18711             case 14:
18712               return 47; /* subx4 */
18713             case 15:
18714               return 48; /* subx8 */
18715             }
18716           break;
18717         case 1:
18718           if (Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (insn) == 1)
18719             return 112; /* srai */
18720           if (Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (insn) == 0)
18721             return 111; /* slli */
18722           switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
18723             {
18724             case 4:
18725               return 113; /* srli */
18726             case 8:
18727               return 108; /* src */
18728             case 9:
18729               if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
18730                 return 109; /* srl */
18731               break;
18732             case 10:
18733               if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18734                 return 107; /* sll */
18735               break;
18736             case 11:
18737               if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
18738                 return 110; /* sra */
18739               break;
18740             case 12:
18741               return 296; /* mul16u */
18742             case 13:
18743               return 297; /* mul16s */
18744             }
18745           break;
18746         case 2:
18747           if (Field_op2_Slot_xt_flix64_slot0_get (insn) == 8)
18748             return 461; /* mull */
18749           break;
18750         case 3:
18751           switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
18752             {
18753             case 2:
18754               return 450; /* sext */
18755             case 3:
18756               return 443; /* clamps */
18757             case 4:
18758               return 444; /* min */
18759             case 5:
18760               return 445; /* max */
18761             case 6:
18762               return 446; /* minu */
18763             case 7:
18764               return 447; /* maxu */
18765             case 8:
18766               return 91; /* moveqz */
18767             case 9:
18768               return 92; /* movnez */
18769             case 10:
18770               return 93; /* movltz */
18771             case 11:
18772               return 94; /* movgez */
18773             }
18774           break;
18775         }
18776       break;
18777     case 2:
18778       switch (Field_r_Slot_xt_flix64_slot0_get (insn))
18779         {
18780         case 0:
18781           return 86; /* l8ui */
18782         case 1:
18783           return 82; /* l16ui */
18784         case 2:
18785           return 84; /* l32i */
18786         case 4:
18787           return 101; /* s8i */
18788         case 5:
18789           return 99; /* s16i */
18790         case 6:
18791           return 100; /* s32i */
18792         case 9:
18793           return 83; /* l16si */
18794         case 10:
18795           return 90; /* movi */
18796         case 12:
18797           return 39; /* addi */
18798         case 13:
18799           return 40; /* addmi */
18800         }
18801       break;
18802     }
18803   if (Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 1)
18804     return 85; /* l32r */
18805   if (Field_sae4_Slot_xt_flix64_slot0_get (insn) == 0 &&
18806       Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (insn) == 3 &&
18807       Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 0 &&
18808       Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn) == 0)
18809     return 32; /* mov.n */
18810   return 0;
18811 }
18812
18813 static int
18814 Slot_xt_flix64_slot1_decode (const xtensa_insnbuf insn)
18815 {
18816   if (Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0 &&
18817       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
18818     return 78; /* extui */
18819   switch (Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
18820     {
18821     case 0:
18822       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18823         return 90; /* movi */
18824       break;
18825     case 2:
18826       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
18827         return 39; /* addi */
18828       break;
18829     case 3:
18830       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
18831         return 40; /* addmi */
18832       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18833           Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (insn) == 0)
18834         return 51; /* xor */
18835       break;
18836     }
18837   switch (Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
18838     {
18839     case 8:
18840       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18841         return 111; /* slli */
18842       break;
18843     case 16:
18844       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18845         return 112; /* srai */
18846       break;
18847     case 19:
18848       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18849           Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18850         return 107; /* sll */
18851       break;
18852     }
18853   switch (Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
18854     {
18855     case 18:
18856       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18857         return 41; /* add */
18858       break;
18859     case 19:
18860       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18861         return 45; /* addx8 */
18862       break;
18863     case 20:
18864       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18865         return 43; /* addx2 */
18866       break;
18867     case 21:
18868       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18869         return 49; /* and */
18870       break;
18871     case 22:
18872       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18873         return 91; /* moveqz */
18874       break;
18875     case 23:
18876       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18877         return 94; /* movgez */
18878       break;
18879     case 24:
18880       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18881         return 44; /* addx4 */
18882       break;
18883     case 25:
18884       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18885         return 93; /* movltz */
18886       break;
18887     case 26:
18888       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18889         return 92; /* movnez */
18890       break;
18891     case 27:
18892       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18893         return 296; /* mul16u */
18894       break;
18895     case 28:
18896       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18897         return 297; /* mul16s */
18898       break;
18899     case 29:
18900       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18901         return 461; /* mull */
18902       break;
18903     case 30:
18904       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18905         return 50; /* or */
18906       break;
18907     case 31:
18908       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18909         return 450; /* sext */
18910       break;
18911     case 34:
18912       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18913         return 108; /* src */
18914       break;
18915     case 36:
18916       if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18917         return 113; /* srli */
18918       break;
18919     }
18920   if (Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 280 &&
18921       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18922       Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18923     return 32; /* mov.n */
18924   if (Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 281 &&
18925       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18926       Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18927     return 81; /* jx */
18928   if (Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 141 &&
18929       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18930       Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18931     return 103; /* ssl */
18932   if (Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 71 &&
18933       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18934       Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18935     return 97; /* nop */
18936   if (Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 148 &&
18937       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18938       Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18939     return 95; /* neg */
18940   if (Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 149 &&
18941       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18942       Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18943     return 110; /* sra */
18944   if (Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 75 &&
18945       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18946       Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18947     return 109; /* srl */
18948   if (Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 5 &&
18949       Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18950       Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18951     return 42; /* sub */
18952   if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 3)
18953     return 80; /* j */
18954   return 0;
18955 }
18956
18957 static int
18958 Slot_xt_flix64_slot3_decode (const xtensa_insnbuf insn)
18959 {
18960   switch (Field_op0_s6_Slot_xt_flix64_slot3_get (insn))
18961     {
18962     case 1:
18963       if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
18964         return 516; /* bbci.w18 */
18965       break;
18966     case 2:
18967       if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
18968         return 517; /* bbsi.w18 */
18969       break;
18970     case 3:
18971       if (Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18972         return 526; /* ball.w18 */
18973       break;
18974     case 4:
18975       if (Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18976         return 524; /* bany.w18 */
18977       break;
18978     case 5:
18979       if (Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18980         return 528; /* bbc.w18 */
18981       break;
18982     case 6:
18983       if (Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18984         return 529; /* bbs.w18 */
18985       break;
18986     case 7:
18987       if (Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18988         return 518; /* beq.w18 */
18989       break;
18990     case 8:
18991       if (Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18992         return 510; /* beqi.w18 */
18993       break;
18994     case 9:
18995       if (Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18996         return 520; /* bge.w18 */
18997       break;
18998     case 10:
18999       if (Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19000         return 512; /* bgei.w18 */
19001       break;
19002     case 11:
19003       if (Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19004         return 522; /* bgeu.w18 */
19005       break;
19006     case 12:
19007       if (Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19008         return 514; /* bgeui.w18 */
19009       break;
19010     case 13:
19011       if (Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19012         return 521; /* blt.w18 */
19013       break;
19014     case 14:
19015       if (Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19016         return 513; /* blti.w18 */
19017       break;
19018     case 15:
19019       if (Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19020         return 523; /* bltu.w18 */
19021       break;
19022     case 16:
19023       if (Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19024         return 515; /* bltui.w18 */
19025       break;
19026     case 17:
19027       if (Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19028         return 527; /* bnall.w18 */
19029       break;
19030     case 18:
19031       if (Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19032         return 519; /* bne.w18 */
19033       break;
19034     case 19:
19035       if (Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19036         return 511; /* bnei.w18 */
19037       break;
19038     case 20:
19039       if (Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19040         return 525; /* bnone.w18 */
19041       break;
19042     case 21:
19043       if (Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19044         return 506; /* beqz.w18 */
19045       break;
19046     case 22:
19047       if (Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19048         return 508; /* bgez.w18 */
19049       break;
19050     case 23:
19051       if (Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19052         return 509; /* bltz.w18 */
19053       break;
19054     case 24:
19055       if (Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19056         return 507; /* bnez.w18 */
19057       break;
19058     case 25:
19059       if (Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19060         return 97; /* nop */
19061       break;
19062     }
19063   return 0;
19064 }
19065
19066 \f
19067 /* Instruction slots.  */
19068
19069 static void
19070 Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
19071                             xtensa_insnbuf slotbuf)
19072 {
19073   slotbuf[1] = 0;
19074   slotbuf[0] = (insn[0] & 0xffffff);
19075 }
19076
19077 static void
19078 Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
19079                             const xtensa_insnbuf slotbuf)
19080 {
19081   insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
19082 }
19083
19084 static void
19085 Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
19086                                 xtensa_insnbuf slotbuf)
19087 {
19088   slotbuf[1] = 0;
19089   slotbuf[0] = (insn[0] & 0xffff);
19090 }
19091
19092 static void
19093 Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
19094                                 const xtensa_insnbuf slotbuf)
19095 {
19096   insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
19097 }
19098
19099 static void
19100 Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
19101                                 xtensa_insnbuf slotbuf)
19102 {
19103   slotbuf[1] = 0;
19104   slotbuf[0] = (insn[0] & 0xffff);
19105 }
19106
19107 static void
19108 Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
19109                                 const xtensa_insnbuf slotbuf)
19110 {
19111   insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
19112 }
19113
19114 static void
19115 Slot_xt_format1_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
19116                                               xtensa_insnbuf slotbuf)
19117 {
19118   slotbuf[1] = 0;
19119   slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
19120 }
19121
19122 static void
19123 Slot_xt_format1_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
19124                                               const xtensa_insnbuf slotbuf)
19125 {
19126   insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
19127 }
19128
19129 static void
19130 Slot_xt_format2_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
19131                                               xtensa_insnbuf slotbuf)
19132 {
19133   slotbuf[1] = 0;
19134   slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
19135 }
19136
19137 static void
19138 Slot_xt_format2_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
19139                                               const xtensa_insnbuf slotbuf)
19140 {
19141   insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
19142 }
19143
19144 static void
19145 Slot_xt_format1_Format_xt_flix64_slot1_28_get (const xtensa_insnbuf insn,
19146                                               xtensa_insnbuf slotbuf)
19147 {
19148   slotbuf[1] = 0;
19149   slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
19150   slotbuf[0] = (slotbuf[0] & ~0xffff0) | ((insn[1] & 0xffff) << 4);
19151 }
19152
19153 static void
19154 Slot_xt_format1_Format_xt_flix64_slot1_28_set (xtensa_insnbuf insn,
19155                                               const xtensa_insnbuf slotbuf)
19156 {
19157   insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
19158   insn[1] = (insn[1] & ~0xffff) | ((slotbuf[0] & 0xffff0) >> 4);
19159 }
19160
19161 static void
19162 Slot_xt_format1_Format_xt_flix64_slot2_48_get (const xtensa_insnbuf insn,
19163                                               xtensa_insnbuf slotbuf)
19164 {
19165   slotbuf[1] = 0;
19166   slotbuf[0] = ((insn[1] & 0xffff0000) >> 16);
19167 }
19168
19169 static void
19170 Slot_xt_format1_Format_xt_flix64_slot2_48_set (xtensa_insnbuf insn,
19171                                               const xtensa_insnbuf slotbuf)
19172 {
19173   insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16);
19174 }
19175
19176 static void
19177 Slot_xt_format2_Format_xt_flix64_slot3_28_get (const xtensa_insnbuf insn,
19178                                               xtensa_insnbuf slotbuf)
19179 {
19180   slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
19181   slotbuf[0] = (slotbuf[0] & ~0xfffffff0) | ((insn[1] & 0xfffffff) << 4);
19182   slotbuf[1] = ((insn[1] & 0x70000000) >> 28);
19183 }
19184
19185 static void
19186 Slot_xt_format2_Format_xt_flix64_slot3_28_set (xtensa_insnbuf insn,
19187                                               const xtensa_insnbuf slotbuf)
19188 {
19189   insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
19190   insn[1] = (insn[1] & ~0xfffffff) | ((slotbuf[0] & 0xfffffff0) >> 4);
19191   insn[1] = (insn[1] & ~0x70000000) | ((slotbuf[1] & 0x7) << 28);
19192 }
19193
19194 static xtensa_get_field_fn
19195 Slot_inst_get_field_fns[] = {
19196   Field_t_Slot_inst_get,
19197   Field_bbi4_Slot_inst_get,
19198   Field_bbi_Slot_inst_get,
19199   Field_imm12_Slot_inst_get,
19200   Field_imm8_Slot_inst_get,
19201   Field_s_Slot_inst_get,
19202   Field_imm12b_Slot_inst_get,
19203   Field_imm16_Slot_inst_get,
19204   Field_m_Slot_inst_get,
19205   Field_n_Slot_inst_get,
19206   Field_offset_Slot_inst_get,
19207   Field_op0_Slot_inst_get,
19208   Field_op1_Slot_inst_get,
19209   Field_op2_Slot_inst_get,
19210   Field_r_Slot_inst_get,
19211   Field_sa4_Slot_inst_get,
19212   Field_sae4_Slot_inst_get,
19213   Field_sae_Slot_inst_get,
19214   Field_sal_Slot_inst_get,
19215   Field_sargt_Slot_inst_get,
19216   Field_sas4_Slot_inst_get,
19217   Field_sas_Slot_inst_get,
19218   Field_sr_Slot_inst_get,
19219   Field_st_Slot_inst_get,
19220   Field_thi3_Slot_inst_get,
19221   Field_imm4_Slot_inst_get,
19222   Field_mn_Slot_inst_get,
19223   0,
19224   0,
19225   0,
19226   0,
19227   0,
19228   0,
19229   0,
19230   0,
19231   Field_r3_Slot_inst_get,
19232   Field_rbit2_Slot_inst_get,
19233   Field_rhi_Slot_inst_get,
19234   Field_t3_Slot_inst_get,
19235   Field_tbit2_Slot_inst_get,
19236   Field_tlo_Slot_inst_get,
19237   Field_w_Slot_inst_get,
19238   Field_y_Slot_inst_get,
19239   Field_x_Slot_inst_get,
19240   Field_t2_Slot_inst_get,
19241   Field_s2_Slot_inst_get,
19242   Field_r2_Slot_inst_get,
19243   Field_t4_Slot_inst_get,
19244   Field_s4_Slot_inst_get,
19245   Field_r4_Slot_inst_get,
19246   Field_t8_Slot_inst_get,
19247   Field_s8_Slot_inst_get,
19248   Field_r8_Slot_inst_get,
19249   Field_xt_wbr15_imm_Slot_inst_get,
19250   Field_xt_wbr18_imm_Slot_inst_get,
19251   0,
19252   0,
19253   0,
19254   0,
19255   0,
19256   0,
19257   0,
19258   0,
19259   0,
19260   0,
19261   0,
19262   0,
19263   0,
19264   0,
19265   0,
19266   0,
19267   0,
19268   0,
19269   0,
19270   0,
19271   0,
19272   0,
19273   0,
19274   0,
19275   0,
19276   0,
19277   0,
19278   0,
19279   0,
19280   0,
19281   0,
19282   0,
19283   0,
19284   0,
19285   0,
19286   0,
19287   0,
19288   0,
19289   0,
19290   0,
19291   0,
19292   0,
19293   0,
19294   0,
19295   0,
19296   0,
19297   0,
19298   0,
19299   0,
19300   0,
19301   0,
19302   0,
19303   0,
19304   0,
19305   0,
19306   0,
19307   0,
19308   0,
19309   0,
19310   0,
19311   0,
19312   0,
19313   0,
19314   0,
19315   0,
19316   0,
19317   0,
19318   0,
19319   Implicit_Field_ar0_get,
19320   Implicit_Field_ar4_get,
19321   Implicit_Field_ar8_get,
19322   Implicit_Field_ar12_get,
19323   Implicit_Field_mr0_get,
19324   Implicit_Field_mr1_get,
19325   Implicit_Field_mr2_get,
19326   Implicit_Field_mr3_get,
19327   Implicit_Field_bt16_get,
19328   Implicit_Field_bs16_get,
19329   Implicit_Field_br16_get,
19330   Implicit_Field_brall_get
19331 };
19332
19333 static xtensa_set_field_fn
19334 Slot_inst_set_field_fns[] = {
19335   Field_t_Slot_inst_set,
19336   Field_bbi4_Slot_inst_set,
19337   Field_bbi_Slot_inst_set,
19338   Field_imm12_Slot_inst_set,
19339   Field_imm8_Slot_inst_set,
19340   Field_s_Slot_inst_set,
19341   Field_imm12b_Slot_inst_set,
19342   Field_imm16_Slot_inst_set,
19343   Field_m_Slot_inst_set,
19344   Field_n_Slot_inst_set,
19345   Field_offset_Slot_inst_set,
19346   Field_op0_Slot_inst_set,
19347   Field_op1_Slot_inst_set,
19348   Field_op2_Slot_inst_set,
19349   Field_r_Slot_inst_set,
19350   Field_sa4_Slot_inst_set,
19351   Field_sae4_Slot_inst_set,
19352   Field_sae_Slot_inst_set,
19353   Field_sal_Slot_inst_set,
19354   Field_sargt_Slot_inst_set,
19355   Field_sas4_Slot_inst_set,
19356   Field_sas_Slot_inst_set,
19357   Field_sr_Slot_inst_set,
19358   Field_st_Slot_inst_set,
19359   Field_thi3_Slot_inst_set,
19360   Field_imm4_Slot_inst_set,
19361   Field_mn_Slot_inst_set,
19362   0,
19363   0,
19364   0,
19365   0,
19366   0,
19367   0,
19368   0,
19369   0,
19370   Field_r3_Slot_inst_set,
19371   Field_rbit2_Slot_inst_set,
19372   Field_rhi_Slot_inst_set,
19373   Field_t3_Slot_inst_set,
19374   Field_tbit2_Slot_inst_set,
19375   Field_tlo_Slot_inst_set,
19376   Field_w_Slot_inst_set,
19377   Field_y_Slot_inst_set,
19378   Field_x_Slot_inst_set,
19379   Field_t2_Slot_inst_set,
19380   Field_s2_Slot_inst_set,
19381   Field_r2_Slot_inst_set,
19382   Field_t4_Slot_inst_set,
19383   Field_s4_Slot_inst_set,
19384   Field_r4_Slot_inst_set,
19385   Field_t8_Slot_inst_set,
19386   Field_s8_Slot_inst_set,
19387   Field_r8_Slot_inst_set,
19388   Field_xt_wbr15_imm_Slot_inst_set,
19389   Field_xt_wbr18_imm_Slot_inst_set,
19390   0,
19391   0,
19392   0,
19393   0,
19394   0,
19395   0,
19396   0,
19397   0,
19398   0,
19399   0,
19400   0,
19401   0,
19402   0,
19403   0,
19404   0,
19405   0,
19406   0,
19407   0,
19408   0,
19409   0,
19410   0,
19411   0,
19412   0,
19413   0,
19414   0,
19415   0,
19416   0,
19417   0,
19418   0,
19419   0,
19420   0,
19421   0,
19422   0,
19423   0,
19424   0,
19425   0,
19426   0,
19427   0,
19428   0,
19429   0,
19430   0,
19431   0,
19432   0,
19433   0,
19434   0,
19435   0,
19436   0,
19437   0,
19438   0,
19439   0,
19440   0,
19441   0,
19442   0,
19443   0,
19444   0,
19445   0,
19446   0,
19447   0,
19448   0,
19449   0,
19450   0,
19451   0,
19452   0,
19453   0,
19454   0,
19455   0,
19456   0,
19457   0,
19458   Implicit_Field_set,
19459   Implicit_Field_set,
19460   Implicit_Field_set,
19461   Implicit_Field_set,
19462   Implicit_Field_set,
19463   Implicit_Field_set,
19464   Implicit_Field_set,
19465   Implicit_Field_set,
19466   Implicit_Field_set,
19467   Implicit_Field_set,
19468   Implicit_Field_set,
19469   Implicit_Field_set
19470 };
19471
19472 static xtensa_get_field_fn
19473 Slot_inst16a_get_field_fns[] = {
19474   Field_t_Slot_inst16a_get,
19475   0,
19476   0,
19477   0,
19478   0,
19479   Field_s_Slot_inst16a_get,
19480   0,
19481   0,
19482   0,
19483   0,
19484   0,
19485   Field_op0_Slot_inst16a_get,
19486   0,
19487   0,
19488   Field_r_Slot_inst16a_get,
19489   0,
19490   0,
19491   0,
19492   0,
19493   0,
19494   0,
19495   0,
19496   Field_sr_Slot_inst16a_get,
19497   Field_st_Slot_inst16a_get,
19498   0,
19499   Field_imm4_Slot_inst16a_get,
19500   0,
19501   Field_i_Slot_inst16a_get,
19502   Field_imm6lo_Slot_inst16a_get,
19503   Field_imm6hi_Slot_inst16a_get,
19504   Field_imm7lo_Slot_inst16a_get,
19505   Field_imm7hi_Slot_inst16a_get,
19506   Field_z_Slot_inst16a_get,
19507   Field_imm6_Slot_inst16a_get,
19508   Field_imm7_Slot_inst16a_get,
19509   0,
19510   0,
19511   0,
19512   0,
19513   0,
19514   0,
19515   0,
19516   0,
19517   0,
19518   Field_t2_Slot_inst16a_get,
19519   Field_s2_Slot_inst16a_get,
19520   Field_r2_Slot_inst16a_get,
19521   Field_t4_Slot_inst16a_get,
19522   Field_s4_Slot_inst16a_get,
19523   Field_r4_Slot_inst16a_get,
19524   Field_t8_Slot_inst16a_get,
19525   Field_s8_Slot_inst16a_get,
19526   Field_r8_Slot_inst16a_get,
19527   0,
19528   0,
19529   0,
19530   0,
19531   0,
19532   0,
19533   0,
19534   0,
19535   0,
19536   0,
19537   0,
19538   0,
19539   0,
19540   0,
19541   0,
19542   0,
19543   0,
19544   0,
19545   0,
19546   0,
19547   0,
19548   0,
19549   0,
19550   0,
19551   0,
19552   0,
19553   0,
19554   0,
19555   0,
19556   0,
19557   0,
19558   0,
19559   0,
19560   0,
19561   0,
19562   0,
19563   0,
19564   0,
19565   0,
19566   0,
19567   0,
19568   0,
19569   0,
19570   0,
19571   0,
19572   0,
19573   0,
19574   0,
19575   0,
19576   0,
19577   0,
19578   0,
19579   0,
19580   0,
19581   0,
19582   0,
19583   0,
19584   0,
19585   0,
19586   0,
19587   0,
19588   0,
19589   0,
19590   0,
19591   0,
19592   0,
19593   0,
19594   0,
19595   0,
19596   0,
19597   Implicit_Field_ar0_get,
19598   Implicit_Field_ar4_get,
19599   Implicit_Field_ar8_get,
19600   Implicit_Field_ar12_get,
19601   Implicit_Field_mr0_get,
19602   Implicit_Field_mr1_get,
19603   Implicit_Field_mr2_get,
19604   Implicit_Field_mr3_get,
19605   Implicit_Field_bt16_get,
19606   Implicit_Field_bs16_get,
19607   Implicit_Field_br16_get,
19608   Implicit_Field_brall_get
19609 };
19610
19611 static xtensa_set_field_fn
19612 Slot_inst16a_set_field_fns[] = {
19613   Field_t_Slot_inst16a_set,
19614   0,
19615   0,
19616   0,
19617   0,
19618   Field_s_Slot_inst16a_set,
19619   0,
19620   0,
19621   0,
19622   0,
19623   0,
19624   Field_op0_Slot_inst16a_set,
19625   0,
19626   0,
19627   Field_r_Slot_inst16a_set,
19628   0,
19629   0,
19630   0,
19631   0,
19632   0,
19633   0,
19634   0,
19635   Field_sr_Slot_inst16a_set,
19636   Field_st_Slot_inst16a_set,
19637   0,
19638   Field_imm4_Slot_inst16a_set,
19639   0,
19640   Field_i_Slot_inst16a_set,
19641   Field_imm6lo_Slot_inst16a_set,
19642   Field_imm6hi_Slot_inst16a_set,
19643   Field_imm7lo_Slot_inst16a_set,
19644   Field_imm7hi_Slot_inst16a_set,
19645   Field_z_Slot_inst16a_set,
19646   Field_imm6_Slot_inst16a_set,
19647   Field_imm7_Slot_inst16a_set,
19648   0,
19649   0,
19650   0,
19651   0,
19652   0,
19653   0,
19654   0,
19655   0,
19656   0,
19657   Field_t2_Slot_inst16a_set,
19658   Field_s2_Slot_inst16a_set,
19659   Field_r2_Slot_inst16a_set,
19660   Field_t4_Slot_inst16a_set,
19661   Field_s4_Slot_inst16a_set,
19662   Field_r4_Slot_inst16a_set,
19663   Field_t8_Slot_inst16a_set,
19664   Field_s8_Slot_inst16a_set,
19665   Field_r8_Slot_inst16a_set,
19666   0,
19667   0,
19668   0,
19669   0,
19670   0,
19671   0,
19672   0,
19673   0,
19674   0,
19675   0,
19676   0,
19677   0,
19678   0,
19679   0,
19680   0,
19681   0,
19682   0,
19683   0,
19684   0,
19685   0,
19686   0,
19687   0,
19688   0,
19689   0,
19690   0,
19691   0,
19692   0,
19693   0,
19694   0,
19695   0,
19696   0,
19697   0,
19698   0,
19699   0,
19700   0,
19701   0,
19702   0,
19703   0,
19704   0,
19705   0,
19706   0,
19707   0,
19708   0,
19709   0,
19710   0,
19711   0,
19712   0,
19713   0,
19714   0,
19715   0,
19716   0,
19717   0,
19718   0,
19719   0,
19720   0,
19721   0,
19722   0,
19723   0,
19724   0,
19725   0,
19726   0,
19727   0,
19728   0,
19729   0,
19730   0,
19731   0,
19732   0,
19733   0,
19734   0,
19735   0,
19736   Implicit_Field_set,
19737   Implicit_Field_set,
19738   Implicit_Field_set,
19739   Implicit_Field_set,
19740   Implicit_Field_set,
19741   Implicit_Field_set,
19742   Implicit_Field_set,
19743   Implicit_Field_set,
19744   Implicit_Field_set,
19745   Implicit_Field_set,
19746   Implicit_Field_set,
19747   Implicit_Field_set
19748 };
19749
19750 static xtensa_get_field_fn
19751 Slot_inst16b_get_field_fns[] = {
19752   Field_t_Slot_inst16b_get,
19753   0,
19754   0,
19755   0,
19756   0,
19757   Field_s_Slot_inst16b_get,
19758   0,
19759   0,
19760   0,
19761   0,
19762   0,
19763   Field_op0_Slot_inst16b_get,
19764   0,
19765   0,
19766   Field_r_Slot_inst16b_get,
19767   0,
19768   0,
19769   0,
19770   0,
19771   0,
19772   0,
19773   0,
19774   Field_sr_Slot_inst16b_get,
19775   Field_st_Slot_inst16b_get,
19776   0,
19777   Field_imm4_Slot_inst16b_get,
19778   0,
19779   Field_i_Slot_inst16b_get,
19780   Field_imm6lo_Slot_inst16b_get,
19781   Field_imm6hi_Slot_inst16b_get,
19782   Field_imm7lo_Slot_inst16b_get,
19783   Field_imm7hi_Slot_inst16b_get,
19784   Field_z_Slot_inst16b_get,
19785   Field_imm6_Slot_inst16b_get,
19786   Field_imm7_Slot_inst16b_get,
19787   0,
19788   0,
19789   0,
19790   0,
19791   0,
19792   0,
19793   0,
19794   0,
19795   0,
19796   Field_t2_Slot_inst16b_get,
19797   Field_s2_Slot_inst16b_get,
19798   Field_r2_Slot_inst16b_get,
19799   Field_t4_Slot_inst16b_get,
19800   Field_s4_Slot_inst16b_get,
19801   Field_r4_Slot_inst16b_get,
19802   Field_t8_Slot_inst16b_get,
19803   Field_s8_Slot_inst16b_get,
19804   Field_r8_Slot_inst16b_get,
19805   0,
19806   0,
19807   0,
19808   0,
19809   0,
19810   0,
19811   0,
19812   0,
19813   0,
19814   0,
19815   0,
19816   0,
19817   0,
19818   0,
19819   0,
19820   0,
19821   0,
19822   0,
19823   0,
19824   0,
19825   0,
19826   0,
19827   0,
19828   0,
19829   0,
19830   0,
19831   0,
19832   0,
19833   0,
19834   0,
19835   0,
19836   0,
19837   0,
19838   0,
19839   0,
19840   0,
19841   0,
19842   0,
19843   0,
19844   0,
19845   0,
19846   0,
19847   0,
19848   0,
19849   0,
19850   0,
19851   0,
19852   0,
19853   0,
19854   0,
19855   0,
19856   0,
19857   0,
19858   0,
19859   0,
19860   0,
19861   0,
19862   0,
19863   0,
19864   0,
19865   0,
19866   0,
19867   0,
19868   0,
19869   0,
19870   0,
19871   0,
19872   0,
19873   0,
19874   0,
19875   Implicit_Field_ar0_get,
19876   Implicit_Field_ar4_get,
19877   Implicit_Field_ar8_get,
19878   Implicit_Field_ar12_get,
19879   Implicit_Field_mr0_get,
19880   Implicit_Field_mr1_get,
19881   Implicit_Field_mr2_get,
19882   Implicit_Field_mr3_get,
19883   Implicit_Field_bt16_get,
19884   Implicit_Field_bs16_get,
19885   Implicit_Field_br16_get,
19886   Implicit_Field_brall_get
19887 };
19888
19889 static xtensa_set_field_fn
19890 Slot_inst16b_set_field_fns[] = {
19891   Field_t_Slot_inst16b_set,
19892   0,
19893   0,
19894   0,
19895   0,
19896   Field_s_Slot_inst16b_set,
19897   0,
19898   0,
19899   0,
19900   0,
19901   0,
19902   Field_op0_Slot_inst16b_set,
19903   0,
19904   0,
19905   Field_r_Slot_inst16b_set,
19906   0,
19907   0,
19908   0,
19909   0,
19910   0,
19911   0,
19912   0,
19913   Field_sr_Slot_inst16b_set,
19914   Field_st_Slot_inst16b_set,
19915   0,
19916   Field_imm4_Slot_inst16b_set,
19917   0,
19918   Field_i_Slot_inst16b_set,
19919   Field_imm6lo_Slot_inst16b_set,
19920   Field_imm6hi_Slot_inst16b_set,
19921   Field_imm7lo_Slot_inst16b_set,
19922   Field_imm7hi_Slot_inst16b_set,
19923   Field_z_Slot_inst16b_set,
19924   Field_imm6_Slot_inst16b_set,
19925   Field_imm7_Slot_inst16b_set,
19926   0,
19927   0,
19928   0,
19929   0,
19930   0,
19931   0,
19932   0,
19933   0,
19934   0,
19935   Field_t2_Slot_inst16b_set,
19936   Field_s2_Slot_inst16b_set,
19937   Field_r2_Slot_inst16b_set,
19938   Field_t4_Slot_inst16b_set,
19939   Field_s4_Slot_inst16b_set,
19940   Field_r4_Slot_inst16b_set,
19941   Field_t8_Slot_inst16b_set,
19942   Field_s8_Slot_inst16b_set,
19943   Field_r8_Slot_inst16b_set,
19944   0,
19945   0,
19946   0,
19947   0,
19948   0,
19949   0,
19950   0,
19951   0,
19952   0,
19953   0,
19954   0,
19955   0,
19956   0,
19957   0,
19958   0,
19959   0,
19960   0,
19961   0,
19962   0,
19963   0,
19964   0,
19965   0,
19966   0,
19967   0,
19968   0,
19969   0,
19970   0,
19971   0,
19972   0,
19973   0,
19974   0,
19975   0,
19976   0,
19977   0,
19978   0,
19979   0,
19980   0,
19981   0,
19982   0,
19983   0,
19984   0,
19985   0,
19986   0,
19987   0,
19988   0,
19989   0,
19990   0,
19991   0,
19992   0,
19993   0,
19994   0,
19995   0,
19996   0,
19997   0,
19998   0,
19999   0,
20000   0,
20001   0,
20002   0,
20003   0,
20004   0,
20005   0,
20006   0,
20007   0,
20008   0,
20009   0,
20010   0,
20011   0,
20012   0,
20013   0,
20014   Implicit_Field_set,
20015   Implicit_Field_set,
20016   Implicit_Field_set,
20017   Implicit_Field_set,
20018   Implicit_Field_set,
20019   Implicit_Field_set,
20020   Implicit_Field_set,
20021   Implicit_Field_set,
20022   Implicit_Field_set,
20023   Implicit_Field_set,
20024   Implicit_Field_set,
20025   Implicit_Field_set
20026 };
20027
20028 static xtensa_get_field_fn
20029 Slot_xt_flix64_slot0_get_field_fns[] = {
20030   Field_t_Slot_xt_flix64_slot0_get,
20031   0,
20032   0,
20033   0,
20034   Field_imm8_Slot_xt_flix64_slot0_get,
20035   Field_s_Slot_xt_flix64_slot0_get,
20036   Field_imm12b_Slot_xt_flix64_slot0_get,
20037   Field_imm16_Slot_xt_flix64_slot0_get,
20038   Field_m_Slot_xt_flix64_slot0_get,
20039   Field_n_Slot_xt_flix64_slot0_get,
20040   0,
20041   0,
20042   Field_op1_Slot_xt_flix64_slot0_get,
20043   Field_op2_Slot_xt_flix64_slot0_get,
20044   Field_r_Slot_xt_flix64_slot0_get,
20045   0,
20046   Field_sae4_Slot_xt_flix64_slot0_get,
20047   Field_sae_Slot_xt_flix64_slot0_get,
20048   Field_sal_Slot_xt_flix64_slot0_get,
20049   Field_sargt_Slot_xt_flix64_slot0_get,
20050   0,
20051   Field_sas_Slot_xt_flix64_slot0_get,
20052   0,
20053   0,
20054   Field_thi3_Slot_xt_flix64_slot0_get,
20055   0,
20056   0,
20057   0,
20058   0,
20059   0,
20060   0,
20061   0,
20062   0,
20063   0,
20064   0,
20065   0,
20066   0,
20067   0,
20068   0,
20069   0,
20070   0,
20071   0,
20072   0,
20073   0,
20074   0,
20075   0,
20076   0,
20077   0,
20078   0,
20079   0,
20080   0,
20081   0,
20082   0,
20083   0,
20084   0,
20085   Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get,
20086   Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get,
20087   Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get,
20088   Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get,
20089   Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get,
20090   Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get,
20091   0,
20092   0,
20093   0,
20094   0,
20095   0,
20096   0,
20097   0,
20098   0,
20099   0,
20100   0,
20101   0,
20102   0,
20103   0,
20104   0,
20105   0,
20106   0,
20107   0,
20108   0,
20109   0,
20110   0,
20111   0,
20112   0,
20113   0,
20114   0,
20115   0,
20116   0,
20117   0,
20118   0,
20119   0,
20120   0,
20121   0,
20122   0,
20123   0,
20124   0,
20125   0,
20126   0,
20127   0,
20128   0,
20129   0,
20130   0,
20131   0,
20132   0,
20133   0,
20134   0,
20135   0,
20136   0,
20137   0,
20138   0,
20139   0,
20140   0,
20141   0,
20142   0,
20143   0,
20144   0,
20145   0,
20146   0,
20147   0,
20148   0,
20149   0,
20150   0,
20151   0,
20152   Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get,
20153   Implicit_Field_ar0_get,
20154   Implicit_Field_ar4_get,
20155   Implicit_Field_ar8_get,
20156   Implicit_Field_ar12_get,
20157   Implicit_Field_mr0_get,
20158   Implicit_Field_mr1_get,
20159   Implicit_Field_mr2_get,
20160   Implicit_Field_mr3_get,
20161   Implicit_Field_bt16_get,
20162   Implicit_Field_bs16_get,
20163   Implicit_Field_br16_get,
20164   Implicit_Field_brall_get
20165 };
20166
20167 static xtensa_set_field_fn
20168 Slot_xt_flix64_slot0_set_field_fns[] = {
20169   Field_t_Slot_xt_flix64_slot0_set,
20170   0,
20171   0,
20172   0,
20173   Field_imm8_Slot_xt_flix64_slot0_set,
20174   Field_s_Slot_xt_flix64_slot0_set,
20175   Field_imm12b_Slot_xt_flix64_slot0_set,
20176   Field_imm16_Slot_xt_flix64_slot0_set,
20177   Field_m_Slot_xt_flix64_slot0_set,
20178   Field_n_Slot_xt_flix64_slot0_set,
20179   0,
20180   0,
20181   Field_op1_Slot_xt_flix64_slot0_set,
20182   Field_op2_Slot_xt_flix64_slot0_set,
20183   Field_r_Slot_xt_flix64_slot0_set,
20184   0,
20185   Field_sae4_Slot_xt_flix64_slot0_set,
20186   Field_sae_Slot_xt_flix64_slot0_set,
20187   Field_sal_Slot_xt_flix64_slot0_set,
20188   Field_sargt_Slot_xt_flix64_slot0_set,
20189   0,
20190   Field_sas_Slot_xt_flix64_slot0_set,
20191   0,
20192   0,
20193   Field_thi3_Slot_xt_flix64_slot0_set,
20194   0,
20195   0,
20196   0,
20197   0,
20198   0,
20199   0,
20200   0,
20201   0,
20202   0,
20203   0,
20204   0,
20205   0,
20206   0,
20207   0,
20208   0,
20209   0,
20210   0,
20211   0,
20212   0,
20213   0,
20214   0,
20215   0,
20216   0,
20217   0,
20218   0,
20219   0,
20220   0,
20221   0,
20222   0,
20223   0,
20224   Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set,
20225   Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set,
20226   Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set,
20227   Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set,
20228   Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set,
20229   Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set,
20230   0,
20231   0,
20232   0,
20233   0,
20234   0,
20235   0,
20236   0,
20237   0,
20238   0,
20239   0,
20240   0,
20241   0,
20242   0,
20243   0,
20244   0,
20245   0,
20246   0,
20247   0,
20248   0,
20249   0,
20250   0,
20251   0,
20252   0,
20253   0,
20254   0,
20255   0,
20256   0,
20257   0,
20258   0,
20259   0,
20260   0,
20261   0,
20262   0,
20263   0,
20264   0,
20265   0,
20266   0,
20267   0,
20268   0,
20269   0,
20270   0,
20271   0,
20272   0,
20273   0,
20274   0,
20275   0,
20276   0,
20277   0,
20278   0,
20279   0,
20280   0,
20281   0,
20282   0,
20283   0,
20284   0,
20285   0,
20286   0,
20287   0,
20288   0,
20289   0,
20290   0,
20291   Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set,
20292   Implicit_Field_set,
20293   Implicit_Field_set,
20294   Implicit_Field_set,
20295   Implicit_Field_set,
20296   Implicit_Field_set,
20297   Implicit_Field_set,
20298   Implicit_Field_set,
20299   Implicit_Field_set,
20300   Implicit_Field_set,
20301   Implicit_Field_set,
20302   Implicit_Field_set,
20303   Implicit_Field_set
20304 };
20305
20306 static xtensa_get_field_fn
20307 Slot_xt_flix64_slot1_get_field_fns[] = {
20308   Field_t_Slot_xt_flix64_slot1_get,
20309   0,
20310   0,
20311   0,
20312   Field_imm8_Slot_xt_flix64_slot1_get,
20313   Field_s_Slot_xt_flix64_slot1_get,
20314   Field_imm12b_Slot_xt_flix64_slot1_get,
20315   0,
20316   0,
20317   0,
20318   Field_offset_Slot_xt_flix64_slot1_get,
20319   0,
20320   0,
20321   Field_op2_Slot_xt_flix64_slot1_get,
20322   Field_r_Slot_xt_flix64_slot1_get,
20323   0,
20324   0,
20325   Field_sae_Slot_xt_flix64_slot1_get,
20326   Field_sal_Slot_xt_flix64_slot1_get,
20327   Field_sargt_Slot_xt_flix64_slot1_get,
20328   0,
20329   0,
20330   0,
20331   0,
20332   0,
20333   0,
20334   0,
20335   0,
20336   0,
20337   0,
20338   0,
20339   0,
20340   0,
20341   0,
20342   0,
20343   0,
20344   0,
20345   0,
20346   0,
20347   0,
20348   0,
20349   0,
20350   0,
20351   0,
20352   0,
20353   0,
20354   0,
20355   0,
20356   0,
20357   0,
20358   0,
20359   0,
20360   0,
20361   0,
20362   0,
20363   0,
20364   0,
20365   0,
20366   0,
20367   0,
20368   0,
20369   Field_op0_s4_Slot_xt_flix64_slot1_get,
20370   Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get,
20371   Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20372   Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20373   Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20374   Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20375   Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20376   Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20377   Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20378   Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20379   Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20380   Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20381   Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20382   Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20383   Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20384   Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20385   Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20386   Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20387   Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20388   Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20389   Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20390   Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20391   0,
20392   0,
20393   0,
20394   0,
20395   0,
20396   0,
20397   0,
20398   0,
20399   0,
20400   0,
20401   0,
20402   0,
20403   0,
20404   0,
20405   0,
20406   0,
20407   0,
20408   0,
20409   0,
20410   0,
20411   0,
20412   0,
20413   0,
20414   0,
20415   0,
20416   0,
20417   0,
20418   0,
20419   0,
20420   0,
20421   0,
20422   0,
20423   0,
20424   0,
20425   0,
20426   0,
20427   0,
20428   0,
20429   0,
20430   0,
20431   Implicit_Field_ar0_get,
20432   Implicit_Field_ar4_get,
20433   Implicit_Field_ar8_get,
20434   Implicit_Field_ar12_get,
20435   Implicit_Field_mr0_get,
20436   Implicit_Field_mr1_get,
20437   Implicit_Field_mr2_get,
20438   Implicit_Field_mr3_get,
20439   Implicit_Field_bt16_get,
20440   Implicit_Field_bs16_get,
20441   Implicit_Field_br16_get,
20442   Implicit_Field_brall_get
20443 };
20444
20445 static xtensa_set_field_fn
20446 Slot_xt_flix64_slot1_set_field_fns[] = {
20447   Field_t_Slot_xt_flix64_slot1_set,
20448   0,
20449   0,
20450   0,
20451   Field_imm8_Slot_xt_flix64_slot1_set,
20452   Field_s_Slot_xt_flix64_slot1_set,
20453   Field_imm12b_Slot_xt_flix64_slot1_set,
20454   0,
20455   0,
20456   0,
20457   Field_offset_Slot_xt_flix64_slot1_set,
20458   0,
20459   0,
20460   Field_op2_Slot_xt_flix64_slot1_set,
20461   Field_r_Slot_xt_flix64_slot1_set,
20462   0,
20463   0,
20464   Field_sae_Slot_xt_flix64_slot1_set,
20465   Field_sal_Slot_xt_flix64_slot1_set,
20466   Field_sargt_Slot_xt_flix64_slot1_set,
20467   0,
20468   0,
20469   0,
20470   0,
20471   0,
20472   0,
20473   0,
20474   0,
20475   0,
20476   0,
20477   0,
20478   0,
20479   0,
20480   0,
20481   0,
20482   0,
20483   0,
20484   0,
20485   0,
20486   0,
20487   0,
20488   0,
20489   0,
20490   0,
20491   0,
20492   0,
20493   0,
20494   0,
20495   0,
20496   0,
20497   0,
20498   0,
20499   0,
20500   0,
20501   0,
20502   0,
20503   0,
20504   0,
20505   0,
20506   0,
20507   0,
20508   Field_op0_s4_Slot_xt_flix64_slot1_set,
20509   Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set,
20510   Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20511   Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20512   Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20513   Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20514   Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20515   Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20516   Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20517   Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20518   Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20519   Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20520   Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20521   Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20522   Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20523   Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20524   Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20525   Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20526   Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20527   Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20528   Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20529   Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20530   0,
20531   0,
20532   0,
20533   0,
20534   0,
20535   0,
20536   0,
20537   0,
20538   0,
20539   0,
20540   0,
20541   0,
20542   0,
20543   0,
20544   0,
20545   0,
20546   0,
20547   0,
20548   0,
20549   0,
20550   0,
20551   0,
20552   0,
20553   0,
20554   0,
20555   0,
20556   0,
20557   0,
20558   0,
20559   0,
20560   0,
20561   0,
20562   0,
20563   0,
20564   0,
20565   0,
20566   0,
20567   0,
20568   0,
20569   0,
20570   Implicit_Field_set,
20571   Implicit_Field_set,
20572   Implicit_Field_set,
20573   Implicit_Field_set,
20574   Implicit_Field_set,
20575   Implicit_Field_set,
20576   Implicit_Field_set,
20577   Implicit_Field_set,
20578   Implicit_Field_set,
20579   Implicit_Field_set,
20580   Implicit_Field_set,
20581   Implicit_Field_set
20582 };
20583
20584 static xtensa_get_field_fn
20585 Slot_xt_flix64_slot2_get_field_fns[] = {
20586   Field_t_Slot_xt_flix64_slot2_get,
20587   0,
20588   0,
20589   0,
20590   0,
20591   Field_s_Slot_xt_flix64_slot2_get,
20592   0,
20593   0,
20594   0,
20595   0,
20596   0,
20597   0,
20598   0,
20599   0,
20600   Field_r_Slot_xt_flix64_slot2_get,
20601   0,
20602   0,
20603   0,
20604   0,
20605   Field_sargt_Slot_xt_flix64_slot2_get,
20606   0,
20607   0,
20608   0,
20609   0,
20610   0,
20611   0,
20612   0,
20613   0,
20614   0,
20615   0,
20616   0,
20617   0,
20618   0,
20619   0,
20620   Field_imm7_Slot_xt_flix64_slot2_get,
20621   0,
20622   0,
20623   0,
20624   0,
20625   0,
20626   0,
20627   0,
20628   0,
20629   0,
20630   0,
20631   0,
20632   0,
20633   0,
20634   0,
20635   0,
20636   0,
20637   0,
20638   0,
20639   0,
20640   0,
20641   0,
20642   0,
20643   0,
20644   0,
20645   0,
20646   0,
20647   0,
20648   0,
20649   0,
20650   0,
20651   0,
20652   0,
20653   0,
20654   0,
20655   0,
20656   0,
20657   0,
20658   0,
20659   0,
20660   0,
20661   0,
20662   0,
20663   0,
20664   0,
20665   0,
20666   0,
20667   0,
20668   0,
20669   Field_op0_s5_Slot_xt_flix64_slot2_get,
20670   Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20671   Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20672   Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20673   Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20674   Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20675   Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20676   Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20677   Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20678   Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20679   Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20680   Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20681   Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20682   Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20683   0,
20684   0,
20685   0,
20686   0,
20687   0,
20688   0,
20689   0,
20690   0,
20691   0,
20692   0,
20693   0,
20694   0,
20695   0,
20696   0,
20697   0,
20698   0,
20699   0,
20700   0,
20701   0,
20702   0,
20703   0,
20704   0,
20705   0,
20706   0,
20707   0,
20708   0,
20709   Implicit_Field_ar0_get,
20710   Implicit_Field_ar4_get,
20711   Implicit_Field_ar8_get,
20712   Implicit_Field_ar12_get,
20713   Implicit_Field_mr0_get,
20714   Implicit_Field_mr1_get,
20715   Implicit_Field_mr2_get,
20716   Implicit_Field_mr3_get,
20717   Implicit_Field_bt16_get,
20718   Implicit_Field_bs16_get,
20719   Implicit_Field_br16_get,
20720   Implicit_Field_brall_get
20721 };
20722
20723 static xtensa_set_field_fn
20724 Slot_xt_flix64_slot2_set_field_fns[] = {
20725   Field_t_Slot_xt_flix64_slot2_set,
20726   0,
20727   0,
20728   0,
20729   0,
20730   Field_s_Slot_xt_flix64_slot2_set,
20731   0,
20732   0,
20733   0,
20734   0,
20735   0,
20736   0,
20737   0,
20738   0,
20739   Field_r_Slot_xt_flix64_slot2_set,
20740   0,
20741   0,
20742   0,
20743   0,
20744   Field_sargt_Slot_xt_flix64_slot2_set,
20745   0,
20746   0,
20747   0,
20748   0,
20749   0,
20750   0,
20751   0,
20752   0,
20753   0,
20754   0,
20755   0,
20756   0,
20757   0,
20758   0,
20759   Field_imm7_Slot_xt_flix64_slot2_set,
20760   0,
20761   0,
20762   0,
20763   0,
20764   0,
20765   0,
20766   0,
20767   0,
20768   0,
20769   0,
20770   0,
20771   0,
20772   0,
20773   0,
20774   0,
20775   0,
20776   0,
20777   0,
20778   0,
20779   0,
20780   0,
20781   0,
20782   0,
20783   0,
20784   0,
20785   0,
20786   0,
20787   0,
20788   0,
20789   0,
20790   0,
20791   0,
20792   0,
20793   0,
20794   0,
20795   0,
20796   0,
20797   0,
20798   0,
20799   0,
20800   0,
20801   0,
20802   0,
20803   0,
20804   0,
20805   0,
20806   0,
20807   0,
20808   Field_op0_s5_Slot_xt_flix64_slot2_set,
20809   Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20810   Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20811   Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20812   Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20813   Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20814   Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20815   Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20816   Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20817   Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20818   Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20819   Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20820   Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20821   Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20822   0,
20823   0,
20824   0,
20825   0,
20826   0,
20827   0,
20828   0,
20829   0,
20830   0,
20831   0,
20832   0,
20833   0,
20834   0,
20835   0,
20836   0,
20837   0,
20838   0,
20839   0,
20840   0,
20841   0,
20842   0,
20843   0,
20844   0,
20845   0,
20846   0,
20847   0,
20848   Implicit_Field_set,
20849   Implicit_Field_set,
20850   Implicit_Field_set,
20851   Implicit_Field_set,
20852   Implicit_Field_set,
20853   Implicit_Field_set,
20854   Implicit_Field_set,
20855   Implicit_Field_set,
20856   Implicit_Field_set,
20857   Implicit_Field_set,
20858   Implicit_Field_set,
20859   Implicit_Field_set
20860 };
20861
20862 static xtensa_get_field_fn
20863 Slot_xt_flix64_slot3_get_field_fns[] = {
20864   Field_t_Slot_xt_flix64_slot3_get,
20865   0,
20866   Field_bbi_Slot_xt_flix64_slot3_get,
20867   0,
20868   0,
20869   Field_s_Slot_xt_flix64_slot3_get,
20870   0,
20871   0,
20872   0,
20873   0,
20874   0,
20875   0,
20876   0,
20877   0,
20878   Field_r_Slot_xt_flix64_slot3_get,
20879   0,
20880   0,
20881   0,
20882   0,
20883   0,
20884   0,
20885   0,
20886   0,
20887   0,
20888   0,
20889   0,
20890   0,
20891   0,
20892   0,
20893   0,
20894   0,
20895   0,
20896   0,
20897   0,
20898   0,
20899   0,
20900   0,
20901   0,
20902   0,
20903   0,
20904   0,
20905   0,
20906   0,
20907   0,
20908   0,
20909   0,
20910   0,
20911   0,
20912   0,
20913   0,
20914   0,
20915   0,
20916   0,
20917   0,
20918   Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get,
20919   0,
20920   0,
20921   0,
20922   0,
20923   0,
20924   0,
20925   0,
20926   0,
20927   0,
20928   0,
20929   0,
20930   0,
20931   0,
20932   0,
20933   0,
20934   0,
20935   0,
20936   0,
20937   0,
20938   0,
20939   0,
20940   0,
20941   0,
20942   0,
20943   0,
20944   0,
20945   0,
20946   0,
20947   0,
20948   0,
20949   0,
20950   0,
20951   0,
20952   0,
20953   0,
20954   0,
20955   0,
20956   0,
20957   0,
20958   0,
20959   0,
20960   0,
20961   Field_op0_s6_Slot_xt_flix64_slot3_get,
20962   Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20963   Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get,
20964   Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20965   Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20966   Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20967   Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20968   Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20969   Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20970   Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20971   Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20972   Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20973   Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20974   Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20975   Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20976   Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20977   Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20978   Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20979   Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20980   Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20981   Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20982   Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20983   Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20984   Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20985   Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20986   0,
20987   Implicit_Field_ar0_get,
20988   Implicit_Field_ar4_get,
20989   Implicit_Field_ar8_get,
20990   Implicit_Field_ar12_get,
20991   Implicit_Field_mr0_get,
20992   Implicit_Field_mr1_get,
20993   Implicit_Field_mr2_get,
20994   Implicit_Field_mr3_get,
20995   Implicit_Field_bt16_get,
20996   Implicit_Field_bs16_get,
20997   Implicit_Field_br16_get,
20998   Implicit_Field_brall_get
20999 };
21000
21001 static xtensa_set_field_fn
21002 Slot_xt_flix64_slot3_set_field_fns[] = {
21003   Field_t_Slot_xt_flix64_slot3_set,
21004   0,
21005   Field_bbi_Slot_xt_flix64_slot3_set,
21006   0,
21007   0,
21008   Field_s_Slot_xt_flix64_slot3_set,
21009   0,
21010   0,
21011   0,
21012   0,
21013   0,
21014   0,
21015   0,
21016   0,
21017   Field_r_Slot_xt_flix64_slot3_set,
21018   0,
21019   0,
21020   0,
21021   0,
21022   0,
21023   0,
21024   0,
21025   0,
21026   0,
21027   0,
21028   0,
21029   0,
21030   0,
21031   0,
21032   0,
21033   0,
21034   0,
21035   0,
21036   0,
21037   0,
21038   0,
21039   0,
21040   0,
21041   0,
21042   0,
21043   0,
21044   0,
21045   0,
21046   0,
21047   0,
21048   0,
21049   0,
21050   0,
21051   0,
21052   0,
21053   0,
21054   0,
21055   0,
21056   0,
21057   Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set,
21058   0,
21059   0,
21060   0,
21061   0,
21062   0,
21063   0,
21064   0,
21065   0,
21066   0,
21067   0,
21068   0,
21069   0,
21070   0,
21071   0,
21072   0,
21073   0,
21074   0,
21075   0,
21076   0,
21077   0,
21078   0,
21079   0,
21080   0,
21081   0,
21082   0,
21083   0,
21084   0,
21085   0,
21086   0,
21087   0,
21088   0,
21089   0,
21090   0,
21091   0,
21092   0,
21093   0,
21094   0,
21095   0,
21096   0,
21097   0,
21098   0,
21099   0,
21100   Field_op0_s6_Slot_xt_flix64_slot3_set,
21101   Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21102   Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set,
21103   Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21104   Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21105   Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21106   Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21107   Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21108   Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21109   Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21110   Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21111   Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21112   Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21113   Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21114   Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21115   Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21116   Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21117   Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21118   Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21119   Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21120   Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21121   Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21122   Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21123   Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21124   Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21125   0,
21126   Implicit_Field_set,
21127   Implicit_Field_set,
21128   Implicit_Field_set,
21129   Implicit_Field_set,
21130   Implicit_Field_set,
21131   Implicit_Field_set,
21132   Implicit_Field_set,
21133   Implicit_Field_set,
21134   Implicit_Field_set,
21135   Implicit_Field_set,
21136   Implicit_Field_set,
21137   Implicit_Field_set
21138 };
21139
21140 static xtensa_slot_internal slots[] = {
21141   { "Inst", "x24", 0,
21142     Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
21143     Slot_inst_get_field_fns, Slot_inst_set_field_fns,
21144     Slot_inst_decode, "nop" },
21145   { "Inst16a", "x16a", 0,
21146     Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
21147     Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
21148     Slot_inst16a_decode, "" },
21149   { "Inst16b", "x16b", 0,
21150     Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
21151     Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
21152     Slot_inst16b_decode, "nop.n" },
21153   { "xt_flix64_slot0", "xt_format1", 0,
21154     Slot_xt_format1_Format_xt_flix64_slot0_4_get, Slot_xt_format1_Format_xt_flix64_slot0_4_set,
21155     Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
21156     Slot_xt_flix64_slot0_decode, "nop" },
21157   { "xt_flix64_slot0", "xt_format2", 0,
21158     Slot_xt_format2_Format_xt_flix64_slot0_4_get, Slot_xt_format2_Format_xt_flix64_slot0_4_set,
21159     Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
21160     Slot_xt_flix64_slot0_decode, "nop" },
21161   { "xt_flix64_slot1", "xt_format1", 1,
21162     Slot_xt_format1_Format_xt_flix64_slot1_28_get, Slot_xt_format1_Format_xt_flix64_slot1_28_set,
21163     Slot_xt_flix64_slot1_get_field_fns, Slot_xt_flix64_slot1_set_field_fns,
21164     Slot_xt_flix64_slot1_decode, "nop" },
21165   { "xt_flix64_slot2", "xt_format1", 2,
21166     Slot_xt_format1_Format_xt_flix64_slot2_48_get, Slot_xt_format1_Format_xt_flix64_slot2_48_set,
21167     Slot_xt_flix64_slot2_get_field_fns, Slot_xt_flix64_slot2_set_field_fns,
21168     Slot_xt_flix64_slot2_decode, "nop" },
21169   { "xt_flix64_slot3", "xt_format2", 1,
21170     Slot_xt_format2_Format_xt_flix64_slot3_28_get, Slot_xt_format2_Format_xt_flix64_slot3_28_set,
21171     Slot_xt_flix64_slot3_get_field_fns, Slot_xt_flix64_slot3_set_field_fns,
21172     Slot_xt_flix64_slot3_decode, "nop" }
21173 };
21174
21175 \f
21176 /* Instruction formats.  */
21177
21178 static void
21179 Format_x24_encode (xtensa_insnbuf insn)
21180 {
21181   insn[0] = 0;
21182   insn[1] = 0;
21183 }
21184
21185 static void
21186 Format_x16a_encode (xtensa_insnbuf insn)
21187 {
21188   insn[0] = 0x8;
21189   insn[1] = 0;
21190 }
21191
21192 static void
21193 Format_x16b_encode (xtensa_insnbuf insn)
21194 {
21195   insn[0] = 0xc;
21196   insn[1] = 0;
21197 }
21198
21199 static void
21200 Format_xt_format1_encode (xtensa_insnbuf insn)
21201 {
21202   insn[0] = 0xe;
21203   insn[1] = 0;
21204 }
21205
21206 static void
21207 Format_xt_format2_encode (xtensa_insnbuf insn)
21208 {
21209   insn[0] = 0xf;
21210   insn[1] = 0;
21211 }
21212
21213 static int Format_x24_slots[] = { 0 };
21214
21215 static int Format_x16a_slots[] = { 1 };
21216
21217 static int Format_x16b_slots[] = { 2 };
21218
21219 static int Format_xt_format1_slots[] = { 3, 5, 6 };
21220
21221 static int Format_xt_format2_slots[] = { 4, 7 };
21222
21223 static xtensa_format_internal formats[] = {
21224   { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
21225   { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
21226   { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
21227   { "xt_format1", 8, Format_xt_format1_encode, 3, Format_xt_format1_slots },
21228   { "xt_format2", 8, Format_xt_format2_encode, 2, Format_xt_format2_slots }
21229 };
21230
21231
21232 static int
21233 format_decoder (const xtensa_insnbuf insn)
21234 {
21235   if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0)
21236     return 0; /* x24 */
21237   if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0)
21238     return 1; /* x16a */
21239   if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0)
21240     return 2; /* x16b */
21241   if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0)
21242     return 3; /* xt_format1 */
21243   if ((insn[0] & 0xf) == 0xf && (insn[1] & 0x80000000) == 0)
21244     return 4; /* xt_format2 */
21245   return -1;
21246 }
21247
21248 static int length_table[16] = {
21249   3,
21250   3,
21251   3,
21252   3,
21253   3,
21254   3,
21255   3,
21256   3,
21257   2,
21258   2,
21259   2,
21260   2,
21261   2,
21262   2,
21263   8,
21264   8
21265 };
21266
21267 static int
21268 length_decoder (const unsigned char *insn)
21269 {
21270   int op0 = insn[0] & 0xf;
21271   return length_table[op0];
21272 }
21273
21274 \f
21275 /* Top-level ISA structure.  */
21276
21277 xtensa_isa_internal xtensa_modules = {
21278   0 /* little-endian */,
21279   8 /* insn_size */, 0,
21280   5, formats, format_decoder, length_decoder,
21281   8, slots,
21282   135 /* num_fields */,
21283   188, operands,
21284   355, iclasses,
21285   530, opcodes, 0,
21286   8, regfiles,
21287   NUM_STATES, states, 0,
21288   NUM_SYSREGS, sysregs, 0,
21289   { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
21290   0, interfaces, 0,
21291   0, funcUnits, 0
21292 };