* ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
[binutils-gdb.git] / gdb / frv-tdep.c
blob9262b103aa8d789ff26d0005b0a7beee5570e276
1 /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
3 Copyright (C) 2002-2005, 2007-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #include "defs.h"
21 #include "gdb_string.h"
22 #include "inferior.h"
23 #include "gdbcore.h"
24 #include "arch-utils.h"
25 #include "regcache.h"
26 #include "frame.h"
27 #include "frame-unwind.h"
28 #include "frame-base.h"
29 #include "trad-frame.h"
30 #include "dis-asm.h"
31 #include "gdb_assert.h"
32 #include "sim-regno.h"
33 #include "gdb/sim-frv.h"
34 #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */
35 #include "symtab.h"
36 #include "elf-bfd.h"
37 #include "elf/frv.h"
38 #include "osabi.h"
39 #include "infcall.h"
40 #include "solib.h"
41 #include "frv-tdep.h"
43 extern void _initialize_frv_tdep (void);
45 struct frv_unwind_cache /* was struct frame_extra_info */
47 /* The previous frame's inner-most stack address. Used as this
48 frame ID's stack_addr. */
49 CORE_ADDR prev_sp;
51 /* The frame's base, optionally used by the high-level debug info. */
52 CORE_ADDR base;
54 /* Table indicating the location of each and every register. */
55 struct trad_frame_saved_reg *saved_regs;
58 /* A structure describing a particular variant of the FRV.
59 We allocate and initialize one of these structures when we create
60 the gdbarch object for a variant.
62 At the moment, all the FR variants we support differ only in which
63 registers are present; the portable code of GDB knows that
64 registers whose names are the empty string don't exist, so the
65 `register_names' array captures all the per-variant information we
66 need.
68 in the future, if we need to have per-variant maps for raw size,
69 virtual type, etc., we should replace register_names with an array
70 of structures, each of which gives all the necessary info for one
71 register. Don't stick parallel arrays in here --- that's so
72 Fortran. */
73 struct gdbarch_tdep
75 /* Which ABI is in use? */
76 enum frv_abi frv_abi;
78 /* How many general-purpose registers does this variant have? */
79 int num_gprs;
81 /* How many floating-point registers does this variant have? */
82 int num_fprs;
84 /* How many hardware watchpoints can it support? */
85 int num_hw_watchpoints;
87 /* How many hardware breakpoints can it support? */
88 int num_hw_breakpoints;
90 /* Register names. */
91 char **register_names;
94 /* Return the FR-V ABI associated with GDBARCH. */
95 enum frv_abi
96 frv_abi (struct gdbarch *gdbarch)
98 return gdbarch_tdep (gdbarch)->frv_abi;
101 /* Fetch the interpreter and executable loadmap addresses (for shared
102 library support) for the FDPIC ABI. Return 0 if successful, -1 if
103 not. (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.) */
105 frv_fdpic_loadmap_addresses (struct gdbarch *gdbarch, CORE_ADDR *interp_addr,
106 CORE_ADDR *exec_addr)
108 if (frv_abi (gdbarch) != FRV_ABI_FDPIC)
109 return -1;
110 else
112 struct regcache *regcache = get_current_regcache ();
114 if (interp_addr != NULL)
116 ULONGEST val;
117 regcache_cooked_read_unsigned (regcache,
118 fdpic_loadmap_interp_regnum, &val);
119 *interp_addr = val;
121 if (exec_addr != NULL)
123 ULONGEST val;
124 regcache_cooked_read_unsigned (regcache,
125 fdpic_loadmap_exec_regnum, &val);
126 *exec_addr = val;
128 return 0;
132 /* Allocate a new variant structure, and set up default values for all
133 the fields. */
134 static struct gdbarch_tdep *
135 new_variant (void)
137 struct gdbarch_tdep *var;
138 int r;
140 var = xmalloc (sizeof (*var));
141 memset (var, 0, sizeof (*var));
143 var->frv_abi = FRV_ABI_EABI;
144 var->num_gprs = 64;
145 var->num_fprs = 64;
146 var->num_hw_watchpoints = 0;
147 var->num_hw_breakpoints = 0;
149 /* By default, don't supply any general-purpose or floating-point
150 register names. */
151 var->register_names
152 = (char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs)
153 * sizeof (char *));
154 for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++)
155 var->register_names[r] = "";
157 /* Do, however, supply default names for the known special-purpose
158 registers. */
160 var->register_names[pc_regnum] = "pc";
161 var->register_names[lr_regnum] = "lr";
162 var->register_names[lcr_regnum] = "lcr";
164 var->register_names[psr_regnum] = "psr";
165 var->register_names[ccr_regnum] = "ccr";
166 var->register_names[cccr_regnum] = "cccr";
167 var->register_names[tbr_regnum] = "tbr";
169 /* Debug registers. */
170 var->register_names[brr_regnum] = "brr";
171 var->register_names[dbar0_regnum] = "dbar0";
172 var->register_names[dbar1_regnum] = "dbar1";
173 var->register_names[dbar2_regnum] = "dbar2";
174 var->register_names[dbar3_regnum] = "dbar3";
176 /* iacc0 (Only found on MB93405.) */
177 var->register_names[iacc0h_regnum] = "iacc0h";
178 var->register_names[iacc0l_regnum] = "iacc0l";
179 var->register_names[iacc0_regnum] = "iacc0";
181 /* fsr0 (Found on FR555 and FR501.) */
182 var->register_names[fsr0_regnum] = "fsr0";
184 /* acc0 - acc7. The architecture provides for the possibility of many
185 more (up to 64 total), but we don't want to make that big of a hole
186 in the G packet. If we need more in the future, we'll add them
187 elsewhere. */
188 for (r = acc0_regnum; r <= acc7_regnum; r++)
190 char *buf;
191 buf = xstrprintf ("acc%d", r - acc0_regnum);
192 var->register_names[r] = buf;
195 /* accg0 - accg7: These are one byte registers. The remote protocol
196 provides the raw values packed four into a slot. accg0123 and
197 accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively.
198 We don't provide names for accg0123 and accg4567 since the user will
199 likely not want to see these raw values. */
201 for (r = accg0_regnum; r <= accg7_regnum; r++)
203 char *buf;
204 buf = xstrprintf ("accg%d", r - accg0_regnum);
205 var->register_names[r] = buf;
208 /* msr0 and msr1. */
210 var->register_names[msr0_regnum] = "msr0";
211 var->register_names[msr1_regnum] = "msr1";
213 /* gner and fner registers. */
214 var->register_names[gner0_regnum] = "gner0";
215 var->register_names[gner1_regnum] = "gner1";
216 var->register_names[fner0_regnum] = "fner0";
217 var->register_names[fner1_regnum] = "fner1";
219 return var;
223 /* Indicate that the variant VAR has NUM_GPRS general-purpose
224 registers, and fill in the names array appropriately. */
225 static void
226 set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs)
228 int r;
230 var->num_gprs = num_gprs;
232 for (r = 0; r < num_gprs; ++r)
234 char buf[20];
236 sprintf (buf, "gr%d", r);
237 var->register_names[first_gpr_regnum + r] = xstrdup (buf);
242 /* Indicate that the variant VAR has NUM_FPRS floating-point
243 registers, and fill in the names array appropriately. */
244 static void
245 set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs)
247 int r;
249 var->num_fprs = num_fprs;
251 for (r = 0; r < num_fprs; ++r)
253 char buf[20];
255 sprintf (buf, "fr%d", r);
256 var->register_names[first_fpr_regnum + r] = xstrdup (buf);
260 static void
261 set_variant_abi_fdpic (struct gdbarch_tdep *var)
263 var->frv_abi = FRV_ABI_FDPIC;
264 var->register_names[fdpic_loadmap_exec_regnum] = xstrdup ("loadmap_exec");
265 var->register_names[fdpic_loadmap_interp_regnum]
266 = xstrdup ("loadmap_interp");
269 static void
270 set_variant_scratch_registers (struct gdbarch_tdep *var)
272 var->register_names[scr0_regnum] = xstrdup ("scr0");
273 var->register_names[scr1_regnum] = xstrdup ("scr1");
274 var->register_names[scr2_regnum] = xstrdup ("scr2");
275 var->register_names[scr3_regnum] = xstrdup ("scr3");
278 static const char *
279 frv_register_name (struct gdbarch *gdbarch, int reg)
281 if (reg < 0)
282 return "?toosmall?";
283 if (reg >= frv_num_regs + frv_num_pseudo_regs)
284 return "?toolarge?";
286 return gdbarch_tdep (gdbarch)->register_names[reg];
290 static struct type *
291 frv_register_type (struct gdbarch *gdbarch, int reg)
293 if (reg >= first_fpr_regnum && reg <= last_fpr_regnum)
294 return builtin_type (gdbarch)->builtin_float;
295 else if (reg == iacc0_regnum)
296 return builtin_type (gdbarch)->builtin_int64;
297 else
298 return builtin_type (gdbarch)->builtin_int32;
301 static enum register_status
302 frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
303 int reg, gdb_byte *buffer)
305 enum register_status status;
307 if (reg == iacc0_regnum)
309 status = regcache_raw_read (regcache, iacc0h_regnum, buffer);
310 if (status == REG_VALID)
311 status = regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
313 else if (accg0_regnum <= reg && reg <= accg7_regnum)
315 /* The accg raw registers have four values in each slot with the
316 lowest register number occupying the first byte. */
318 int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4;
319 int byte_num = (reg - accg0_regnum) % 4;
320 gdb_byte buf[4];
322 status = regcache_raw_read (regcache, raw_regnum, buf);
323 if (status == REG_VALID)
325 memset (buffer, 0, 4);
326 /* FR-V is big endian, so put the requested byte in the
327 first byte of the buffer allocated to hold the
328 pseudo-register. */
329 buffer[0] = buf[byte_num];
332 else
333 gdb_assert_not_reached ("invalid pseudo register number");
335 return status;
338 static void
339 frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
340 int reg, const gdb_byte *buffer)
342 if (reg == iacc0_regnum)
344 regcache_raw_write (regcache, iacc0h_regnum, buffer);
345 regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4);
347 else if (accg0_regnum <= reg && reg <= accg7_regnum)
349 /* The accg raw registers have four values in each slot with the
350 lowest register number occupying the first byte. */
352 int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4;
353 int byte_num = (reg - accg0_regnum) % 4;
354 char buf[4];
356 regcache_raw_read (regcache, raw_regnum, buf);
357 buf[byte_num] = ((bfd_byte *) buffer)[0];
358 regcache_raw_write (regcache, raw_regnum, buf);
362 static int
363 frv_register_sim_regno (struct gdbarch *gdbarch, int reg)
365 static const int spr_map[] =
367 H_SPR_PSR, /* psr_regnum */
368 H_SPR_CCR, /* ccr_regnum */
369 H_SPR_CCCR, /* cccr_regnum */
370 -1, /* fdpic_loadmap_exec_regnum */
371 -1, /* fdpic_loadmap_interp_regnum */
372 -1, /* 134 */
373 H_SPR_TBR, /* tbr_regnum */
374 H_SPR_BRR, /* brr_regnum */
375 H_SPR_DBAR0, /* dbar0_regnum */
376 H_SPR_DBAR1, /* dbar1_regnum */
377 H_SPR_DBAR2, /* dbar2_regnum */
378 H_SPR_DBAR3, /* dbar3_regnum */
379 H_SPR_SCR0, /* scr0_regnum */
380 H_SPR_SCR1, /* scr1_regnum */
381 H_SPR_SCR2, /* scr2_regnum */
382 H_SPR_SCR3, /* scr3_regnum */
383 H_SPR_LR, /* lr_regnum */
384 H_SPR_LCR, /* lcr_regnum */
385 H_SPR_IACC0H, /* iacc0h_regnum */
386 H_SPR_IACC0L, /* iacc0l_regnum */
387 H_SPR_FSR0, /* fsr0_regnum */
388 /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs. */
389 -1, /* acc0_regnum */
390 -1, /* acc1_regnum */
391 -1, /* acc2_regnum */
392 -1, /* acc3_regnum */
393 -1, /* acc4_regnum */
394 -1, /* acc5_regnum */
395 -1, /* acc6_regnum */
396 -1, /* acc7_regnum */
397 -1, /* acc0123_regnum */
398 -1, /* acc4567_regnum */
399 H_SPR_MSR0, /* msr0_regnum */
400 H_SPR_MSR1, /* msr1_regnum */
401 H_SPR_GNER0, /* gner0_regnum */
402 H_SPR_GNER1, /* gner1_regnum */
403 H_SPR_FNER0, /* fner0_regnum */
404 H_SPR_FNER1, /* fner1_regnum */
407 gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
409 if (first_gpr_regnum <= reg && reg <= last_gpr_regnum)
410 return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM;
411 else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum)
412 return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM;
413 else if (pc_regnum == reg)
414 return SIM_FRV_PC_REGNUM;
415 else if (reg >= first_spr_regnum
416 && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0]))
418 int spr_reg_offset = spr_map[reg - first_spr_regnum];
420 if (spr_reg_offset < 0)
421 return SIM_REGNO_DOES_NOT_EXIST;
422 else
423 return SIM_FRV_SPR0_REGNUM + spr_reg_offset;
426 internal_error (__FILE__, __LINE__, _("Bad register number %d"), reg);
429 static const unsigned char *
430 frv_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenp)
432 static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01};
433 *lenp = sizeof (breakpoint);
434 return breakpoint;
437 /* Define the maximum number of instructions which may be packed into a
438 bundle (VLIW instruction). */
439 static const int max_instrs_per_bundle = 8;
441 /* Define the size (in bytes) of an FR-V instruction. */
442 static const int frv_instr_size = 4;
444 /* Adjust a breakpoint's address to account for the FR-V architecture's
445 constraint that a break instruction must not appear as any but the
446 first instruction in the bundle. */
447 static CORE_ADDR
448 frv_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr)
450 int count = max_instrs_per_bundle;
451 CORE_ADDR addr = bpaddr - frv_instr_size;
452 CORE_ADDR func_start = get_pc_function_start (bpaddr);
454 /* Find the end of the previous packing sequence. This will be indicated
455 by either attempting to access some inaccessible memory or by finding
456 an instruction word whose packing bit is set to one. */
457 while (count-- > 0 && addr >= func_start)
459 char instr[frv_instr_size];
460 int status;
462 status = target_read_memory (addr, instr, sizeof instr);
464 if (status != 0)
465 break;
467 /* This is a big endian architecture, so byte zero will have most
468 significant byte. The most significant bit of this byte is the
469 packing bit. */
470 if (instr[0] & 0x80)
471 break;
473 addr -= frv_instr_size;
476 if (count > 0)
477 bpaddr = addr + frv_instr_size;
479 return bpaddr;
483 /* Return true if REG is a caller-saves ("scratch") register,
484 false otherwise. */
485 static int
486 is_caller_saves_reg (int reg)
488 return ((4 <= reg && reg <= 7)
489 || (14 <= reg && reg <= 15)
490 || (32 <= reg && reg <= 47));
494 /* Return true if REG is a callee-saves register, false otherwise. */
495 static int
496 is_callee_saves_reg (int reg)
498 return ((16 <= reg && reg <= 31)
499 || (48 <= reg && reg <= 63));
503 /* Return true if REG is an argument register, false otherwise. */
504 static int
505 is_argument_reg (int reg)
507 return (8 <= reg && reg <= 13);
510 /* Scan an FR-V prologue, starting at PC, until frame->PC.
511 If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
512 We assume FRAME's saved_regs array has already been allocated and cleared.
513 Return the first PC value after the prologue.
515 Note that, for unoptimized code, we almost don't need this function
516 at all; all arguments and locals live on the stack, so we just need
517 the FP to find everything. The catch: structures passed by value
518 have their addresses living in registers; they're never spilled to
519 the stack. So if you ever want to be able to get to these
520 arguments in any frame but the top, you'll need to do this serious
521 prologue analysis. */
522 static CORE_ADDR
523 frv_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
524 struct frame_info *this_frame,
525 struct frv_unwind_cache *info)
527 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
529 /* When writing out instruction bitpatterns, we use the following
530 letters to label instruction fields:
531 P - The parallel bit. We don't use this.
532 J - The register number of GRj in the instruction description.
533 K - The register number of GRk in the instruction description.
534 I - The register number of GRi.
535 S - a signed imediate offset.
536 U - an unsigned immediate offset.
538 The dots below the numbers indicate where hex digit boundaries
539 fall, to make it easier to check the numbers. */
541 /* Non-zero iff we've seen the instruction that initializes the
542 frame pointer for this function's frame. */
543 int fp_set = 0;
545 /* If fp_set is non_zero, then this is the distance from
546 the stack pointer to frame pointer: fp = sp + fp_offset. */
547 int fp_offset = 0;
549 /* Total size of frame prior to any alloca operations. */
550 int framesize = 0;
552 /* Flag indicating if lr has been saved on the stack. */
553 int lr_saved_on_stack = 0;
555 /* The number of the general-purpose register we saved the return
556 address ("link register") in, or -1 if we haven't moved it yet. */
557 int lr_save_reg = -1;
559 /* Offset (from sp) at which lr has been saved on the stack. */
561 int lr_sp_offset = 0;
563 /* If gr_saved[i] is non-zero, then we've noticed that general
564 register i has been saved at gr_sp_offset[i] from the stack
565 pointer. */
566 char gr_saved[64];
567 int gr_sp_offset[64];
569 /* The address of the most recently scanned prologue instruction. */
570 CORE_ADDR last_prologue_pc;
572 /* The address of the next instruction. */
573 CORE_ADDR next_pc;
575 /* The upper bound to of the pc values to scan. */
576 CORE_ADDR lim_pc;
578 memset (gr_saved, 0, sizeof (gr_saved));
580 last_prologue_pc = pc;
582 /* Try to compute an upper limit (on how far to scan) based on the
583 line number info. */
584 lim_pc = skip_prologue_using_sal (gdbarch, pc);
585 /* If there's no line number info, lim_pc will be 0. In that case,
586 set the limit to be 100 instructions away from pc. Hopefully, this
587 will be far enough away to account for the entire prologue. Don't
588 worry about overshooting the end of the function. The scan loop
589 below contains some checks to avoid scanning unreasonably far. */
590 if (lim_pc == 0)
591 lim_pc = pc + 400;
593 /* If we have a frame, we don't want to scan past the frame's pc. This
594 will catch those cases where the pc is in the prologue. */
595 if (this_frame)
597 CORE_ADDR frame_pc = get_frame_pc (this_frame);
598 if (frame_pc < lim_pc)
599 lim_pc = frame_pc;
602 /* Scan the prologue. */
603 while (pc < lim_pc)
605 char buf[frv_instr_size];
606 LONGEST op;
608 if (target_read_memory (pc, buf, sizeof buf) != 0)
609 break;
610 op = extract_signed_integer (buf, sizeof buf, byte_order);
612 next_pc = pc + 4;
614 /* The tests in this chain of ifs should be in order of
615 decreasing selectivity, so that more particular patterns get
616 to fire before less particular patterns. */
618 /* Some sort of control transfer instruction: stop scanning prologue.
619 Integer Conditional Branch:
620 X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX
621 Floating-point / media Conditional Branch:
622 X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX
623 LCR Conditional Branch to LR
624 X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX
625 Integer conditional Branches to LR
626 X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX
627 X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX
628 Floating-point/Media Branches to LR
629 X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX
630 X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX
631 Jump and Link
632 X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX
633 X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX
634 Call
635 X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX
636 Return from Trap
637 X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX
638 Integer Conditional Trap
639 X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX
640 X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX
641 Floating-point /media Conditional Trap
642 X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX
643 X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX
644 Break
645 X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX
646 Media Trap
647 X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */
648 if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */
649 || (op & 0x01f80000) == 0x00300000 /* Jump and Link */
650 || (op & 0x01f80000) == 0x00100000 /* Return from Trap, Trap */
651 || (op & 0x01f80000) == 0x00700000) /* Trap immediate */
653 /* Stop scanning; not in prologue any longer. */
654 break;
657 /* Loading something from memory into fp probably means that
658 we're in the epilogue. Stop scanning the prologue.
659 ld @(GRi, GRk), fp
660 X 000010 0000010 XXXXXX 000100 XXXXXX
661 ldi @(GRi, d12), fp
662 X 000010 0110010 XXXXXX XXXXXXXXXXXX */
663 else if ((op & 0x7ffc0fc0) == 0x04080100
664 || (op & 0x7ffc0000) == 0x04c80000)
666 break;
669 /* Setting the FP from the SP:
670 ori sp, 0, fp
671 P 000010 0100010 000001 000000000000 = 0x04881000
672 0 111111 1111111 111111 111111111111 = 0x7fffffff
673 . . . . . . . .
674 We treat this as part of the prologue. */
675 else if ((op & 0x7fffffff) == 0x04881000)
677 fp_set = 1;
678 fp_offset = 0;
679 last_prologue_pc = next_pc;
682 /* Move the link register to the scratch register grJ, before saving:
683 movsg lr, grJ
684 P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
685 0 111111 1111111 111111 111111 000000 = 0x7fffffc0
686 . . . . . . . .
687 We treat this as part of the prologue. */
688 else if ((op & 0x7fffffc0) == 0x080d01c0)
690 int gr_j = op & 0x3f;
692 /* If we're moving it to a scratch register, that's fine. */
693 if (is_caller_saves_reg (gr_j))
695 lr_save_reg = gr_j;
696 last_prologue_pc = next_pc;
700 /* To save multiple callee-saves registers on the stack, at
701 offset zero:
703 std grK,@(sp,gr0)
704 P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
705 0 000000 1111111 111111 111111 111111 = 0x01ffffff
707 stq grK,@(sp,gr0)
708 P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
709 0 000000 1111111 111111 111111 111111 = 0x01ffffff
710 . . . . . . . .
711 We treat this as part of the prologue, and record the register's
712 saved address in the frame structure. */
713 else if ((op & 0x01ffffff) == 0x000c10c0
714 || (op & 0x01ffffff) == 0x000c1100)
716 int gr_k = ((op >> 25) & 0x3f);
717 int ope = ((op >> 6) & 0x3f);
718 int count;
719 int i;
721 /* Is it an std or an stq? */
722 if (ope == 0x03)
723 count = 2;
724 else
725 count = 4;
727 /* Is it really a callee-saves register? */
728 if (is_callee_saves_reg (gr_k))
730 for (i = 0; i < count; i++)
732 gr_saved[gr_k + i] = 1;
733 gr_sp_offset[gr_k + i] = 4 * i;
735 last_prologue_pc = next_pc;
739 /* Adjusting the stack pointer. (The stack pointer is GR1.)
740 addi sp, S, sp
741 P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
742 0 111111 1111111 111111 000000000000 = 0x7ffff000
743 . . . . . . . .
744 We treat this as part of the prologue. */
745 else if ((op & 0x7ffff000) == 0x02401000)
747 if (framesize == 0)
749 /* Sign-extend the twelve-bit field.
750 (Isn't there a better way to do this?) */
751 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
753 framesize -= s;
754 last_prologue_pc = pc;
756 else
758 /* If the prologue is being adjusted again, we've
759 likely gone too far; i.e. we're probably in the
760 epilogue. */
761 break;
765 /* Setting the FP to a constant distance from the SP:
766 addi sp, S, fp
767 P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
768 0 111111 1111111 111111 000000000000 = 0x7ffff000
769 . . . . . . . .
770 We treat this as part of the prologue. */
771 else if ((op & 0x7ffff000) == 0x04401000)
773 /* Sign-extend the twelve-bit field.
774 (Isn't there a better way to do this?) */
775 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
776 fp_set = 1;
777 fp_offset = s;
778 last_prologue_pc = pc;
781 /* To spill an argument register to a scratch register:
782 ori GRi, 0, GRk
783 P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
784 0 000000 1111111 000000 111111111111 = 0x01fc0fff
785 . . . . . . . .
786 For the time being, we treat this as a prologue instruction,
787 assuming that GRi is an argument register. This one's kind
788 of suspicious, because it seems like it could be part of a
789 legitimate body instruction. But we only come here when the
790 source info wasn't helpful, so we have to do the best we can.
791 Hopefully once GCC and GDB agree on how to emit line number
792 info for prologues, then this code will never come into play. */
793 else if ((op & 0x01fc0fff) == 0x00880000)
795 int gr_i = ((op >> 12) & 0x3f);
797 /* Make sure that the source is an arg register; if it is, we'll
798 treat it as a prologue instruction. */
799 if (is_argument_reg (gr_i))
800 last_prologue_pc = next_pc;
803 /* To spill 16-bit values to the stack:
804 sthi GRk, @(fp, s)
805 P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
806 0 000000 1111111 111111 000000000000 = 0x01fff000
807 . . . . . . . .
808 And for 8-bit values, we use STB instructions.
809 stbi GRk, @(fp, s)
810 P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
811 0 000000 1111111 111111 000000000000 = 0x01fff000
812 . . . . . . . .
813 We check that GRk is really an argument register, and treat
814 all such as part of the prologue. */
815 else if ( (op & 0x01fff000) == 0x01442000
816 || (op & 0x01fff000) == 0x01402000)
818 int gr_k = ((op >> 25) & 0x3f);
820 /* Make sure that GRk is really an argument register; treat
821 it as a prologue instruction if so. */
822 if (is_argument_reg (gr_k))
823 last_prologue_pc = next_pc;
826 /* To save multiple callee-saves register on the stack, at a
827 non-zero offset:
829 stdi GRk, @(sp, s)
830 P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
831 0 000000 1111111 111111 000000000000 = 0x01fff000
832 . . . . . . . .
833 stqi GRk, @(sp, s)
834 P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
835 0 000000 1111111 111111 000000000000 = 0x01fff000
836 . . . . . . . .
837 We treat this as part of the prologue, and record the register's
838 saved address in the frame structure. */
839 else if ((op & 0x01fff000) == 0x014c1000
840 || (op & 0x01fff000) == 0x01501000)
842 int gr_k = ((op >> 25) & 0x3f);
843 int count;
844 int i;
846 /* Is it a stdi or a stqi? */
847 if ((op & 0x01fff000) == 0x014c1000)
848 count = 2;
849 else
850 count = 4;
852 /* Is it really a callee-saves register? */
853 if (is_callee_saves_reg (gr_k))
855 /* Sign-extend the twelve-bit field.
856 (Isn't there a better way to do this?) */
857 int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
859 for (i = 0; i < count; i++)
861 gr_saved[gr_k + i] = 1;
862 gr_sp_offset[gr_k + i] = s + (4 * i);
864 last_prologue_pc = next_pc;
868 /* Storing any kind of integer register at any constant offset
869 from any other register.
871 st GRk, @(GRi, gr0)
872 P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
873 0 000000 1111111 000000 111111 111111 = 0x01fc0fff
874 . . . . . . . .
875 sti GRk, @(GRi, d12)
876 P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
877 0 000000 1111111 000000 000000000000 = 0x01fc0000
878 . . . . . . . .
879 These could be almost anything, but a lot of prologue
880 instructions fall into this pattern, so let's decode the
881 instruction once, and then work at a higher level. */
882 else if (((op & 0x01fc0fff) == 0x000c0080)
883 || ((op & 0x01fc0000) == 0x01480000))
885 int gr_k = ((op >> 25) & 0x3f);
886 int gr_i = ((op >> 12) & 0x3f);
887 int offset;
889 /* Are we storing with gr0 as an offset, or using an
890 immediate value? */
891 if ((op & 0x01fc0fff) == 0x000c0080)
892 offset = 0;
893 else
894 offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800;
896 /* If the address isn't relative to the SP or FP, it's not a
897 prologue instruction. */
898 if (gr_i != sp_regnum && gr_i != fp_regnum)
900 /* Do nothing; not a prologue instruction. */
903 /* Saving the old FP in the new frame (relative to the SP). */
904 else if (gr_k == fp_regnum && gr_i == sp_regnum)
906 gr_saved[fp_regnum] = 1;
907 gr_sp_offset[fp_regnum] = offset;
908 last_prologue_pc = next_pc;
911 /* Saving callee-saves register(s) on the stack, relative to
912 the SP. */
913 else if (gr_i == sp_regnum
914 && is_callee_saves_reg (gr_k))
916 gr_saved[gr_k] = 1;
917 if (gr_i == sp_regnum)
918 gr_sp_offset[gr_k] = offset;
919 else
920 gr_sp_offset[gr_k] = offset + fp_offset;
921 last_prologue_pc = next_pc;
924 /* Saving the scratch register holding the return address. */
925 else if (lr_save_reg != -1
926 && gr_k == lr_save_reg)
928 lr_saved_on_stack = 1;
929 if (gr_i == sp_regnum)
930 lr_sp_offset = offset;
931 else
932 lr_sp_offset = offset + fp_offset;
933 last_prologue_pc = next_pc;
936 /* Spilling int-sized arguments to the stack. */
937 else if (is_argument_reg (gr_k))
938 last_prologue_pc = next_pc;
940 pc = next_pc;
943 if (this_frame && info)
945 int i;
946 ULONGEST this_base;
948 /* If we know the relationship between the stack and frame
949 pointers, record the addresses of the registers we noticed.
950 Note that we have to do this as a separate step at the end,
951 because instructions may save relative to the SP, but we need
952 their addresses relative to the FP. */
953 if (fp_set)
954 this_base = get_frame_register_unsigned (this_frame, fp_regnum);
955 else
956 this_base = get_frame_register_unsigned (this_frame, sp_regnum);
958 for (i = 0; i < 64; i++)
959 if (gr_saved[i])
960 info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i];
962 info->prev_sp = this_base - fp_offset + framesize;
963 info->base = this_base;
965 /* If LR was saved on the stack, record its location. */
966 if (lr_saved_on_stack)
967 info->saved_regs[lr_regnum].addr
968 = this_base - fp_offset + lr_sp_offset;
970 /* The call instruction moves the caller's PC in the callee's LR.
971 Since this is an unwind, do the reverse. Copy the location of LR
972 into PC (the address / regnum) so that a request for PC will be
973 converted into a request for the LR. */
974 info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum];
976 /* Save the previous frame's computed SP value. */
977 trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp);
980 return last_prologue_pc;
984 static CORE_ADDR
985 frv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
987 CORE_ADDR func_addr, func_end, new_pc;
989 new_pc = pc;
991 /* If the line table has entry for a line *within* the function
992 (i.e., not in the prologue, and not past the end), then that's
993 our location. */
994 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
996 struct symtab_and_line sal;
998 sal = find_pc_line (func_addr, 0);
1000 if (sal.line != 0 && sal.end < func_end)
1002 new_pc = sal.end;
1006 /* The FR-V prologue is at least five instructions long (twenty bytes).
1007 If we didn't find a real source location past that, then
1008 do a full analysis of the prologue. */
1009 if (new_pc < pc + 20)
1010 new_pc = frv_analyze_prologue (gdbarch, pc, 0, 0);
1012 return new_pc;
1016 /* Examine the instruction pointed to by PC. If it corresponds to
1017 a call to __main, return the address of the next instruction.
1018 Otherwise, return PC. */
1020 static CORE_ADDR
1021 frv_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1023 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1024 gdb_byte buf[4];
1025 unsigned long op;
1026 CORE_ADDR orig_pc = pc;
1028 if (target_read_memory (pc, buf, 4))
1029 return pc;
1030 op = extract_unsigned_integer (buf, 4, byte_order);
1032 /* In PIC code, GR15 may be loaded from some offset off of FP prior
1033 to the call instruction.
1035 Skip over this instruction if present. It won't be present in
1036 non-PIC code, and even in PIC code, it might not be present.
1037 (This is due to the fact that GR15, the FDPIC register, already
1038 contains the correct value.)
1040 The general form of the LDI is given first, followed by the
1041 specific instruction with the GRi and GRk filled in as FP and
1042 GR15.
1044 ldi @(GRi, d12), GRk
1045 P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x00c80000
1046 0 000000 1111111 000000 000000000000 = 0x01fc0000
1047 . . . . . . . .
1048 ldi @(FP, d12), GR15
1049 P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x1ec82000
1050 0 001111 1111111 000010 000000000000 = 0x7ffff000
1051 . . . . . . . . */
1053 if ((op & 0x7ffff000) == 0x1ec82000)
1055 pc += 4;
1056 if (target_read_memory (pc, buf, 4))
1057 return orig_pc;
1058 op = extract_unsigned_integer (buf, 4, byte_order);
1061 /* The format of an FRV CALL instruction is as follows:
1063 call label24
1064 P HHHHHH 0001111 LLLLLLLLLLLLLLLLLL = 0x003c0000
1065 0 000000 1111111 000000000000000000 = 0x01fc0000
1066 . . . . . . . .
1068 where label24 is constructed by concatenating the H bits with the
1069 L bits. The call target is PC + (4 * sign_ext(label24)). */
1071 if ((op & 0x01fc0000) == 0x003c0000)
1073 LONGEST displ;
1074 CORE_ADDR call_dest;
1075 struct minimal_symbol *s;
1077 displ = ((op & 0xfe000000) >> 7) | (op & 0x0003ffff);
1078 if ((displ & 0x00800000) != 0)
1079 displ |= ~((LONGEST) 0x00ffffff);
1081 call_dest = pc + 4 * displ;
1082 s = lookup_minimal_symbol_by_pc (call_dest);
1084 if (s != NULL
1085 && SYMBOL_LINKAGE_NAME (s) != NULL
1086 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0)
1088 pc += 4;
1089 return pc;
1092 return orig_pc;
1096 static struct frv_unwind_cache *
1097 frv_frame_unwind_cache (struct frame_info *this_frame,
1098 void **this_prologue_cache)
1100 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1101 struct frv_unwind_cache *info;
1103 if ((*this_prologue_cache))
1104 return (*this_prologue_cache);
1106 info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache);
1107 (*this_prologue_cache) = info;
1108 info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1110 /* Prologue analysis does the rest... */
1111 frv_analyze_prologue (gdbarch,
1112 get_frame_func (this_frame), this_frame, info);
1114 return info;
1117 static void
1118 frv_extract_return_value (struct type *type, struct regcache *regcache,
1119 gdb_byte *valbuf)
1121 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1122 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1123 int len = TYPE_LENGTH (type);
1125 if (len <= 4)
1127 ULONGEST gpr8_val;
1128 regcache_cooked_read_unsigned (regcache, 8, &gpr8_val);
1129 store_unsigned_integer (valbuf, len, byte_order, gpr8_val);
1131 else if (len == 8)
1133 ULONGEST regval;
1135 regcache_cooked_read_unsigned (regcache, 8, &regval);
1136 store_unsigned_integer (valbuf, 4, byte_order, regval);
1137 regcache_cooked_read_unsigned (regcache, 9, &regval);
1138 store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, byte_order, regval);
1140 else
1141 internal_error (__FILE__, __LINE__,
1142 _("Illegal return value length: %d"), len);
1145 static CORE_ADDR
1146 frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1148 /* Require dword alignment. */
1149 return align_down (sp, 8);
1152 static CORE_ADDR
1153 find_func_descr (struct gdbarch *gdbarch, CORE_ADDR entry_point)
1155 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1156 CORE_ADDR descr;
1157 char valbuf[4];
1158 CORE_ADDR start_addr;
1160 /* If we can't find the function in the symbol table, then we assume
1161 that the function address is already in descriptor form. */
1162 if (!find_pc_partial_function (entry_point, NULL, &start_addr, NULL)
1163 || entry_point != start_addr)
1164 return entry_point;
1166 descr = frv_fdpic_find_canonical_descriptor (entry_point);
1168 if (descr != 0)
1169 return descr;
1171 /* Construct a non-canonical descriptor from space allocated on
1172 the stack. */
1174 descr = value_as_long (value_allocate_space_in_inferior (8));
1175 store_unsigned_integer (valbuf, 4, byte_order, entry_point);
1176 write_memory (descr, valbuf, 4);
1177 store_unsigned_integer (valbuf, 4, byte_order,
1178 frv_fdpic_find_global_pointer (entry_point));
1179 write_memory (descr + 4, valbuf, 4);
1180 return descr;
1183 static CORE_ADDR
1184 frv_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
1185 struct target_ops *targ)
1187 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1188 CORE_ADDR entry_point;
1189 CORE_ADDR got_address;
1191 entry_point = get_target_memory_unsigned (targ, addr, 4, byte_order);
1192 got_address = get_target_memory_unsigned (targ, addr + 4, 4, byte_order);
1194 if (got_address == frv_fdpic_find_global_pointer (entry_point))
1195 return entry_point;
1196 else
1197 return addr;
1200 static CORE_ADDR
1201 frv_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1202 struct regcache *regcache, CORE_ADDR bp_addr,
1203 int nargs, struct value **args, CORE_ADDR sp,
1204 int struct_return, CORE_ADDR struct_addr)
1206 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1207 int argreg;
1208 int argnum;
1209 char *val;
1210 char valbuf[4];
1211 struct value *arg;
1212 struct type *arg_type;
1213 int len;
1214 enum type_code typecode;
1215 CORE_ADDR regval;
1216 int stack_space;
1217 int stack_offset;
1218 enum frv_abi abi = frv_abi (gdbarch);
1219 CORE_ADDR func_addr = find_function_addr (function, NULL);
1221 #if 0
1222 printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
1223 nargs, (int) sp, struct_return, struct_addr);
1224 #endif
1226 stack_space = 0;
1227 for (argnum = 0; argnum < nargs; ++argnum)
1228 stack_space += align_up (TYPE_LENGTH (value_type (args[argnum])), 4);
1230 stack_space -= (6 * 4);
1231 if (stack_space > 0)
1232 sp -= stack_space;
1234 /* Make sure stack is dword aligned. */
1235 sp = align_down (sp, 8);
1237 stack_offset = 0;
1239 argreg = 8;
1241 if (struct_return)
1242 regcache_cooked_write_unsigned (regcache, struct_return_regnum,
1243 struct_addr);
1245 for (argnum = 0; argnum < nargs; ++argnum)
1247 arg = args[argnum];
1248 arg_type = check_typedef (value_type (arg));
1249 len = TYPE_LENGTH (arg_type);
1250 typecode = TYPE_CODE (arg_type);
1252 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
1254 store_unsigned_integer (valbuf, 4, byte_order,
1255 value_address (arg));
1256 typecode = TYPE_CODE_PTR;
1257 len = 4;
1258 val = valbuf;
1260 else if (abi == FRV_ABI_FDPIC
1261 && len == 4
1262 && typecode == TYPE_CODE_PTR
1263 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC)
1265 /* The FDPIC ABI requires function descriptors to be passed instead
1266 of entry points. */
1267 CORE_ADDR addr = extract_unsigned_integer
1268 (value_contents (arg), 4, byte_order);
1269 addr = find_func_descr (gdbarch, addr);
1270 store_unsigned_integer (valbuf, 4, byte_order, addr);
1271 typecode = TYPE_CODE_PTR;
1272 len = 4;
1273 val = valbuf;
1275 else
1277 val = (char *) value_contents (arg);
1280 while (len > 0)
1282 int partial_len = (len < 4 ? len : 4);
1284 if (argreg < 14)
1286 regval = extract_unsigned_integer (val, partial_len, byte_order);
1287 #if 0
1288 printf(" Argnum %d data %x -> reg %d\n",
1289 argnum, (int) regval, argreg);
1290 #endif
1291 regcache_cooked_write_unsigned (regcache, argreg, regval);
1292 ++argreg;
1294 else
1296 #if 0
1297 printf(" Argnum %d data %x -> offset %d (%x)\n",
1298 argnum, *((int *)val), stack_offset,
1299 (int) (sp + stack_offset));
1300 #endif
1301 write_memory (sp + stack_offset, val, partial_len);
1302 stack_offset += align_up (partial_len, 4);
1304 len -= partial_len;
1305 val += partial_len;
1309 /* Set the return address. For the frv, the return breakpoint is
1310 always at BP_ADDR. */
1311 regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr);
1313 if (abi == FRV_ABI_FDPIC)
1315 /* Set the GOT register for the FDPIC ABI. */
1316 regcache_cooked_write_unsigned
1317 (regcache, first_gpr_regnum + 15,
1318 frv_fdpic_find_global_pointer (func_addr));
1321 /* Finally, update the SP register. */
1322 regcache_cooked_write_unsigned (regcache, sp_regnum, sp);
1324 return sp;
1327 static void
1328 frv_store_return_value (struct type *type, struct regcache *regcache,
1329 const gdb_byte *valbuf)
1331 int len = TYPE_LENGTH (type);
1333 if (len <= 4)
1335 bfd_byte val[4];
1336 memset (val, 0, sizeof (val));
1337 memcpy (val + (4 - len), valbuf, len);
1338 regcache_cooked_write (regcache, 8, val);
1340 else if (len == 8)
1342 regcache_cooked_write (regcache, 8, valbuf);
1343 regcache_cooked_write (regcache, 9, (bfd_byte *) valbuf + 4);
1345 else
1346 internal_error (__FILE__, __LINE__,
1347 _("Don't know how to return a %d-byte value."), len);
1350 static enum return_value_convention
1351 frv_return_value (struct gdbarch *gdbarch, struct value *function,
1352 struct type *valtype, struct regcache *regcache,
1353 gdb_byte *readbuf, const gdb_byte *writebuf)
1355 int struct_return = TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1356 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1357 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY;
1359 if (writebuf != NULL)
1361 gdb_assert (!struct_return);
1362 frv_store_return_value (valtype, regcache, writebuf);
1365 if (readbuf != NULL)
1367 gdb_assert (!struct_return);
1368 frv_extract_return_value (valtype, regcache, readbuf);
1371 if (struct_return)
1372 return RETURN_VALUE_STRUCT_CONVENTION;
1373 else
1374 return RETURN_VALUE_REGISTER_CONVENTION;
1377 static CORE_ADDR
1378 frv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1380 return frame_unwind_register_unsigned (next_frame, pc_regnum);
1383 /* Given a GDB frame, determine the address of the calling function's
1384 frame. This will be used to create a new GDB frame struct. */
1386 static void
1387 frv_frame_this_id (struct frame_info *this_frame,
1388 void **this_prologue_cache, struct frame_id *this_id)
1390 struct frv_unwind_cache *info
1391 = frv_frame_unwind_cache (this_frame, this_prologue_cache);
1392 CORE_ADDR base;
1393 CORE_ADDR func;
1394 struct minimal_symbol *msym_stack;
1395 struct frame_id id;
1397 /* The FUNC is easy. */
1398 func = get_frame_func (this_frame);
1400 /* Check if the stack is empty. */
1401 msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL);
1402 if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack))
1403 return;
1405 /* Hopefully the prologue analysis either correctly determined the
1406 frame's base (which is the SP from the previous frame), or set
1407 that base to "NULL". */
1408 base = info->prev_sp;
1409 if (base == 0)
1410 return;
1412 id = frame_id_build (base, func);
1413 (*this_id) = id;
1416 static struct value *
1417 frv_frame_prev_register (struct frame_info *this_frame,
1418 void **this_prologue_cache, int regnum)
1420 struct frv_unwind_cache *info
1421 = frv_frame_unwind_cache (this_frame, this_prologue_cache);
1422 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
1425 static const struct frame_unwind frv_frame_unwind = {
1426 NORMAL_FRAME,
1427 default_frame_unwind_stop_reason,
1428 frv_frame_this_id,
1429 frv_frame_prev_register,
1430 NULL,
1431 default_frame_sniffer
1434 static CORE_ADDR
1435 frv_frame_base_address (struct frame_info *this_frame, void **this_cache)
1437 struct frv_unwind_cache *info
1438 = frv_frame_unwind_cache (this_frame, this_cache);
1439 return info->base;
1442 static const struct frame_base frv_frame_base = {
1443 &frv_frame_unwind,
1444 frv_frame_base_address,
1445 frv_frame_base_address,
1446 frv_frame_base_address
1449 static CORE_ADDR
1450 frv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1452 return frame_unwind_register_unsigned (next_frame, sp_regnum);
1456 /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
1457 frame. The frame ID's base needs to match the TOS value saved by
1458 save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
1460 static struct frame_id
1461 frv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1463 CORE_ADDR sp = get_frame_register_unsigned (this_frame, sp_regnum);
1464 return frame_id_build (sp, get_frame_pc (this_frame));
1467 static struct gdbarch *
1468 frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1470 struct gdbarch *gdbarch;
1471 struct gdbarch_tdep *var;
1472 int elf_flags = 0;
1474 /* Check to see if we've already built an appropriate architecture
1475 object for this executable. */
1476 arches = gdbarch_list_lookup_by_info (arches, &info);
1477 if (arches)
1478 return arches->gdbarch;
1480 /* Select the right tdep structure for this variant. */
1481 var = new_variant ();
1482 switch (info.bfd_arch_info->mach)
1484 case bfd_mach_frv:
1485 case bfd_mach_frvsimple:
1486 case bfd_mach_fr500:
1487 case bfd_mach_frvtomcat:
1488 case bfd_mach_fr550:
1489 set_variant_num_gprs (var, 64);
1490 set_variant_num_fprs (var, 64);
1491 break;
1493 case bfd_mach_fr400:
1494 case bfd_mach_fr450:
1495 set_variant_num_gprs (var, 32);
1496 set_variant_num_fprs (var, 32);
1497 break;
1499 default:
1500 /* Never heard of this variant. */
1501 return 0;
1504 /* Extract the ELF flags, if available. */
1505 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1506 elf_flags = elf_elfheader (info.abfd)->e_flags;
1508 if (elf_flags & EF_FRV_FDPIC)
1509 set_variant_abi_fdpic (var);
1511 if (elf_flags & EF_FRV_CPU_FR450)
1512 set_variant_scratch_registers (var);
1514 gdbarch = gdbarch_alloc (&info, var);
1516 set_gdbarch_short_bit (gdbarch, 16);
1517 set_gdbarch_int_bit (gdbarch, 32);
1518 set_gdbarch_long_bit (gdbarch, 32);
1519 set_gdbarch_long_long_bit (gdbarch, 64);
1520 set_gdbarch_float_bit (gdbarch, 32);
1521 set_gdbarch_double_bit (gdbarch, 64);
1522 set_gdbarch_long_double_bit (gdbarch, 64);
1523 set_gdbarch_ptr_bit (gdbarch, 32);
1525 set_gdbarch_num_regs (gdbarch, frv_num_regs);
1526 set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs);
1528 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
1529 set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum);
1530 set_gdbarch_pc_regnum (gdbarch, pc_regnum);
1532 set_gdbarch_register_name (gdbarch, frv_register_name);
1533 set_gdbarch_register_type (gdbarch, frv_register_type);
1534 set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno);
1536 set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read);
1537 set_gdbarch_pseudo_register_write (gdbarch, frv_pseudo_register_write);
1539 set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue);
1540 set_gdbarch_skip_main_prologue (gdbarch, frv_skip_main_prologue);
1541 set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc);
1542 set_gdbarch_adjust_breakpoint_address
1543 (gdbarch, frv_adjust_breakpoint_address);
1545 set_gdbarch_return_value (gdbarch, frv_return_value);
1547 /* Frame stuff. */
1548 set_gdbarch_unwind_pc (gdbarch, frv_unwind_pc);
1549 set_gdbarch_unwind_sp (gdbarch, frv_unwind_sp);
1550 set_gdbarch_frame_align (gdbarch, frv_frame_align);
1551 frame_base_set_default (gdbarch, &frv_frame_base);
1552 /* We set the sniffer lower down after the OSABI hooks have been
1553 established. */
1555 /* Settings for calling functions in the inferior. */
1556 set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call);
1557 set_gdbarch_dummy_id (gdbarch, frv_dummy_id);
1559 /* Settings that should be unnecessary. */
1560 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1562 /* Hardware watchpoint / breakpoint support. */
1563 switch (info.bfd_arch_info->mach)
1565 case bfd_mach_frv:
1566 case bfd_mach_frvsimple:
1567 case bfd_mach_fr500:
1568 case bfd_mach_frvtomcat:
1569 /* fr500-style hardware debugging support. */
1570 var->num_hw_watchpoints = 4;
1571 var->num_hw_breakpoints = 4;
1572 break;
1574 case bfd_mach_fr400:
1575 case bfd_mach_fr450:
1576 /* fr400-style hardware debugging support. */
1577 var->num_hw_watchpoints = 2;
1578 var->num_hw_breakpoints = 4;
1579 break;
1581 default:
1582 /* Otherwise, assume we don't have hardware debugging support. */
1583 var->num_hw_watchpoints = 0;
1584 var->num_hw_breakpoints = 0;
1585 break;
1588 set_gdbarch_print_insn (gdbarch, print_insn_frv);
1589 if (frv_abi (gdbarch) == FRV_ABI_FDPIC)
1590 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
1591 frv_convert_from_func_ptr_addr);
1593 set_solib_ops (gdbarch, &frv_so_ops);
1595 /* Hook in ABI-specific overrides, if they have been registered. */
1596 gdbarch_init_osabi (info, gdbarch);
1598 /* Set the fallback (prologue based) frame sniffer. */
1599 frame_unwind_append_unwinder (gdbarch, &frv_frame_unwind);
1601 /* Enable TLS support. */
1602 set_gdbarch_fetch_tls_load_module_address (gdbarch,
1603 frv_fetch_objfile_link_map);
1605 return gdbarch;
1608 void
1609 _initialize_frv_tdep (void)
1611 register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init);