| blob | 17df8b30eb63f821c1c0db047d7d3484cd07ca1d |
1 /* 32-bit ELF support for ARM
2 Copyright (C) 1998-2024 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 #include <limits.h>
34 /* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36 #define RELOC_SECTION(HTAB, NAME) \
39 /* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41 #define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
46 /* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48 #define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
53 /* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55 #define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
60 #define elf_info_to_howto NULL
61 #define elf_info_to_howto_rel elf32_arm_info_to_howto
63 #define ARM_ELF_ABI_VERSION 0
64 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
66 /* The Adjusted Place, as defined by AAELF. */
67 #define Pa(X) ((X) & 0xfffffffc)
74 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
79 {
80 /* No relocation. */
109 /* 32 bit absolute */
124 /* standard 32bit pc-relative reloc */
139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
154 /* 16 bit absolute */
169 /* 12 bit absolute */
198 /* 8 bit absolute */
297 /* BLX instruction for the ARM. */
312 /* BLX instruction for the Thumb. */
327 /* Dynamic TLS relocations. */
371 /* Relocs used in ARM Linux */
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
894 /* Group relocations. */
1274 /* End of group relocations. */
1488 /* GNU extension to record C++ vtable member usage */
1503 /* GNU extension to record C++ vtable hierarchy */
1546 /* TLS relocations */
1659 /* 112-127 private relocations. */
1677 /* R_ARM_ME_TOO, obsolete. */
1747 /* Relocations for Armv8.1-M Mainline. */
1787 };
1789 /* 160 onwards: */
1791 {
1896 };
1898 /* 249-255 extended, currently unused, relocations: */
1900 {
1956 };
1960 {
1973 }
1975 static bool
1978 {
1983 {
1984 /* xgettext:c-format */
1989 }
1991 }
1993 struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
1997 };
1999 /* All entries in this list must also be present in elf32_arm_howto_table. */
2001 {
2102 };
2106 bfd_reloc_code_real_type code)
2107 {
2115 }
2120 {
2139 }
2141 /* Support for core dump NOTE sections. */
2143 static bool
2145 {
2150 {
2155 /* pr_cursig */
2158 /* pr_pid */
2161 /* pr_reg */
2166 }
2168 /* Make a ".reg/999" section. */
2171 }
2173 static bool
2175 {
2177 {
2188 }
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
2193 {
2199 }
2202 }
2207 {
2209 {
2214 {
2221 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2222 DIAGNOSTIC_PUSH;
2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228 #endif
2230 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2231 DIAGNOSTIC_POP;
2232 #endif
2237 }
2240 {
2259 }
2260 }
2261 }
2263 #define TARGET_LITTLE_SYM arm_elf32_le_vec
2265 #define TARGET_BIG_SYM arm_elf32_be_vec
2268 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2270 #define elf_backend_write_core_note elf32_arm_nabi_write_core_note
2275 /* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
2277 #define INTERWORK_FLAG(abfd) \
2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
2282 /* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
2285 name can be changed. The only requirement is the %s be present. */
2307 /* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2311 /* FDPIC default stack size. */
2312 #define DEFAULT_STACK_SIZE 0x8000
2315 {
2319 };
2322 {
2330 + dl_tlsdesc_lazy_resolver(GOT) */
2332 };
2334 /* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2339 /* ARM FDPIC PLT entry. */
2340 /* The last 5 words contain PLT lazy fragment code and data. */
2342 {
2353 };
2355 /* Thumb FDPIC PLT entry. */
2356 /* The last 5 words contain PLT lazy fragment code and data. */
2358 {
2369 };
2371 #ifdef FOUR_WORD_PLT
2373 /* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
2375 called before the relocation has been set up calls the dynamic
2376 linker first. */
2378 {
2383 };
2385 /* Subsequent entries in a procedure linkage table look like
2386 this. */
2388 {
2393 };
2397 /* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
2402 {
2408 };
2410 /* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2413 {
2417 };
2419 /* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2422 {
2427 };
2433 /* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2437 {
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
2442 /* add lr, pc */
2445 };
2447 /* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2450 {
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
2457 /* b .-4 */
2458 };
2460 /* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2463 {
2468 };
2470 /* The format of subsequent entries in a VxWorks executable. */
2472 {
2479 };
2481 /* The format of entries in a VxWorks shared library. */
2483 {
2490 };
2492 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2493 #define PLT_THUMB_STUB_SIZE 4
2495 {
2498 };
2500 /* The first entry in a procedure linkage table looks like
2501 this. It is set up so that any shared library function that is
2502 called before the relocation has been set up calls the dynamic
2503 linker first. */
2505 {
2506 /* First bundle: */
2511 /* Second bundle: */
2516 /* Third bundle: */
2520 /* .Lplt_tail: */
2522 /* Fourth bundle: */
2527 };
2528 #define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2530 /* Subsequent entries in a procedure linkage table look like this. */
2532 {
2537 };
2539 /* PR 28924:
2540 There was a bug due to too high values of THM_MAX_FWD_BRANCH_OFFSET and
2541 THM2_MAX_FWD_BRANCH_OFFSET. The first macro concerns the case when Thumb-2
2542 is not available, and second macro when Thumb-2 is available. Among other
2543 things, they affect the range of branches represented as BLX instructions
2544 in Encoding T2 defined in Section A8.8.25 of the ARM Architecture
2545 Reference Manual ARMv7-A and ARMv7-R edition issue C.d. Such branches are
2546 specified there to have a maximum forward offset that is a multiple of 4.
2547 Previously, the respective values defined here were multiples of 2 but not
2548 4 and they are included in comments for reference. */
2549 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2550 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2551 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) - 4 + 4)
2552 /* #def THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) - 2 + 4) */
2553 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2554 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 4) + 4)
2555 /* #def THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4) */
2556 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2557 #define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2558 #define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
2560 enum stub_insn_type
2561 {
2563 THUMB32_TYPE,
2564 ARM_TYPE,
2565 DATA_TYPE
2566 };
2568 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2569 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2570 is inserted in arm_build_one_stub(). */
2571 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2572 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2573 #define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2574 #define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
2575 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2576 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2577 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2578 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2581 {
2582 bfd_vma data;
2588 /* See note [Thumb nop sequence] when adding a veneer. */
2590 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2591 to reach the stub if necessary. */
2593 {
2596 };
2598 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2599 available. */
2601 {
2605 };
2607 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2609 {
2617 };
2619 /* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2621 {
2624 };
2626 /* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2627 M-profile architectures. */
2629 {
2633 };
2635 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2636 allowed. */
2638 {
2644 };
2646 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2647 available. */
2649 {
2654 };
2656 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2657 one, when the destination is close enough. */
2659 {
2663 };
2665 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2666 blx to reach the stub if necessary. */
2668 {
2672 };
2674 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2675 blx to reach the stub if necessary. We can not add into pc;
2676 it is not guaranteed to mode switch (different in ARMv6 and
2677 ARMv7). */
2679 {
2684 };
2686 /* V4T ARM -> ARM long branch stub, PIC. */
2688 {
2693 };
2695 /* V4T Thumb -> ARM long branch stub, PIC. */
2697 {
2703 };
2705 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2706 architectures. */
2708 {
2716 };
2718 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2719 allowed. */
2721 {
2728 };
2730 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2731 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2733 {
2737 };
2739 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2740 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2742 {
2748 };
2750 /* NaCl ARM -> ARM long branch stub. */
2752 {
2761 };
2763 /* NaCl ARM -> ARM long branch stub, PIC. */
2765 {
2774 };
2776 /* Stub used for transition to secure state (aka SG veneer). */
2778 {
2781 };
2784 /* Cortex-A8 erratum-workaround stubs. */
2786 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2787 can't use a conditional branch to reach this stub). */
2790 {
2794 };
2796 /* Stub used for b.w and bl.w instructions. */
2799 {
2801 };
2804 {
2806 };
2808 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2809 instruction (which switches to ARM mode) to point to this stub. Jump to the
2810 real destination using an ARM-mode branch. */
2813 {
2815 };
2817 /* For each section group there can be a specially created linker section
2818 to hold the stubs for that group. The name of the stub section is based
2819 upon the name of another section within that group with the suffix below
2820 applied.
2822 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2823 create what appeared to be a linker stub section when it actually
2824 contained user code/data. For example, consider this fragment:
2826 const char * stubborn_problems[] = { "np" };
2828 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2829 section called:
2831 .data.rel.local.stubborn_problems
2833 This then causes problems in arm32_arm_build_stubs() as it triggers:
2835 // Ignore non-stub sections.
2836 if (!strstr (stub_sec->name, STUB_SUFFIX))
2837 continue;
2839 And so the section would be ignored instead of being processed. Hence
2840 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2841 C identifier. */
2844 /* One entry per long/short branch stub defined above. */
2845 #define DEF_STUBS \
2846 DEF_STUB (long_branch_any_any) \
2847 DEF_STUB (long_branch_v4t_arm_thumb) \
2848 DEF_STUB (long_branch_thumb_only) \
2849 DEF_STUB (long_branch_v4t_thumb_thumb) \
2850 DEF_STUB (long_branch_v4t_thumb_arm) \
2851 DEF_STUB (short_branch_v4t_thumb_arm) \
2852 DEF_STUB (long_branch_any_arm_pic) \
2853 DEF_STUB (long_branch_any_thumb_pic) \
2854 DEF_STUB (long_branch_v4t_thumb_thumb_pic) \
2855 DEF_STUB (long_branch_v4t_arm_thumb_pic) \
2856 DEF_STUB (long_branch_v4t_thumb_arm_pic) \
2857 DEF_STUB (long_branch_thumb_only_pic) \
2858 DEF_STUB (long_branch_any_tls_pic) \
2859 DEF_STUB (long_branch_v4t_thumb_tls_pic) \
2860 DEF_STUB (long_branch_arm_nacl) \
2861 DEF_STUB (long_branch_arm_nacl_pic) \
2862 DEF_STUB (cmse_branch_thumb_only) \
2863 DEF_STUB (a8_veneer_b_cond) \
2864 DEF_STUB (a8_veneer_b) \
2865 DEF_STUB (a8_veneer_bl) \
2866 DEF_STUB (a8_veneer_blx) \
2867 DEF_STUB (long_branch_thumb2_only) \
2868 DEF_STUB (long_branch_thumb2_only_pure)
2870 #define DEF_STUB(x) arm_stub_##x,
2871 enum elf32_arm_stub_type
2872 {
2873 arm_stub_none,
2874 DEF_STUBS
2875 max_stub_type
2876 };
2877 #undef DEF_STUB
2879 /* Note the first a8_veneer type. */
2883 {
2888 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2890 {
2892 DEF_STUBS
2893 };
2895 struct elf32_arm_stub_hash_entry
2896 {
2897 /* Base hash table entry structure. */
2900 /* The stub section. */
2903 /* Offset within stub_sec of the beginning of this stub. */
2904 bfd_vma stub_offset;
2906 /* Given the symbol's value and its section we can determine its final
2907 value when building the stubs (so the stub knows where to jump). */
2908 bfd_vma target_value;
2911 /* Same as above but for the source of the branch to the stub. Used for
2912 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2913 such, source section does not need to be recorded since Cortex-A8 erratum
2914 workaround stubs are only generated when both source and target are in the
2915 same section. */
2916 bfd_vma source_value;
2918 /* The instruction which caused this stub to be generated (only valid for
2919 Cortex-A8 erratum workaround stubs at present). */
2922 /* The stub type. */
2924 /* Its encoding size in bytes. */
2926 /* Its template. */
2928 /* The size of the template (number of entries). */
2931 /* The symbol table entry, if any, that this was derived from. */
2934 /* Type of branch. */
2937 /* Where this stub is being called from, or, in the case of combined
2938 stub sections, the first input section in the group. */
2941 /* The name for the local symbol at the start of this stub. The
2942 stub name in the hash table has to be unique; this does not, so
2943 it can be friendlier. */
2945 };
2947 /* Used to build a map of a section. This is required for mixed-endian
2948 code/data. */
2951 {
2952 bfd_vma vma;
2954 }
2955 elf32_arm_section_map;
2957 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2960 {
2961 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2962 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2963 VFP11_ERRATUM_ARM_VENEER,
2964 VFP11_ERRATUM_THUMB_VENEER
2965 }
2966 elf32_vfp11_erratum_type;
2969 {
2971 bfd_vma vma;
2972 union
2973 {
2974 struct
2975 {
2979 struct
2980 {
2985 elf32_vfp11_erratum_type type;
2986 }
2987 elf32_vfp11_erratum_list;
2989 /* Information about a STM32L4XX erratum veneer, or a branch to such a
2990 veneer. */
2992 {
2993 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2994 STM32L4XX_ERRATUM_VENEER
2995 }
2996 elf32_stm32l4xx_erratum_type;
2999 {
3001 bfd_vma vma;
3002 union
3003 {
3004 struct
3005 {
3009 struct
3010 {
3015 elf32_stm32l4xx_erratum_type type;
3016 }
3017 elf32_stm32l4xx_erratum_list;
3020 {
3021 DELETE_EXIDX_ENTRY,
3022 INSERT_EXIDX_CANTUNWIND_AT_END
3023 }
3024 arm_unwind_edit_type;
3026 /* A (sorted) list of edits to apply to an unwind table. */
3028 {
3029 arm_unwind_edit_type type;
3030 /* Note: we sometimes want to insert an unwind entry corresponding to a
3031 section different from the one we're currently writing out, so record the
3032 (text) section this edit relates to here. */
3036 }
3037 arm_unwind_table_edit;
3040 {
3041 /* Information about mapping symbols. */
3046 /* Information about CPU errata. */
3052 /* Information about unwind tables. */
3053 union
3054 {
3055 /* Unwind info attached to a text section. */
3056 struct
3057 {
3061 /* Unwind info attached to an .ARM.exidx section. */
3062 struct
3063 {
3068 }
3069 _arm_elf_section_data;
3071 #define elf32_arm_section_data(sec) \
3072 ((_arm_elf_section_data *) elf_section_data (sec))
3074 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3075 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3076 so may be created multiple times: we use an array of these entries whilst
3077 relaxing which we can refresh easily, then create stubs for each potentially
3078 erratum-triggering instruction once we've settled on a solution. */
3080 struct a8_erratum_fix
3081 {
3084 bfd_vma offset;
3085 bfd_vma target_offset;
3090 };
3092 /* A table of relocs applied to branches which might trigger Cortex-A8
3093 erratum. */
3095 struct a8_erratum_reloc
3096 {
3097 bfd_vma from;
3098 bfd_vma destination;
3104 };
3106 /* The size of the thread control block. */
3107 #define TCB_SIZE 8
3109 /* ARM-specific information about a PLT entry, over and above the usual
3110 gotplt_union. */
3111 struct arm_plt_info
3112 {
3113 /* We reference count Thumb references to a PLT entry separately,
3114 so that we can emit the Thumb trampoline only if needed. */
3115 bfd_signed_vma thumb_refcount;
3117 /* Some references from Thumb code may be eliminated by BL->BLX
3118 conversion, so record them separately. */
3119 bfd_signed_vma maybe_thumb_refcount;
3121 /* How many of the recorded PLT accesses were from non-call relocations.
3122 This information is useful when deciding whether anything takes the
3123 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3124 non-call references to the function should resolve directly to the
3125 real runtime target. */
3128 /* Since PLT entries have variable size if the Thumb prologue is
3129 used, we need to record the index into .got.plt instead of
3130 recomputing it from the PLT offset. */
3131 bfd_signed_vma got_offset;
3132 };
3134 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
3135 struct arm_local_iplt_info
3136 {
3137 /* The information that is usually found in the generic ELF part of
3138 the hash table entry. */
3141 /* The information that is usually found in the ARM-specific part of
3142 the hash table entry. */
3145 /* A list of all potential dynamic relocations against this symbol. */
3147 };
3149 /* Structure to handle FDPIC support for local functions. */
3150 struct fdpic_local
3151 {
3155 };
3157 struct elf_arm_obj_tdata
3158 {
3161 /* Zero to warn when linking objects with incompatible enum sizes. */
3164 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3167 /* The number of entries in each of the arrays in this strcuture.
3168 Used to avoid buffer overruns. */
3169 bfd_size_type num_entries;
3171 /* tls_type for each local got entry. */
3174 /* GOTPLT entries for TLS descriptors. */
3177 /* Information for local symbols that need entries in .iplt. */
3180 /* Maintains FDPIC counters and funcdesc info. */
3182 };
3184 #define elf_arm_tdata(bfd) \
3185 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
3187 #define elf32_arm_num_entries(bfd) \
3188 (elf_arm_tdata (bfd)->num_entries)
3190 #define elf32_arm_local_got_tls_type(bfd) \
3191 (elf_arm_tdata (bfd)->local_got_tls_type)
3193 #define elf32_arm_local_tlsdesc_gotent(bfd) \
3194 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3196 #define elf32_arm_local_iplt(bfd) \
3197 (elf_arm_tdata (bfd)->local_iplt)
3199 #define elf32_arm_local_fdpic_cnts(bfd) \
3200 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3202 #define is_arm_elf(bfd) \
3203 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3204 && elf_tdata (bfd) != NULL \
3205 && elf_object_id (bfd) == ARM_ELF_DATA)
3207 static bool
3209 {
3211 ARM_ELF_DATA);
3212 }
3214 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3216 /* Structure to handle FDPIC support for extern functions. */
3223 };
3225 /* Arm ELF linker hash entry. */
3226 struct elf32_arm_link_hash_entry
3227 {
3230 /* ARM-specific PLT information. */
3233 #define GOT_UNKNOWN 0
3234 #define GOT_NORMAL 1
3235 #define GOT_TLS_GD 2
3236 #define GOT_TLS_IE 4
3237 #define GOT_TLS_GDESC 8
3238 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
3241 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3246 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3247 starting at the end of the jump table. */
3248 bfd_vma tlsdesc_got;
3250 /* The symbol marking the real symbol location for exported thumb
3251 symbols with Arm stubs. */
3254 /* A pointer to the most recently used stub hash entry against this
3255 symbol. */
3258 /* Counter for FDPIC relocations against this symbol. */
3260 };
3262 /* Traverse an arm ELF linker hash table. */
3263 #define elf32_arm_link_hash_traverse(table, func, info) \
3264 (elf_link_hash_traverse \
3265 (&(table)->root, \
3266 (bool (*) (struct elf_link_hash_entry *, void *)) (func), \
3267 (info)))
3269 /* Get the ARM elf linker hash table from a link_info structure. */
3270 #define elf32_arm_hash_table(p) \
3271 ((is_elf_hash_table ((p)->hash) \
3272 && elf_hash_table_id (elf_hash_table (p)) == ARM_ELF_DATA) \
3273 ? (struct elf32_arm_link_hash_table *) (p)->hash : NULL)
3275 #define arm_stub_hash_lookup(table, string, create, copy) \
3276 ((struct elf32_arm_stub_hash_entry *) \
3277 bfd_hash_lookup ((table), (string), (create), (copy)))
3279 /* Array to keep track of which stub sections have been created, and
3280 information on stub grouping. */
3281 struct map_stub
3282 {
3283 /* This is the section to which stubs in the group will be
3284 attached. */
3286 /* The stub section. */
3288 };
3290 #define elf32_arm_compute_jump_table_size(htab) \
3291 ((htab)->next_tls_desc_index * 4)
3293 /* ARM ELF linker hash table. */
3294 struct elf32_arm_link_hash_table
3295 {
3296 /* The main hash table. */
3299 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3300 bfd_size_type thumb_glue_size;
3302 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3303 bfd_size_type arm_glue_size;
3305 /* The size in bytes of section containing the ARMv4 BX veneers. */
3306 bfd_size_type bx_glue_size;
3308 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3309 veneer has been populated. */
3312 /* The size in bytes of the section containing glue for VFP11 erratum
3313 veneers. */
3314 bfd_size_type vfp11_erratum_glue_size;
3316 /* The size in bytes of the section containing glue for STM32L4XX erratum
3317 veneers. */
3318 bfd_size_type stm32l4xx_erratum_glue_size;
3320 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3321 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3322 elf32_arm_write_section(). */
3326 /* An arbitrary input BFD chosen to hold the glue sections. */
3329 /* Nonzero to output a BE8 image. */
3332 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3333 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3336 /* The relocation to use for R_ARM_TARGET2 relocations. */
3339 /* 0 = Ignore R_ARM_V4BX.
3340 1 = Convert BX to MOV PC.
3341 2 = Generate v4 interworing stubs. */
3344 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3347 /* Whether we should fix the ARM1176 BLX immediate issue. */
3350 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3353 /* What sort of code sequences we should look for which may trigger the
3354 VFP11 denorm erratum. */
3355 bfd_arm_vfp11_fix vfp11_fix;
3357 /* Global counter for the number of fixes we have emitted. */
3360 /* What sort of code sequences we should look for which may trigger the
3361 STM32L4XX erratum. */
3362 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3364 /* Global counter for the number of fixes we have emitted. */
3367 /* Nonzero to force PIC branch veneers. */
3370 /* The number of bytes in the initial entry in the PLT. */
3371 bfd_size_type plt_header_size;
3373 /* The number of bytes in the subsequent PLT etries. */
3374 bfd_size_type plt_entry_size;
3376 /* True if the target uses REL relocations. */
3379 /* Nonzero if import library must be a secure gateway import library
3380 as per ARMv8-M Security Extensions. */
3383 /* The import library whose symbols' address must remain stable in
3384 the import library generated. */
3387 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3388 bfd_vma next_tls_desc_index;
3390 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3391 bfd_vma num_tls_desc;
3393 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3396 /* Offset in .plt section of tls_arm_trampoline. */
3397 bfd_vma tls_trampoline;
3399 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
3400 union
3401 {
3402 bfd_signed_vma refcount;
3403 bfd_vma offset;
3406 /* For convenience in allocate_dynrelocs. */
3409 /* The amount of space used by the reserved portion of the sgotplt
3410 section, plus whatever space is used by the jump slots. */
3411 bfd_vma sgotplt_jump_table_size;
3413 /* The stub hash table. */
3416 /* Linker stub bfd. */
3419 /* Linker call-backs. */
3424 /* Array to keep track of which stub sections have been created, and
3425 information on stub grouping. */
3428 /* Input stub section holding secure gateway veneers. */
3431 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3432 start to be allocated. */
3433 bfd_vma new_cmse_stub_offset;
3435 /* Number of elements in stub_group. */
3438 /* Assorted information used by elf32_arm_size_stubs. */
3443 /* True if the target system uses FDPIC. */
3446 /* Fixup section. Used for FDPIC. */
3448 };
3450 /* Add an FDPIC read-only fixup. */
3451 static void
3453 {
3454 bfd_vma fixup_offset;
3459 }
3463 {
3464 #if GCC_VERSION >= 3004
3466 #else
3470 {
3474 }
3476 #endif
3477 }
3481 {
3482 #if GCC_VERSION >= 3004
3484 #else
3489 {
3491 sum++;
3493 }
3495 #endif
3496 }
3501 static void
3507 bfd_vma addr,
3508 bfd_vma dynreloc_value,
3509 bfd_vma seg)
3510 {
3512 {
3517 {
3519 Elf_Internal_Rela outrel;
3528 }
3529 else
3530 {
3544 }
3546 }
3547 }
3549 /* Create an entry in an ARM ELF linker hash table. */
3555 {
3559 /* Allocate the structure if it has not already been allocated by a
3560 subclass. */
3567 /* Call the allocation method of the superclass. */
3572 {
3589 }
3592 }
3594 /* Ensure that we have allocated bookkeeping structures for ABFD's local
3595 symbols. */
3597 static bool
3599 {
3601 {
3602 bfd_size_type num_syms;
3606 /* Whilst it might be tempting to allocate a single block of memory and
3607 then divide it up amoungst the arrays in the elf_arm_obj_tdata
3608 structure, this interferes with the work of memory checkers looking
3609 for buffer overruns. So allocate each array individually. */
3645 #if GCC_VERSION >= 3000
3654 #endif
3655 }
3657 }
3659 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
3660 to input bfd ABFD. Create the information if it doesn't already exist.
3661 Return null if an allocation fails. */
3665 {
3677 }
3679 /* Try to obtain PLT information for the symbol with index R_SYMNDX
3680 in ABFD's symbol table. If the symbol is global, H points to its
3681 hash table entry, otherwise H is null.
3683 Return true if the symbol does have PLT information. When returning
3684 true, point *ROOT_PLT at the target-independent reference count/offset
3685 union and *ARM_PLT at the ARM-specific information. */
3687 static bool
3692 {
3699 {
3703 }
3718 }
3722 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3723 before it. */
3725 static bool
3728 {
3735 }
3737 /* Return a pointer to the head of the dynamic reloc list that should
3738 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3739 ABFD's symbol table. Return null if an error occurs. */
3744 {
3746 {
3753 }
3754 else
3755 {
3756 /* Track dynamic relocs needed for local syms too.
3757 We really need local syms available to do this
3758 easily. Oh well. */
3768 }
3769 }
3771 /* Initialize an entry in the stub hash table. */
3777 {
3778 /* Allocate the structure if it has not already been allocated by a
3779 subclass. */
3781 {
3786 }
3788 /* Call the allocation method of the superclass. */
3791 {
3794 /* Initialize the local fields. */
3809 }
3812 }
3814 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3815 shortcuts to them in our hash table. */
3817 static bool
3819 {
3829 /* Also create .rofixup. */
3831 {
3838 }
3841 }
3843 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3845 static bool
3847 {
3852 flagword flags;
3860 {
3867 }
3870 {
3878 }
3881 {
3887 }
3889 }
3891 /* Determine if we're dealing with a Thumb only architecture. */
3893 static bool
3895 {
3898 Tag_CPU_arch_profile);
3905 /* Force return logic to be reviewed for each new architecture. */
3917 }
3919 /* Determine if we're dealing with a Thumb-2 object. */
3921 static bool
3923 {
3926 Tag_THUMB_ISA_use);
3928 /* No use of thumb permitted, or a legacy thumb-1/2 definition. */
3932 /* Variant of thumb is described by the architecture tag. */
3935 /* Force return logic to be reviewed for each new architecture. */
3945 }
3947 /* Determine whether Thumb-2 BL instruction is available. */
3949 static bool
3951 {
3955 /* Force return logic to be reviewed for each new architecture. */
3958 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3961 }
3963 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3964 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3965 hash table. */
3967 static bool
3969 {
3983 {
3988 {
3990 htab->plt_entry_size
3992 }
3993 else
3994 {
3995 htab->plt_header_size
3997 htab->plt_entry_size
3999 }
4003 }
4004 else
4005 {
4006 /* PR ld/16017
4007 Test for thumb only architectures. Note - we cannot just call
4008 using_thumb_only() as the attributes in the output bfd have not been
4009 initialised at this point, so instead we use the input bfd. */
4014 {
4017 }
4019 }
4025 else
4027 }
4036 }
4038 /* Copy the extra info we tack onto an elf_link_hash_entry. */
4040 static void
4044 {
4051 {
4052 /* Copy over PLT info. */
4060 /* Copy FDPIC counters. */
4065 /* We should only allocate a function to .iplt once the final
4066 symbol information is known. */
4070 {
4073 }
4074 }
4077 }
4079 /* Destroy an ARM elf linker hash table. */
4081 static void
4083 {
4089 }
4091 /* Create an ARM elf linker hash table. */
4095 {
4104 elf32_arm_link_hash_newfunc,
4106 ARM_ELF_DATA))
4107 {
4110 }
4114 #ifdef FOUR_WORD_PLT
4117 #else
4120 #endif
4127 {
4130 }
4134 }
4136 /* Determine what kind of NOPs are available. */
4138 static bool
4140 {
4142 Tag_CPU_arch);
4144 /* Force return logic to be reviewed for each new architecture. */
4153 }
4155 static bool
4157 {
4159 {
4176 }
4177 }
4179 /* Determine the type of stub needed, if any, for a call. */
4181 static enum elf32_arm_stub_type
4188 bfd_vma destination,
4192 {
4193 bfd_vma location;
4194 bfd_signed_vma branch_offset;
4219 /* True for architectures that implement the thumb2 movw instruction. */
4222 /* Determine where the call point is. */
4229 /* Don't pretend we know what stub to use (if any) when we target a
4230 Thumb-only target and we don't know the actual destination
4231 type. */
4235 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4236 are considering a function call relocation. */
4240 {
4242 /* As an exception, assume that absolute symbols are of the
4243 right kind (Thumb). They are presumably defined in the
4244 linker script, where it is not possible to declare them as
4245 Thumb (and thus are seen as Arm mode). We'll inform the
4246 user with a warning, though, in
4247 elf32_arm_final_link_relocate. */
4249 else
4250 /* Otherwise do not silently build a stub, and let the users
4251 know they have to fix their code. Indeed, we could decide
4252 to insert a stub involving Arm code and/or BLX, leading to
4253 a run-time crash. */
4255 }
4257 /* For TLS call relocs, it is the caller's responsibility to provide
4258 the address of the appropriate trampoline. */
4265 {
4270 else
4273 {
4276 /* Note when dealing with PLT entries: the main PLT stub is in
4277 ARM mode, so if the branch is in Thumb mode, another
4278 Thumb->ARM stub will be inserted later just before the ARM
4279 PLT stub. If a long branch stub is needed, we'll add a
4280 Thumb->Arm one and branch directly to the ARM PLT entry.
4281 Here, we have to check if a pre-PLT Thumb->ARM stub
4282 is needed and if it will be close enough. */
4289 /* Thumb branch/call to PLT: it can become a branch to ARM
4290 or to Thumb. We must perform the same checks and
4291 corrections as in elf32_arm_final_link_relocate. */
4294 {
4298 {
4299 /* If the Thumb BLX instruction is available, convert
4300 the BL to a BLX instruction to call the ARM-mode
4301 PLT entry. */
4303 }
4304 else
4305 {
4307 /* Target the Thumb stub before the ARM PLT entry. */
4310 }
4311 }
4312 else
4313 {
4315 }
4316 }
4317 }
4318 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4325 {
4326 /* Handle cases where:
4327 - this call goes too far (different Thumb/Thumb2 max
4328 distance)
4329 - it's a Thumb->Arm call and blx is not available, or it's a
4330 Thumb->Arm branch (not bl). A stub is needed in this case,
4331 but only if this call is not through a PLT entry. Indeed,
4332 PLT stubs handle mode switching already. */
4336 || (thumb2_bl
4339 || (thumb2
4349 {
4350 /* If we need to insert a Thumb-Thumb long branch stub to a
4351 PLT, use one that branches directly to the ARM PLT
4352 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4353 stub, undo this now. */
4355 {
4358 }
4361 {
4362 /* Thumb to thumb. */
4364 {
4366 _bfd_error_handler
4368 " section with SHF_ARM_PURECODE section"
4369 " attribute is only supported for M-profile"
4374 /* PIC stubs. */
4377 /* V5T and above. Stub starts with ARM code, so
4378 we must be able to switch mode before
4379 reaching it, which is only possible for 'bl'
4380 (ie R_ARM_THM_CALL relocation). */
4381 ? arm_stub_long_branch_any_thumb_pic
4382 /* On V4T, use Thumb code only. */
4385 /* non-PIC stubs. */
4388 /* V5T and above. */
4389 ? arm_stub_long_branch_any_any
4390 /* V4T. */
4392 }
4393 else
4394 {
4397 else
4398 {
4400 _bfd_error_handler
4402 " section with SHF_ARM_PURECODE section"
4403 " attribute is only supported for M-profile"
4408 /* PIC stub. */
4409 ? arm_stub_long_branch_thumb_only_pic
4410 /* non-PIC stub. */
4413 }
4414 }
4415 }
4416 else
4417 {
4419 _bfd_error_handler
4421 " section with SHF_ARM_PURECODE section"
4426 /* Thumb to arm. */
4430 {
4431 _bfd_error_handler
4435 }
4437 stub_type =
4439 /* PIC stubs. */
4441 /* TLS PIC stubs. */
4445 /* V5T PIC and above. */
4446 ? arm_stub_long_branch_any_arm_pic
4447 /* V4T PIC stub. */
4450 /* non-PIC stubs. */
4452 /* V5T and above. */
4453 ? arm_stub_long_branch_any_any
4454 /* V4T. */
4457 /* Handle v4t short branches. */
4462 }
4463 }
4464 }
4469 {
4471 _bfd_error_handler
4473 " section with SHF_ARM_PURECODE section"
4474 " attribute is only supported for M-profile"
4478 {
4479 /* Arm to thumb. */
4484 {
4485 _bfd_error_handler
4489 }
4491 /* We have an extra 2-bytes reach because of
4492 the mode change (bit 24 (H) of BLX encoding). */
4498 {
4500 /* PIC stubs. */
4502 /* V5T and above. */
4503 ? arm_stub_long_branch_any_thumb_pic
4504 /* V4T stub. */
4507 /* non-PIC stubs. */
4509 /* V5T and above. */
4510 ? arm_stub_long_branch_any_any
4511 /* V4T. */
4513 }
4514 }
4515 else
4516 {
4517 /* Arm to arm. */
4520 {
4521 stub_type =
4523 /* PIC stubs. */
4525 /* TLS PIC Stub. */
4526 ? arm_stub_long_branch_any_tls_pic
4528 ? arm_stub_long_branch_arm_nacl_pic
4530 /* non-PIC stubs. */
4532 ? arm_stub_long_branch_arm_nacl
4534 }
4535 }
4536 }
4538 /* If a stub is needed, record the actual destination type. */
4543 }
4545 /* Build a name for an entry in the stub hash table. */
4553 {
4555 bfd_size_type len;
4558 {
4567 }
4568 else
4569 {
4581 }
4584 }
4586 /* Look up an entry in the stub hash. Stub entries are cached because
4587 creating the stub name takes a bit of time. */
4596 {
4604 /* If the input section is the CMSE stubs one and it needs a long
4605 branch stub to reach it's final destination, give up with an
4606 error message: this is not supported. See PR ld/24709. */
4608 {
4614 CMSE_STUB_NAME,
4620 /* Exit, rather than leave incompletely processed
4621 relocations. */
4623 }
4625 /* If this input section is part of a group of sections sharing one
4626 stub section, then use the id of the first section in the group.
4627 Stub names need to include a section id, as there may well be
4628 more than one stub used to reach say, printf, and we need to
4629 distinguish between them. */
4637 {
4639 }
4640 else
4641 {
4654 }
4657 }
4659 /* Whether veneers of type STUB_TYPE require to be in a dedicated output
4660 section. */
4662 static bool
4664 {
4669 {
4675 }
4678 }
4680 /* Required alignment (as a power of 2) for the dedicated section holding
4681 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4682 with input sections. */
4684 static int
4685 arm_dedicated_stub_output_section_required_alignment
4687 {
4692 {
4693 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4694 boundary. */
4701 }
4704 }
4706 /* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4707 NULL if veneers of this type are interspersed with input sections. */
4711 {
4716 {
4723 }
4726 }
4728 /* If veneers of type STUB_TYPE should go in a dedicated output section,
4729 returns the address of the hash table field in HTAB holding a pointer to the
4730 corresponding input section. Otherwise, returns NULL. */
4735 {
4740 {
4747 }
4750 }
4752 /* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4753 is the section that branch into veneer and can be NULL if stub should go in
4754 a dedicated output section. Returns a pointer to the stub section, and the
4755 section to which the stub section will be attached (in *LINK_SEC_P).
4756 LINK_SEC_P may be NULL. */
4762 {
4770 {
4780 {
4784 }
4785 }
4786 else
4787 {
4797 }
4800 {
4802 bfd_size_type len;
4814 align);
4821 }
4830 }
4832 /* Add a new stub entry to the stub hash. Not all fields of the new
4833 stub entry are initialised. */
4839 {
4845 stub_type);
4849 /* Enter this entry into the linker stub hash table. */
4853 {
4859 }
4866 }
4868 /* Store an Arm insn into an output section not processed by
4869 elf32_arm_write_section. */
4871 static void
4874 {
4877 else
4879 }
4881 /* Store a 16-bit Thumb insn into an output section not processed by
4882 elf32_arm_write_section. */
4884 static void
4887 {
4890 else
4892 }
4894 /* Store a Thumb2 insn into an output section not processed by
4895 elf32_arm_write_section. */
4897 static void
4900 {
4901 /* T2 instructions are 16-bit streamed. */
4903 {
4906 }
4907 else
4908 {
4911 }
4912 }
4914 /* If it's possible to change R_TYPE to a more efficient access
4915 model, return the new reloc type. */
4917 static unsigned
4920 {
4927 /* We do not support relaxations for Old TLS models. */
4929 {
4936 }
4939 }
4941 static bfd_reloc_status_type elf32_arm_final_link_relocate
4947 static unsigned int
4949 {
4951 {
4983 }
4984 }
4986 /* Returns whether stubs of type STUB_TYPE take over the symbol they are
4987 veneering (TRUE) or have their own symbol (FALSE). */
4989 static bool
4991 {
4996 {
5002 }
5005 }
5007 /* Returns the padding needed for the dedicated section used stubs of type
5008 STUB_TYPE. */
5010 static int
5012 {
5017 {
5023 }
5026 }
5028 /* If veneers of type STUB_TYPE should go in a dedicated output section,
5029 returns the address of the hash table field in HTAB holding the offset at
5030 which new veneers should be layed out in the stub section. */
5035 {
5037 {
5044 }
5045 }
5047 static bool
5050 {
5051 #define MAXRELOCS 3
5059 bfd_vma sym_value;
5069 /* Massage our args to the form they really have. */
5073 /* Fail if the target section could not be assigned to an output
5074 section. The user should fix his linker script. */
5089 /* We have to do less-strictly-aligned fixes last. */
5092 /* Assign a slot at the end of section if none assigned yet. */
5094 {
5097 }
5102 /* This is the address of the stub destination. */
5112 {
5114 {
5116 {
5119 {
5120 /* We've borrowed the reloc_addend field to mean we should
5121 insert a condition code into this (Thumb-1 branch)
5122 instruction. See THUMB16_BCOND_INSN. */
5125 }
5128 }
5138 {
5141 }
5148 /* Handle cases where the target is encoded within the
5149 instruction. */
5151 {
5154 }
5168 }
5169 }
5174 /* Stub size has already been computed in arm_size_one_stub. Check
5175 consistency. */
5178 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
5182 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5183 to relocate in each stub. */
5184 removed_sg_veneer =
5189 {
5190 Elf_Internal_Rela rel;
5193 bfd_vma points_to =
5202 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5203 template should refer back to the instruction after the original
5204 branch. We use target_section as Cortex-A8 erratum workaround stubs
5205 are only generated when both source and target are in the same
5206 section. */
5218 }
5221 #undef MAXRELOCS
5222 }
5224 /* Calculate the template, template size and instruction size for a stub.
5225 Return value is the instruction size. */
5227 static unsigned int
5231 {
5246 {
5248 {
5262 }
5263 }
5266 }
5268 /* As above, but don't actually build the stub. Just bump offset so
5269 we know stub section sizes. */
5271 static bool
5274 {
5279 /* Massage our args to the form they really have. */
5288 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5290 {
5294 }
5296 /* Already accounted for. */
5304 }
5306 /* External entry points for sizing and building linker stubs. */
5308 /* Set up various things so that we can make a list of input sections
5309 for each output section included in the link. Returns -1 on error,
5310 0 when no stubs will be needed, and 1 on success. */
5312 int
5315 {
5327 /* Count the number of input BFDs and find the top input section id. */
5331 {
5336 {
5339 }
5340 }
5349 /* We can't use output_bfd->section_count here to find the top output
5350 section index as some sections may have been removed, and
5351 _bfd_strip_section_from_output doesn't renumber the indices. */
5355 {
5358 }
5367 /* For sections we aren't interested in, mark their entries with a
5368 value we can check later. */
5370 do
5377 {
5380 }
5383 }
5385 /* The linker repeatedly calls this function for each input section,
5386 in the order that input sections are linked into output sections.
5387 Build lists of input sections to determine groupings between which
5388 we may insert linker stubs. */
5390 void
5393 {
5400 {
5404 {
5405 /* Steal the link_sec pointer for our list. */
5406 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5407 /* This happens to make the list in reverse order,
5408 which we reverse later. */
5411 }
5412 }
5413 }
5415 /* See whether we can group stub sections together. Grouping stub
5416 sections may result in fewer stubs. More importantly, we need to
5417 put all .init* and .fini* stubs at the end of the .init or
5418 .fini output sections respectively, because glibc splits the
5419 _init and _fini functions into multiple parts. Putting a stub in
5420 the middle of a function is not a good idea. */
5422 static void
5424 bfd_size_type stub_group_size,
5426 {
5429 do
5430 {
5437 /* Reverse the list: we must avoid placing stubs at the
5438 beginning of the section because the beginning of the text
5439 section may be required for an interrupt vector in bare metal
5440 code. */
5441 #define NEXT_SEC PREV_SEC
5444 {
5445 /* Pop from tail. */
5449 /* Push on head. */
5452 }
5455 {
5459 bfd_vma end_of_next;
5463 {
5467 /* End of NEXT is too far from start, so stop. */
5469 /* Add NEXT to the group. */
5471 }
5473 /* OK, the size from the start to the start of CURR is less
5474 than stub_group_size and thus can be handled by one stub
5475 section. (Or the head section is itself larger than
5476 stub_group_size, in which case we may be toast.)
5477 We should really be keeping track of the total size of
5478 stubs added here, as stubs contribute to the final output
5479 section size. */
5480 do
5481 {
5483 /* Set up this stub group. */
5485 }
5488 /* But wait, there's more! Input sections up to stub_group_size
5489 bytes after the stub section can be handled by it too. */
5491 {
5495 {
5498 /* End of NEXT is too far from stubs, so stop. */
5500 /* Add NEXT to the stub group. */
5504 }
5505 }
5507 }
5508 }
5512 #undef PREV_SEC
5513 #undef NEXT_SEC
5514 }
5516 /* Comparison function for sorting/searching relocations relating to Cortex-A8
5517 erratum fix. */
5519 static int
5521 {
5529 else
5531 }
5536 /* Helper function to scan code for sequences which might trigger the Cortex-A8
5537 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
5538 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
5539 otherwise. */
5541 static bool
5551 {
5564 {
5568 bfd_vma base_vma;
5587 {
5598 /* Span is entirely within a single 4KB region: skip scanning. */
5603 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5605 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5606 * The branch target is in the same 4KB region as the
5607 first half of the branch.
5608 * The instruction before the branch is a 32-bit
5609 length non-branch instruction. */
5611 {
5620 {
5621 /* Load the rest of the insn (in manual-friendly order). */
5624 /* Encoding T4: B<c>.W. */
5626 /* Encoding T1: BL<c>.W. */
5628 /* Encoding T2: BLX<c>.W. */
5630 /* Encoding T3: B<c>.W (not permitted in IT block). */
5633 }
5638 && insn_32bit
5639 && is_32bit_branch
5640 && last_was_32bit
5642 {
5646 bfd_vma target;
5658 {
5662 /* We don't care about the error returned from this
5663 function, only if there is glue or not. */
5670 /* Keep a simpler condition, for the sake of clarity. */
5676 {
5680 else
5682 }
5683 }
5685 /* Check if we have an offending branch instruction. */
5688 /* We've already made a stub for this instruction, e.g.
5689 it's a long branch or a Thumb->ARM stub. Assume that
5690 stub will suffice to work around the A8 erratum (see
5691 setting of always_after_branch above). */
5692 ;
5694 {
5703 }
5705 {
5725 }
5728 {
5731 /* The original instruction is a BL, but the target is
5732 an ARM instruction. If we were not making a stub,
5733 the BL would have been converted to a BLX. Use the
5734 BLX stub instead in that case. */
5737 {
5741 }
5742 /* Conversely, if the original instruction was
5743 BLX but the target is Thumb mode, use the BL
5744 stub. */
5747 {
5751 }
5756 /* If we found a relocation, use the proper destination,
5757 not the offset in the (unrelocated) instruction.
5758 Note this is always done if we switched the stub type
5759 above. */
5761 offset =
5764 /* If the stub will use a Thumb-mode branch to a
5765 PLT target, redirect it to the preceding Thumb
5766 entry point. */
5772 /* The BLX stub is ARM-mode code. Adjust the offset to
5773 take the different PC value (+8 instead of +4) into
5774 account. */
5779 {
5783 {
5789 }
5792 {
5793 /* If we're doing a subsequent scan,
5794 check if we've found the same fix as
5795 before, and try and reuse the stub
5796 name. */
5800 {
5804 }
5805 }
5808 {
5812 }
5825 num_a8_fixes++;
5826 }
5827 }
5828 }
5833 }
5834 }
5838 }
5845 }
5847 /* Create or update a stub entry depending on whether the stub can already be
5848 found in HTAB. The stub is identified by:
5849 - its type STUB_TYPE
5850 - its source branch (note that several can share the same stub) whose
5851 section and relocation (if any) are given by SECTION and IRELA
5852 respectively
5853 - its target symbol whose input section, hash, name, value and branch type
5854 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5855 respectively
5857 If found, the value of the stub's target symbol is updated from SYM_VALUE
5858 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5859 TRUE and the stub entry is initialized.
5861 Returns the stub that was created or updated, or NULL if an error
5862 occurred. */
5871 {
5883 else
5884 {
5889 /* Support for grouping stub sections. */
5892 /* Get the name of this stub. */
5894 stub_type);
5897 }
5901 /* The proper stub has already been created, just update its value. */
5903 {
5908 }
5912 {
5916 }
5926 else
5927 {
5934 {
5937 }
5939 /* For historical reasons, use the existing names for ARM-to-Thumb and
5940 Thumb-to-ARM stubs. */
5951 else
5953 }
5957 }
5959 /* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5960 gateway veneer to transition from non secure to secure state and create them
5961 accordingly.
5963 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5964 defines the conditions that govern Secure Gateway veneer creation for a
5965 given symbol <SYM> as follows:
5966 - it has function type
5967 - it has non local binding
5968 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5969 same type, binding and value as <SYM> (called normal symbol).
5970 An entry function can handle secure state transition itself in which case
5971 its special symbol would have a different value from the normal symbol.
5973 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5974 entry mapping while HTAB gives the name to hash entry mapping.
5975 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5976 created.
5978 The return value gives whether a stub failed to be allocated. */
5980 static bool
5984 {
5992 bfd_vma sym_value;
6008 NULL);
6012 /* Scan symbols. */
6014 {
6018 {
6026 /* Special symbol with local binding. */
6028 }
6029 else
6030 {
6039 /* Special symbol has incorrect binding or type. */
6044 }
6047 {
6053 }
6056 {
6063 }
6069 /* No associated normal symbol or it is neither global nor weak. */
6074 {
6075 /* Initialize here to avoid warning about use of possibly
6076 uninitialized variable. */
6080 {
6081 /* Searching for a normal symbol with local binding. */
6083 {
6084 lsym_name =
6090 }
6091 }
6094 {
6095 _bfd_error_handler
6099 }
6100 else
6101 _bfd_error_handler
6106 }
6112 {
6113 _bfd_error_handler
6117 }
6121 /* If this section is a link-once section that will be discarded, then
6122 don't create any stubs. */
6124 {
6125 _bfd_error_handler
6128 }
6131 {
6132 _bfd_error_handler
6135 }
6140 stub_entry
6147 else
6148 {
6151 }
6152 }
6157 }
6159 /* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6160 code entry function, ie can be called from non secure code without using a
6161 veneer. */
6163 static bool
6165 {
6169 file_ptr offset;
6172 /* Defined symbol of function type. */
6179 /* Read first instruction. */
6189 /* Starts by SG instruction. */
6191 }
6193 /* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6194 secure gateway veneers (ie. the veneers was not in the input import library)
6195 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6197 static bool
6199 {
6203 /* Massage our args to the form they really have. */
6217 }
6219 /* Set offset of each secure gateway veneers so that its address remain
6220 identical to the one in the input import library referred by
6221 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6222 (present in input import library but absent from the executable being
6223 linked) or if new veneers appeared and there is no output import library
6224 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6225 number of secure gateway veneers found in the input import library.
6227 The function returns whether an error occurred. If no error occurred,
6228 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6229 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6230 veneer observed set for new veneers to be layed out after. */
6232 static bool
6236 {
6239 flagword flags;
6246 bfd_size_type cmse_stub_size;
6255 /* No input secure gateway import library. */
6261 {
6265 }
6267 /* Get symbol table size. */
6272 /* Read in the input secure gateway import library's symbol table. */
6279 {
6282 }
6285 cmse_stub_size =
6289 out_sec_name =
6291 stub_out_sec =
6296 /* Set addresses of veneers mentionned in input secure gateway import
6297 library's symbol table. */
6299 {
6310 {
6312 "symbol should be absolute, global and "
6317 }
6326 /* Stub entry should have been created by cmse_scan or the symbol be of
6327 a secure function callable from non secure code. */
6329 {
6332 _bfd_error_handler
6336 stub_entry
6343 else
6344 {
6346 new_cmse_stubs_created++;
6348 }
6351 }
6352 /* Symbol found is not callable from non secure code. */
6354 {
6356 {
6358 sym_name);
6360 }
6362 }
6363 else
6364 {
6365 /* Only stubs for SG veneers should have been created. */
6368 /* Check visibility hasn't changed. */
6371 _bfd_error_handler
6373 sym_name);
6376 }
6378 /* Size should match that of a SG veneer. */
6380 {
6384 }
6386 /* Previous veneer address is before current SG veneer section. */
6388 {
6389 /* Avoid offset underflow. */
6394 }
6396 /* Complain if stub offset not a multiple of stub size. */
6398 {
6399 _bfd_error_handler
6403 }
6408 new_cmse_stubs_created--;
6414 }
6417 {
6419 _bfd_error_handler
6423 }
6426 {
6427 _bfd_error_handler
6429 out_sec_name);
6431 }
6433 free_sym_buf:
6436 }
6438 /* Determine and set the size of the stub section for a final link.
6440 The basic idea here is to examine all the relocations looking for
6441 PC-relative calls to a target that is unreachable with a "bl"
6442 instruction. */
6444 bool
6448 bfd_signed_vma group_size,
6450 asection *,
6453 {
6457 bfd_size_type stub_group_size;
6469 {
6474 }
6476 /* Propagate mach to stub bfd, because it may not have been
6477 finalized when we created stub_bfd. */
6481 /* Stash our params away. */
6490 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6491 as the first half of a 32-bit branch straddling two 4K pages. This is a
6492 crude way of enforcing that. */
6498 else
6502 {
6503 /* Default values. */
6504 /* Thumb branch range is +-4MB has to be used as the default
6505 maximum size (a given section can contain both ARM and Thumb
6506 code, so the worst case has to be taken into account).
6508 This value is 24K less than that, which allows for 2025
6509 12-byte stubs. If we exceed that, then we will fail to link.
6510 The user will have to relink with an explicit group size
6511 option. */
6513 }
6517 /* If we're applying the cortex A8 fix, we need to determine the
6518 program header size now, because we cannot change it later --
6519 that could alter section placements. Notice the A8 erratum fix
6520 ends up requiring the section addresses to remain unchanged
6521 modulo the page size. That's something we cannot represent
6522 inside BFD, and we don't want to force the section alignment to
6523 be the page size. */
6528 {
6540 {
6554 /* We'll need the symbol table in a second. */
6559 /* Limit scan of symbols to object file whose profile is
6560 Microcontroller to not hinder performance in the general case. */
6562 {
6572 }
6574 /* Walk over each section attached to the input bfd. */
6578 {
6581 /* If there aren't any relocs, then there's nothing more
6582 to do. */
6588 /* If this section is a link-once section that will be
6589 discarded, then don't create any stubs. */
6594 /* Get the relocs. */
6595 internal_relocs
6601 /* Now examine each relocation. */
6605 {
6608 bfd_vma sym_value;
6609 bfd_vma destination;
6620 {
6622 error_ret_free_internal:
6625 /* Fall through. */
6626 error_ret_free_local:
6630 }
6634 hash = elf32_arm_hash_entry
6638 /* Only look for stubs on branch instructions, or
6639 non-relaxed TLSCALL */
6653 : (elf32_arm_local_got_tls_type
6658 /* Now determine the call target, its name, value,
6659 section. */
6667 {
6668 /* A non-relaxed TLS call. The target is the
6669 plt-resident trampoline and nothing to do
6670 with the symbol. */
6677 }
6679 {
6680 /* It's a local symbol. */
6684 {
6685 local_syms
6688 local_syms
6694 }
6703 else
6704 sym_sec =
6708 /* This is an undefined symbol. It can never
6709 be resolved. */
6718 branch_type =
6720 sym_name
6724 }
6725 else
6726 {
6727 /* It's an external symbol. */
6735 {
6742 /* For a destination in a shared library,
6743 use the PLT stub as target address to
6744 decide whether a branch stub is
6745 needed. */
6750 {
6754 destination = (sym_value
6757 }
6762 }
6765 {
6766 /* For a shared library, use the PLT stub as
6767 target address to decide whether a long
6768 branch stub is needed.
6769 For absolute code, they cannot be handled. */
6777 {
6781 destination = (sym_value
6784 }
6785 else
6787 }
6788 else
6789 {
6792 }
6794 branch_type =
6797 }
6799 do
6800 {
6804 /* Determine what (if any) linker stub is needed. */
6812 /* We've either created a stub for this reloc already,
6813 or we are about to. */
6814 stub_entry =
6825 else
6827 }
6830 /* Look for relocations which might trigger Cortex-A8
6831 erratum. */
6837 {
6843 {
6844 /* Found a candidate. Note we haven't checked the
6845 destination is within 4K here: if we do so (and
6846 don't create an entry in a8_relocs) we can't tell
6847 that a branch should have been relocated when
6848 scanning later. */
6850 {
6856 }
6866 num_a8_relocs++;
6867 }
6868 }
6869 }
6871 /* We're done with the internal relocs, free them. */
6874 }
6877 {
6878 /* Sort relocs which might apply to Cortex-A8 erratum. */
6883 /* Scan for branches which might trigger Cortex-A8 erratum. */
6890 }
6894 {
6897 else
6899 }
6900 }
6913 /* OK, we've added some stubs. Find out the new size of the
6914 stub sections. */
6918 {
6919 /* Ignore non-stub sections. */
6924 }
6926 /* Add new SG veneers after those already in the input import
6927 library. */
6929 stub_type++)
6930 {
6942 }
6944 /* Compute stub section size, considering padding. */
6947 stub_type++)
6948 {
6954 /* Skip if no stub input section or no stub section padding
6955 required. */
6958 /* Stub section padding required but no dedicated section. */
6964 }
6966 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6969 {
6976 stub_sec->size
6978 NULL);
6979 }
6982 /* Ask the linker to do its stuff. */
6985 }
6987 /* Add stubs for Cortex-A8 erratum fixes now. */
6989 {
6991 {
7004 {
7008 }
7027 }
7029 /* Stash the Cortex-A8 erratum fix array for use later in
7030 elf32_arm_write_section(). */
7033 }
7034 else
7035 {
7038 }
7040 }
7042 /* Build all the stubs associated with the current output file. The
7043 stubs are kept in a hash table attached to the main linker hash
7044 table. We also set up the .plt entries for statically linked PIC
7045 functions here. This function is called via arm_elf_finish in the
7046 linker. */
7048 bool
7050 {
7063 {
7064 bfd_size_type size;
7066 /* Ignore non-stub sections. */
7070 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
7071 must at least be done for stub section requiring padding and for SG
7072 veneers to ensure that a non secure code branching to a removed SG
7073 veneer causes an error. */
7080 }
7082 /* Add new SG veneers after those already in the input import library. */
7084 {
7096 }
7098 /* Build the stubs as directed by the stub hash table. */
7102 {
7103 /* Place the cortex a8 stubs last. */
7106 }
7109 }
7111 /* Locate the Thumb encoded calling stub for NAME. */
7117 {
7122 /* We need a pointer to the armelf specific hash table. */
7134 hash = elf_link_hash_lookup
7138 {
7143 }
7148 }
7150 /* Locate the ARM encoded calling stub for NAME. */
7156 {
7161 /* We need a pointer to the elfarm specific hash table. */
7172 myh = elf_link_hash_lookup
7176 {
7181 }
7185 }
7187 /* ARM->Thumb glue (static images):
7189 .arm
7190 __func_from_arm:
7191 ldr r12, __func_addr
7192 bx r12
7193 __func_addr:
7194 .word func @ behave as if you saw a ARM_32 reloc.
7196 (v5t static images)
7197 .arm
7198 __func_from_arm:
7199 ldr pc, __func_addr
7200 __func_addr:
7201 .word func @ behave as if you saw a ARM_32 reloc.
7203 (relocatable images)
7204 .arm
7205 __func_from_arm:
7206 ldr r12, __func_offset
7207 add r12, r12, pc
7208 bx r12
7209 __func_offset:
7210 .word func - . */
7212 #define ARM2THUMB_STATIC_GLUE_SIZE 12
7217 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7221 #define ARM2THUMB_PIC_GLUE_SIZE 16
7226 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
7228 .thumb .thumb
7229 .align 2 .align 2
7230 __func_from_thumb: __func_from_thumb:
7231 bx pc push {r6, lr}
7232 nop ldr r6, __func_addr
7233 .arm mov lr, pc
7234 b func bx r6
7235 .arm
7236 ;; back_to_thumb
7237 ldmia r13! {r6, lr}
7238 bx lr
7239 __func_addr:
7240 .word func */
7242 #define THUMB2ARM_GLUE_SIZE 8
7247 #define VFP11_ERRATUM_VENEER_SIZE 8
7248 #define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7249 #define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
7251 #define ARM_BX_VENEER_SIZE 12
7256 #ifndef ELFARM_NABI_C_INCLUDED
7257 static void
7259 {
7264 {
7265 /* Do not include empty glue sections in the output. */
7267 {
7271 }
7273 }
7284 }
7286 bool
7288 {
7296 ARM2THUMB_GLUE_SECTION_NAME);
7300 THUMB2ARM_GLUE_SECTION_NAME);
7304 VFP11_ERRATUM_VENEER_SECTION_NAME);
7308 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7312 ARM_BX_GLUE_SECTION_NAME);
7315 }
7317 /* Allocate space and symbols for calling a Thumb function from Arm mode.
7318 returns the symbol identifying the stub. */
7323 {
7330 bfd_vma val;
7331 bfd_size_type size;
7337 s = bfd_get_linker_section
7348 myh = elf_link_hash_lookup
7352 {
7353 /* We've already seen this guy. */
7356 }
7358 /* The only trick here is using hash_table->arm_glue_size as the value.
7359 Even though the section isn't allocated yet, this is where we will be
7360 putting it. The +1 on the value marks that the stub has not been
7361 output yet - not that it is a Thumb function. */
7379 else
7386 }
7388 /* Allocate space for ARMv4 BX veneers. */
7390 static void
7392 {
7398 bfd_vma val;
7400 /* BX PC does not need a veneer. */
7408 /* Check if this veneer has already been allocated. */
7412 s = bfd_get_linker_section
7417 /* Add symbol for veneer. */
7424 myh = elf_link_hash_lookup
7442 }
7445 /* Add an entry to the code/data map for section SEC. */
7447 static void
7449 {
7454 {
7459 }
7464 {
7469 }
7472 {
7475 }
7476 }
7479 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7480 veneers are handled for now. */
7482 static bfd_vma
7488 {
7494 bfd_vma val;
7502 s = bfd_get_linker_section
7516 myh = elf_link_hash_lookup
7531 /* Link veneer back to calling location. */
7545 /* A symbol for the return from the veneer. */
7549 myh = elf_link_hash_lookup
7566 /* Generate a mapping symbol for the veneer section, and explicitly add an
7567 entry for that symbol to the code/data map for the section. */
7569 {
7571 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
7572 ever requires this erratum fix. */
7582 /* The elf32_arm_init_maps function only cares about symbols from input
7583 BFDs. We must make a note of this generated mapping symbol
7584 ourselves so that code byteswapping works properly in
7585 elf32_arm_write_section. */
7587 }
7593 /* The offset of the veneer. */
7595 }
7597 /* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7598 veneers need to be handled because used only in Cortex-M. */
7600 static bfd_vma
7606 bfd_size_type veneer_size)
7607 {
7613 bfd_vma val;
7621 s = bfd_get_linker_section
7635 myh = elf_link_hash_lookup
7650 /* Link veneer back to calling location. */
7664 /* A symbol for the return from the veneer. */
7668 myh = elf_link_hash_lookup
7685 /* Generate a mapping symbol for the veneer section, and explicitly add an
7686 entry for that symbol to the code/data map for the section. */
7688 {
7690 /* Creates a THUMB symbol since there is no other choice. */
7700 /* The elf32_arm_init_maps function only cares about symbols from input
7701 BFDs. We must make a note of this generated mapping symbol
7702 ourselves so that code byteswapping works properly in
7703 elf32_arm_write_section. */
7705 }
7711 /* The offset of the veneer. */
7713 }
7715 #define ARM_GLUE_SECTION_FLAGS \
7716 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7717 | SEC_READONLY | SEC_LINKER_CREATED)
7719 /* Create a fake section for use by the ARM backend of the linker. */
7721 static bool
7723 {
7728 /* Already made. */
7737 /* Set the gc mark to prevent the section from being removed by garbage
7738 collection, despite the fact that no relocs refer to this section. */
7742 }
7744 /* Set size of .plt entries. This function is called from the
7745 linker scripts in ld/emultempl/{armelf}.em. */
7747 void
7749 {
7751 }
7753 /* Add the glue sections to ABFD. This function is called from the
7754 linker scripts in ld/emultempl/{armelf}.em. */
7756 bool
7759 {
7765 /* If we are only performing a partial
7766 link do not bother adding the glue. */
7778 return addglue
7780 }
7782 /* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7783 ensures they are not marked for deletion by
7784 strip_excluded_output_sections () when veneers are going to be created
7785 later. Not doing so would trigger assert on empty section size in
7786 lang_size_sections_1 (). */
7788 void
7790 {
7793 /* If we are only performing a partial
7794 link do not bother adding the glue. */
7799 {
7810 }
7811 }
7813 /* Select a BFD to be used to hold the sections used by the glue code.
7814 This function is called from the linker scripts in ld/emultempl/
7815 {armelf/pe}.em. */
7817 bool
7819 {
7822 /* If we are only performing a partial link
7823 do not bother getting a bfd to hold the glue. */
7827 /* Make sure we don't attach the glue sections to a dynamic object. */
7836 /* Save the bfd for later use. */
7840 }
7842 static void
7844 {
7848 Tag_CPU_arch);
7851 {
7854 }
7855 else
7856 {
7859 }
7860 }
7862 bool
7865 {
7874 /* If we are only performing a partial link do not bother
7875 to construct any glue. */
7879 /* Here we have a bfd that is to be included on the link. We have a
7880 hook to do reloc rummaging, before section sizes are nailed down. */
7887 {
7889 abfd);
7891 }
7893 /* PR 5398: If we have not decided to include any loadable sections in
7894 the output then we will not have a glue owner bfd. This is OK, it
7895 just means that there is nothing else for us to do here. */
7899 /* Rummage around all the relocs and map the glue vectors. */
7906 {
7916 /* Load the relocs. */
7917 internal_relocs
7925 {
7934 /* These are the only relocation types we care about. */
7939 /* Get the section contents if we haven't done so already. */
7941 {
7942 /* Get cached copy if it exists. */
7945 else
7946 {
7947 /* Go get them off disk. */
7950 }
7951 }
7954 {
7960 }
7962 /* If the relocation is not against a symbol it cannot concern us. */
7965 /* We don't care about local symbols. */
7969 /* This is an external symbol. */
7974 /* If the relocation is against a static symbol it must be within
7975 the current section and so cannot be a cross ARM/Thumb relocation. */
7979 /* If the call will go through a PLT entry then we do not need
7980 glue. */
7985 {
7987 /* This one is a call from arm code. We need to look up
7988 the target of the call. If it is a thumb target, we
7989 insert glue. */
7997 }
7998 }
8007 }
8011 error_return:
8018 }
8019 #endif
8022 /* Initialise maps of ARM/Thumb/data for input BFDs. */
8024 void
8026 {
8031 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
8041 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8042 should contain the number of local symbols, which should come before any
8043 global symbols. Mapping symbols are always local. */
8045 NULL);
8047 /* No internal symbols read? Skip this BFD. */
8052 {
8059 {
8064 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
8066 }
8067 }
8068 }
8071 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8072 say what they wanted. */
8074 void
8076 {
8084 {
8085 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8090 else
8092 }
8093 }
8096 void
8098 {
8104 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8106 {
8108 {
8115 /* Give a warning, but do as the user requests anyway. */
8118 }
8119 }
8121 /* For earlier architectures, we might need the workaround, but do not
8122 enable it by default. If users is running with broken hardware, they
8123 must enable the erratum fix explicitly. */
8125 }
8127 void
8129 {
8136 /* We assume only Cortex-M4 may require the fix. */
8139 {
8141 /* Give a warning, but do as the user requests anyway. */
8142 _bfd_error_handler
8145 }
8146 }
8148 enum bfd_arm_vfp11_pipe
8149 {
8150 VFP11_FMAC,
8151 VFP11_LS,
8152 VFP11_DS,
8153 VFP11_BAD
8154 };
8156 /* Return a VFP register number. This is encoded as RX:X for single-precision
8157 registers, or X:RX for double-precision registers, where RX is the group of
8158 four bits in the instruction encoding and X is the single extension bit.
8159 RX and X fields are specified using their lowest (starting) bit. The return
8160 value is:
8162 0...31: single-precision registers s0...s31
8163 32...63: double-precision registers d0...d31.
8165 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8166 encounter VFP3 instructions, so we allow the full range for DP registers. */
8168 static unsigned int
8171 {
8174 else
8176 }
8178 /* Set bits in *WMASK according to a register number REG as encoded by
8179 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8181 static void
8183 {
8188 }
8190 /* Return TRUE if WMASK overwrites anything in REGS. */
8192 static bool
8194 {
8198 {
8211 }
8214 }
8216 /* In this function, we're interested in two things: finding input registers
8217 for VFP data-processing instructions, and finding the set of registers which
8218 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8219 hold the written set, so FLDM etc. are easy to deal with (we're only
8220 interested in 32 SP registers or 16 dp registers, due to the VFP version
8221 implemented by the chip in question). DP registers are marked by setting
8222 both SP registers in the write mask). */
8224 static enum bfd_arm_vfp11_pipe
8227 {
8232 {
8242 {
8264 vfp_binop:
8272 {
8277 {
8291 /* These instructions will not bounce due to underflow. */
8297 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8298 registers to cause the erratum in previous instructions. */
8304 {
8309 /* Only FCVTSD can underflow. */
8316 }
8321 }
8322 }
8327 }
8328 }
8329 /* Two-register transfer. */
8331 {
8335 {
8338 else
8339 {
8342 }
8343 }
8346 }
8348 {
8353 {
8360 {
8368 }
8378 }
8381 }
8382 /* Single-register transfer. Note L==0. */
8384 {
8389 {
8392 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8393 destination register. I don't know if this is exactly right,
8394 but it is the conservative choice. */
8400 }
8403 }
8406 }
8412 /* Look for potentially-troublesome code sequences which might trigger the
8413 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8414 (available from ARM) for details of the erratum. A short version is
8415 described in ld.texinfo. */
8417 bool
8419 {
8430 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8431 The states transition as follows:
8433 0 -> 1 (vector) or 0 -> 2 (scalar)
8434 A VFP FMAC-pipeline instruction has been seen. Fill
8435 regs[0]..regs[numregs-1] with its input operands. Remember this
8436 instruction in 'first_fmac'.
8438 1 -> 2
8439 Any instruction, except for a VFP instruction which overwrites
8440 regs[*].
8442 1 -> 3 [ -> 0 ] or
8443 2 -> 3 [ -> 0 ]
8444 A VFP instruction has been seen which overwrites any of regs[*].
8445 We must make a veneer! Reset state to 0 before examining next
8446 instruction.
8448 2 -> 0
8449 If we fail to match anything in state 2, reset to state 0 and reset
8450 the instruction pointer to the instruction after 'first_fmac'.
8452 If the VFP11 vector mode is in use, there must be at least two unrelated
8453 instructions between anti-dependent VFP11 instructions to properly avoid
8454 triggering the erratum, hence the use of the extra state 1. */
8456 /* If we are only performing a partial link do not bother
8457 to construct any glue. */
8461 /* Skip if this bfd does not correspond to an ELF image. */
8465 /* We should have chosen a fix type by the time we get here. */
8471 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8476 {
8480 /* If we don't have executable progbits, we're not interested in this
8481 section. Also skip if section is to be excluded. */
8501 elf32_arm_compare_mapping);
8504 {
8510 /* FIXME: Only ARM mode is supported at present. We may need to
8511 support Thumb-2 mode also at some point. */
8516 {
8531 {
8535 /* I'm assuming the VFP11 erratum can trigger with denorm
8536 operands on either the FMAC or the DS pipeline. This might
8537 lead to slightly overenthusiastic veneer insertion. */
8539 {
8543 }
8547 {
8550 other_regs,
8554 numregs))
8556 else
8558 }
8562 {
8565 other_regs,
8569 numregs))
8571 else
8572 {
8575 }
8576 }
8581 }
8584 {
8593 {
8600 }
8603 first_fmac);
8611 }
8614 }
8615 }
8620 }
8624 error_return:
8629 }
8631 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8632 after sections have been laid out, using specially-named symbols. */
8634 void
8637 {
8645 /* Skip if this bfd does not correspond to an ELF image. */
8658 {
8663 {
8665 bfd_vma vma;
8668 {
8671 /* Find veneer symbol. */
8675 myh = elf_link_hash_lookup
8691 /* Find return location. */
8695 myh = elf_link_hash_lookup
8711 }
8712 }
8713 }
8716 }
8718 /* Find virtual-memory addresses for STM32L4XX erratum veneers and
8719 return locations after sections have been laid out, using
8720 specially-named symbols. */
8722 void
8725 {
8733 /* Skip if this bfd does not correspond to an ELF image. */
8746 {
8751 {
8753 bfd_vma vma;
8756 {
8758 /* Find veneer symbol. */
8762 myh = elf_link_hash_lookup
8777 /* Find return location. */
8781 myh = elf_link_hash_lookup
8797 }
8798 }
8799 }
8802 }
8806 {
8807 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8808 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8810 }
8814 {
8815 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8816 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8818 }
8822 {
8823 /* A6.5 Extension register load or store instruction
8824 A7.7.229
8825 We look for SP 32-bit and DP 64-bit registers.
8826 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8827 <list> is consecutive 64-bit registers
8828 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
8829 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8830 <list> is consecutive 32-bit registers
8831 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8832 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8833 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8834 return
8839 /* (IA with !), includes VPOP (when reg number is SP). */
8841 /* (DB with !). */
8843 }
8845 /* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8846 VLDM opcode and:
8847 - computes the number and the mode of memory accesses
8848 - decides if the replacement should be done:
8849 . replaces only if > 8-word accesses
8850 . or (testing purposes only) replaces all accesses. */
8852 static bool
8854 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8855 {
8858 /* The field encoding the register list is the same for both LDMIA
8859 and LDMDB encodings. */
8865 /* DEFAULT mode accounts for the real bug condition situation,
8866 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8870 }
8872 /* Look for potentially-troublesome code sequences which might trigger
8873 the STM STM32L4XX erratum. */
8875 bool
8878 {
8886 /* If we are only performing a partial link do not bother
8887 to construct any glue. */
8891 /* Skip if this bfd does not correspond to an ELF image. */
8898 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8903 {
8907 /* If we don't have executable progbits, we're not interested in this
8908 section. Also skip if section is to be excluded. */
8928 elf32_arm_compare_mapping);
8931 {
8938 /* Only Thumb2 mode need be supported with this CM4 specific
8939 code, we should not encounter any arm mode eg span_type
8940 != 'a'. */
8945 {
8952 /* The first 16-bits of all 32-bit thumb2 instructions start
8953 with opcode[15..13]=0b111 and the encoded op1 can be anything
8954 except opcode[12..11]!=0b00.
8955 See 32-bit Thumb instruction encoding. */
8959 /* Compute the predicate that tells if the instruction
8960 is concerned by the IT block
8961 - Creates an error if there is a ldm that is not
8962 last in the IT block thus cannot be replaced
8963 - Otherwise we can create a branch at the end of the
8964 IT block, it will be controlled naturally by IT
8965 with the proper pseudo-predicate
8966 - So the only interesting predicate is the one that
8967 tells that we are not on the last item of an IT
8968 block. */
8973 {
8974 /* Load the rest of the insn (in manual-friendly order). */
8979 /* Veneers are created for (v)ldm depending on
8980 option flags and memory accesses conditions; but
8981 if the instruction is not the last instruction of
8982 an IT block, we cannot create a jump there, so we
8983 bail out. */
8985 && stm32l4xx_need_create_replacing_stub
8987 {
8989 {
8990 _bfd_error_handler
8991 /* xgettext:c-format */
8993 " in non-last IT block instruction:"
8994 " STM32L4XX veneer cannot be generated; "
8995 "use gcc option -mrestrict-it to generate"
8998 }
8999 else
9000 {
9003 bfd_zmalloc
9009 /* We create only thumb branches. */
9011 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
9012 record_stm32l4xx_erratum_veneer
9014 i,
9015 is_ldm ?
9016 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
9017 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
9021 }
9022 }
9023 }
9024 else
9025 {
9026 /* A7.7.37 IT p208
9027 IT blocks are only encoded in T1
9028 Encoding T1: IT{x{y{z}}} <firstcond>
9029 1 0 1 1 - 1 1 1 1 - firstcond - mask
9030 if mask = '0000' then see 'related encodings'
9031 We don't deal with UNPREDICTABLE, just ignore these.
9032 There can be no nested IT blocks so an IT block
9033 is naturally a new one for which it is worth
9034 computing its size. */
9037 /* If we have a new IT block we compute its size. */
9039 {
9040 /* Compute the number of instructions controlled
9041 by the IT block, it will be used to decide
9042 whether we are inside an IT block or not. */
9045 }
9046 }
9049 }
9050 }
9055 }
9059 error_return:
9064 }
9066 /* Set target relocation values needed during linking. */
9068 void
9072 {
9088 else
9089 {
9092 }
9099 else
9111 }
9113 /* Replace the target offset of a Thumb bl or b.w instruction. */
9115 static void
9117 {
9118 bfd_vma upper;
9119 bfd_vma lower;
9136 }
9138 /* Thumb code calling an ARM function. */
9140 static int
9148 bfd_vma offset,
9149 bfd_signed_vma addend,
9150 bfd_vma val,
9152 {
9154 bfd_vma my_offset;
9170 THUMB2ARM_GLUE_SECTION_NAME);
9177 {
9181 {
9182 _bfd_error_handler
9188 }
9199 ret_offset =
9200 /* Address of destination of the stub. */
9203 /* Offset from the start of the current section
9204 to the start of the stubs. */
9206 /* Offset of the start of this stub from the start of the stubs. */
9207 + my_offset
9208 /* Address of the start of the current section. */
9210 /* The branch instruction is 4 bytes into the stub. */
9212 /* ARM branches work from the pc of the instruction + 8. */
9218 }
9222 /* Now go back and fix up the original BL insn to point to here. */
9223 ret_offset =
9224 /* Address of where the stub is located. */
9226 /* Address of where the BL is located. */
9229 /* Addend in the relocation. */
9230 - addend
9231 /* Biassing for PC-relative addressing. */
9237 }
9239 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
9247 bfd_vma val,
9250 {
9251 bfd_vma my_offset;
9267 {
9271 {
9272 _bfd_error_handler
9276 }
9283 {
9284 /* For relocatable objects we can't use absolute addresses,
9285 so construct the address from a relative offset. */
9286 /* TODO: If the offset is small it's probably worth
9287 constructing the address with adds. */
9294 /* Adjust the offset by 4 for the position of the add,
9295 and 8 for the pipeline offset. */
9302 }
9304 {
9308 /* It's a thumb address. Add the low order bit. */
9311 }
9312 else
9313 {
9320 /* It's a thumb address. Add the low order bit. */
9325 }
9326 }
9331 }
9333 /* Arm code calling a Thumb function. */
9335 static int
9343 bfd_vma offset,
9344 bfd_signed_vma addend,
9345 bfd_vma val,
9347 {
9349 bfd_vma my_offset;
9360 ARM2THUMB_GLUE_SECTION_NAME);
9374 /* Somehow these are both 4 too far, so subtract 8. */
9376 + my_offset
9388 }
9390 /* Populate Arm stub for an exported Thumb function. */
9392 static bool
9394 {
9401 bfd_vma val;
9405 /* Allocate stubs for exported Thumb functions on v4t. */
9414 ARM2THUMB_GLUE_SECTION_NAME);
9432 }
9434 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9436 static bfd_vma
9438 {
9440 bfd_vma glue_addr;
9449 ARM_BX_GLUE_SECTION_NAME);
9459 {
9465 }
9468 }
9470 /* Generate Arm stubs for exported Thumb symbols. */
9471 static void
9474 {
9478 /* Ignore this if we are not called by the ELF backend linker. */
9485 /* If blx is available then exported Thumb symbols are OK and there is
9486 nothing to do. */
9491 link_info);
9492 }
9494 /* Reserve space for COUNT dynamic relocations in relocation selection
9495 SRELOC. */
9497 static void
9499 bfd_size_type count)
9500 {
9508 }
9510 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9511 dynamic, the relocations should go in SRELOC, otherwise they should
9512 go in the special .rel.iplt section. */
9514 static void
9516 bfd_size_type count)
9517 {
9523 else
9524 {
9527 }
9528 }
9530 /* Add relocation REL to the end of relocation section SRELOC. */
9532 static void
9535 {
9550 }
9552 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9553 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9554 to .plt. */
9556 static void
9561 {
9569 {
9573 /* NaCl uses a special first entry in .iplt too. */
9577 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9579 }
9580 else
9581 {
9586 {
9587 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9588 /* For lazy binding, relocations will be put into .rel.plt, in
9589 .rel.got otherwise. */
9590 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9593 else
9595 }
9596 else
9597 {
9598 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9600 }
9602 /* If this is the first .plt entry, make room for the special
9603 first entry. */
9608 }
9610 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9616 /* We also need to make an entry in the .got.plt section, which
9617 will be placed in the .got section by the linker script. */
9620 else
9623 /* Function descriptor takes 64 bits in GOT. */
9625 else
9627 }
9629 static bfd_vma
9631 {
9633 }
9635 static bfd_vma
9637 {
9639 }
9641 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9642 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9643 Otherwise, DYNINDX is the index of the symbol in the dynamic
9644 symbol table and SYM_VALUE is undefined.
9646 ROOT_PLT points to the offset of the PLT entry from the start of its
9647 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
9648 bookkeeping information.
9650 Returns FALSE if there was a problem. */
9652 static bool
9657 {
9663 bfd_vma plt_index;
9664 Elf_Internal_Rela rel;
9665 bfd_vma got_header_size;
9669 /* Pick the appropriate sections and sizes. */
9671 {
9676 /* There are no reserved entries in .igot.plt, and no special
9677 first entry in .iplt. */
9679 }
9680 else
9681 {
9687 }
9696 /* Get the offset into the .(i)got.plt table of the entry that
9697 corresponds to this function. */
9700 /* Get the index in the procedure linkage table which
9701 corresponds to this symbol. This is the index of this symbol
9702 in all the symbols for which we are making plt entries.
9703 After the reserved .got.plt entries, all symbols appear in
9704 the same order as in .plt. */
9706 /* Function descriptor takes 8 bytes. */
9708 else
9711 /* Calculate the address of the GOT entry. */
9716 /* ...and the address of the PLT entry. */
9723 {
9725 bfd_vma val;
9728 {
9736 else
9738 }
9739 }
9741 {
9743 bfd_vma val;
9746 {
9756 else
9758 }
9763 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9764 referencing the GOT for this PLT entry. */
9771 /* Create the R_ARM_ABS32 relocation referencing the
9772 beginning of the PLT for this GOT entry. */
9777 }
9779 {
9780 /* Calculate the displacement between the PLT slot and the
9781 common tail that's part of the special initial PLT slot. */
9782 int32_t tail_displacement
9792 /* Calculate the displacement between the PLT slot and the entry
9793 in the GOT. The offset accounts for the value produced by
9794 adding to pc in the penultimate instruction of the PLT stub. */
9795 got_displacement = (got_address
9798 /* NaCl does not support interworking at all. */
9816 }
9818 {
9820 ? elf32_arm_fdpic_thumb_plt_entry
9823 /* Fill-up Thumb stub if needed. */
9825 {
9830 }
9831 /* As we are using 32 bit instructions even for the Thumb
9832 version, we have to use 'put_arm_insn' instead of
9833 'put_thumb_insn'. */
9841 {
9842 /* funcdesc_value_reloc_offset. */
9850 }
9851 }
9853 {
9854 /* PR ld/16017: Generate thumb only PLT entries. */
9856 {
9857 /* FIXME: We ought to be able to generate thumb-1 PLT
9858 instructions... */
9860 output_bfd);
9862 }
9864 /* Calculate the displacement between the PLT slot and the entry in
9865 the GOT. The 12-byte offset accounts for the value produced by
9866 adding to pc in the 3rd instruction of the PLT stub. */
9869 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9870 instead of 'put_thumb_insn'. */
9891 }
9892 else
9893 {
9894 /* Calculate the displacement between the PLT slot and the
9895 entry in the GOT. The eight-byte offset accounts for the
9896 value produced by adding to pc in the first instruction
9897 of the PLT stub. */
9901 {
9906 }
9909 {
9924 #ifdef FOUR_WORD_PLT
9926 #endif
9927 }
9928 else
9929 {
9946 }
9947 }
9949 /* Fill in the entry in the .rel(a).(i)plt section. */
9953 {
9954 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9955 The dynamic linker or static executable then calls SYM_VALUE
9956 to determine the correct run-time value of the .igot.plt entry. */
9959 }
9960 else
9961 {
9962 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9963 used by PLT entry. */
9965 {
9968 }
9969 else
9970 {
9975 /* PR ld/16017
9976 When thumb only we need to set the LSB for any address that
9977 will be used with an interworking branch instruction. */
9980 }
9981 }
9983 /* Fill in the entry in the global offset table. */
9988 {
9989 /* Setup initial funcdesc value. */
9990 /* FIXME: we don't support lazy binding because there is a
9991 race condition between both words getting written and
9992 some other thread attempting to read them. The ARM
9993 architecture does not have an atomic 64 bit load/store
9994 instruction that could be used to prevent it; it is
9995 recommended that threaded FDPIC applications run with the
9996 LD_BIND_NOW environment variable set. */
10001 }
10005 else
10006 {
10008 {
10009 /* For FDPIC we put PLT relocationss into .rel.got when not
10010 lazy binding otherwise we put them in .rel.plt. For now,
10011 we don't support lazy binding so put it in .rel.got. */
10014 else
10016 }
10017 else
10018 {
10021 }
10022 }
10025 }
10027 /* Some relocations map to different relocations depending on the
10028 target. Return the real relocation. */
10030 static int
10033 {
10035 {
10039 else
10047 }
10048 }
10050 /* Return the base VMA address which should be subtracted from real addresses
10051 when resolving @dtpoff relocation.
10052 This is PT_TLS segment p_vaddr. */
10054 static bfd_vma
10056 {
10057 /* If tls_sec is NULL, we should have signalled an error already. */
10061 }
10063 /* Return the relocation value for @tpoff relocation
10064 if STT_TLS virtual address is ADDRESS. */
10066 static bfd_vma
10068 {
10070 bfd_vma base;
10072 /* If tls_sec is NULL, we should have signalled an error already. */
10077 }
10079 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10080 VALUE is the relocation value. */
10082 static bfd_reloc_status_type
10084 {
10091 }
10093 /* Handle TLS relaxations. Relaxing is possible for symbols that use
10094 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10095 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10097 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10098 is to then call final_link_relocate. Return other values in the
10099 case of error.
10101 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10102 the pre-relaxed code. It would be nice if the relocs were updated
10103 to match the optimization. */
10105 static bfd_reloc_status_type
10109 {
10113 {
10120 else
10121 {
10125 else
10127 }
10132 /* Thumb insn. */
10135 {
10137 /* nop */
10139 }
10141 {
10143 /* nop */
10145 else
10146 /* ldr rx,[ry] */
10148 }
10150 {
10152 /* nop */
10154 else
10155 /* mov r0, rx */
10158 }
10159 else
10160 {
10162 /* It's a 32 bit instruction, fetch the rest of it for
10163 error generation. */
10166 _bfd_error_handler
10167 /* xgettext:c-format */
10173 }
10177 /* arm insn. */
10180 {
10182 /* mov rx, ry */
10185 }
10187 {
10189 /* nop */
10191 else
10192 /* ldr rx,[ry] */
10195 }
10197 {
10199 /* nop */
10201 else
10202 /* mov r0, rx */
10205 }
10206 else
10207 {
10208 _bfd_error_handler
10209 /* xgettext:c-format */
10215 }
10219 /* GD->IE relaxation, turn the instruction into 'nop' or
10220 'ldr r0, [pc,r0]' */
10226 /* GD->IE relaxation. */
10228 /* add r0,pc; ldr r0, [r0] */
10231 /* nop.w */
10233 else
10234 /* nop; nop */
10240 }
10242 }
10244 /* For a given value of n, calculate the value of G_n as required to
10245 deal with group relocations. We return it in the form of an
10246 encoded constant-and-rotation, together with the final residual. If n is
10247 specified as less than zero, then final_residual is filled with the
10248 input value and no further action is performed. */
10250 static bfd_vma
10252 {
10254 bfd_vma g_n;
10259 {
10262 /* Calculate which part of the value to mask. */
10265 else
10266 {
10269 /* Determine the most significant bit in the residual and
10270 align the resulting value to a 2-bit boundary. */
10275 /* The desired shift is now (msb - 6), or zero, whichever
10276 is the greater. */
10280 }
10282 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10287 /* Calculate the residual for the next time around. */
10289 }
10294 }
10296 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
10297 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
10299 static int
10301 {
10311 }
10313 /* Perform a relocation as part of a final link. */
10315 static bfd_reloc_status_type
10322 bfd_vma value,
10331 {
10341 bfd_vma addend;
10342 bfd_signed_vma signed_addend;
10344 bfd_vma dynreloc_value;
10349 bfd_vma plt_offset;
10350 bfd_vma gotplt_offset;
10361 /* Some relocation types map to different relocations depending on the
10362 target. We pick the right one here. */
10365 /* It is possible to have linker relaxations on some TLS access
10366 models. Update our information here. */
10379 else
10385 {
10386 bfd_vma sign;
10389 {
10394 }
10395 /* Note: the addend and signed_addend calculated here are
10396 incorrect for any split field. */
10402 }
10403 else
10406 /* Record the symbol information that should be used in dynamic
10407 relocations. */
10413 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10414 VALUE appropriately for relocations that we resolve at link time. */
10419 {
10424 {
10428 /* Populate .iplt entries here, because not all of them will
10429 be seen by finish_dynamic_symbol. The lower bit is set if
10430 we have already populated the entry. */
10432 plt_offset--;
10433 else
10434 {
10438 else
10440 }
10442 /* Static relocations always resolve to the .iplt entry. */
10449 /* If there are non-call relocations that resolve to the .iplt
10450 entry, then all dynamic ones must too. */
10452 {
10455 }
10456 }
10457 else
10458 /* We populate the .plt entry in finish_dynamic_symbol. */
10460 }
10461 else
10462 {
10466 }
10468 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we are
10469 resolving a function call relocation. We want to inform the user
10470 that something is wrong. */
10475 /* Calls through a PLT are special: the assembly source code
10476 cannot be annotated with '.type foo(PLT), %function', and
10477 they handled specifically below anyway. */
10479 {
10481 {
10482 /* As an exception, assume that absolute symbols are of the
10483 right kind (Thumb). They are presumably defined in the
10484 linker script, where it is not possible to declare them as
10485 Thumb (and thus are seen as Arm mode). Inform the user with
10486 a warning, though. */
10490 _bfd_error_handler
10494 else
10495 _bfd_error_handler
10499 }
10500 else
10501 /* Otherwise do not silently build a stub, and let the users
10502 know they have to fix their code. Indeed, we could decide
10503 to insert a stub involving Arm code and/or BLX, leading to
10504 a run-time crash. */
10506 }
10508 /* Fail early if branch_type is ST_BRANCH_UNKNOWN and we target a
10509 Thumb-only CPU. We could emit a warning on Arm-capable targets
10510 too, but that would be too verbose (a lot of legacy code does not
10511 use the .type foo, %function directive). */
10516 /* Exception to the rule above: a branch to an undefined weak
10517 symbol is turned into a jump to the next instruction unless a
10518 PLT entry will be created (see below). */
10521 {
10524 _bfd_error_handler
10527 else
10528 _bfd_error_handler
10533 }
10539 {
10541 /* We don't need to find a value for this symbol. It's just a
10542 marker. */
10549 /* Fall through. */
10561 /* Handle relocations which should use the PLT entry. ABS32/REL32
10562 will use the symbol's value, which may point to a PLT entry, but we
10563 don't need to handle that here. If we created a PLT entry, all
10564 branches in this object should go to it, except if the PLT is too
10565 far away, in which case a long branch stub should be inserted. */
10572 {
10573 /* If we've created a .plt section, and assigned a PLT entry
10574 to this function, it must either be a STT_GNU_IFUNC reference
10575 or not be known to bind locally. In other cases, we should
10576 have cleared the PLT entry by now. */
10586 }
10588 /* When generating a shared library or PIE, these relocations
10589 are copied into the output file to be resolved at run time. */
10609 {
10610 Elf_Internal_Rela outrel;
10616 {
10622 _bfd_error_handler
10627 }
10632 {
10638 }
10663 else
10664 {
10667 /* This symbol is local, or marked to become local. */
10670 /* On SVR4-ish systems, the dynamic loader cannot
10671 relocate the text and data segments independently,
10672 so the symbol does not matter. */
10675 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10676 to the .iplt entry. Instead, every non-call reference
10677 must use an R_ARM_IRELATIVE relocation to obtain the
10678 correct run-time address. */
10682 else
10686 else
10688 }
10692 else
10695 /* If this reloc is against an external symbol, we do not want to
10696 fiddle with the addend. Otherwise, we need to include the symbol
10697 value so that it becomes an addend for the dynamic reloc. */
10704 }
10706 {
10715 {
10719 {
10720 /* Check for Arm calling Arm function. */
10721 /* FIXME: Should we translate the instruction into a BL
10722 instruction instead ? */
10724 _bfd_error_handler
10729 }
10731 {
10732 /* Check for Arm calling Thumb function. */
10734 {
10739 error_message))
10741 else
10743 }
10744 }
10746 /* Check if a stub has to be inserted because the
10747 destination is too far or we are changing mode. */
10751 {
10762 {
10763 /* The target is out of reach, so redirect the
10764 branch to the local stub for this function. */
10768 stub_type);
10769 {
10777 }
10778 }
10779 else
10780 {
10781 /* If the call goes through a PLT entry, make sure to
10782 check distance to the right destination address. */
10784 {
10789 /* The PLT entry is in ARM mode, regardless of the
10790 target function. */
10792 }
10793 }
10794 }
10796 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10797 where:
10798 S is the address of the symbol in the relocation.
10799 P is address of the instruction being relocated.
10800 A is the addend (extracted from the instruction) in bytes.
10802 S is held in 'value'.
10803 P is the base address of the section containing the
10804 instruction plus the offset of the reloc into that
10805 section, ie:
10806 (input_section->output_section->vma +
10807 input_section->output_offset +
10808 rel->r_offset).
10809 A is the addend, converted into bytes, ie:
10810 (signed_addend * 4)
10812 Note: None of these operations have knowledge of the pipeline
10813 size of the processor, thus it is up to the assembler to
10814 encode this information into the addend. */
10823 /* A branch to an undefined weak symbol is turned into a jump to
10824 the next instruction unless a PLT entry will be created.
10825 Do the same for local undefined symbols (but not for STN_UNDEF).
10826 The jump to the next instruction is optimized as a NOP depending
10827 on the architecture. */
10831 {
10836 else
10838 }
10839 else
10840 {
10841 /* Perform a signed range check. */
10852 {
10853 /* Set the H bit in the BLX instruction. */
10855 {
10858 else
10860 }
10862 /* Select the correct instruction (BL or BLX). */
10863 /* Only if we are not handling a BL to a stub. In this
10864 case, mode switching is performed by the stub. */
10868 {
10871 }
10872 }
10873 }
10874 }
10906 {
10907 /* Check for overflow. */
10910 }
10916 }
10924 /* There is no way to tell whether the user intended to use a signed or
10925 unsigned addend. When checking for overflow we accept either,
10926 as specified by the AAELF. */
10936 /* See comment for R_ARM_ABS8. */
10944 /* Support ldr and str instructions for the thumb. */
10946 {
10947 /* Need to refetch addend. */
10949 /* ??? Need to determine shift amount from operand size. */
10951 }
10954 /* ??? Isn't value unsigned? */
10958 /* ??? Value needs to be properly shifted into place first. */
10964 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10965 {
10966 bfd_vma insn;
10967 bfd_signed_vma relocation;
10973 {
10978 }
10985 /* PR 21523: Use an absolute value. The user of this reloc will
10986 have already selected an ADD or SUB insn appropriately. */
10992 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
11006 }
11009 /* PR 10073: This reloc is not generated by the GNU toolchain,
11010 but it is supported for compatibility with third party libraries
11011 generated by other compilers, specifically the ARM/IAR. */
11012 {
11013 bfd_vma insn;
11014 bfd_signed_vma relocation;
11028 /* We do not check for overflow of this reloc. Although strictly
11029 speaking this is incorrect, it appears to be necessary in order
11030 to work with IAR generated relocs. Since GCC and GAS do not
11031 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
11032 a problem for them. */
11040 }
11043 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11044 {
11045 bfd_vma insn;
11046 bfd_signed_vma relocation;
11052 {
11056 }
11076 }
11081 /* Thumb BL (branch long instruction). */
11082 {
11083 bfd_vma relocation;
11084 bfd_vma reloc_sign;
11088 bfd_signed_vma reloc_signed_max;
11089 bfd_signed_vma reloc_signed_min;
11090 bfd_vma check;
11091 bfd_signed_vma signed_check;
11096 /* A branch to an undefined weak symbol is turned into a jump to
11097 the next instruction unless a PLT entry will be created.
11098 The jump to the next instruction is optimized as a NOP.W for
11099 Thumb-2 enabled architectures. */
11102 {
11104 {
11107 }
11108 else
11109 {
11112 }
11114 }
11116 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
11117 with Thumb-1) involving the J1 and J2 bits. */
11119 {
11129 /* Sign extend. */
11133 }
11136 {
11137 /* Check for Thumb to Thumb call. */
11138 /* FIXME: Should we translate the instruction into a BL
11139 instruction instead ? */
11141 _bfd_error_handler
11146 }
11147 else
11148 {
11149 /* If it is not a call to Thumb, assume call to Arm.
11150 If it is a call relative to a section name, then it is not a
11151 function call at all, but rather a long jump. Calls through
11152 the PLT do not require stubs. */
11154 {
11156 {
11157 /* Convert BL to BLX. */
11159 }
11162 {
11166 error_message))
11168 else
11170 }
11171 }
11175 {
11176 /* Make sure this is a BL. */
11178 }
11179 }
11183 {
11184 /* Check if a stub has to be inserted because the destination
11185 is too far. */
11197 {
11198 /* The target is out of reach or we are changing modes, so
11199 redirect the branch to the local stub for this
11200 function. */
11204 stub_type);
11206 {
11213 }
11215 /* If this call becomes a call to Arm, force BLX. */
11217 {
11222 }
11223 }
11224 }
11226 /* Handle calls via the PLT. */
11228 {
11236 {
11237 /* If the Thumb BLX instruction is available, convert
11238 the BL to a BLX instruction to call the ARM-mode
11239 PLT entry. */
11242 }
11243 else
11244 {
11246 /* Target the Thumb stub before the ARM PLT entry. */
11249 }
11251 }
11261 /* If this is a signed value, the rightshift just dropped
11262 leading 1 bits (assuming twos complement). */
11265 else
11268 /* Calculate the permissable maximum and minimum values for
11269 this relocation according to whether we're relocating for
11270 Thumb-2 or not. */
11277 /* Assumes two's complement. */
11282 /* For a BLX instruction, make sure that the relocation is rounded up
11283 to a word boundary. This follows the semantics of the instruction
11284 which specifies that bit 1 of the target address will come from bit
11285 1 of the base address. */
11288 /* Put RELOCATION back into the insn. Assumes two's complement.
11289 We use the Thumb-2 encoding, which is safe even if dealing with
11290 a Thumb-1 instruction by virtue of our overflow check above. */
11300 /* Put the relocated value back in the object file: */
11305 }
11309 /* Thumb32 conditional branch instruction. */
11310 {
11311 bfd_vma relocation;
11317 bfd_signed_vma signed_check;
11322 /* Need to refetch the addend, reconstruct the top three bits,
11323 and squish the two 11 bit pieces together. */
11325 {
11339 }
11341 /* Handle calls via the PLT. */
11343 {
11347 /* Target the Thumb stub before the ARM PLT entry. */
11350 }
11359 {
11363 stub_type);
11365 {
11369 }
11370 }
11381 /* Put RELOCATION back into the insn. */
11382 {
11391 }
11393 /* Put the relocated value back in the object file: */
11398 }
11403 /* Thumb B (branch) instruction). */
11404 {
11405 bfd_signed_vma relocation;
11408 bfd_signed_vma signed_check;
11410 /* CZB cannot jump backward. */
11412 {
11416 }
11429 else
11435 /* Assumes two's complement. */
11440 }
11445 {
11446 bfd_vma insn;
11447 bfd_vma relocation;
11451 {
11452 /* Extract the addend. */
11455 }
11465 }
11473 /* Relocation is relative to the start of the
11474 global offset table. */
11480 /* If we are addressing a Thumb function, we need to adjust the
11481 address by one, so that attempts to call the function pointer will
11482 correctly interpret it as Thumb code. */
11486 /* Note that sgot->output_offset is not involved in this
11487 calculation. We always want the start of .got. If we
11488 define _GLOBAL_OFFSET_TABLE in a different way, as is
11489 permitted by the ABI, we might have to change this
11490 calculation. */
11497 /* Use global offset table as symbol value. */
11511 /* Relocation is to the entry for this symbol in the
11512 global offset table. */
11519 {
11520 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11521 symbol, and the relocation resolves directly to the runtime
11522 target rather than to the .iplt entry. This means that any
11523 .got entry would be the same value as the .igot.plt entry,
11524 so there's no point creating both. */
11527 }
11529 {
11530 bfd_vma off;
11535 {
11536 /* We have already processsed one GOT relocation against
11537 this symbol. */
11542 }
11543 else
11544 {
11545 Elf_Internal_Rela outrel;
11550 {
11551 /* If the symbol doesn't resolve locally in a static
11552 object, we have an undefined reference. If the
11553 symbol doesn't resolve locally in a dynamic object,
11554 it should be resolved by the dynamic linker. */
11556 {
11559 }
11560 else
11563 }
11564 else
11565 {
11571 else
11572 {
11576 }
11578 }
11580 /* The GOT entry is initialized to zero by default.
11581 See if we should install a different value. */
11584 {
11588 }
11597 {
11602 }
11605 }
11607 }
11608 else
11609 {
11610 bfd_vma off;
11617 /* The offset must always be a multiple of 4. We use the
11618 least significant bit to record whether we have already
11619 generated the necessary reloc. */
11622 else
11623 {
11624 Elf_Internal_Rela outrel;
11631 else
11632 {
11636 }
11638 /* The GOT entry is initialized to zero by default.
11639 See if we should install a different value. */
11650 {
11656 }
11659 }
11662 }
11679 {
11680 bfd_vma off;
11689 else
11690 {
11691 /* If we don't know the module number, create a relocation
11692 for it. */
11694 {
11695 Elf_Internal_Rela outrel;
11710 }
11711 else
11715 }
11718 {
11724 }
11725 else
11726 {
11734 }
11735 }
11746 {
11754 {
11759 h)
11762 {
11765 }
11769 }
11770 else
11771 {
11775 {
11778 input_bfd,
11780 r_symndx);
11782 }
11786 }
11788 /* Linker relaxations happens from one of the
11789 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
11797 else
11798 {
11800 Elf_Internal_Rela outrel;
11803 /* The GOT entries have not been initialized yet. Do it
11804 now, and emit any relocations. If both an IE GOT and a
11805 GD GOT are necessary, we emit the GD first. */
11812 {
11815 }
11818 {
11821 /* We should have relaxed, unless this is an undefined
11822 weak symbol. */
11831 + offplt
11843 /* For globals, the first word in the relocation gets
11844 the relocation index and the top bit set, or zero,
11845 if we're binding now. For locals, it gets the
11846 symbol's offset in the tls section. */
11854 /* Second word in the relocation is always zero. */
11858 }
11860 {
11862 {
11878 else
11879 {
11882 R_ARM_TLS_DTPOFF32);
11891 }
11892 }
11893 else
11894 {
11895 /* If we are not emitting relocations for a
11896 general dynamic reference, then we must be in a
11897 static link or an executable link with the
11898 symbol binding locally. Mark it as belonging
11899 to module 1, the executable. */
11904 }
11907 }
11910 {
11912 {
11915 else
11927 }
11928 else
11932 }
11936 else
11938 }
11947 {
11948 bfd_signed_vma offset;
11949 /* TLS stubs are arm mode. The original symbol is a
11950 data object, so branch_type is bogus. */
11952 enum elf32_arm_stub_type stub_type
11960 {
11962 = elf32_arm_get_stub_entry
11968 }
11969 else
11975 {
11985 }
11986 else
11987 {
11988 /* Thumb blx encodes the offset in a complicated
11989 fashion. */
11999 {
12001 }
12002 else
12003 {
12005 /* Round up the offset to a word boundary. */
12007 }
12019 }
12020 }
12021 /* These relocations needs special care, as besides the fact
12022 they point somewhere in .gotplt, the addend must be
12023 adjusted accordingly depending on the type of instruction
12024 we refer to. */
12026 {
12035 {
12042 /* bl/blx */
12045 /* add */
12047 else
12048 {
12049 _bfd_error_handler
12050 /* xgettext:c-format */
12052 "unexpected %s instruction '%#lx' "
12057 }
12058 }
12059 else
12060 {
12064 {
12075 _bfd_error_handler
12076 /* xgettext:c-format */
12078 "unexpected %s instruction '%#lx' "
12083 }
12084 }
12092 }
12093 else
12101 {
12102 /* For FDPIC relocations, resolve to the offset of the GOT
12103 entry from the start of GOT. */
12109 }
12110 else
12111 {
12115 }
12116 }
12120 {
12121 _bfd_error_handler
12122 /* xgettext:c-format */
12127 }
12128 else
12137 {
12140 /* Ensure that we have a BX instruction. */
12144 {
12145 /* Branch to veneer. */
12146 bfd_vma glue_addr;
12153 }
12154 else
12155 {
12156 /* Preserve Rm (lowest four bits) and the condition code
12157 (highest four bits). Other bits encode MOV PC,Rm. */
12159 }
12162 }
12169 /* Until we properly support segment-base-relative addressing then
12170 we assume the segment base to be zero, as for the group relocations.
12171 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12172 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12176 {
12180 {
12183 }
12205 }
12212 /* Until we properly support segment-base-relative addressing then
12213 we assume the segment base to be zero, as for the above relocations.
12214 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12215 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12216 as R_ARM_THM_MOVT_ABS. */
12220 {
12221 bfd_vma insn;
12227 {
12233 }
12259 }
12272 {
12276 /* sb is the origin of the *segment* containing the symbol. */
12278 bfd_vma residual;
12279 bfd_vma g_n;
12280 bfd_signed_vma signed_value;
12283 /* Determine which group of bits to select. */
12285 {
12307 }
12309 /* If REL, extract the addend from the insn. If RELA, it will
12310 have already been fetched for us. */
12312 {
12319 else
12320 {
12321 /* Compensate for the fact that in the instruction, the
12322 rotation is stored in multiples of 2 bits. */
12325 /* Rotate "constant" right by "rotation" bits. */
12328 }
12330 /* Determine if the instruction is an ADD or a SUB.
12331 (For REL, this determines the sign of the addend.) */
12334 {
12335 _bfd_error_handler
12336 /* xgettext:c-format */
12341 }
12344 }
12346 /* Compute the value (X) to go in the place. */
12352 /* PC relative. */
12354 else
12355 /* Section base relative. */
12358 /* If the target symbol is a Thumb function, then set the
12359 Thumb bit in the address. */
12363 /* Calculate the value of the relevant G_n, in encoded
12364 constant-with-rotation format. */
12368 /* Check for overflow if required. */
12375 {
12376 _bfd_error_handler
12377 /* xgettext:c-format */
12384 }
12386 /* Mask out the value and the ADD/SUB part of the opcode; take care
12387 not to destroy the S bit. */
12390 /* Set the opcode according to whether the value to go in the
12391 place is negative. */
12394 else
12397 /* Encode the offset. */
12401 }
12410 {
12414 /* sb is the origin of the *segment* containing the symbol. */
12416 bfd_vma residual;
12417 bfd_signed_vma signed_value;
12420 /* Determine which groups of bits to calculate. */
12422 {
12440 }
12442 /* If REL, extract the addend from the insn. If RELA, it will
12443 have already been fetched for us. */
12445 {
12448 }
12450 /* Compute the value (X) to go in the place. */
12454 /* PC relative. */
12456 else
12457 /* Section base relative. */
12460 /* Calculate the value of the relevant G_{n-1} to obtain
12461 the residual at that stage. */
12465 /* Check for overflow. */
12467 {
12468 _bfd_error_handler
12469 /* xgettext:c-format */
12476 }
12478 /* Mask out the value and U bit. */
12481 /* Set the U bit if the value to go in the place is non-negative. */
12485 /* Encode the offset. */
12489 }
12498 {
12502 /* sb is the origin of the *segment* containing the symbol. */
12504 bfd_vma residual;
12505 bfd_signed_vma signed_value;
12508 /* Determine which groups of bits to calculate. */
12510 {
12528 }
12530 /* If REL, extract the addend from the insn. If RELA, it will
12531 have already been fetched for us. */
12533 {
12536 }
12538 /* Compute the value (X) to go in the place. */
12542 /* PC relative. */
12544 else
12545 /* Section base relative. */
12548 /* Calculate the value of the relevant G_{n-1} to obtain
12549 the residual at that stage. */
12553 /* Check for overflow. */
12555 {
12556 _bfd_error_handler
12557 /* xgettext:c-format */
12564 }
12566 /* Mask out the value and U bit. */
12569 /* Set the U bit if the value to go in the place is non-negative. */
12573 /* Encode the offset. */
12577 }
12586 {
12590 /* sb is the origin of the *segment* containing the symbol. */
12592 bfd_vma residual;
12593 bfd_signed_vma signed_value;
12596 /* Determine which groups of bits to calculate. */
12598 {
12616 }
12618 /* If REL, extract the addend from the insn. If RELA, it will
12619 have already been fetched for us. */
12621 {
12624 }
12626 /* Compute the value (X) to go in the place. */
12630 /* PC relative. */
12632 else
12633 /* Section base relative. */
12636 /* Calculate the value of the relevant G_{n-1} to obtain
12637 the residual at that stage. */
12641 /* Check for overflow. (The absolute value to go in the place must be
12642 divisible by four and, after having been divided by four, must
12643 fit in eight bits.) */
12645 {
12646 _bfd_error_handler
12647 /* xgettext:c-format */
12654 }
12656 /* Mask out the value and U bit. */
12659 /* Set the U bit if the value to go in the place is non-negative. */
12663 /* Encode the offset. */
12667 }
12674 {
12680 /* Compute address. */
12686 /* Clean imm8 insn. */
12688 /* And update with correct part of address. */
12690 /* Update insn. */
12692 }
12698 {
12700 {
12705 {
12708 }
12715 {
12718 }
12720 /* Resolve relocation. */
12723 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12724 not done yet. */
12728 }
12729 else
12730 {
12733 bfd_vma addr;
12736 /* For static binaries, sym_sec can be null. */
12738 {
12741 }
12742 else
12743 {
12746 }
12749 {
12752 }
12754 /* This case cannot occur since funcdesc is allocated by
12755 the dynamic loader so we cannot resolve the relocation. */
12757 {
12760 }
12762 /* Resolve relocation. */
12765 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12769 }
12770 }
12775 {
12777 {
12778 Elf_Internal_Rela outrel;
12780 /* Resolve relocation. */
12784 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12786 {
12789 bfd_vma addr;
12792 /* For static binaries sym_sec can be null. */
12794 {
12797 }
12798 else
12799 {
12802 }
12804 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12808 }
12810 /* Add a dynamic relocation on GOT entry if not already done. */
12812 {
12814 {
12819 else
12823 sgot->contents
12825 }
12826 else
12827 {
12829 }
12837 else
12840 else
12843 }
12844 }
12845 else
12846 {
12847 /* Such relocation on static function should not have been
12848 emitted by the compiler. */
12850 }
12851 }
12856 {
12858 {
12860 Elf_Internal_Rela outrel;
12864 {
12867 }
12874 {
12877 }
12879 /* Replace static FUNCDESC relocation with a
12880 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12881 executable. */
12888 else
12894 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12898 }
12899 else
12900 {
12902 {
12905 bfd_vma addr;
12907 Elf_Internal_Rela outrel;
12909 /* For static binaries sym_sec can be null. */
12911 {
12914 }
12915 else
12916 {
12919 }
12924 /* Replace static FUNCDESC relocation with a
12925 R_ARM_RELATIVE dynamic relocation. */
12932 else
12938 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12942 }
12943 else
12944 {
12945 Elf_Internal_Rela outrel;
12947 /* Add a dynamic relocation. */
12953 }
12954 }
12955 }
12960 {
12961 bfd_vma relocation;
12966 {
12974 /* Sign extend. */
12976 }
12983 /* Put RELOCATION back into the insn. */
12984 {
12991 }
12993 /* Put the relocated value back in the object file: */
12998 }
13001 {
13002 bfd_vma relocation;
13007 {
13015 /* Sign extend. */
13018 }
13025 /* Put RELOCATION back into the insn. */
13026 {
13033 }
13035 /* Put the relocated value back in the object file: */
13040 }
13043 {
13044 bfd_vma relocation;
13049 {
13057 /* Sign extend. */
13060 }
13067 /* Put RELOCATION back into the insn. */
13068 {
13075 }
13077 /* Put the relocated value back in the object file: */
13082 }
13086 }
13087 }
13089 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13090 static void
13094 bfd_signed_vma increment)
13095 {
13096 bfd_signed_vma addend;
13100 {
13118 }
13119 else
13120 {
13121 bfd_vma contents;
13125 /* Get the (signed) value from the instruction. */
13128 {
13129 bfd_signed_vma mask;
13134 }
13136 /* Add in the increment, (which is a byte value). */
13138 {
13150 /* Should we check for overflow here ? */
13152 /* Drop any undesired bits. */
13155 }
13160 }
13161 }
13163 #define IS_ARM_TLS_RELOC(R_TYPE) \
13164 ((R_TYPE) == R_ARM_TLS_GD32 \
13165 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
13166 || (R_TYPE) == R_ARM_TLS_LDO32 \
13167 || (R_TYPE) == R_ARM_TLS_LDM32 \
13168 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
13169 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13170 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13171 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13172 || (R_TYPE) == R_ARM_TLS_LE32 \
13173 || (R_TYPE) == R_ARM_TLS_IE32 \
13174 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
13175 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13177 /* Specific set of relocations for the gnu tls dialect. */
13178 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13179 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13180 || (R_TYPE) == R_ARM_TLS_CALL \
13181 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13182 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13183 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
13185 /* Relocate an ARM ELF section. */
13187 static int
13196 {
13214 {
13221 bfd_vma relocation;
13222 bfd_reloc_status_type r;
13223 arelent bfd_reloc;
13246 {
13251 /* An object file might have a reference to a local
13252 undefined symbol. This is a daft object file, but we
13253 should at least do something about it. V4BX & NONE
13254 relocations do not use the symbol and are explicitly
13255 allowed to use the undefined symbol, so allow those.
13256 Likewise for relocations against STN_UNDEF. */
13269 {
13276 {
13281 {
13303 {
13304 _bfd_error_handler
13305 /* xgettext:c-format */
13311 }
13315 /* Get the (signed) value from the instruction. */
13318 {
13319 bfd_signed_vma mask;
13324 }
13326 }
13329 addend =
13334 /* Cases here must match those in the preceding
13335 switch statement. */
13337 {
13360 }
13361 }
13362 }
13363 else
13365 }
13366 else
13367 {
13376 }
13383 {
13384 /* This is a relocatable link. We don't have to change
13385 anything, unless the reloc is against a section symbol,
13386 in which case we have to adjust according to where the
13387 section symbol winds up in the output section. */
13389 {
13393 else
13395 }
13397 }
13401 else
13402 {
13403 name = (bfd_elf_string_from_elf_section
13407 }
13415 {
13416 _bfd_error_handler
13418 /* xgettext:c-format */
13420 /* xgettext:c-format */
13422 input_bfd,
13423 input_section,
13426 name);
13427 }
13429 /* We call elf32_arm_final_link_relocate unless we're completely
13430 done, i.e., the relaxation produced the final output we want,
13431 and we won't let anybody mess with it. Also, we have to do
13432 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
13433 both in relaxed and non-relaxed cases. */
13439 {
13442 /* This may have been marked unresolved because it came from
13443 a shared library. But we've just dealt with that. */
13445 }
13446 else
13450 {
13461 }
13463 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13464 because such sections are not SEC_ALLOC and thus ld.so will
13465 not process them. */
13471 {
13472 _bfd_error_handler
13473 /* xgettext:c-format */
13476 input_bfd,
13477 input_section,
13482 }
13485 {
13487 {
13489 /* If the overflowing reloc was to an undefined symbol,
13490 we have already printed one error message and there
13491 is no point complaining again. */
13512 /* error_message should already be set. */
13517 /* Fall through. */
13519 common_error:
13524 }
13525 }
13526 }
13529 }
13531 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
13532 adds the edit to the start of the list. (The list must be built in order of
13533 ascending TINDEX: the function's callers are primarily responsible for
13534 maintaining that condition). */
13536 static void
13539 arm_unwind_edit_type type,
13542 {
13551 {
13561 }
13562 else
13563 {
13570 }
13571 }
13575 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13577 static void
13579 {
13587 /* Adjust size of output section. */
13589 }
13591 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13593 static void
13595 {
13599 add_unwind_table_edit
13607 }
13609 /* Scan .ARM.exidx tables, and create a list describing edits which should be
13610 made to those tables, such that:
13612 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13613 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
13614 codes which have been inlined into the index).
13616 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13618 The edits are applied when the tables are written
13619 (in elf32_arm_write_section). */
13621 bool
13626 {
13633 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13634 text sections. */
13636 {
13640 {
13648 {
13649 Elf_Internal_Shdr *linked_hdr
13657 /* Link this .ARM.exidx section back from the text section it
13658 describes. */
13660 }
13661 }
13662 }
13664 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13665 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
13666 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
13669 {
13676 bfd_vma j;
13687 {
13688 /* Section has no unwind data. */
13692 /* Ignore zero sized sections. */
13699 }
13701 /* Skip /DISCARD/ sections. */
13718 /* An error? */
13722 {
13724 /* Add cantunwind if first unwind item does not match section
13725 start. */
13727 {
13730 }
13731 }
13734 {
13739 /* An EXIDX_CANTUNWIND entry. */
13741 {
13745 }
13746 /* Inlined unwinding data. Merge if equal to previous. */
13748 {
13754 }
13755 /* Normal table entry. In theory we could merge these too,
13756 but duplicate entries are likely to be much less common. */
13757 else
13761 {
13766 }
13769 }
13771 /* Free contents if we allocated it ourselves. */
13775 /* Record edits to be applied later (in elf32_arm_write_section). */
13784 }
13786 /* Add terminating CANTUNWIND entry. */
13792 }
13794 static bool
13797 {
13813 }
13815 static bool
13817 {
13824 /* Invoke the regular ELF backend linker to do all the work. */
13828 /* Process stub sections (eg BE8 encoding, ...). */
13832 {
13834 /* Only process it once, in its link_sec slot. */
13836 {
13842 }
13843 }
13845 /* Write out any glue sections now that we have created all the
13846 stubs. */
13848 {
13851 ARM2THUMB_GLUE_SECTION_NAME))
13856 THUMB2ARM_GLUE_SECTION_NAME))
13861 VFP11_ERRATUM_VENEER_SECTION_NAME))
13866 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13871 ARM_BX_GLUE_SECTION_NAME))
13873 }
13876 }
13878 /* Return a best guess for the machine number based on the attributes. */
13880 static unsigned int
13882 {
13886 {
13893 {
13900 {
13908 {
13914 {
13918 }
13919 }
13920 }
13923 }
13957 /* Force entry to be added for any new known Tag_CPU_arch value. */
13960 /* Unknown Tag_CPU_arch value. */
13962 }
13963 }
13965 /* Set the right machine number. */
13967 static bool
13969 {
13979 }
13981 /* Function to keep ARM specific flags in the ELF header. */
13983 static bool
13985 {
13988 {
13990 {
13992 _bfd_error_handler
13993 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
13994 abfd);
13995 else
13996 _bfd_error_handler
13998 abfd);
13999 }
14000 }
14001 else
14002 {
14005 }
14008 }
14010 /* Copy backend specific data from one object module to another. */
14012 static bool
14014 {
14015 flagword in_flags;
14016 flagword out_flags;
14027 {
14028 /* Cannot mix APCS26 and APCS32 code. */
14032 /* Cannot mix float APCS and non-float APCS code. */
14036 /* If the src and dest have different interworking flags
14037 then turn off the interworking bit. */
14039 {
14041 _bfd_error_handler
14042 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
14046 }
14048 /* Likewise for PIC, though don't warn for this case. */
14051 }
14057 }
14059 /* Values for Tag_ABI_PCS_R9_use. */
14060 enum
14061 {
14062 AEABI_R9_V6,
14063 AEABI_R9_SB,
14064 AEABI_R9_TLS,
14065 AEABI_R9_unused
14066 };
14068 /* Values for Tag_ABI_PCS_RW_data. */
14069 enum
14070 {
14071 AEABI_PCS_RW_data_absolute,
14072 AEABI_PCS_RW_data_PCrel,
14073 AEABI_PCS_RW_data_SBrel,
14074 AEABI_PCS_RW_data_unused
14075 };
14077 /* Values for Tag_ABI_enum_size. */
14078 enum
14079 {
14080 AEABI_enum_unused,
14081 AEABI_enum_short,
14082 AEABI_enum_wide,
14083 AEABI_enum_forced_wide
14084 };
14086 /* Determine whether an object attribute tag takes an integer, a
14087 string or both. */
14089 static int
14091 {
14100 else
14102 }
14104 /* The ABI defines that Tag_conformance should be emitted first, and that
14105 Tag_nodefaults should be second (if either is defined). This sets those
14106 two positions, and bumps up the position of all the remaining tags to
14107 compensate. */
14108 static int
14110 {
14120 }
14122 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
14123 static bool
14125 {
14127 {
14128 _bfd_error_handler
14133 }
14134 else
14135 {
14136 _bfd_error_handler
14140 }
14141 }
14143 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
14144 Returns -1 if no architecture could be read. */
14146 static int
14148 {
14152 /* Note: the tag and its argument below are uleb128 values, though
14153 currently-defined values fit in one byte for each. */
14160 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14162 }
14164 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14165 The tag is removed if ARCH is -1. */
14167 static void
14169 {
14174 {
14177 }
14179 /* Note: the tag and its argument below are uleb128 values, though
14180 currently-defined values fit in one byte for each. */
14186 }
14188 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14189 into account. */
14191 static int
14194 {
14195 #define T(X) TAG_CPU_ARCH_##X
14198 {
14208 };
14210 {
14221 };
14223 {
14235 };
14237 {
14250 };
14252 {
14266 };
14268 {
14283 };
14285 {
14308 };
14310 {
14327 };
14329 {
14347 };
14349 {
14368 };
14370 {
14393 };
14395 {
14419 };
14421 {
14446 };
14448 {
14449 v6t2,
14450 v6k,
14451 v7,
14452 v6_m,
14453 v6s_m,
14454 v7e_m,
14455 v8,
14456 v8r,
14457 v8m_baseline,
14458 v8m_mainline,
14459 NULL,
14460 NULL,
14461 NULL,
14462 v8_1m_mainline,
14463 v9,
14464 /* Pseudo-architecture. */
14465 v4t_plus_v6_m
14466 };
14468 /* Check we've not got a higher architecture than we know about. */
14471 {
14474 }
14476 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14482 /* And override the new tag if we have a Tag_also_compatible_with on the
14483 input. */
14492 /* Architectures before V6KZ add features monotonically. */
14498 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14499 as the canonical version. */
14501 {
14504 }
14505 else
14509 {
14513 }
14516 #undef T
14517 }
14519 /* Query attributes object to see if integer divide instructions may be
14520 present in an object. */
14521 static bool
14523 {
14528 {
14530 /* Integer divide allowed if instruction contained in archetecture. */
14535 else
14539 /* Integer divide explicitly prohibited. */
14543 /* Unrecognised case - treat as allowing divide everywhere. */
14545 /* Integer divide allowed in ARM state. */
14547 }
14548 }
14550 /* Query attributes object to see if integer divide instructions are
14551 forbidden to be in the object. This is not the inverse of
14552 elf32_arm_attributes_accept_div. */
14553 static bool
14555 {
14557 }
14559 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14560 are conflicting attributes. */
14562 static bool
14564 {
14568 /* Some tags have 0 = don't care, 1 = strong requirement,
14569 2 = weak requirement. */
14575 /* Skip the linker stubs file. This preserves previous behavior
14576 of accepting unknown attributes in the first input file - but
14577 is that a bug? */
14581 /* Skip any input that hasn't attribute section.
14582 This enables to link object files without attribute section with
14583 any others. */
14588 {
14589 /* This is the first object. Copy the attributes. */
14594 /* Use the Tag_null value to indicate the attributes have been
14595 initialized. */
14598 /* We do not output objects with Tag_MPextension_use_legacy - we move
14599 the attribute's value to Tag_MPextension_use. */
14601 {
14605 {
14606 _bfd_error_handler
14610 }
14616 }
14618 /* PR 28859 and 28848: Handle the case where the first input file,
14619 eg crti.o, has a Tag_ABI_HardFP_use of 3 but no Tag_FP_arch set.
14620 Using Tag_ABI_HardFP_use in this way is deprecated, so reset the
14621 attribute to zero.
14622 FIXME: Should we handle other non-zero values of Tag_ABI_HardFO_use ? */
14627 }
14631 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14633 {
14634 /* Ignore mismatches if the object doesn't use floating point or is
14635 floating point ABI independent. */
14642 {
14643 _bfd_error_handler
14648 }
14649 }
14652 {
14653 /* Merge this attribute with existing attributes. */
14655 {
14658 /* These are merged after Tag_CPU_arch. */
14663 /* Use the first value seen. */
14667 {
14672 {
14673 /* These aren't real CPU names, but we can't guess
14674 that from the architecture version alone. */
14698 };
14700 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14706 secondary_compat,
14707 name_table);
14709 /* Return with error if failed to merge. */
14717 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14721 {
14722 /* The output architecture has been changed to match the
14723 input architecture. Use the input names. */
14730 }
14731 else
14732 {
14735 }
14737 /* If we still don't have a value for Tag_CPU_name,
14738 make one up now. Tag_CPU_raw_name remains blank. */
14743 }
14750 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
14764 /* Use the largest value specified. */
14771 /* Use the smallest value specified. */
14780 {
14781 /* This error message should be enabled once all non-conformant
14782 binaries in the toolchain have had the attributes set
14783 properly.
14784 _bfd_error_handler
14785 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
14786 obfd, ibfd);
14787 result = false; */
14788 }
14789 /* Fall through. */
14792 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14793 value if greater than 2 (for future-proofing). */
14801 /* The virtualization tag effectively stores two bits of
14802 information: the intended use of TrustZone (in bit 0), and the
14803 intended use of Virtualization (in bit 1). */
14808 {
14811 else
14812 {
14813 _bfd_error_handler
14818 }
14819 }
14824 {
14825 /* 0 will merge with anything.
14826 'A' and 'S' merge to 'A'.
14827 'R' and 'S' merge to 'R'.
14828 'M' and 'A|R|S' is an error. */
14837 else
14838 {
14839 _bfd_error_handler
14841 ibfd,
14845 }
14846 }
14850 /* No need to change output value if any of:
14851 - pre (<=) ARMv5T input architecture (do not have DSP)
14852 - M input profile not ARMv7E-M and do not have DSP. */
14858 /* Output value should be 0 if DSP part of architecture, ie.
14859 - post (>=) ARMv5te architecture output
14860 - A, R or S profile output or ARMv7E-M output architecture. */
14867 /* Otherwise, DSP instructions are added and not part of output
14868 architecture. */
14869 else
14874 {
14875 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14876 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14877 when it's 0. It might mean absence of FP hardware if
14878 Tag_FP_arch is zero. */
14880 #define VFP_VERSION_COUNT 9
14881 static const struct
14882 {
14886 {
14896 };
14901 /* If the output has no requirement about FP hardware,
14902 follow the requirement of the input. */
14904 {
14905 /* This assert is still reasonable, we shouldn't
14906 produce the suspicious build attribute
14907 combination (See below for in_attr). */
14913 }
14914 /* If the input has no requirement about FP hardware, do
14915 nothing. */
14917 {
14918 /* We used to assert that Tag_ABI_HardFP_use was
14919 zero here, but we should never assert when
14920 consuming an object file that has suspicious
14921 build attributes. The single precision variant
14922 of 'no FP architecture' is still 'no FP
14923 architecture', so we just ignore the tag in this
14924 case. */
14926 }
14928 /* Both the input and the output have nonzero Tag_FP_arch.
14929 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
14931 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14932 do nothing. */
14935 ;
14936 /* If the input and the output have different Tag_ABI_HardFP_use,
14937 the combination of them is 0 (implied by Tag_FP_arch). */
14942 /* Now we can handle Tag_FP_arch. */
14944 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14945 pick the biggest. */
14948 {
14951 }
14952 /* The output uses the superset of input features
14953 (ISA version) and registers. */
14960 /* This assumes all possible supersets are also a valid
14961 options. */
14963 {
14967 }
14969 }
14975 {
14976 /* It's sometimes ok to mix different configs, so this is only
14977 a warning. */
14978 _bfd_error_handler
14980 }
14986 {
14987 _bfd_error_handler
14990 }
14998 {
14999 _bfd_error_handler
15001 ibfd);
15003 }
15004 /* Use the smallest value specified. */
15011 {
15012 _bfd_error_handler
15013 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
15015 }
15021 {
15024 {
15025 /* The existing object is compatible with anything.
15026 Use whatever requirements the new object has. */
15028 }
15032 {
15043 _bfd_error_handler
15044 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
15046 }
15047 }
15050 /* Aready done. */
15054 {
15055 _bfd_error_handler
15059 }
15062 /* Merged in target-independent code. */
15065 /* This is handled along with Tag_FP_arch. */
15069 {
15071 {
15072 _bfd_error_handler
15076 }
15077 }
15083 /* A value of zero on input means that the divide instruction may
15084 be used if available in the base architecture as specified via
15085 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15086 the user did not want divide instructions. A value of 2
15087 explicitly means that divide instructions were allowed in ARM
15088 and Thumb state. */
15102 /* We don't output objects with Tag_MPextension_use_legacy - we
15103 move the value to Tag_MPextension_use. */
15105 {
15107 {
15108 _bfd_error_handler
15111 ibfd);
15113 }
15114 }
15122 /* This tag is set if it exists, but the value is unused (and is
15123 typically zero). We don't actually need to do anything here -
15124 the merge happens automatically when the type flags are merged
15125 below. */
15128 /* Already done in Tag_CPU_arch. */
15131 /* Keep the attribute if it matches. Throw it away otherwise.
15132 No attribute means no claim to conform. */
15139 result
15141 }
15143 /* If out_attr was copied from in_attr then it won't have a type yet. */
15146 }
15148 /* Merge Tag_compatibility attributes and any common GNU ones. */
15152 /* Check for any attributes not known on ARM. */
15156 }
15159 /* Return TRUE if the two EABI versions are incompatible. */
15161 static bool
15163 {
15164 /* v4 and v5 are the same spec before and after it was released,
15165 so allow mixing them. */
15171 }
15173 /* Merge backend specific data from an object file to the output
15174 object file when linking. */
15176 static bool
15179 /* Display the flags field. */
15181 static bool
15183 {
15189 /* Print normal ELF private data. */
15193 /* Ignore init flag - it may not be set, despite the flags field
15194 containing valid data. */
15199 {
15201 /* The following flag bits are GNU extensions and not part of the
15202 official ARM ELF extended ABI. Hence they are only decoded if
15203 the EABI version is not set. */
15209 else
15214 else
15242 else
15253 else
15285 eabi:
15298 }
15319 }
15321 static int
15323 {
15325 {
15330 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15331 This allows us to distinguish between data used by Thumb instructions
15332 and non-data (which is probably code) inside Thumb regions of an
15333 executable. */
15340 }
15343 }
15351 {
15354 {
15358 }
15361 }
15363 /* Look through the relocs for a section during the first phase. */
15365 static bool
15368 {
15405 {
15417 /* PR 9934: It is possible to have relocations that do not
15418 refer to symbols, thus it is also possible to have an
15419 object file containing relocations but no symbol table. */
15421 {
15423 r_symndx);
15425 }
15430 {
15432 {
15433 /* A local symbol. */
15438 }
15439 else
15440 {
15445 }
15446 }
15454 /* Could be done earlier, if h were already available. */
15457 {
15459 {
15461 {
15468 }
15469 else
15470 {
15472 }
15473 }
15477 {
15479 {
15480 /* Such a relocation is not supposed to be generated
15481 by gcc on a static function. */
15482 /* Anyway if needed it could be handled. */
15484 }
15485 else
15486 {
15488 }
15489 }
15493 {
15495 {
15502 }
15503 else
15504 {
15506 }
15507 }
15521 /* This symbol requires a global offset table entry. */
15522 {
15526 {
15539 }
15545 {
15548 }
15549 else
15550 {
15551 /* This is a global offset table entry for a local symbol. */
15555 {
15557 r_symndx);
15559 }
15563 }
15565 /* If a variable is accessed with both tls methods, two
15566 slots may be created. */
15571 /* We will already have issued an error message if there
15572 is a TLS/non-TLS mismatch, based on the symbol
15573 type. So just combine any TLS types needed. */
15578 /* If the symbol is accessed in both IE and GDESC
15579 method, we're able to relax. Turn off the GDESC flag,
15580 without messing up with any other kind of tls types
15581 that may be involved. */
15586 {
15589 else
15591 }
15592 }
15593 /* Fall through. */
15599 /* Fall through. */
15621 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15622 ldr __GOTT_INDEX__ offsets. */
15624 {
15627 }
15630 /* Fall through. */
15637 {
15638 _bfd_error_handler
15639 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
15644 }
15646 /* Fall through. */
15649 jump_over:
15651 {
15653 }
15654 /* Fall through. */
15662 /* Should the interworking branches be listed here? */
15666 {
15669 {
15670 /* In shared libraries and relocatable executables,
15671 we treat local relative references as calls;
15672 see the related SYMBOL_CALLS_LOCAL code in
15673 allocate_dynrelocs. */
15676 }
15677 else
15678 /* We are creating a shared library or relocatable
15679 executable, and this is a reloc against a global symbol,
15680 or a non-PC-relative reloc against a local symbol.
15681 We may need to copy the reloc into the output. */
15683 }
15684 else
15688 /* This relocation describes the C++ object vtable hierarchy.
15689 Reconstruct it for later use during GC. */
15695 /* This relocation describes which C++ vtable entries are actually
15696 used. Record for later use during GC. */
15701 }
15704 {
15706 /* We may need a .plt entry if the function this reloc
15707 refers to is in a different object, regardless of the
15708 symbol's type. We can't tell for sure yet, because
15709 something later might force the symbol local. */
15712 /* If this reloc is in a read-only section, we might
15713 need a copy reloc. We can't check reliably at this
15714 stage whether the section is read-only, as input
15715 sections have not yet been mapped to output sections.
15716 Tentatively set the flag for now, and correct in
15717 adjust_dynamic_symbol. */
15719 }
15723 {
15729 {
15732 }
15733 else
15734 {
15740 }
15742 /* If the symbol is a function that doesn't bind locally,
15743 this relocation will need a PLT entry. */
15750 /* It's too early to use htab->use_blx here, so we have to
15751 record possible blx references separately from
15752 relocs that definitely need a thumb stub. */
15760 }
15763 {
15766 /* Create a reloc section in dynobj. */
15768 {
15769 sreloc = _bfd_elf_make_dynamic_reloc_section
15774 }
15776 /* If this is a global symbol, count the number of
15777 relocations we need for this symbol. */
15780 else
15781 {
15785 }
15789 {
15800 }
15807 {
15808 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15809 that will become rofixup. */
15810 /* This is due to the fact that we suppose all will become rofixup. */
15811 _bfd_error_handler
15816 }
15817 }
15818 }
15821 }
15823 static void
15826 {
15848 {
15851 }
15853 {
15856 }
15857 else
15869 {
15872 {
15875 irela++;
15876 count++;
15877 }
15879 {
15883 bfd_size_type j;
15884 bfd_vma offset;
15900 else
15904 {
15906 {
15908 bfd_vma bias;
15909 bfd_vma reloc_index;
15919 {
15920 bias++;
15922 }
15926 {
15928 irela++;
15929 count++;
15930 }
15933 }
15936 {
15937 /* New relocation entity. */
15946 irela++;
15947 count++;
15948 }
15949 }
15950 else
15951 {
15953 {
15956 irela++;
15957 }
15960 }
15961 }
15962 }
15970 {
15973 irela++;
15974 count--;
15975 }
15979 /* Hashes are no longer valid. */
15982 }
15984 /* Unwinding tables are not referenced directly. This pass marks them as
15985 required if the corresponding code section is marked. Similarly, ARMv8-M
15986 secure entry functions can only be referenced by SG veneers which are
15987 created after the GC process. They need to be marked in case they reside in
15988 their own section (as would be the case if code was compiled with
15989 -ffunction-sections). */
15991 static bool
15993 elf_gc_mark_hook_fn gc_mark_hook)
15994 {
16014 /* Marking EH data may cause additional code sections to be marked,
16015 requiring multiple passes. */
16018 {
16021 {
16029 {
16038 {
16042 }
16043 }
16045 /* Mark section holding ARMv8-M secure entry functions. We mark all
16046 of them so no need for a second browsing. */
16048 {
16057 /* Scan symbols. */
16059 {
16064 /* Assume it is a special symbol. If not, cmse_scan will
16065 warn about it and user can do something about it. */
16067 CMSE_PREFIX))
16068 {
16073 /* The debug sections related to these secure entry
16074 functions are marked on enabling below flag. */
16076 }
16077 }
16080 {
16081 /* Looping over all the sections of the object file containing
16082 Armv8-M secure entry functions and marking all the debug
16083 sections. */
16085 {
16086 /* If not a debug sections, skip it. */
16088 {
16091 }
16092 }
16094 }
16095 }
16096 }
16099 }
16101 /* PR 30354: If we have added extra marks then make sure that any
16102 dependencies of the newly marked sections are also marked. */
16107 }
16109 /* Treat mapping symbols as special target symbols. */
16111 static bool
16113 {
16115 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
16116 }
16118 /* If the ELF symbol SYM might be a function in SEC, return the
16119 function size and set *CODE_OFF to the function's entry point,
16120 otherwise return zero. */
16122 static bfd_size_type
16125 {
16126 bfd_size_type size;
16138 {
16140 /* Ignore symbols created by the annobin plugin for gcc and clang.
16141 These symbols are hidden, local, notype and have a size of 0. */
16146 /* Fall through. */
16149 /* FIXME: Allow STT_GNU_IFUNC as well ? */
16153 }
16157 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16162 /* Do not return 0 for the function's size. */
16165 }
16167 static bool
16172 {
16178 }
16180 /* Adjust a symbol defined by a dynamic object and referenced by a
16181 regular object. The current definition is in some section of the
16182 dynamic object, but we're not including those sections. We have to
16183 change the definition to something the rest of the link can
16184 understand. */
16186 static bool
16189 {
16201 /* Make sure we know what is going on here. */
16212 /* If this is a function, put it in the procedure linkage table. We
16213 will fill in the contents of the procedure linkage table later,
16214 when we know the address of the .got section. */
16216 {
16217 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16218 symbol binds locally. */
16224 {
16225 /* This case can occur if we saw a PLT32 reloc in an input
16226 file, but the symbol was never referred to by a dynamic
16227 object, or if all references were garbage collected. In
16228 such a case, we don't actually need to build a procedure
16229 linkage table, and we can just do a PC24 reloc instead. */
16235 }
16238 }
16239 else
16240 {
16241 /* It's possible that we incorrectly decided a .plt reloc was
16242 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16243 in check_relocs. We can't decide accurately between function
16244 and non-function syms in check-relocs; Objects loaded later in
16245 the link may change h->type. So fix it now. */
16250 }
16252 /* If this is a weak symbol, and there is a real definition, the
16253 processor independent code will have arranged for us to see the
16254 real definition first, and we can just use the same value. */
16256 {
16262 }
16264 /* If there are no non-GOT references, we do not need a copy
16265 relocation. */
16269 /* This is a reference to a symbol defined by a dynamic object which
16270 is not a function. */
16272 /* If we are creating a shared library, we must presume that the
16273 only references to the symbol are via the global offset table.
16274 For such cases we need not do anything here; the relocations will
16275 be handled correctly by relocate_section. */
16279 /* We must allocate the symbol in our .dynbss section, which will
16280 become part of the .bss section of the executable. There will be
16281 an entry for this symbol in the .dynsym section. The dynamic
16282 object will contain position independent code, so all references
16283 from the dynamic object to this symbol will go through the global
16284 offset table. The dynamic linker will use the .dynsym entry to
16285 determine the address it must put in the global offset table, so
16286 both the dynamic object and the regular object will refer to the
16287 same memory location for the variable. */
16288 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16289 linker to copy the initial value out of the dynamic object and into
16290 the runtime process image. We need to remember the offset into the
16291 .rel(a).bss section we are going to use. */
16293 {
16296 }
16297 else
16298 {
16301 }
16305 {
16308 }
16311 }
16313 /* Allocate space in .plt, .got and associated reloc sections for
16314 dynamic relocs. */
16316 static bool
16318 {
16336 {
16337 /* Make sure this symbol is output as a dynamic symbol.
16338 Undefined weak syms won't yet be marked as dynamic. */
16341 {
16344 }
16346 /* If the call in the PLT entry binds locally, the associated
16347 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16348 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16349 than the .plt section. */
16351 {
16355 /* All non-call references can be resolved directly.
16356 This means that they can (and in some cases, must)
16357 resolve directly to the run-time target, rather than
16358 to the PLT. That in turns means that any .got entry
16359 would be equal to the .igot.plt entry, so there's
16360 no point having both. */
16362 }
16367 {
16370 /* If this symbol is not defined in a regular file, and we are
16371 not generating a shared library, then set the symbol to this
16372 location in the .plt. This is required to make function
16373 pointers compare as equal between the normal executable and
16374 the shared library. */
16377 {
16381 /* Make sure the function is not marked as Thumb, in case
16382 it is the target of an ABS32 relocation, which will
16383 point to the PLT entry. */
16385 }
16387 /* VxWorks executables have a second set of relocations for
16388 each PLT entry. They go in a separate relocation section,
16389 which is processed by the kernel loader. */
16391 {
16392 /* There is a relocation for the initial PLT entry:
16393 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16397 /* There are two extra relocations for each subsequent
16398 PLT entry: an R_ARM_32 relocation for the GOT entry,
16399 and an R_ARM_32 relocation for the PLT entry. */
16401 }
16402 }
16403 else
16404 {
16407 }
16408 }
16409 else
16410 {
16413 }
16419 {
16425 /* Make sure this symbol is output as a dynamic symbol.
16426 Undefined weak syms won't yet be marked as dynamic. */
16431 {
16434 }
16443 /* Non-TLS symbols need one GOT slot. */
16445 else
16446 {
16448 {
16449 /* R_ARM_TLS_DESC needs 2 GOT slots. */
16450 eh->tlsdesc_got
16455 /* plt.got_offset needs to know there's a TLS_DESC
16456 reloc in the middle of .got.plt. */
16458 }
16461 {
16462 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16463 consecutive GOT slots. If the symbol is both GD
16464 and GDESC, got.offset may have been
16465 overwritten. */
16468 }
16471 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16472 slot. */
16474 }
16488 {
16496 {
16498 /* GDESC needs a trampoline to jump to. */
16500 }
16502 /* Only GD needs it. GDESC just emits one relocation per
16503 2 entries. */
16506 }
16509 {
16511 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16513 }
16516 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16517 they all resolve dynamically instead. Reserve room for the
16518 GOT entry's R_ARM_IRELATIVE relocation. */
16522 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
16525 /* Reserve room for rofixup for FDPIC executable. */
16526 /* TLS relocs do not need space since they are completely
16527 resolved. */
16529 }
16530 else
16533 /* FDPIC support. */
16535 {
16536 /* Symbol musn't be exported. */
16540 /* We only allocate one function descriptor with its associated
16541 relocation. */
16543 {
16548 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16551 else
16553 }
16554 }
16557 {
16566 {
16567 /* We only allocate one function descriptor with its
16568 associated relocation. */
16570 {
16574 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two
16575 rofixups. */
16578 else
16580 }
16581 }
16583 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16584 R_ARM_RELATIVE/rofixup relocation on it. */
16589 else
16591 }
16594 {
16601 {
16602 /* We only allocate one function descriptor with its
16603 associated relocation. */
16605 {
16610 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two
16611 rofixups. */
16614 else
16616 }
16617 }
16619 {
16620 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16622 }
16623 else
16624 {
16625 /* Will need one dynamic reloc per reference. will be either
16626 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16629 }
16630 }
16632 /* Allocate stubs for exported Thumb functions on v4t. */
16637 {
16644 /* Create a new symbol to regist the real location of the function. */
16658 /* Point the symbol at the stub. */
16663 }
16668 /* In the shared -Bsymbolic case, discard space allocated for
16669 dynamic pc-relative relocs against symbols which turn out to be
16670 defined in regular objects. For the normal shared case, discard
16671 space for pc-relative relocs that have become local due to symbol
16672 visibility changes. */
16676 {
16677 /* Relocs that use pc_count are PC-relative forms, which will appear
16678 on something like ".long foo - ." or "movw REG, foo - .". We want
16679 calls to protected symbols to resolve directly to the function
16680 rather than going via the plt. If people want function pointer
16681 comparisons to work as expected then they should avoid writing
16682 assembly like ".long foo - .". */
16684 {
16688 {
16693 else
16695 }
16696 }
16699 {
16703 {
16706 else
16708 }
16709 }
16711 /* Also discard relocs on undefined weak syms with non-default
16712 visibility. */
16715 {
16720 /* Make sure undefined weak symbols are output as a dynamic
16721 symbol in PIEs. */
16724 {
16727 }
16728 }
16729 }
16730 else
16731 {
16732 /* For the non-shared case, discard space for relocs against
16733 symbols which turn out to need copy relocs or are not
16734 dynamic. */
16742 {
16743 /* Make sure this symbol is output as a dynamic symbol.
16744 Undefined weak syms won't yet be marked as dynamic. */
16747 {
16750 }
16752 /* If that succeeded, we know we'll be keeping all the
16753 relocs. */
16756 }
16760 keep: ;
16761 }
16763 /* Finally, allocate space. */
16765 {
16777 else
16779 }
16782 }
16784 void
16787 {
16795 }
16797 /* Set the sizes of the dynamic sections. */
16799 static bool
16802 {
16820 {
16821 /* Set the contents of the .interp section to the interpreter. */
16823 {
16828 }
16829 }
16831 /* Set up .got offsets for local syms, and space for local dynamic
16832 relocs. */
16834 {
16840 bfd_size_type locsymcount;
16850 {
16855 {
16858 {
16859 /* Input section has been discarded, either because
16860 it is a copy of a linkonce section or due to
16861 linker script /DISCARD/, so we'll be discarding
16862 the relocs too. */
16863 }
16867 {
16868 /* Relocations in vxworks .tls_vars sections are
16869 handled specially by the loader. */
16870 }
16872 {
16876 else
16880 }
16881 }
16882 }
16901 {
16908 /* FDPIC support. */
16910 {
16912 {
16916 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16919 else
16921 }
16922 }
16925 {
16927 {
16931 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16934 else
16936 }
16938 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16941 else
16943 }
16946 {
16950 {
16955 /* All references to the PLT are calls, so all
16956 non-call references can resolve directly to the
16957 run-time target. This means that the .got entry
16958 would be the same as the .igot.plt entry, so there's
16959 no point creating both. */
16961 }
16962 else
16963 {
16966 }
16969 {
16975 else
16977 }
16978 }
16980 {
16985 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16988 {
16993 /* plt.got_offset needs to know there's a TLS_DESC
16994 reloc in the middle of .got.plt. */
16996 }
17001 {
17002 /* If the symbol is both GD and GDESC, *local_got
17003 may have been overwritten. */
17006 }
17009 symndx);
17013 /* If all references to an STT_GNU_IFUNC PLT are calls,
17014 then all non-call references, including this GOT entry,
17015 resolve directly to the run-time target. */
17021 {
17029 {
17033 }
17034 }
17035 }
17036 else
17038 }
17039 }
17042 {
17043 /* Allocate two GOT entries and one dynamic relocation (if necessary)
17044 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
17049 }
17050 else
17053 /* At the very end of the .rofixup section is a pointer to the GOT,
17054 reserve space for it. */
17058 /* Allocate global sym .plt and .got entries, and space for global
17059 sym dynamic relocs. */
17062 /* Here we rummage through the found bfds to collect glue information. */
17064 {
17068 /* Initialise mapping tables for code/data. */
17075 }
17077 /* Allocate space for the glue sections now that we've sized them. */
17080 /* For every jump slot reserved in the sgotplt, reloc_count is
17081 incremented. However, when we reserve space for TLS descriptors,
17082 it's not incremented, so in order to compute the space reserved
17083 for them, it suffices to multiply the reloc count by the jump
17084 slot size. */
17089 {
17096 /* If we're not using lazy TLS relocations, don't generate the
17097 PLT and GOT entries they require. */
17100 else
17101 {
17107 }
17108 }
17110 /* The check_relocs and adjust_dynamic_symbol entry points have
17111 determined the sizes of the various dynamic sections. Allocate
17112 memory for them. */
17115 {
17121 /* It's OK to base decisions on the section name, because none
17122 of the dynobj section names depend upon the input files. */
17126 {
17127 /* Remember whether there is a PLT. */
17128 ;
17129 }
17131 {
17133 {
17134 /* Remember whether there are any reloc sections other
17135 than .rel(a).plt and .rela.plt.unloaded. */
17139 /* We use the reloc_count field as a counter if we need
17140 to copy relocs into the output file. */
17142 }
17143 }
17151 {
17152 /* It's not one of our sections, so don't allocate space. */
17154 }
17157 {
17158 /* If we don't need this section, strip it from the
17159 output file. This is mostly to handle .rel(a).bss and
17160 .rel(a).plt. We must create both sections in
17161 create_dynamic_sections, because they must be created
17162 before the linker maps input sections to output
17163 sections. The linker does that before
17164 adjust_dynamic_symbol is called, and it is that
17165 function which decides whether anything needs to go
17166 into these sections. */
17169 }
17174 /* Allocate memory for the section contents. */
17178 }
17181 relocs);
17182 }
17184 /* Size sections even though they're not dynamic. We use it to setup
17185 _TLS_MODULE_BASE_, if needed. */
17187 static bool
17189 {
17201 {
17204 tlsbase = elf_link_hash_lookup
17208 {
17224 }
17225 }
17233 }
17235 /* Finish up dynamic symbol handling. We set the contents of various
17236 dynamic sections here. */
17238 static bool
17243 {
17252 {
17254 {
17259 }
17262 {
17263 /* Mark the symbol as undefined, rather than as defined in
17264 the .plt section. */
17266 /* If the symbol is weak we need to clear the value.
17267 Otherwise, the PLT entry would provide a definition for
17268 the symbol even if the symbol wasn't defined anywhere,
17269 and so the symbol would never be NULL. Leave the value if
17270 there were any relocations where pointer equality matters
17271 (this is a clue for the dynamic linker, to make function
17272 pointer comparisons work between an application and shared
17273 library). */
17276 }
17278 {
17279 /* At least one non-call relocation references this .iplt entry,
17280 so the .iplt entry is the function's canonical address. */
17288 }
17289 }
17292 {
17294 Elf_Internal_Rela rel;
17296 /* This symbol needs a copy reloc. Set it up. */
17308 else
17311 }
17313 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
17314 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17315 it is relative to the ".got" section. */
17323 }
17325 static void
17329 {
17333 {
17336 /* Emit mov pc,rx if bx is not permitted. */
17340 }
17341 }
17343 /* Install the special first PLT entry for elf32-arm-nacl. Unlike
17344 other variants, NaCl needs this entry in a static executable's
17345 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17346 zero. For .iplt really only the last bundle is useful, and .iplt
17347 could have a shorter first entry, with each individual PLT entry's
17348 relative branch calculated differently so it targets the last
17349 bundle instead of the instruction before it (labelled .Lplt_tail
17350 above). But it's simpler to keep the size and layout of PLT0
17351 consistent with the dynamic case, at the cost of some dead code at
17352 the start of .iplt and the one dead store to the stack at the start
17353 of .Lplt_tail. */
17354 static void
17357 {
17373 }
17375 /* Finish up the dynamic sections. */
17377 static bool
17379 {
17392 /* A broken linker script might have discarded the dynamic sections.
17393 Catch this here so that we do not seg-fault later on. */
17399 {
17411 {
17412 Elf_Internal_Dyn dyn;
17419 {
17439 get_vma:
17442 {
17443 _bfd_error_handler
17447 }
17479 /* Set the bottom bit of DT_INIT/FINI if the
17480 corresponding function is Thumb. */
17486 get_sym:
17487 /* If it wasn't set by elf_bfd_final_link
17488 then there is nothing to adjust. */
17490 {
17498 {
17501 }
17502 }
17504 }
17505 }
17507 /* Fill in the first entry in the procedure linkage table. */
17509 {
17513 /* Calculate the addresses of the GOT and PLT. */
17518 {
17519 /* The VxWorks GOT is relocated by the dynamic linker.
17520 Therefore, we must emit relocations rather than simply
17521 computing the values now. */
17522 Elf_Internal_Rela rel;
17533 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
17539 }
17544 {
17556 }
17557 else
17558 {
17571 #ifdef FOUR_WORD_PLT
17572 /* The displacement value goes in the otherwise-unused
17573 last word of the second entry. */
17575 #else
17577 #endif
17578 }
17579 }
17581 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17582 really seem like the right value. */
17587 {
17588 bfd_vma got_address
17592 bfd_vma plt_address
17608 }
17611 {
17615 #ifdef FOUR_WORD_PLT
17618 #endif
17619 }
17624 {
17625 /* Correct the .rel(a).plt.unloaded relocations. They will have
17626 incorrect symbol indexes. */
17635 {
17636 Elf_Internal_Rela rel;
17647 }
17648 }
17649 }
17654 /* NaCl uses a special first entry in .iplt too. */
17657 /* Fill in the first three entries in the global offset table. */
17659 {
17661 {
17664 else
17670 }
17673 }
17675 /* At the very end of the .rofixup section is a pointer to the GOT. */
17677 {
17686 /* Make sure we allocated and generated the same number of fixups. */
17688 }
17691 }
17693 static bool
17695 {
17710 {
17717 }
17721 {
17725 else
17727 }
17729 /* Scan segment to set p_flags attribute if it contains only sections with
17730 SHF_ARM_PURECODE flag. */
17732 {
17738 {
17741 }
17743 {
17746 }
17747 }
17749 }
17751 static enum elf_reloc_type_class
17755 {
17760 {
17761 /* Check relocation against STT_GNU_IFUNC symbol if there are
17762 dynamic symbols. */
17767 {
17768 Elf_Internal_Sym sym;
17773 {
17774 /* xgettext:c-format */
17778 /* Ideally an error class should be returned here. */
17779 }
17782 }
17783 }
17786 {
17797 }
17798 }
17800 static void
17802 {
17804 }
17806 static bool
17808 {
17811 }
17813 /* Return TRUE if this is an unwinding table entry. */
17815 static bool
17817 {
17820 }
17823 /* Set the type and flags for an ARM section. We do this by
17824 the section name, which is a hack, but ought to work. */
17826 static bool
17828 {
17834 {
17837 }
17843 }
17845 /* Handle an ARM specific section when reading an object file. This is
17846 called when bfd_section_from_shdr finds a section with an unknown
17847 type. */
17849 static bool
17854 {
17855 /* There ought to be a place to keep ELF backend specific flags, but
17856 at the moment there isn't one. We just keep track of the
17857 sections by their name, instead. Fortunately, the ABI gives
17858 names for all the ARM specific sections, so we will probably get
17859 away with this. */
17861 {
17869 }
17875 }
17879 {
17882 else
17884 }
17887 {
17896 enum map_symbol_type
17897 {
17898 ARM_MAP_ARM,
17899 ARM_MAP_THUMB,
17900 ARM_MAP_DATA
17901 };
17904 /* Output a single mapping symbol. */
17906 static bool
17909 bfd_vma offset)
17910 {
17912 Elf_Internal_Sym sym;
17924 }
17926 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17927 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
17929 static bool
17934 {
17946 {
17949 }
17950 else
17951 {
17954 }
17960 {
17969 }
17971 {
17974 }
17976 {
17978 ? ARM_MAP_THUMB
17991 }
17993 {
17996 }
17997 else
17998 {
18003 {
18006 }
18007 #ifdef FOUR_WORD_PLT
18012 #else
18013 /* A three-word PLT with no Thumb thunk contains only Arm code,
18014 so only need to output a mapping symbol for the first PLT entry and
18015 entries with thumb thunks. */
18017 {
18020 }
18021 #endif
18022 }
18025 }
18027 /* Output mapping symbols for PLT entries associated with H. */
18029 static bool
18031 {
18039 /* When warning symbols are created, they **replace** the "real"
18040 entry in the hash table, thus we never get to see the real
18041 symbol in a hash traversal. So look at it now. */
18047 }
18049 /* Bind a veneered symbol to its veneer identified by its hash entry
18050 STUB_ENTRY. The veneered location thus loose its symbol. */
18052 static void
18054 {
18061 }
18063 /* Output a single local symbol for a generated stub. */
18065 static bool
18068 {
18069 Elf_Internal_Sym sym;
18080 }
18082 static bool
18085 {
18088 bfd_vma addr;
18097 /* Massage our args to the form they really have. */
18103 /* Ensure this stub is attached to the current section being
18104 processed. */
18113 else
18114 {
18117 {
18132 }
18133 }
18138 {
18140 {
18157 }
18160 {
18164 }
18167 {
18184 }
18185 }
18188 }
18190 /* Output mapping symbols for linker generated sections,
18191 and for those data-only sections that do not have a
18192 $d. */
18194 static bool
18199 Elf_Internal_Sym *,
18200 asection *,
18202 {
18203 output_arch_syminfo osi;
18205 bfd_vma offset;
18206 bfd_size_type size;
18224 /* Add a $d mapping symbol to data-only sections that
18225 don't have any mapping symbol. This may result in (harmless) redundant
18226 mapping symbols. */
18230 {
18235 {
18240 == SEC_HAS_CONTENTS
18245 {
18250 }
18251 }
18252 }
18254 /* ARM->Thumb glue. */
18256 {
18258 ARM2THUMB_GLUE_SECTION_NAME);
18267 else
18271 {
18274 }
18275 }
18277 /* Thumb->ARM glue. */
18279 {
18281 THUMB2ARM_GLUE_SECTION_NAME);
18288 {
18291 }
18292 }
18294 /* ARMv4 BX veneers. */
18296 {
18298 ARM_BX_GLUE_SECTION_NAME);
18304 }
18306 /* Long calls stubs. */
18308 {
18314 {
18315 /* Ignore non-stub sections. */
18325 }
18326 }
18328 /* Finally, output mapping symbols for the PLT. */
18330 {
18335 /* Output mapping symbols for the plt header. */
18337 {
18338 /* VxWorks shared libraries have no PLT header. */
18340 {
18345 }
18346 }
18348 {
18351 }
18353 {
18360 }
18362 {
18365 #ifndef FOUR_WORD_PLT
18368 #endif
18369 }
18370 }
18374 {
18375 /* NaCl uses a special first entry in .iplt too. */
18381 }
18384 {
18389 {
18395 {
18398 {
18401 input_bfd,
18403 num_syms);
18405 }
18412 }
18413 }
18414 }
18416 {
18417 /* Mapping symbols for the lazy tls trampoline. */
18425 }
18427 {
18428 /* Mapping symbols for the tls trampoline. */
18431 #ifdef FOUR_WORD_PLT
18435 #endif
18436 }
18439 }
18441 /* Filter normal symbols of CMSE entry functions of ABFD to include in
18442 the import library. All SYMCOUNT symbols of ABFD can be examined
18443 from their pointers in SYMS. Pointers of symbols to keep should be
18444 stored continuously at the beginning of that array.
18446 Returns the number of symbols to keep. */
18448 static unsigned int
18452 {
18467 {
18470 flagword flags;
18485 {
18489 }
18501 }
18507 }
18509 /* Filter symbols of ABFD to include in the import library. All
18510 SYMCOUNT symbols of ABFD can be examined from their pointers in
18511 SYMS. Pointers of symbols to keep should be stored continuously at
18512 the beginning of that array.
18514 Returns the number of symbols to keep. */
18516 static unsigned int
18520 {
18523 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18524 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18525 library to be a relocatable object file. */
18529 else
18531 }
18533 /* Allocate target specific section data. */
18535 static bool
18537 {
18539 {
18547 }
18550 }
18553 /* Used to order a list of mapping symbols by address. */
18555 static int
18557 {
18566 /* Ensure results do not depend on the host qsort for objects with
18567 multiple mapping symbols at the same address by sorting on type
18568 after vma. */
18572 else
18574 }
18576 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18578 static unsigned long
18580 {
18582 }
18584 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18585 relocations. */
18587 static void
18589 {
18593 /* High bit of first word is supposed to be zero. */
18597 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18598 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18604 }
18606 /* Data for make_branch_to_a8_stub(). */
18608 struct a8_branch_to_stub_data
18609 {
18612 };
18615 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
18616 places for a particular section. */
18618 static bool
18621 {
18627 bfd_signed_vma branch_offset;
18640 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18641 generated when both source and target are in the same section. */
18658 /* We attempt to avoid this condition by setting stubs_always_after_branch
18659 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18660 This check is just to be on the safe side... */
18662 {
18666 }
18669 {
18680 {
18685 jump24:
18687 {
18688 /* There's not much we can do apart from complain if this
18689 happens. */
18693 }
18695 /* i1 = not(j1 eor s), so:
18696 not i1 = j1 eor s
18697 j1 = (not i1) eor s. */
18709 }
18715 }
18721 }
18723 /* Beginning of stm32l4xx work-around. */
18725 /* Functions encoding instructions necessary for the emission of the
18726 fix-stm32l4xx-629360.
18727 Encoding is extracted from the
18728 ARM (C) Architecture Reference Manual
18729 ARMv7-A and ARMv7-R edition
18730 ARM DDI 0406C.b (ID072512). */
18734 {
18735 /* A8.8.18 B (A8-334)
18736 B target_address (Encoding T4). */
18737 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18738 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18739 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18756 }
18760 {
18761 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18762 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18769 }
18773 {
18774 /* A8.8.60 LDMDB/LDMEA (A8-402)
18775 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18782 }
18786 {
18787 /* A8.8.103 MOV (register) (A8-486)
18788 MOV Rd, Rm (Encoding T1). */
18795 }
18799 {
18800 /* A8.8.221 SUB (immediate) (A8-708)
18801 SUB Rd, Rn, #value (Encoding T3). */
18811 }
18816 {
18817 /* A8.8.332 VLDM (A8-922)
18818 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18827 }
18832 {
18833 /* A8.8.332 VLDM (A8-922)
18834 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18842 }
18846 {
18847 /* A8.8.247 UDF (A8-758)
18848 Undefined (Encoding T2). */
18854 }
18858 {
18859 /* A8.8.247 UDF (A8-758)
18860 Undefined (Encoding T1). */
18865 }
18867 /* Functions writing an instruction in memory, returning the next
18868 memory position to write to. */
18873 {
18876 }
18881 {
18884 }
18886 /* Function filling up a region in memory with T1 and T2 UDFs taking
18887 care of alignment. */
18895 {
18898 /* Fill the remaining of the stub with deterministic contents : UDF
18899 instructions.
18900 Check if realignment is needed on modulo 4 frontier using T1, to
18901 further use T2. */
18905 current_stub_contents =
18910 current_stub_contents =
18915 }
18917 /* Functions writing the stream of instructions equivalent to the
18918 derived sequence for ldmia, ldmdb, vldm respectively. */
18920 static void
18926 {
18939 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18940 smaller than 8 registers load sequences that do not cause the
18941 hardware issue. */
18943 {
18944 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18945 current_stub_contents =
18947 initial_insn);
18949 /* B initial_insn_addr+4. */
18951 current_stub_contents =
18953 create_instruction_branch_absolute
18956 /* Fill the remaining of the stub with deterministic contents. */
18957 current_stub_contents =
18960 base_stub_contents +
18961 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18964 }
18966 /* - reg_list[13] == 0. */
18969 /* - reg_list[14] & reg_list[15] != 1. */
18972 /* - if (wback==1) reg_list[rn] == 0. */
18975 /* - nb_registers > 8. */
18978 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18980 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18981 - One with the 7 lowest registers (register mask 0x007F)
18982 This LDM will finally contain between 2 and 7 registers
18983 - One with the 7 highest registers (register mask 0xDF80)
18984 This ldm will finally contain between 2 and 7 registers. */
18988 /* A spare register may be needed during this veneer to temporarily
18989 handle the base register. This register will be restored with the
18990 last LDM operation.
18991 The usable register may be any general purpose register (that
18992 excludes PC, SP, LR : register mask is 0x1FFF). */
18995 /* Generate the stub function. */
18997 {
18998 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18999 current_stub_contents =
19001 create_instruction_ldmia
19004 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
19005 current_stub_contents =
19007 create_instruction_ldmia
19010 {
19011 /* B initial_insn_addr+4. */
19012 current_stub_contents =
19014 create_instruction_branch_absolute
19016 }
19017 }
19019 {
19022 /* If Rn is not part of the high-register-list, move it there. */
19024 {
19025 /* Choose a Ri in the high-register-list that will be restored. */
19028 /* MOV Ri, Rn. */
19029 current_stub_contents =
19032 }
19034 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
19035 current_stub_contents =
19037 create_instruction_ldmia
19040 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
19041 current_stub_contents =
19043 create_instruction_ldmia
19047 {
19048 /* B initial_insn_addr+4. */
19049 current_stub_contents =
19051 create_instruction_branch_absolute
19053 }
19054 }
19056 /* Fill the remaining of the stub with deterministic contents. */
19057 current_stub_contents =
19060 base_stub_contents +
19061 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19062 }
19064 static void
19070 {
19083 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19084 smaller than 8 registers load sequences that do not cause the
19085 hardware issue. */
19087 {
19088 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19089 current_stub_contents =
19091 initial_insn);
19093 /* B initial_insn_addr+4. */
19094 current_stub_contents =
19096 create_instruction_branch_absolute
19099 /* Fill the remaining of the stub with deterministic contents. */
19100 current_stub_contents =
19103 base_stub_contents +
19104 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19107 }
19109 /* - reg_list[13] == 0. */
19112 /* - reg_list[14] & reg_list[15] != 1. */
19115 /* - if (wback==1) reg_list[rn] == 0. */
19118 /* - nb_registers > 8. */
19121 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19123 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19124 - One with the 7 lowest registers (register mask 0x007F)
19125 This LDM will finally contain between 2 and 7 registers
19126 - One with the 7 highest registers (register mask 0xDF80)
19127 This ldm will finally contain between 2 and 7 registers. */
19131 /* A spare register may be needed during this veneer to temporarily
19132 handle the base register. This register will be restored with
19133 the last LDM operation.
19134 The usable register may be any general purpose register (that excludes
19135 PC, SP, LR : register mask is 0x1FFF). */
19138 /* Generate the stub function. */
19140 {
19141 /* Choose a Ri in the low-register-list that will be restored. */
19144 /* MOV Ri, Rn. */
19145 current_stub_contents =
19149 /* LDMDB Ri!, {R-high-register-list}. */
19150 current_stub_contents =
19152 create_instruction_ldmdb
19155 /* LDMDB Ri, {R-low-register-list}. */
19156 current_stub_contents =
19158 create_instruction_ldmdb
19161 /* B initial_insn_addr+4. */
19162 current_stub_contents =
19164 create_instruction_branch_absolute
19166 }
19168 {
19169 /* LDMDB Rn!, {R-high-register-list}. */
19170 current_stub_contents =
19172 create_instruction_ldmdb
19175 /* LDMDB Rn!, {R-low-register-list}. */
19176 current_stub_contents =
19178 create_instruction_ldmdb
19181 /* B initial_insn_addr+4. */
19182 current_stub_contents =
19184 create_instruction_branch_absolute
19186 }
19188 {
19189 /* Choose a Ri in the high-register-list that will be restored. */
19192 /* SUB Ri, Rn, #(4*nb_registers). */
19193 current_stub_contents =
19197 /* LDMIA Ri!, {R-low-register-list}. */
19198 current_stub_contents =
19200 create_instruction_ldmia
19203 /* LDMIA Ri, {R-high-register-list}. */
19204 current_stub_contents =
19206 create_instruction_ldmia
19208 }
19210 {
19211 /* Choose a Ri in the high-register-list that will be restored. */
19214 /* SUB Rn, Rn, #(4*nb_registers) */
19215 current_stub_contents =
19219 /* MOV Ri, Rn. */
19220 current_stub_contents =
19224 /* LDMIA Ri!, {R-low-register-list}. */
19225 current_stub_contents =
19227 create_instruction_ldmia
19230 /* LDMIA Ri, {R-high-register-list}. */
19231 current_stub_contents =
19233 create_instruction_ldmia
19235 }
19237 {
19240 {
19241 /* Choose a Ri in the low-register-list that will be restored. */
19244 /* MOV Ri, Rn. */
19245 current_stub_contents =
19248 }
19250 /* LDMDB Ri!, {R-high-register-list}. */
19251 current_stub_contents =
19253 create_instruction_ldmdb
19256 /* LDMDB Ri, {R-low-register-list}. */
19257 current_stub_contents =
19259 create_instruction_ldmdb
19262 /* B initial_insn_addr+4. */
19263 current_stub_contents =
19265 create_instruction_branch_absolute
19267 }
19269 {
19272 {
19273 /* Choose a Ri in the high-register-list that will be restored. */
19275 }
19277 /* SUB Ri, Rn, #(4*nb_registers). */
19278 current_stub_contents =
19282 /* LDMIA Ri!, {R-low-register-list}. */
19283 current_stub_contents =
19285 create_instruction_ldmia
19288 /* LDMIA Ri, {R-high-register-list}. */
19289 current_stub_contents =
19291 create_instruction_ldmia
19293 }
19295 {
19296 /* The assembler should not have accepted to encode this. */
19299 }
19301 /* Fill the remaining of the stub with deterministic contents. */
19302 current_stub_contents =
19305 base_stub_contents +
19306 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19308 }
19310 static void
19316 {
19322 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19323 smaller than 8 words load sequences that do not cause the
19324 hardware issue. */
19326 {
19327 /* Untouched instruction. */
19328 current_stub_contents =
19330 initial_insn);
19332 /* B initial_insn_addr+4. */
19333 current_stub_contents =
19335 create_instruction_branch_absolute
19337 }
19338 else
19339 {
19349 /* d = UInt (Vd:D);. */
19353 /* Compute the number of 8-words chunks needed to split. */
19357 /* The test coverage has been done assuming the following
19358 hypothesis that exactly one of the previous is_ predicates is
19359 true. */
19363 /* We treat the cutting of the words in one pass for all
19364 cases, then we emit the adjustments:
19366 vldm rx, {...}
19367 -> vldm rx!, {8_words_or_less} for each needed 8_word
19368 -> sub rx, rx, #size (list)
19370 vldm rx!, {...}
19371 -> vldm rx!, {8_words_or_less} for each needed 8_word
19372 This also handles vpop instruction (when rx is sp)
19374 vldmd rx!, {...}
19375 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
19377 {
19381 {
19382 new_insn = create_instruction_vldmia
19384 is_dp,
19389 }
19391 {
19392 new_insn = create_instruction_vldmdb
19394 is_dp,
19398 }
19401 current_stub_contents =
19403 new_insn);
19404 }
19406 /* Only this case requires the base register compensation
19407 subtract. */
19409 {
19410 current_stub_contents =
19412 create_instruction_sub
19414 }
19416 /* B initial_insn_addr+4. */
19417 current_stub_contents =
19419 create_instruction_branch_absolute
19421 }
19423 /* Fill the remaining of the stub with deterministic contents. */
19424 current_stub_contents =
19427 base_stub_contents +
19428 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19429 }
19431 static void
19437 {
19441 stub_contents);
19445 stub_contents);
19449 stub_contents);
19450 }
19452 /* End of stm32l4xx work-around. */
19455 /* Do code byteswapping. Return FALSE afterwards so that the section is
19456 written out as normal. */
19458 static bool
19463 {
19470 bfd_vma ptr;
19471 bfd_vma end;
19473 bfd_byte tmp;
19479 /* If this section has not been allocated an _arm_elf_section_data
19480 structure then we cannot record anything. */
19490 {
19495 {
19499 {
19501 {
19502 bfd_vma branch_to_veneer;
19503 /* Original condition code of instruction, plus bit mask for
19504 ARM B instruction. */
19508 /* The instruction is before the label. */
19511 /* Above offset included in -4 below. */
19525 }
19529 {
19530 bfd_vma branch_from_veneer;
19533 /* Take size of veneer into account. */
19542 /* Original instruction. */
19549 /* Branch back to insn after original insn. */
19555 }
19560 }
19561 }
19562 }
19565 {
19569 {
19573 {
19575 {
19577 bfd_vma branch_to_veneer =
19582 {
19583 bfd_vma out_of_range =
19589 _bfd_error_handler
19591 "cannot create STM32L4XX veneer; "
19594 output_bfd,
19598 }
19600 insn = create_instruction_branch_absolute
19603 /* The instruction is before the label. */
19608 }
19612 {
19618 veneer_r = veneer
19623 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19624 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19625 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19628 {
19632 }
19634 /* Original instruction. */
19637 stm32l4xx_create_replacing_stub
19639 }
19644 }
19645 }
19646 }
19649 {
19650 arm_unwind_table_edit *edit_node
19652 /* Now, sec->size is the size of the section we will write. The original
19653 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
19654 markers) was sec->rawsize. (This isn't the case if we perform no
19655 edits, then rawsize will be zero and we should use size). */
19664 {
19666 {
19670 {
19673 out_index++;
19674 in_index++;
19675 }
19679 {
19681 {
19683 in_index++;
19688 {
19696 /* Note: this is meant to be equivalent to an
19697 R_ARM_PREL31 relocation. These synthetic
19698 EXIDX_CANTUNWIND markers are not relocated by the
19699 usual BFD method. */
19703 {
19704 /* Here relocation for new EXIDX_CANTUNWIND is
19705 created, so there is no need to
19706 adjust offset by hand. */
19709 }
19711 /* First address we can't unwind. */
19715 /* Code for EXIDX_CANTUNWIND. */
19719 out_index++;
19721 }
19723 }
19726 }
19727 }
19728 else
19729 {
19730 /* No more edits, copy remaining entries verbatim. */
19733 out_index++;
19734 in_index++;
19735 }
19736 }
19740 edited_contents,
19744 }
19746 /* Fix code to point to Cortex-A8 erratum stubs. */
19748 {
19756 }
19762 {
19767 {
19770 else
19774 {
19776 /* Byte swap code words. */
19778 {
19786 }
19790 /* Byte swap code halfwords. */
19792 {
19797 }
19801 /* Leave data alone. */
19803 }
19805 }
19806 }
19814 }
19816 /* Mangle thumb function symbols as we read them in. */
19818 static bool
19823 {
19828 /* New EABI objects mark thumb function symbols by setting the low bit of
19829 the address. */
19832 {
19834 {
19837 ST_BRANCH_TO_THUMB);
19838 }
19839 else
19841 }
19843 {
19846 }
19849 else
19853 }
19856 /* Mangle thumb function symbols as we write them out. */
19858 static void
19863 {
19864 Elf_Internal_Sym newsym;
19866 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19867 of the address set, as per the new EABI. We do this unconditionally
19868 because objcopy does not set the elf header flags until after
19869 it writes out the symbol table. */
19871 {
19876 {
19877 /* Do this only for defined symbols. At link type, the static
19878 linker will simulate the work of dynamic linker of resolving
19879 symbols and will carry over the thumbness of found symbols to
19880 the output symbol table. It's not clear how it happens, but
19881 the thumbness of undefined symbols can well be different at
19882 runtime, and writing '1' for them will be confusing for users
19883 and possibly for dynamic linker itself.
19884 */
19886 }
19889 }
19891 }
19893 /* Add the PT_ARM_EXIDX program header. */
19895 static bool
19898 {
19904 {
19905 /* If there is already a PT_ARM_EXIDX header, then we do not
19906 want to add another one. This situation arises when running
19907 "strip"; the input binary already has the header. */
19912 {
19923 }
19924 }
19927 }
19929 /* We may add a PT_ARM_EXIDX program header. */
19931 static int
19934 {
19940 else
19942 }
19944 /* Hook called by the linker routine which adds symbols from an object
19945 file. */
19947 static bool
19951 {
19961 }
19963 /* We use this to override swap_symbol_in and swap_symbol_out. */
19965 {
19978 bfd_elf32_write_out_phdrs,
19979 bfd_elf32_write_shdrs_and_ehdr,
19980 bfd_elf32_checksum_contents,
19981 bfd_elf32_write_relocs,
19982 elf32_arm_swap_symbol_in,
19983 elf32_arm_swap_symbol_out,
19984 bfd_elf32_slurp_reloc_table,
19985 bfd_elf32_slurp_symbol_table,
19986 bfd_elf32_swap_dyn_in,
19987 bfd_elf32_swap_dyn_out,
19988 bfd_elf32_swap_reloc_in,
19989 bfd_elf32_swap_reloc_out,
19990 bfd_elf32_swap_reloca_in,
19991 bfd_elf32_swap_reloca_out
19992 };
19994 static bfd_vma
19996 {
19997 /* V7 BE8 code is always little endian. */
20002 }
20004 static bfd_vma
20006 {
20007 /* V7 BE8 code is always little endian. */
20012 }
20014 /* Return size of plt0 entry starting at ADDR
20015 or (bfd_vma) -1 if size can not be determined. */
20017 static bfd_vma
20019 bfd_size_type data_size)
20020 {
20021 bfd_vma first_word;
20022 bfd_vma plt0_size;
20033 else
20034 /* We don't yet handle this PLT format. */
20038 }
20040 /* Return size of plt entry starting at offset OFFSET
20041 of plt section located at address START
20042 or (bfd_vma) -1 if size can not be determined. */
20044 static bfd_vma
20046 bfd_size_type data_size)
20047 {
20048 bfd_vma first_insn;
20051 /* PLT entry size if fixed on Thumb-only platforms. */
20055 /* Respect Thumb stub if necessary. */
20059 {
20061 }
20063 /* Strip immediate from first add. */
20068 #ifdef FOUR_WORD_PLT
20071 #else
20076 #endif
20077 else
20078 /* We don't yet handle this PLT format. */
20082 }
20084 /* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20086 static long
20093 {
20102 bfd_vma offset;
20137 {
20141 }
20146 {
20149 }
20155 {
20163 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20164 we are defining a symbol, ensure one of them is set. */
20176 {
20183 ;
20187 }
20192 }
20196 }
20198 static bool
20200 {
20204 }
20206 static flagword
20208 {
20213 }
20215 static unsigned int
20217 {
20222 }
20224 /* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
20225 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
20226 FALSE otherwise. ISECTION is the best guess matching section from the
20227 input bfd IBFD, but it might be NULL. */
20229 static bool
20234 {
20236 {
20238 {
20246 /* The sh_link field must be set to the text section associated with
20247 this index section. Unfortunately the ARM EHABI does not specify
20248 exactly how to determine this association. Our caller does try
20249 to match up OSECTION with its corresponding input section however
20250 so that is a good first guess. */
20261 )
20262 {
20267 }
20270 {
20271 /* Failing that we have to find a matching section ourselves. If
20272 we had the output section name available we could compare that
20273 with input section names. Unfortunately we don't. So instead
20274 we use a simple heuristic and look for the nearest executable
20275 section before this one. */
20287 }
20290 {
20292 /* If the text section was part of a group
20293 then the index section should be too. */
20297 }
20298 }
20310 }
20313 }
20315 /* Returns TRUE if NAME is an ARM mapping symbol.
20316 Traditionally the symbols $a, $d and $t have been used.
20317 The ARM ELF standard also defines $x (for A64 code). It also allows a
20318 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20319 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20320 not support them here. $t.x indicates the start of ThumbEE instructions. */
20322 static bool
20324 {
20327 the mapping symbols could have acquired a prefix.
20328 We do not support this here, since such symbols no
20329 longer conform to the ARM ELF ABI. */
20332 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20333 any characters that follow the period are legal characters for the body
20334 of a symbol's name. For now we just assume that this is the case. */
20335 }
20337 /* Make sure that mapping symbols in object files are not removed via the
20338 "strip --strip-unneeded" tool. These symbols are needed in order to
20339 correctly generate interworking veneers, and for byte swapping code
20340 regions. Once an object file has been linked, it is safe to remove the
20341 symbols as they will no longer be needed. */
20343 static void
20345 {
20350 }
20352 #undef elf_backend_copy_special_section_fields
20353 #define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20355 #define ELF_ARCH bfd_arch_arm
20356 #define ELF_TARGET_ID ARM_ELF_DATA
20357 #define ELF_MACHINE_CODE EM_ARM
20358 #define ELF_MAXPAGESIZE 0x1000
20359 #define ELF_COMMONPAGESIZE 0x1000
20361 #define bfd_elf32_mkobject elf32_arm_mkobject
20363 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20364 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
20365 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20366 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
20367 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
20368 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
20369 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
20370 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
20371 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
20372 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
20373 #define bfd_elf32_bfd_final_link elf32_arm_final_link
20374 #define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
20376 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20377 #define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
20378 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
20379 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
20380 #define elf_backend_check_relocs elf32_arm_check_relocs
20381 #define elf_backend_update_relocs elf32_arm_update_relocs
20382 #define elf_backend_relocate_section elf32_arm_relocate_section
20383 #define elf_backend_write_section elf32_arm_write_section
20384 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
20385 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
20386 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20387 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20388 #define elf_backend_late_size_sections elf32_arm_late_size_sections
20389 #define elf_backend_early_size_sections elf32_arm_early_size_sections
20390 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
20391 #define elf_backend_init_file_header elf32_arm_init_file_header
20392 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
20393 #define elf_backend_object_p elf32_arm_object_p
20394 #define elf_backend_fake_sections elf32_arm_fake_sections
20395 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20396 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20397 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
20398 #define elf_backend_size_info elf32_arm_size_info
20399 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20400 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20401 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
20402 #define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
20403 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
20404 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
20405 #define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
20406 #define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
20408 #define elf_backend_can_refcount 1
20409 #define elf_backend_can_gc_sections 1
20410 #define elf_backend_plt_readonly 1
20411 #define elf_backend_want_got_plt 1
20412 #define elf_backend_want_plt_sym 0
20413 #define elf_backend_want_dynrelro 1
20414 #define elf_backend_may_use_rel_p 1
20415 #define elf_backend_may_use_rela_p 0
20416 #define elf_backend_default_use_rela_p 0
20417 #define elf_backend_dtrel_excludes_plt 1
20419 #define elf_backend_got_header_size 12
20420 #define elf_backend_extern_protected_data 0
20422 #undef elf_backend_obj_attrs_vendor
20424 #undef elf_backend_obj_attrs_section
20426 #undef elf_backend_obj_attrs_arg_type
20427 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
20428 #undef elf_backend_obj_attrs_section_type
20429 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
20430 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
20431 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
20433 #undef elf_backend_section_flags
20434 #define elf_backend_section_flags elf32_arm_section_flags
20435 #undef elf_backend_lookup_section_flags_hook
20436 #define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
20438 #define elf_backend_linux_prpsinfo32_ugid16 true
20442 /* Native Client targets. */
20444 #undef TARGET_LITTLE_SYM
20445 #define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
20446 #undef TARGET_LITTLE_NAME
20448 #undef TARGET_BIG_SYM
20449 #define TARGET_BIG_SYM arm_elf32_nacl_be_vec
20450 #undef TARGET_BIG_NAME
20453 /* Like elf32_arm_link_hash_table_create -- but overrides
20454 appropriately for NaCl. */
20458 {
20463 {
20469 }
20471 }
20473 /* Since NaCl doesn't use the ARM-specific unwind format, we don't
20474 really need to use elf32_arm_modify_segment_map. But we do it
20475 anyway just to reduce gratuitous differences with the stock ARM backend. */
20477 static bool
20479 {
20482 }
20484 static bool
20486 {
20489 }
20491 static bfd_vma
20494 {
20498 }
20500 #undef elf32_bed
20501 #define elf32_bed elf32_arm_nacl_bed
20502 #undef bfd_elf32_bfd_link_hash_table_create
20503 #define bfd_elf32_bfd_link_hash_table_create \
20504 elf32_arm_nacl_link_hash_table_create
20505 #undef elf_backend_plt_alignment
20506 #define elf_backend_plt_alignment 4
20507 #undef elf_backend_modify_segment_map
20508 #define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20509 #undef elf_backend_modify_headers
20510 #define elf_backend_modify_headers nacl_modify_headers
20511 #undef elf_backend_final_write_processing
20512 #define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
20513 #undef bfd_elf32_get_synthetic_symtab
20514 #undef elf_backend_plt_sym_val
20515 #define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
20516 #undef elf_backend_copy_special_section_fields
20518 #undef ELF_MINPAGESIZE
20519 #undef ELF_COMMONPAGESIZE
20521 #undef ELF_TARGET_OS
20522 #define ELF_TARGET_OS is_nacl
20526 /* Reset to defaults. */
20527 #undef elf_backend_plt_alignment
20528 #undef elf_backend_modify_segment_map
20529 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20530 #undef elf_backend_modify_headers
20531 #undef elf_backend_final_write_processing
20532 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20533 #undef ELF_MINPAGESIZE
20534 #undef ELF_COMMONPAGESIZE
20535 #define ELF_COMMONPAGESIZE 0x1000
20538 /* FDPIC Targets. */
20540 #undef TARGET_LITTLE_SYM
20541 #define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20542 #undef TARGET_LITTLE_NAME
20544 #undef TARGET_BIG_SYM
20545 #define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20546 #undef TARGET_BIG_NAME
20548 #undef elf_match_priority
20549 #define elf_match_priority 128
20550 #undef ELF_OSABI
20551 #define ELF_OSABI ELFOSABI_ARM_FDPIC
20553 /* Like elf32_arm_link_hash_table_create -- but overrides
20554 appropriately for FDPIC. */
20558 {
20563 {
20567 }
20569 }
20571 /* We need dynamic symbols for every section, since segments can
20572 relocate independently. */
20573 static bool
20576 ATTRIBUTE_UNUSED,
20578 {
20580 {
20583 /* If sh_type is yet undecided, assume it could be
20584 SHT_PROGBITS/SHT_NOBITS. */
20588 /* There shouldn't be section relative relocations
20589 against any other section. */
20592 }
20593 }
20595 #undef elf32_bed
20596 #define elf32_bed elf32_arm_fdpic_bed
20598 #undef bfd_elf32_bfd_link_hash_table_create
20599 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
20601 #undef elf_backend_omit_section_dynsym
20602 #define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20604 #undef ELF_TARGET_OS
20608 #undef elf_match_priority
20609 #undef ELF_OSABI
20610 #undef elf_backend_omit_section_dynsym
20612 /* VxWorks Targets. */
20614 #undef TARGET_LITTLE_SYM
20615 #define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20616 #undef TARGET_LITTLE_NAME
20618 #undef TARGET_BIG_SYM
20619 #define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20620 #undef TARGET_BIG_NAME
20623 /* Like elf32_arm_link_hash_table_create -- but overrides
20624 appropriately for VxWorks. */
20628 {
20633 {
20637 }
20639 }
20641 static bool
20643 {
20646 }
20648 #undef elf32_bed
20649 #define elf32_bed elf32_arm_vxworks_bed
20651 #undef bfd_elf32_bfd_link_hash_table_create
20652 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
20653 #undef elf_backend_final_write_processing
20654 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20655 #undef elf_backend_emit_relocs
20656 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
20658 #undef elf_backend_may_use_rel_p
20659 #define elf_backend_may_use_rel_p 0
20660 #undef elf_backend_may_use_rela_p
20661 #define elf_backend_may_use_rela_p 1
20662 #undef elf_backend_default_use_rela_p
20663 #define elf_backend_default_use_rela_p 1
20664 #undef elf_backend_want_plt_sym
20665 #define elf_backend_want_plt_sym 1
20666 #undef ELF_MAXPAGESIZE
20667 #define ELF_MAXPAGESIZE 0x1000
20668 #undef ELF_TARGET_OS
20669 #define ELF_TARGET_OS is_vxworks
20674 /* Merge backend specific data from an object file to the output
20675 object file when linking. */
20677 static bool
20679 {
20681 flagword out_flags;
20682 flagword in_flags;
20686 /* Check if we have the same endianness. */
20696 /* The input BFD must have had its flags initialised. */
20697 /* The following seems bogus to me -- The flags are initialized in
20698 the assembler but I don't think an elf_flags_init field is
20699 written into the object. */
20700 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20705 /* In theory there is no reason why we couldn't handle this. However
20706 in practice it isn't even close to working and there is no real
20707 reason to want it. */
20711 {
20713 ibfd);
20715 }
20718 {
20719 /* If the input has no flags set, then do not set the output flags.
20720 This will allow future bfds to determine the desired output flags.
20721 If no input bfds have any flags set, then neither will the output bfd.
20723 Note - we used to restrict this test to when the input architecture
20724 variant was the default variant, but this does not allow for
20725 linker scripts which override the default. See PR 28910 for an
20726 example. */
20738 }
20740 /* Determine what should happen if the input ARM architecture
20741 does not match the output ARM architecture. */
20745 /* Identical flags must be compatible. */
20749 /* Check to see if the input BFD actually contains any sections. If
20750 not, its flags may not have been initialised either, but it
20751 cannot actually cause any incompatiblity. Do not short-circuit
20752 dynamic objects; their section list may be emptied by
20753 elf_link_add_object_symbols.
20755 Also check to see if there are no code sections in the input.
20756 In this case there is no need to check for code specific flags.
20757 XXX - do we need to worry about floating-point format compatability
20758 in data sections ? */
20760 {
20765 {
20766 /* Ignore synthetic glue sections. */
20769 {
20777 }
20778 }
20782 }
20784 /* Complain about various flag mismatches. */
20787 {
20788 _bfd_error_handler
20793 }
20795 /* Not sure what needs to be checked for EABI versions >= 1. */
20796 /* VxWorks libraries do not use these flags. */
20800 {
20802 {
20803 _bfd_error_handler
20808 }
20811 {
20813 _bfd_error_handler
20814 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
20816 else
20817 _bfd_error_handler
20818 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
20822 }
20825 {
20827 _bfd_error_handler
20830 else
20831 _bfd_error_handler
20836 }
20838 #ifdef EF_ARM_SOFT_FLOAT
20840 {
20841 /* We can allow interworking between code that is VFP format
20842 layout, and uses either soft float or integer regs for
20843 passing floating point arguments and results. We already
20844 know that the APCS_FLOAT flags match; similarly for VFP
20845 flags. */
20848 {
20850 _bfd_error_handler
20853 else
20854 _bfd_error_handler
20859 }
20860 }
20861 #endif
20863 /* Interworking mismatch is only a warning. */
20865 {
20867 {
20868 _bfd_error_handler
20871 }
20872 else
20873 {
20874 _bfd_error_handler
20877 }
20878 }
20879 }
20882 }