[binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM_BF16
[binutils-gdb.git] / sim / common / sim-reg.c
blobae578584e64d8acb72a45ffb65c295283293be19
1 /* Generic register read/write.
2 Copyright (C) 1998-2019 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #include "sim-main.h"
21 #include "sim-assert.h"
23 /* Generic implementation of sim_fetch_register for simulators using
24 CPU_REG_FETCH.
25 The contents of BUF are in target byte order. */
26 /* ??? Obviously the interface needs to be extended to handle multiple
27 cpus. */
29 int
30 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *buf, int length)
32 SIM_CPU *cpu = STATE_CPU (sd, 0);
34 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
35 return (* CPU_REG_FETCH (cpu)) (cpu, rn, buf, length);
38 /* Generic implementation of sim_store_register for simulators using
39 CPU_REG_STORE.
40 The contents of BUF are in target byte order. */
41 /* ??? Obviously the interface needs to be extended to handle multiple
42 cpus. */
44 int
45 sim_store_register (SIM_DESC sd, int rn, unsigned char *buf, int length)
47 SIM_CPU *cpu = STATE_CPU (sd, 0);
49 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
50 return (* CPU_REG_STORE (cpu)) (cpu, rn, buf, length);