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[binutils-gdb/blckswan.git] / gdb / nios2-tdep.c
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1 /* Target-machine dependent code for Nios II, for GDB.
2 Copyright (C) 2012-2022 Free Software Foundation, Inc.
3 Contributed by Peter Brookes (pbrookes@altera.com)
4 and Andrew Draper (adraper@altera.com).
5 Contributed by Mentor Graphics, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "defs.h"
23 #include "frame.h"
24 #include "frame-unwind.h"
25 #include "frame-base.h"
26 #include "trad-frame.h"
27 #include "dwarf2/frame.h"
28 #include "symtab.h"
29 #include "inferior.h"
30 #include "gdbtypes.h"
31 #include "gdbcore.h"
32 #include "gdbcmd.h"
33 #include "osabi.h"
34 #include "target.h"
35 #include "dis-asm.h"
36 #include "regcache.h"
37 #include "value.h"
38 #include "symfile.h"
39 #include "arch-utils.h"
40 #include "infcall.h"
41 #include "regset.h"
42 #include "target-descriptions.h"
44 /* To get entry_point_address. */
45 #include "objfiles.h"
46 #include <algorithm>
48 /* Nios II specific header. */
49 #include "nios2-tdep.h"
51 #include "features/nios2.c"
53 /* Control debugging information emitted in this file. */
55 static bool nios2_debug = false;
57 /* The following structures are used in the cache for prologue
58 analysis; see the reg_value and reg_saved tables in
59 struct nios2_unwind_cache, respectively. */
61 /* struct reg_value is used to record that a register has reg's initial
62 value at the start of a function plus the given constant offset.
63 If reg == 0, then the value is just the offset.
64 If reg < 0, then the value is unknown. */
66 struct reg_value
68 int reg;
69 int offset;
72 /* struct reg_saved is used to record that a register value has been saved at
73 basereg + addr, for basereg >= 0. If basereg < 0, that indicates
74 that the register is not known to have been saved. Note that when
75 basereg == NIOS2_Z_REGNUM (that is, r0, which holds value 0),
76 addr is an absolute address. */
78 struct reg_saved
80 int basereg;
81 CORE_ADDR addr;
84 struct nios2_unwind_cache
86 /* The frame's base, optionally used by the high-level debug info. */
87 CORE_ADDR base;
89 /* The previous frame's inner most stack address. Used as this
90 frame ID's stack_addr. */
91 CORE_ADDR cfa;
93 /* The address of the first instruction in this function. */
94 CORE_ADDR pc;
96 /* Which register holds the return address for the frame. */
97 int return_regnum;
99 /* Table indicating what changes have been made to each register. */
100 struct reg_value reg_value[NIOS2_NUM_REGS];
102 /* Table indicating where each register has been saved. */
103 struct reg_saved reg_saved[NIOS2_NUM_REGS];
107 /* This array is a mapping from Dwarf-2 register numbering to GDB's. */
109 static int nios2_dwarf2gdb_regno_map[] =
111 0, 1, 2, 3,
112 4, 5, 6, 7,
113 8, 9, 10, 11,
114 12, 13, 14, 15,
115 16, 17, 18, 19,
116 20, 21, 22, 23,
117 24, 25,
118 NIOS2_GP_REGNUM, /* 26 */
119 NIOS2_SP_REGNUM, /* 27 */
120 NIOS2_FP_REGNUM, /* 28 */
121 NIOS2_EA_REGNUM, /* 29 */
122 NIOS2_BA_REGNUM, /* 30 */
123 NIOS2_RA_REGNUM, /* 31 */
124 NIOS2_PC_REGNUM, /* 32 */
125 NIOS2_STATUS_REGNUM, /* 33 */
126 NIOS2_ESTATUS_REGNUM, /* 34 */
127 NIOS2_BSTATUS_REGNUM, /* 35 */
128 NIOS2_IENABLE_REGNUM, /* 36 */
129 NIOS2_IPENDING_REGNUM, /* 37 */
130 NIOS2_CPUID_REGNUM, /* 38 */
131 39, /* CTL6 */ /* 39 */
132 NIOS2_EXCEPTION_REGNUM, /* 40 */
133 NIOS2_PTEADDR_REGNUM, /* 41 */
134 NIOS2_TLBACC_REGNUM, /* 42 */
135 NIOS2_TLBMISC_REGNUM, /* 43 */
136 NIOS2_ECCINJ_REGNUM, /* 44 */
137 NIOS2_BADADDR_REGNUM, /* 45 */
138 NIOS2_CONFIG_REGNUM, /* 46 */
139 NIOS2_MPUBASE_REGNUM, /* 47 */
140 NIOS2_MPUACC_REGNUM /* 48 */
143 gdb_static_assert (ARRAY_SIZE (nios2_dwarf2gdb_regno_map) == NIOS2_NUM_REGS);
145 /* Implement the dwarf2_reg_to_regnum gdbarch method. */
147 static int
148 nios2_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int dw_reg)
150 if (dw_reg < 0 || dw_reg >= NIOS2_NUM_REGS)
151 return -1;
153 return nios2_dwarf2gdb_regno_map[dw_reg];
156 /* Canonical names for the 49 registers. */
158 static const char *const nios2_reg_names[NIOS2_NUM_REGS] =
160 "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7",
161 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
162 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
163 "et", "bt", "gp", "sp", "fp", "ea", "sstatus", "ra",
164 "pc",
165 "status", "estatus", "bstatus", "ienable",
166 "ipending", "cpuid", "ctl6", "exception",
167 "pteaddr", "tlbacc", "tlbmisc", "eccinj",
168 "badaddr", "config", "mpubase", "mpuacc"
171 /* Implement the register_name gdbarch method. */
173 static const char *
174 nios2_register_name (struct gdbarch *gdbarch, int regno)
176 /* Use mnemonic aliases for GPRs. */
177 if (regno >= 0 && regno < NIOS2_NUM_REGS)
178 return nios2_reg_names[regno];
179 else
180 return tdesc_register_name (gdbarch, regno);
183 /* Implement the register_type gdbarch method. */
185 static struct type *
186 nios2_register_type (struct gdbarch *gdbarch, int regno)
188 /* If the XML description has register information, use that to
189 determine the register type. */
190 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
191 return tdesc_register_type (gdbarch, regno);
193 if (regno == NIOS2_PC_REGNUM)
194 return builtin_type (gdbarch)->builtin_func_ptr;
195 else if (regno == NIOS2_SP_REGNUM)
196 return builtin_type (gdbarch)->builtin_data_ptr;
197 else
198 return builtin_type (gdbarch)->builtin_uint32;
201 /* Given a return value in REGCACHE with a type VALTYPE,
202 extract and copy its value into VALBUF. */
204 static void
205 nios2_extract_return_value (struct gdbarch *gdbarch, struct type *valtype,
206 struct regcache *regcache, gdb_byte *valbuf)
208 int len = TYPE_LENGTH (valtype);
210 /* Return values of up to 8 bytes are returned in $r2 $r3. */
211 if (len <= register_size (gdbarch, NIOS2_R2_REGNUM))
212 regcache->cooked_read (NIOS2_R2_REGNUM, valbuf);
213 else
215 gdb_assert (len <= (register_size (gdbarch, NIOS2_R2_REGNUM)
216 + register_size (gdbarch, NIOS2_R3_REGNUM)));
217 regcache->cooked_read (NIOS2_R2_REGNUM, valbuf);
218 regcache->cooked_read (NIOS2_R3_REGNUM, valbuf + 4);
222 /* Write into appropriate registers a function return value
223 of type TYPE, given in virtual format. */
225 static void
226 nios2_store_return_value (struct gdbarch *gdbarch, struct type *valtype,
227 struct regcache *regcache, const gdb_byte *valbuf)
229 int len = TYPE_LENGTH (valtype);
231 /* Return values of up to 8 bytes are returned in $r2 $r3. */
232 if (len <= register_size (gdbarch, NIOS2_R2_REGNUM))
233 regcache->cooked_write (NIOS2_R2_REGNUM, valbuf);
234 else
236 gdb_assert (len <= (register_size (gdbarch, NIOS2_R2_REGNUM)
237 + register_size (gdbarch, NIOS2_R3_REGNUM)));
238 regcache->cooked_write (NIOS2_R2_REGNUM, valbuf);
239 regcache->cooked_write (NIOS2_R3_REGNUM, valbuf + 4);
244 /* Set up the default values of the registers. */
246 static void
247 nios2_setup_default (struct nios2_unwind_cache *cache)
249 int i;
251 for (i = 0; i < NIOS2_NUM_REGS; i++)
253 /* All registers start off holding their previous values. */
254 cache->reg_value[i].reg = i;
255 cache->reg_value[i].offset = 0;
257 /* All registers start off not saved. */
258 cache->reg_saved[i].basereg = -1;
259 cache->reg_saved[i].addr = 0;
263 /* Initialize the unwind cache. */
265 static void
266 nios2_init_cache (struct nios2_unwind_cache *cache, CORE_ADDR pc)
268 cache->base = 0;
269 cache->cfa = 0;
270 cache->pc = pc;
271 cache->return_regnum = NIOS2_RA_REGNUM;
272 nios2_setup_default (cache);
275 /* Read and identify an instruction at PC. If INSNP is non-null,
276 store the instruction word into that location. Return the opcode
277 pointer or NULL if the memory couldn't be read or disassembled. */
279 static const struct nios2_opcode *
280 nios2_fetch_insn (struct gdbarch *gdbarch, CORE_ADDR pc,
281 unsigned int *insnp)
283 LONGEST memword;
284 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
285 unsigned int insn;
287 if (mach == bfd_mach_nios2r2)
289 if (!safe_read_memory_integer (pc, NIOS2_OPCODE_SIZE,
290 BFD_ENDIAN_LITTLE, &memword)
291 && !safe_read_memory_integer (pc, NIOS2_CDX_OPCODE_SIZE,
292 BFD_ENDIAN_LITTLE, &memword))
293 return NULL;
295 else if (!safe_read_memory_integer (pc, NIOS2_OPCODE_SIZE,
296 gdbarch_byte_order (gdbarch), &memword))
297 return NULL;
299 insn = (unsigned int) memword;
300 if (insnp)
301 *insnp = insn;
302 return nios2_find_opcode_hash (insn, mach);
306 /* Match and disassemble an ADD-type instruction, with 3 register operands.
307 Returns true on success, and fills in the operand pointers. */
309 static int
310 nios2_match_add (uint32_t insn, const struct nios2_opcode *op,
311 unsigned long mach, int *ra, int *rb, int *rc)
313 int is_r2 = (mach == bfd_mach_nios2r2);
315 if (!is_r2 && (op->match == MATCH_R1_ADD || op->match == MATCH_R1_MOV))
317 *ra = GET_IW_R_A (insn);
318 *rb = GET_IW_R_B (insn);
319 *rc = GET_IW_R_C (insn);
320 return 1;
322 else if (!is_r2)
323 return 0;
324 else if (op->match == MATCH_R2_ADD || op->match == MATCH_R2_MOV)
326 *ra = GET_IW_F3X6L5_A (insn);
327 *rb = GET_IW_F3X6L5_B (insn);
328 *rc = GET_IW_F3X6L5_C (insn);
329 return 1;
331 else if (op->match == MATCH_R2_ADD_N)
333 *ra = nios2_r2_reg3_mappings[GET_IW_T3X1_A3 (insn)];
334 *rb = nios2_r2_reg3_mappings[GET_IW_T3X1_B3 (insn)];
335 *rc = nios2_r2_reg3_mappings[GET_IW_T3X1_C3 (insn)];
336 return 1;
338 else if (op->match == MATCH_R2_MOV_N)
340 *ra = GET_IW_F2_A (insn);
341 *rb = 0;
342 *rc = GET_IW_F2_B (insn);
343 return 1;
345 return 0;
348 /* Match and disassemble a SUB-type instruction, with 3 register operands.
349 Returns true on success, and fills in the operand pointers. */
351 static int
352 nios2_match_sub (uint32_t insn, const struct nios2_opcode *op,
353 unsigned long mach, int *ra, int *rb, int *rc)
355 int is_r2 = (mach == bfd_mach_nios2r2);
357 if (!is_r2 && op->match == MATCH_R1_SUB)
359 *ra = GET_IW_R_A (insn);
360 *rb = GET_IW_R_B (insn);
361 *rc = GET_IW_R_C (insn);
362 return 1;
364 else if (!is_r2)
365 return 0;
366 else if (op->match == MATCH_R2_SUB)
368 *ra = GET_IW_F3X6L5_A (insn);
369 *rb = GET_IW_F3X6L5_B (insn);
370 *rc = GET_IW_F3X6L5_C (insn);
371 return 1;
373 else if (op->match == MATCH_R2_SUB_N)
375 *ra = nios2_r2_reg3_mappings[GET_IW_T3X1_A3 (insn)];
376 *rb = nios2_r2_reg3_mappings[GET_IW_T3X1_B3 (insn)];
377 *rc = nios2_r2_reg3_mappings[GET_IW_T3X1_C3 (insn)];
378 return 1;
380 return 0;
383 /* Match and disassemble an ADDI-type instruction, with 2 register operands
384 and one immediate operand.
385 Returns true on success, and fills in the operand pointers. */
387 static int
388 nios2_match_addi (uint32_t insn, const struct nios2_opcode *op,
389 unsigned long mach, int *ra, int *rb, int *imm)
391 int is_r2 = (mach == bfd_mach_nios2r2);
393 if (!is_r2 && op->match == MATCH_R1_ADDI)
395 *ra = GET_IW_I_A (insn);
396 *rb = GET_IW_I_B (insn);
397 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16;
398 return 1;
400 else if (!is_r2)
401 return 0;
402 else if (op->match == MATCH_R2_ADDI)
404 *ra = GET_IW_F2I16_A (insn);
405 *rb = GET_IW_F2I16_B (insn);
406 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16;
407 return 1;
409 else if (op->match == MATCH_R2_ADDI_N || op->match == MATCH_R2_SUBI_N)
411 *ra = nios2_r2_reg3_mappings[GET_IW_T2X1I3_A3 (insn)];
412 *rb = nios2_r2_reg3_mappings[GET_IW_T2X1I3_B3 (insn)];
413 *imm = nios2_r2_asi_n_mappings[GET_IW_T2X1I3_IMM3 (insn)];
414 if (op->match == MATCH_R2_SUBI_N)
415 *imm = - (*imm);
416 return 1;
418 else if (op->match == MATCH_R2_SPADDI_N)
420 *ra = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (insn)];
421 *rb = NIOS2_SP_REGNUM;
422 *imm = GET_IW_T1I7_IMM7 (insn) << 2;
423 return 1;
425 else if (op->match == MATCH_R2_SPINCI_N || op->match == MATCH_R2_SPDECI_N)
427 *ra = NIOS2_SP_REGNUM;
428 *rb = NIOS2_SP_REGNUM;
429 *imm = GET_IW_X1I7_IMM7 (insn) << 2;
430 if (op->match == MATCH_R2_SPDECI_N)
431 *imm = - (*imm);
432 return 1;
434 return 0;
437 /* Match and disassemble an ORHI-type instruction, with 2 register operands
438 and one unsigned immediate operand.
439 Returns true on success, and fills in the operand pointers. */
441 static int
442 nios2_match_orhi (uint32_t insn, const struct nios2_opcode *op,
443 unsigned long mach, int *ra, int *rb, unsigned int *uimm)
445 int is_r2 = (mach == bfd_mach_nios2r2);
447 if (!is_r2 && op->match == MATCH_R1_ORHI)
449 *ra = GET_IW_I_A (insn);
450 *rb = GET_IW_I_B (insn);
451 *uimm = GET_IW_I_IMM16 (insn);
452 return 1;
454 else if (!is_r2)
455 return 0;
456 else if (op->match == MATCH_R2_ORHI)
458 *ra = GET_IW_F2I16_A (insn);
459 *rb = GET_IW_F2I16_B (insn);
460 *uimm = GET_IW_F2I16_IMM16 (insn);
461 return 1;
463 return 0;
466 /* Match and disassemble a STW-type instruction, with 2 register operands
467 and one immediate operand.
468 Returns true on success, and fills in the operand pointers. */
470 static int
471 nios2_match_stw (uint32_t insn, const struct nios2_opcode *op,
472 unsigned long mach, int *ra, int *rb, int *imm)
474 int is_r2 = (mach == bfd_mach_nios2r2);
476 if (!is_r2 && (op->match == MATCH_R1_STW || op->match == MATCH_R1_STWIO))
478 *ra = GET_IW_I_A (insn);
479 *rb = GET_IW_I_B (insn);
480 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16;
481 return 1;
483 else if (!is_r2)
484 return 0;
485 else if (op->match == MATCH_R2_STW)
487 *ra = GET_IW_F2I16_A (insn);
488 *rb = GET_IW_F2I16_B (insn);
489 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16;
490 return 1;
492 else if (op->match == MATCH_R2_STWIO)
494 *ra = GET_IW_F2X4I12_A (insn);
495 *rb = GET_IW_F2X4I12_B (insn);
496 *imm = (signed) (GET_IW_F2X4I12_IMM12 (insn) << 20) >> 20;
497 return 1;
499 else if (op->match == MATCH_R2_STW_N)
501 *ra = nios2_r2_reg3_mappings[GET_IW_T2I4_A3 (insn)];
502 *rb = nios2_r2_reg3_mappings[GET_IW_T2I4_B3 (insn)];
503 *imm = GET_IW_T2I4_IMM4 (insn) << 2;
504 return 1;
506 else if (op->match == MATCH_R2_STWSP_N)
508 *ra = NIOS2_SP_REGNUM;
509 *rb = GET_IW_F1I5_B (insn);
510 *imm = GET_IW_F1I5_IMM5 (insn) << 2;
511 return 1;
513 else if (op->match == MATCH_R2_STWZ_N)
515 *ra = nios2_r2_reg3_mappings[GET_IW_T1X1I6_A3 (insn)];
516 *rb = 0;
517 *imm = GET_IW_T1X1I6_IMM6 (insn) << 2;
518 return 1;
520 return 0;
523 /* Match and disassemble a LDW-type instruction, with 2 register operands
524 and one immediate operand.
525 Returns true on success, and fills in the operand pointers. */
527 static int
528 nios2_match_ldw (uint32_t insn, const struct nios2_opcode *op,
529 unsigned long mach, int *ra, int *rb, int *imm)
531 int is_r2 = (mach == bfd_mach_nios2r2);
533 if (!is_r2 && (op->match == MATCH_R1_LDW || op->match == MATCH_R1_LDWIO))
535 *ra = GET_IW_I_A (insn);
536 *rb = GET_IW_I_B (insn);
537 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16;
538 return 1;
540 else if (!is_r2)
541 return 0;
542 else if (op->match == MATCH_R2_LDW)
544 *ra = GET_IW_F2I16_A (insn);
545 *rb = GET_IW_F2I16_B (insn);
546 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16;
547 return 1;
549 else if (op->match == MATCH_R2_LDWIO)
551 *ra = GET_IW_F2X4I12_A (insn);
552 *rb = GET_IW_F2X4I12_B (insn);
553 *imm = (signed) (GET_IW_F2X4I12_IMM12 (insn) << 20) >> 20;
554 return 1;
556 else if (op->match == MATCH_R2_LDW_N)
558 *ra = nios2_r2_reg3_mappings[GET_IW_T2I4_A3 (insn)];
559 *rb = nios2_r2_reg3_mappings[GET_IW_T2I4_B3 (insn)];
560 *imm = GET_IW_T2I4_IMM4 (insn) << 2;
561 return 1;
563 else if (op->match == MATCH_R2_LDWSP_N)
565 *ra = NIOS2_SP_REGNUM;
566 *rb = GET_IW_F1I5_B (insn);
567 *imm = GET_IW_F1I5_IMM5 (insn) << 2;
568 return 1;
570 return 0;
573 /* Match and disassemble a RDCTL instruction, with 2 register operands.
574 Returns true on success, and fills in the operand pointers. */
576 static int
577 nios2_match_rdctl (uint32_t insn, const struct nios2_opcode *op,
578 unsigned long mach, int *ra, int *rc)
580 int is_r2 = (mach == bfd_mach_nios2r2);
582 if (!is_r2 && (op->match == MATCH_R1_RDCTL))
584 *ra = GET_IW_R_IMM5 (insn);
585 *rc = GET_IW_R_C (insn);
586 return 1;
588 else if (!is_r2)
589 return 0;
590 else if (op->match == MATCH_R2_RDCTL)
592 *ra = GET_IW_F3X6L5_IMM5 (insn);
593 *rc = GET_IW_F3X6L5_C (insn);
594 return 1;
596 return 0;
599 /* Match and disassemble a PUSH.N or STWM instruction.
600 Returns true on success, and fills in the operand pointers. */
602 static int
603 nios2_match_stwm (uint32_t insn, const struct nios2_opcode *op,
604 unsigned long mach, unsigned int *reglist,
605 int *ra, int *imm, int *wb, int *id)
607 int is_r2 = (mach == bfd_mach_nios2r2);
609 if (!is_r2)
610 return 0;
611 else if (op->match == MATCH_R2_PUSH_N)
613 *reglist = 1 << 31;
614 if (GET_IW_L5I4X1_FP (insn))
615 *reglist |= (1 << 28);
616 if (GET_IW_L5I4X1_CS (insn))
618 int val = GET_IW_L5I4X1_REGRANGE (insn);
619 *reglist |= nios2_r2_reg_range_mappings[val];
621 *ra = NIOS2_SP_REGNUM;
622 *imm = GET_IW_L5I4X1_IMM4 (insn) << 2;
623 *wb = 1;
624 *id = 0;
625 return 1;
627 else if (op->match == MATCH_R2_STWM)
629 unsigned int rawmask = GET_IW_F1X4L17_REGMASK (insn);
630 if (GET_IW_F1X4L17_RS (insn))
632 *reglist = ((rawmask << 14) & 0x00ffc000);
633 if (rawmask & (1 << 10))
634 *reglist |= (1 << 28);
635 if (rawmask & (1 << 11))
636 *reglist |= (1 << 31);
638 else
639 *reglist = rawmask << 2;
640 *ra = GET_IW_F1X4L17_A (insn);
641 *imm = 0;
642 *wb = GET_IW_F1X4L17_WB (insn);
643 *id = GET_IW_F1X4L17_ID (insn);
644 return 1;
646 return 0;
649 /* Match and disassemble a POP.N or LDWM instruction.
650 Returns true on success, and fills in the operand pointers. */
652 static int
653 nios2_match_ldwm (uint32_t insn, const struct nios2_opcode *op,
654 unsigned long mach, unsigned int *reglist,
655 int *ra, int *imm, int *wb, int *id, int *ret)
657 int is_r2 = (mach == bfd_mach_nios2r2);
659 if (!is_r2)
660 return 0;
661 else if (op->match == MATCH_R2_POP_N)
663 *reglist = 1 << 31;
664 if (GET_IW_L5I4X1_FP (insn))
665 *reglist |= (1 << 28);
666 if (GET_IW_L5I4X1_CS (insn))
668 int val = GET_IW_L5I4X1_REGRANGE (insn);
669 *reglist |= nios2_r2_reg_range_mappings[val];
671 *ra = NIOS2_SP_REGNUM;
672 *imm = GET_IW_L5I4X1_IMM4 (insn) << 2;
673 *wb = 1;
674 *id = 1;
675 *ret = 1;
676 return 1;
678 else if (op->match == MATCH_R2_LDWM)
680 unsigned int rawmask = GET_IW_F1X4L17_REGMASK (insn);
681 if (GET_IW_F1X4L17_RS (insn))
683 *reglist = ((rawmask << 14) & 0x00ffc000);
684 if (rawmask & (1 << 10))
685 *reglist |= (1 << 28);
686 if (rawmask & (1 << 11))
687 *reglist |= (1 << 31);
689 else
690 *reglist = rawmask << 2;
691 *ra = GET_IW_F1X4L17_A (insn);
692 *imm = 0;
693 *wb = GET_IW_F1X4L17_WB (insn);
694 *id = GET_IW_F1X4L17_ID (insn);
695 *ret = GET_IW_F1X4L17_PC (insn);
696 return 1;
698 return 0;
701 /* Match and disassemble a branch instruction, with (potentially)
702 2 register operands and one immediate operand.
703 Returns true on success, and fills in the operand pointers. */
705 enum branch_condition {
706 branch_none,
707 branch_eq,
708 branch_ne,
709 branch_ge,
710 branch_geu,
711 branch_lt,
712 branch_ltu
715 static int
716 nios2_match_branch (uint32_t insn, const struct nios2_opcode *op,
717 unsigned long mach, int *ra, int *rb, int *imm,
718 enum branch_condition *cond)
720 int is_r2 = (mach == bfd_mach_nios2r2);
722 if (!is_r2)
724 switch (op->match)
726 case MATCH_R1_BR:
727 *cond = branch_none;
728 break;
729 case MATCH_R1_BEQ:
730 *cond = branch_eq;
731 break;
732 case MATCH_R1_BNE:
733 *cond = branch_ne;
734 break;
735 case MATCH_R1_BGE:
736 *cond = branch_ge;
737 break;
738 case MATCH_R1_BGEU:
739 *cond = branch_geu;
740 break;
741 case MATCH_R1_BLT:
742 *cond = branch_lt;
743 break;
744 case MATCH_R1_BLTU:
745 *cond = branch_ltu;
746 break;
747 default:
748 return 0;
750 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16;
751 *ra = GET_IW_I_A (insn);
752 *rb = GET_IW_I_B (insn);
753 return 1;
755 else
757 switch (op->match)
759 case MATCH_R2_BR_N:
760 *cond = branch_none;
761 *ra = NIOS2_Z_REGNUM;
762 *rb = NIOS2_Z_REGNUM;
763 *imm = (signed) ((GET_IW_I10_IMM10 (insn) << 1) << 21) >> 21;
764 return 1;
765 case MATCH_R2_BEQZ_N:
766 *cond = branch_eq;
767 *ra = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (insn)];
768 *rb = NIOS2_Z_REGNUM;
769 *imm = (signed) ((GET_IW_T1I7_IMM7 (insn) << 1) << 24) >> 24;
770 return 1;
771 case MATCH_R2_BNEZ_N:
772 *cond = branch_ne;
773 *ra = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (insn)];
774 *rb = NIOS2_Z_REGNUM;
775 *imm = (signed) ((GET_IW_T1I7_IMM7 (insn) << 1) << 24) >> 24;
776 return 1;
777 case MATCH_R2_BR:
778 *cond = branch_none;
779 break;
780 case MATCH_R2_BEQ:
781 *cond = branch_eq;
782 break;
783 case MATCH_R2_BNE:
784 *cond = branch_ne;
785 break;
786 case MATCH_R2_BGE:
787 *cond = branch_ge;
788 break;
789 case MATCH_R2_BGEU:
790 *cond = branch_geu;
791 break;
792 case MATCH_R2_BLT:
793 *cond = branch_lt;
794 break;
795 case MATCH_R2_BLTU:
796 *cond = branch_ltu;
797 break;
798 default:
799 return 0;
801 *ra = GET_IW_F2I16_A (insn);
802 *rb = GET_IW_F2I16_B (insn);
803 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16;
804 return 1;
806 return 0;
809 /* Match and disassemble a direct jump instruction, with an
810 unsigned operand. Returns true on success, and fills in the operand
811 pointer. */
813 static int
814 nios2_match_jmpi (uint32_t insn, const struct nios2_opcode *op,
815 unsigned long mach, unsigned int *uimm)
817 int is_r2 = (mach == bfd_mach_nios2r2);
819 if (!is_r2 && op->match == MATCH_R1_JMPI)
821 *uimm = GET_IW_J_IMM26 (insn) << 2;
822 return 1;
824 else if (!is_r2)
825 return 0;
826 else if (op->match == MATCH_R2_JMPI)
828 *uimm = GET_IW_L26_IMM26 (insn) << 2;
829 return 1;
831 return 0;
834 /* Match and disassemble a direct call instruction, with an
835 unsigned operand. Returns true on success, and fills in the operand
836 pointer. */
838 static int
839 nios2_match_calli (uint32_t insn, const struct nios2_opcode *op,
840 unsigned long mach, unsigned int *uimm)
842 int is_r2 = (mach == bfd_mach_nios2r2);
844 if (!is_r2 && op->match == MATCH_R1_CALL)
846 *uimm = GET_IW_J_IMM26 (insn) << 2;
847 return 1;
849 else if (!is_r2)
850 return 0;
851 else if (op->match == MATCH_R2_CALL)
853 *uimm = GET_IW_L26_IMM26 (insn) << 2;
854 return 1;
856 return 0;
859 /* Match and disassemble an indirect jump instruction, with a
860 (possibly implicit) register operand. Returns true on success, and fills
861 in the operand pointer. */
863 static int
864 nios2_match_jmpr (uint32_t insn, const struct nios2_opcode *op,
865 unsigned long mach, int *ra)
867 int is_r2 = (mach == bfd_mach_nios2r2);
869 if (!is_r2)
870 switch (op->match)
872 case MATCH_R1_JMP:
873 *ra = GET_IW_I_A (insn);
874 return 1;
875 case MATCH_R1_RET:
876 *ra = NIOS2_RA_REGNUM;
877 return 1;
878 case MATCH_R1_ERET:
879 *ra = NIOS2_EA_REGNUM;
880 return 1;
881 case MATCH_R1_BRET:
882 *ra = NIOS2_BA_REGNUM;
883 return 1;
884 default:
885 return 0;
887 else
888 switch (op->match)
890 case MATCH_R2_JMP:
891 *ra = GET_IW_F2I16_A (insn);
892 return 1;
893 case MATCH_R2_JMPR_N:
894 *ra = GET_IW_F1X1_A (insn);
895 return 1;
896 case MATCH_R2_RET:
897 case MATCH_R2_RET_N:
898 *ra = NIOS2_RA_REGNUM;
899 return 1;
900 case MATCH_R2_ERET:
901 *ra = NIOS2_EA_REGNUM;
902 return 1;
903 case MATCH_R2_BRET:
904 *ra = NIOS2_BA_REGNUM;
905 return 1;
906 default:
907 return 0;
909 return 0;
912 /* Match and disassemble an indirect call instruction, with a register
913 operand. Returns true on success, and fills in the operand pointer. */
915 static int
916 nios2_match_callr (uint32_t insn, const struct nios2_opcode *op,
917 unsigned long mach, int *ra)
919 int is_r2 = (mach == bfd_mach_nios2r2);
921 if (!is_r2 && op->match == MATCH_R1_CALLR)
923 *ra = GET_IW_I_A (insn);
924 return 1;
926 else if (!is_r2)
927 return 0;
928 else if (op->match == MATCH_R2_CALLR)
930 *ra = GET_IW_F2I16_A (insn);
931 return 1;
933 else if (op->match == MATCH_R2_CALLR_N)
935 *ra = GET_IW_F1X1_A (insn);
936 return 1;
938 return 0;
941 /* Match and disassemble a break instruction, with an unsigned operand.
942 Returns true on success, and fills in the operand pointer. */
944 static int
945 nios2_match_break (uint32_t insn, const struct nios2_opcode *op,
946 unsigned long mach, unsigned int *uimm)
948 int is_r2 = (mach == bfd_mach_nios2r2);
950 if (!is_r2 && op->match == MATCH_R1_BREAK)
952 *uimm = GET_IW_R_IMM5 (insn);
953 return 1;
955 else if (!is_r2)
956 return 0;
957 else if (op->match == MATCH_R2_BREAK)
959 *uimm = GET_IW_F3X6L5_IMM5 (insn);
960 return 1;
962 else if (op->match == MATCH_R2_BREAK_N)
964 *uimm = GET_IW_X2L5_IMM5 (insn);
965 return 1;
967 return 0;
970 /* Match and disassemble a trap instruction, with an unsigned operand.
971 Returns true on success, and fills in the operand pointer. */
973 static int
974 nios2_match_trap (uint32_t insn, const struct nios2_opcode *op,
975 unsigned long mach, unsigned int *uimm)
977 int is_r2 = (mach == bfd_mach_nios2r2);
979 if (!is_r2 && op->match == MATCH_R1_TRAP)
981 *uimm = GET_IW_R_IMM5 (insn);
982 return 1;
984 else if (!is_r2)
985 return 0;
986 else if (op->match == MATCH_R2_TRAP)
988 *uimm = GET_IW_F3X6L5_IMM5 (insn);
989 return 1;
991 else if (op->match == MATCH_R2_TRAP_N)
993 *uimm = GET_IW_X2L5_IMM5 (insn);
994 return 1;
996 return 0;
999 /* Helper function to identify when we're in a function epilogue;
1000 that is, the part of the function from the point at which the
1001 stack adjustments are made, to the return or sibcall.
1002 Note that we may have several stack adjustment instructions, and
1003 this function needs to test whether the stack teardown has already
1004 started before current_pc, not whether it has completed. */
1006 static int
1007 nios2_in_epilogue_p (struct gdbarch *gdbarch,
1008 CORE_ADDR current_pc,
1009 CORE_ADDR start_pc)
1011 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
1012 int is_r2 = (mach == bfd_mach_nios2r2);
1013 /* Maximum number of possibly-epilogue instructions to check.
1014 Note that this number should not be too large, else we can
1015 potentially end up iterating through unmapped memory. */
1016 int ninsns, max_insns = 5;
1017 unsigned int insn;
1018 const struct nios2_opcode *op = NULL;
1019 unsigned int uimm;
1020 int imm;
1021 int wb, id, ret;
1022 int ra, rb, rc;
1023 enum branch_condition cond;
1024 CORE_ADDR pc;
1026 /* There has to be a previous instruction in the function. */
1027 if (current_pc <= start_pc)
1028 return 0;
1030 /* Find the previous instruction before current_pc. For R2, it might
1031 be either a 16-bit or 32-bit instruction; the only way to know for
1032 sure is to scan through from the beginning of the function,
1033 disassembling as we go. */
1034 if (is_r2)
1035 for (pc = start_pc; ; )
1037 op = nios2_fetch_insn (gdbarch, pc, &insn);
1038 if (op == NULL)
1039 return 0;
1040 if (pc + op->size < current_pc)
1041 pc += op->size;
1042 else
1043 break;
1044 /* We can skip over insns to a forward branch target. Since
1045 the branch offset is relative to the next instruction,
1046 it's correct to do this after incrementing the pc above. */
1047 if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond)
1048 && imm > 0
1049 && pc + imm < current_pc)
1050 pc += imm;
1052 /* Otherwise just go back to the previous 32-bit insn. */
1053 else
1054 pc = current_pc - NIOS2_OPCODE_SIZE;
1056 /* Beginning with the previous instruction we just located, check whether
1057 we are in a sequence of at least one stack adjustment instruction.
1058 Possible instructions here include:
1059 ADDI sp, sp, n
1060 ADD sp, sp, rn
1061 LDW sp, n(sp)
1062 SPINCI.N n
1063 LDWSP.N sp, n(sp)
1064 LDWM {reglist}, (sp)++, wb */
1065 for (ninsns = 0; ninsns < max_insns; ninsns++)
1067 int ok = 0;
1069 /* Fetch the insn at pc. */
1070 op = nios2_fetch_insn (gdbarch, pc, &insn);
1071 if (op == NULL)
1072 return 0;
1073 pc += op->size;
1075 /* Was it a stack adjustment? */
1076 if (nios2_match_addi (insn, op, mach, &ra, &rb, &imm))
1077 ok = (rb == NIOS2_SP_REGNUM);
1078 else if (nios2_match_add (insn, op, mach, &ra, &rb, &rc))
1079 ok = (rc == NIOS2_SP_REGNUM);
1080 else if (nios2_match_ldw (insn, op, mach, &ra, &rb, &imm))
1081 ok = (rb == NIOS2_SP_REGNUM);
1082 else if (nios2_match_ldwm (insn, op, mach, &uimm, &ra,
1083 &imm, &wb, &ret, &id))
1084 ok = (ra == NIOS2_SP_REGNUM && wb && id);
1085 if (!ok)
1086 break;
1089 /* No stack adjustments found. */
1090 if (ninsns == 0)
1091 return 0;
1093 /* We found more stack adjustments than we expect GCC to be generating.
1094 Since it looks like a stack unwind might be in progress tell GDB to
1095 treat it as such. */
1096 if (ninsns == max_insns)
1097 return 1;
1099 /* The next instruction following the stack adjustments must be a
1100 return, jump, or unconditional branch, or a CDX pop.n or ldwm
1101 that does an implicit return. */
1102 if (nios2_match_jmpr (insn, op, mach, &ra)
1103 || nios2_match_jmpi (insn, op, mach, &uimm)
1104 || (nios2_match_ldwm (insn, op, mach, &uimm, &ra, &imm, &wb, &id, &ret)
1105 && ret)
1106 || (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond)
1107 && cond == branch_none))
1108 return 1;
1110 return 0;
1113 /* Implement the stack_frame_destroyed_p gdbarch method. */
1115 static int
1116 nios2_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1118 CORE_ADDR func_addr;
1120 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1121 return nios2_in_epilogue_p (gdbarch, pc, func_addr);
1123 return 0;
1126 /* Do prologue analysis, returning the PC of the first instruction
1127 after the function prologue. Assumes CACHE has already been
1128 initialized. THIS_FRAME can be null, in which case we are only
1129 interested in skipping the prologue. Otherwise CACHE is filled in
1130 from the frame information.
1132 The prologue may consist of the following parts:
1133 1) Profiling instrumentation. For non-PIC code it looks like:
1134 mov r8, ra
1135 call mcount
1136 mov ra, r8
1138 2) A stack adjustment and save of R4-R7 for varargs functions.
1139 For R2 CDX this is typically handled with a STWM, otherwise
1140 this is typically merged with item 3.
1142 3) A stack adjustment and save of the callee-saved registers.
1143 For R2 CDX these are typically handled with a PUSH.N or STWM,
1144 otherwise as an explicit SP decrement and individual register
1145 saves.
1147 There may also be a stack switch here in an exception handler
1148 in place of a stack adjustment. It looks like:
1149 movhi rx, %hiadj(newstack)
1150 addhi rx, rx, %lo(newstack)
1151 stw sp, constant(rx)
1152 mov sp, rx
1154 4) A frame pointer save, which can be either a MOV or ADDI.
1156 5) A further stack pointer adjustment. This is normally included
1157 adjustment in step 3 unless the total adjustment is too large
1158 to be done in one step.
1160 7) A stack overflow check, which can take either of these forms:
1161 bgeu sp, rx, +8
1162 trap 3
1164 bltu sp, rx, .Lstack_overflow
1166 .Lstack_overflow:
1167 trap 3
1169 Older versions of GCC emitted "break 3" instead of "trap 3" here,
1170 so we check for both cases.
1172 Older GCC versions emitted stack overflow checks after the SP
1173 adjustments in both steps 3 and 4. Starting with GCC 6, there is
1174 at most one overflow check, which is placed before the first
1175 stack adjustment for R2 CDX and after the first stack adjustment
1176 otherwise.
1178 The prologue instructions may be combined or interleaved with other
1179 instructions.
1181 To cope with all this variability we decode all the instructions
1182 from the start of the prologue until we hit an instruction that
1183 cannot possibly be a prologue instruction, such as a branch, call,
1184 return, or epilogue instruction. The prologue is considered to end
1185 at the last instruction that can definitely be considered a
1186 prologue instruction. */
1188 static CORE_ADDR
1189 nios2_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc,
1190 const CORE_ADDR current_pc,
1191 struct nios2_unwind_cache *cache,
1192 struct frame_info *this_frame)
1194 /* Maximum number of possibly-prologue instructions to check.
1195 Note that this number should not be too large, else we can
1196 potentially end up iterating through unmapped memory. */
1197 int ninsns, max_insns = 50;
1198 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1199 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
1201 /* Does the frame set up the FP register? */
1202 int base_reg = 0;
1204 struct reg_value *value = cache->reg_value;
1205 struct reg_value temp_value[NIOS2_NUM_REGS];
1207 /* Save the starting PC so we can correct the pc after running
1208 through the prolog, using symbol info. */
1209 CORE_ADDR pc = start_pc;
1211 /* Is this an exception handler? */
1212 int exception_handler = 0;
1214 /* What was the original value of SP (or fake original value for
1215 functions which switch stacks? */
1216 CORE_ADDR frame_high;
1218 /* The last definitely-prologue instruction seen. */
1219 CORE_ADDR prologue_end;
1221 /* Is this the innermost function? */
1222 int innermost = (this_frame ? (frame_relative_level (this_frame) == 0) : 1);
1224 if (nios2_debug)
1225 gdb_printf (gdb_stdlog,
1226 "{ nios2_analyze_prologue start=%s, current=%s ",
1227 paddress (gdbarch, start_pc),
1228 paddress (gdbarch, current_pc));
1230 /* Set up the default values of the registers. */
1231 nios2_setup_default (cache);
1233 /* Find the prologue instructions. */
1234 prologue_end = start_pc;
1235 for (ninsns = 0; ninsns < max_insns; ninsns++)
1237 /* Present instruction. */
1238 uint32_t insn;
1239 const struct nios2_opcode *op;
1240 int ra, rb, rc, imm;
1241 unsigned int uimm;
1242 unsigned int reglist;
1243 int wb, id, ret;
1244 enum branch_condition cond;
1246 if (pc == current_pc)
1248 /* When we reach the current PC we must save the current
1249 register state (for the backtrace) but keep analysing
1250 because there might be more to find out (eg. is this an
1251 exception handler). */
1252 memcpy (temp_value, value, sizeof (temp_value));
1253 value = temp_value;
1254 if (nios2_debug)
1255 gdb_printf (gdb_stdlog, "*");
1258 op = nios2_fetch_insn (gdbarch, pc, &insn);
1260 /* Unknown opcode? Stop scanning. */
1261 if (op == NULL)
1262 break;
1263 pc += op->size;
1265 if (nios2_debug)
1267 if (op->size == 2)
1268 gdb_printf (gdb_stdlog, "[%04X]", insn & 0xffff);
1269 else
1270 gdb_printf (gdb_stdlog, "[%08X]", insn);
1273 /* The following instructions can appear in the prologue. */
1275 if (nios2_match_add (insn, op, mach, &ra, &rb, &rc))
1277 /* ADD rc, ra, rb (also used for MOV) */
1278 if (rc == NIOS2_SP_REGNUM
1279 && rb == 0
1280 && value[ra].reg == cache->reg_saved[NIOS2_SP_REGNUM].basereg)
1282 /* If the previous value of SP is available somewhere
1283 near the new stack pointer value then this is a
1284 stack switch. */
1286 /* If any registers were saved on the stack before then
1287 we can't backtrace into them now. */
1288 for (int i = 0 ; i < NIOS2_NUM_REGS ; i++)
1290 if (cache->reg_saved[i].basereg == NIOS2_SP_REGNUM)
1291 cache->reg_saved[i].basereg = -1;
1292 if (value[i].reg == NIOS2_SP_REGNUM)
1293 value[i].reg = -1;
1296 /* Create a fake "high water mark" 4 bytes above where SP
1297 was stored and fake up the registers to be consistent
1298 with that. */
1299 value[NIOS2_SP_REGNUM].reg = NIOS2_SP_REGNUM;
1300 value[NIOS2_SP_REGNUM].offset
1301 = (value[ra].offset
1302 - cache->reg_saved[NIOS2_SP_REGNUM].addr
1303 - 4);
1304 cache->reg_saved[NIOS2_SP_REGNUM].basereg = NIOS2_SP_REGNUM;
1305 cache->reg_saved[NIOS2_SP_REGNUM].addr = -4;
1308 else if (rc == NIOS2_SP_REGNUM && ra == NIOS2_FP_REGNUM)
1309 /* This is setting SP from FP. This only happens in the
1310 function epilogue. */
1311 break;
1313 else if (rc != 0)
1315 if (value[rb].reg == 0)
1316 value[rc].reg = value[ra].reg;
1317 else if (value[ra].reg == 0)
1318 value[rc].reg = value[rb].reg;
1319 else
1320 value[rc].reg = -1;
1321 value[rc].offset = value[ra].offset + value[rb].offset;
1324 /* The add/move is only considered a prologue instruction
1325 if the destination is SP or FP. */
1326 if (rc == NIOS2_SP_REGNUM || rc == NIOS2_FP_REGNUM)
1327 prologue_end = pc;
1330 else if (nios2_match_sub (insn, op, mach, &ra, &rb, &rc))
1332 /* SUB rc, ra, rb */
1333 if (rc == NIOS2_SP_REGNUM && rb == NIOS2_SP_REGNUM
1334 && value[rc].reg != 0)
1335 /* If we are decrementing the SP by a non-constant amount,
1336 this is alloca, not part of the prologue. */
1337 break;
1338 else if (rc != 0)
1340 if (value[rb].reg == 0)
1341 value[rc].reg = value[ra].reg;
1342 else
1343 value[rc].reg = -1;
1344 value[rc].offset = value[ra].offset - value[rb].offset;
1348 else if (nios2_match_addi (insn, op, mach, &ra, &rb, &imm))
1350 /* ADDI rb, ra, imm */
1352 /* A positive stack adjustment has to be part of the epilogue. */
1353 if (rb == NIOS2_SP_REGNUM
1354 && (imm > 0 || value[ra].reg != NIOS2_SP_REGNUM))
1355 break;
1357 /* Likewise restoring SP from FP. */
1358 else if (rb == NIOS2_SP_REGNUM && ra == NIOS2_FP_REGNUM)
1359 break;
1361 if (rb != 0)
1363 value[rb].reg = value[ra].reg;
1364 value[rb].offset = value[ra].offset + imm;
1367 /* The add is only considered a prologue instruction
1368 if the destination is SP or FP. */
1369 if (rb == NIOS2_SP_REGNUM || rb == NIOS2_FP_REGNUM)
1370 prologue_end = pc;
1373 else if (nios2_match_orhi (insn, op, mach, &ra, &rb, &uimm))
1375 /* ORHI rb, ra, uimm (also used for MOVHI) */
1376 if (rb != 0)
1378 value[rb].reg = (value[ra].reg == 0) ? 0 : -1;
1379 value[rb].offset = value[ra].offset | (uimm << 16);
1383 else if (nios2_match_stw (insn, op, mach, &ra, &rb, &imm))
1385 /* STW rb, imm(ra) */
1387 /* Are we storing the original value of a register to the stack?
1388 For exception handlers the value of EA-4 (return
1389 address from interrupts etc) is sometimes stored. */
1390 int orig = value[rb].reg;
1391 if (orig > 0
1392 && (value[rb].offset == 0
1393 || (orig == NIOS2_EA_REGNUM && value[rb].offset == -4))
1394 && value[ra].reg == NIOS2_SP_REGNUM)
1396 if (pc < current_pc)
1398 /* Save off callee saved registers. */
1399 cache->reg_saved[orig].basereg = value[ra].reg;
1400 cache->reg_saved[orig].addr = value[ra].offset + imm;
1403 prologue_end = pc;
1405 if (orig == NIOS2_EA_REGNUM || orig == NIOS2_ESTATUS_REGNUM)
1406 exception_handler = 1;
1408 else
1409 /* Non-stack memory writes cannot appear in the prologue. */
1410 break;
1413 else if (nios2_match_stwm (insn, op, mach,
1414 &reglist, &ra, &imm, &wb, &id))
1416 /* PUSH.N {reglist}, adjust
1418 STWM {reglist}, --(SP)[, writeback] */
1419 int off = 0;
1421 if (ra != NIOS2_SP_REGNUM || id != 0)
1422 /* This is a non-stack-push memory write and cannot be
1423 part of the prologue. */
1424 break;
1426 for (int i = 31; i >= 0; i--)
1427 if (reglist & (1 << i))
1429 int orig = value[i].reg;
1431 off += 4;
1432 if (orig > 0 && value[i].offset == 0 && pc < current_pc)
1434 cache->reg_saved[orig].basereg
1435 = value[NIOS2_SP_REGNUM].reg;
1436 cache->reg_saved[orig].addr
1437 = value[NIOS2_SP_REGNUM].offset - off;
1441 if (wb)
1442 value[NIOS2_SP_REGNUM].offset -= off;
1443 value[NIOS2_SP_REGNUM].offset -= imm;
1445 prologue_end = pc;
1448 else if (nios2_match_rdctl (insn, op, mach, &ra, &rc))
1450 /* RDCTL rC, ctlN
1451 This can appear in exception handlers in combination with
1452 a subsequent save to the stack frame. */
1453 if (rc != 0)
1455 value[rc].reg = NIOS2_STATUS_REGNUM + ra;
1456 value[rc].offset = 0;
1460 else if (nios2_match_calli (insn, op, mach, &uimm))
1462 if (value[8].reg == NIOS2_RA_REGNUM
1463 && value[8].offset == 0
1464 && value[NIOS2_SP_REGNUM].reg == NIOS2_SP_REGNUM
1465 && value[NIOS2_SP_REGNUM].offset == 0)
1467 /* A CALL instruction. This is treated as a call to mcount
1468 if ra has been stored into r8 beforehand and if it's
1469 before the stack adjust.
1470 Note mcount corrupts r2-r3, r9-r15 & ra. */
1471 for (int i = 2 ; i <= 3 ; i++)
1472 value[i].reg = -1;
1473 for (int i = 9 ; i <= 15 ; i++)
1474 value[i].reg = -1;
1475 value[NIOS2_RA_REGNUM].reg = -1;
1477 prologue_end = pc;
1480 /* Other calls are not part of the prologue. */
1481 else
1482 break;
1485 else if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond))
1487 /* Branches not involving a stack overflow check aren't part of
1488 the prologue. */
1489 if (ra != NIOS2_SP_REGNUM)
1490 break;
1491 else if (cond == branch_geu)
1493 /* BGEU sp, rx, +8
1494 TRAP 3 (or BREAK 3)
1495 This instruction sequence is used in stack checking;
1496 we can ignore it. */
1497 unsigned int next_insn;
1498 const struct nios2_opcode *next_op
1499 = nios2_fetch_insn (gdbarch, pc, &next_insn);
1500 if (next_op != NULL
1501 && (nios2_match_trap (next_insn, op, mach, &uimm)
1502 || nios2_match_break (next_insn, op, mach, &uimm)))
1503 pc += next_op->size;
1504 else
1505 break;
1507 else if (cond == branch_ltu)
1509 /* BLTU sp, rx, .Lstackoverflow
1510 If the location branched to holds a TRAP or BREAK
1511 instruction then this is also stack overflow detection. */
1512 unsigned int next_insn;
1513 const struct nios2_opcode *next_op
1514 = nios2_fetch_insn (gdbarch, pc + imm, &next_insn);
1515 if (next_op != NULL
1516 && (nios2_match_trap (next_insn, op, mach, &uimm)
1517 || nios2_match_break (next_insn, op, mach, &uimm)))
1519 else
1520 break;
1522 else
1523 break;
1526 /* All other calls, jumps, returns, TRAPs, or BREAKs terminate
1527 the prologue. */
1528 else if (nios2_match_callr (insn, op, mach, &ra)
1529 || nios2_match_jmpr (insn, op, mach, &ra)
1530 || nios2_match_jmpi (insn, op, mach, &uimm)
1531 || (nios2_match_ldwm (insn, op, mach, &reglist, &ra,
1532 &imm, &wb, &id, &ret)
1533 && ret)
1534 || nios2_match_trap (insn, op, mach, &uimm)
1535 || nios2_match_break (insn, op, mach, &uimm))
1536 break;
1539 /* If THIS_FRAME is NULL, we are being called from skip_prologue
1540 and are only interested in the PROLOGUE_END value, so just
1541 return that now and skip over the cache updates, which depend
1542 on having frame information. */
1543 if (this_frame == NULL)
1544 return prologue_end;
1546 /* If we are in the function epilogue and have already popped
1547 registers off the stack in preparation for returning, then we
1548 want to go back to the original register values. */
1549 if (innermost && nios2_in_epilogue_p (gdbarch, current_pc, start_pc))
1550 nios2_setup_default (cache);
1552 /* Exception handlers use a different return address register. */
1553 if (exception_handler)
1554 cache->return_regnum = NIOS2_EA_REGNUM;
1556 if (nios2_debug)
1557 gdb_printf (gdb_stdlog, "\n-> retreg=%d, ", cache->return_regnum);
1559 if (cache->reg_value[NIOS2_FP_REGNUM].reg == NIOS2_SP_REGNUM)
1560 /* If the FP now holds an offset from the CFA then this is a
1561 normal frame which uses the frame pointer. */
1562 base_reg = NIOS2_FP_REGNUM;
1563 else if (cache->reg_value[NIOS2_SP_REGNUM].reg == NIOS2_SP_REGNUM)
1564 /* FP doesn't hold an offset from the CFA. If SP still holds an
1565 offset from the CFA then we might be in a function which omits
1566 the frame pointer, or we might be partway through the prologue.
1567 In both cases we can find the CFA using SP. */
1568 base_reg = NIOS2_SP_REGNUM;
1569 else
1571 /* Somehow the stack pointer has been corrupted.
1572 We can't return. */
1573 if (nios2_debug)
1574 gdb_printf (gdb_stdlog, "<can't reach cfa> }\n");
1575 return 0;
1578 if (cache->reg_value[base_reg].offset == 0
1579 || cache->reg_saved[NIOS2_RA_REGNUM].basereg != NIOS2_SP_REGNUM
1580 || cache->reg_saved[cache->return_regnum].basereg != NIOS2_SP_REGNUM)
1582 /* If the frame didn't adjust the stack, didn't save RA or
1583 didn't save EA in an exception handler then it must either
1584 be a leaf function (doesn't call any other functions) or it
1585 can't return. If it has called another function then it
1586 can't be a leaf, so set base == 0 to indicate that we can't
1587 backtrace past it. */
1589 if (!innermost)
1591 /* If it isn't the innermost function then it can't be a
1592 leaf, unless it was interrupted. Check whether RA for
1593 this frame is the same as PC. If so then it probably
1594 wasn't interrupted. */
1595 CORE_ADDR ra
1596 = get_frame_register_unsigned (this_frame, NIOS2_RA_REGNUM);
1598 if (ra == current_pc)
1600 if (nios2_debug)
1601 gdb_printf
1602 (gdb_stdlog,
1603 "<noreturn ADJUST %s, r31@r%d+?>, r%d@r%d+?> }\n",
1604 paddress (gdbarch, cache->reg_value[base_reg].offset),
1605 cache->reg_saved[NIOS2_RA_REGNUM].basereg,
1606 cache->return_regnum,
1607 cache->reg_saved[cache->return_regnum].basereg);
1608 return 0;
1613 /* Get the value of whichever register we are using for the
1614 base. */
1615 cache->base = get_frame_register_unsigned (this_frame, base_reg);
1617 /* What was the value of SP at the start of this function (or just
1618 after the stack switch). */
1619 frame_high = cache->base - cache->reg_value[base_reg].offset;
1621 /* Adjust all the saved registers such that they contain addresses
1622 instead of offsets. */
1623 for (int i = 0; i < NIOS2_NUM_REGS; i++)
1624 if (cache->reg_saved[i].basereg == NIOS2_SP_REGNUM)
1626 cache->reg_saved[i].basereg = NIOS2_Z_REGNUM;
1627 cache->reg_saved[i].addr += frame_high;
1630 for (int i = 0; i < NIOS2_NUM_REGS; i++)
1631 if (cache->reg_saved[i].basereg == NIOS2_GP_REGNUM)
1633 CORE_ADDR gp = get_frame_register_unsigned (this_frame,
1634 NIOS2_GP_REGNUM);
1636 for ( ; i < NIOS2_NUM_REGS; i++)
1637 if (cache->reg_saved[i].basereg == NIOS2_GP_REGNUM)
1639 cache->reg_saved[i].basereg = NIOS2_Z_REGNUM;
1640 cache->reg_saved[i].addr += gp;
1644 /* Work out what the value of SP was on the first instruction of
1645 this function. If we didn't switch stacks then this can be
1646 trivially computed from the base address. */
1647 if (cache->reg_saved[NIOS2_SP_REGNUM].basereg == NIOS2_Z_REGNUM)
1648 cache->cfa
1649 = read_memory_unsigned_integer (cache->reg_saved[NIOS2_SP_REGNUM].addr,
1650 4, byte_order);
1651 else
1652 cache->cfa = frame_high;
1654 /* Exception handlers restore ESTATUS into STATUS. */
1655 if (exception_handler)
1657 cache->reg_saved[NIOS2_STATUS_REGNUM]
1658 = cache->reg_saved[NIOS2_ESTATUS_REGNUM];
1659 cache->reg_saved[NIOS2_ESTATUS_REGNUM].basereg = -1;
1662 if (nios2_debug)
1663 gdb_printf (gdb_stdlog, "cfa=%s }\n",
1664 paddress (gdbarch, cache->cfa));
1666 return prologue_end;
1669 /* Implement the skip_prologue gdbarch hook. */
1671 static CORE_ADDR
1672 nios2_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
1674 CORE_ADDR func_addr;
1676 struct nios2_unwind_cache cache;
1678 /* See if we can determine the end of the prologue via the symbol
1679 table. If so, then return either PC, or the PC after the
1680 prologue, whichever is greater. */
1681 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
1683 CORE_ADDR post_prologue_pc
1684 = skip_prologue_using_sal (gdbarch, func_addr);
1686 if (post_prologue_pc != 0)
1687 return std::max (start_pc, post_prologue_pc);
1690 /* Prologue analysis does the rest.... */
1691 nios2_init_cache (&cache, start_pc);
1692 return nios2_analyze_prologue (gdbarch, start_pc, start_pc, &cache, NULL);
1695 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1697 static int
1698 nios2_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
1700 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
1702 if (mach == bfd_mach_nios2r2)
1704 unsigned int insn;
1705 const struct nios2_opcode *op
1706 = nios2_fetch_insn (gdbarch, *pcptr, &insn);
1708 if (op && op->size == NIOS2_CDX_OPCODE_SIZE)
1709 return NIOS2_CDX_OPCODE_SIZE;
1710 else
1711 return NIOS2_OPCODE_SIZE;
1713 else
1714 return NIOS2_OPCODE_SIZE;
1717 /* Implement the sw_breakpoint_from_kind gdbarch method. */
1719 static const gdb_byte *
1720 nios2_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
1722 /* The Nios II ABI for Linux says: "Userspace programs should not use
1723 the break instruction and userspace debuggers should not insert
1724 one." and "Userspace breakpoints are accomplished using the trap
1725 instruction with immediate operand 31 (all ones)."
1727 So, we use "trap 31" consistently as the breakpoint on bare-metal
1728 as well as Linux targets. */
1730 /* R2 trap encoding:
1731 ((0x2d << 26) | (0x1f << 21) | (0x1d << 16) | (0x20 << 0))
1732 0xb7fd0020
1733 CDX trap.n encoding:
1734 ((0xd << 12) | (0x1f << 6) | (0x9 << 0))
1735 0xd7c9
1736 Note that code is always little-endian on R2. */
1737 *size = kind;
1739 if (kind == NIOS2_CDX_OPCODE_SIZE)
1741 static const gdb_byte cdx_breakpoint_le[] = {0xc9, 0xd7};
1743 return cdx_breakpoint_le;
1745 else
1747 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
1749 if (mach == bfd_mach_nios2r2)
1751 static const gdb_byte r2_breakpoint_le[] = {0x20, 0x00, 0xfd, 0xb7};
1753 return r2_breakpoint_le;
1755 else
1757 enum bfd_endian byte_order_for_code
1758 = gdbarch_byte_order_for_code (gdbarch);
1759 /* R1 trap encoding:
1760 ((0x1d << 17) | (0x2d << 11) | (0x1f << 6) | (0x3a << 0))
1761 0x003b6ffa */
1762 static const gdb_byte r1_breakpoint_le[] = {0xfa, 0x6f, 0x3b, 0x0};
1763 static const gdb_byte r1_breakpoint_be[] = {0x0, 0x3b, 0x6f, 0xfa};
1765 if (byte_order_for_code == BFD_ENDIAN_BIG)
1766 return r1_breakpoint_be;
1767 else
1768 return r1_breakpoint_le;
1773 /* Implement the frame_align gdbarch method. */
1775 static CORE_ADDR
1776 nios2_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1778 return align_down (addr, 4);
1782 /* Implement the return_value gdbarch method. */
1784 static enum return_value_convention
1785 nios2_return_value (struct gdbarch *gdbarch, struct value *function,
1786 struct type *type, struct regcache *regcache,
1787 gdb_byte *readbuf, const gdb_byte *writebuf)
1789 if (TYPE_LENGTH (type) > 8)
1790 return RETURN_VALUE_STRUCT_CONVENTION;
1792 if (readbuf)
1793 nios2_extract_return_value (gdbarch, type, regcache, readbuf);
1794 if (writebuf)
1795 nios2_store_return_value (gdbarch, type, regcache, writebuf);
1797 return RETURN_VALUE_REGISTER_CONVENTION;
1800 /* Implement the push_dummy_call gdbarch method. */
1802 static CORE_ADDR
1803 nios2_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1804 struct regcache *regcache, CORE_ADDR bp_addr,
1805 int nargs, struct value **args, CORE_ADDR sp,
1806 function_call_return_method return_method,
1807 CORE_ADDR struct_addr)
1809 int argreg;
1810 int argnum;
1811 int arg_space = 0;
1812 int stack_offset = 0;
1813 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1815 /* Set the return address register to point to the entry point of
1816 the program, where a breakpoint lies in wait. */
1817 regcache_cooked_write_signed (regcache, NIOS2_RA_REGNUM, bp_addr);
1819 /* Now make space on the stack for the args. */
1820 for (argnum = 0; argnum < nargs; argnum++)
1821 arg_space += align_up (TYPE_LENGTH (value_type (args[argnum])), 4);
1822 sp -= arg_space;
1824 /* Initialize the register pointer. */
1825 argreg = NIOS2_FIRST_ARGREG;
1827 /* The struct_return pointer occupies the first parameter-passing
1828 register. */
1829 if (return_method == return_method_struct)
1830 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
1832 /* Now load as many as possible of the first arguments into
1833 registers, and push the rest onto the stack. Loop through args
1834 from first to last. */
1835 for (argnum = 0; argnum < nargs; argnum++)
1837 const gdb_byte *val;
1838 struct value *arg = args[argnum];
1839 struct type *arg_type = check_typedef (value_type (arg));
1840 int len = TYPE_LENGTH (arg_type);
1842 val = value_contents (arg).data ();
1844 /* Copy the argument to general registers or the stack in
1845 register-sized pieces. Large arguments are split between
1846 registers and stack. */
1847 while (len > 0)
1849 int partial_len = (len < 4 ? len : 4);
1851 if (argreg <= NIOS2_LAST_ARGREG)
1853 /* The argument is being passed in a register. */
1854 CORE_ADDR regval = extract_unsigned_integer (val, partial_len,
1855 byte_order);
1857 regcache_cooked_write_unsigned (regcache, argreg, regval);
1858 argreg++;
1860 else
1862 /* The argument is being passed on the stack. */
1863 CORE_ADDR addr = sp + stack_offset;
1865 write_memory (addr, val, partial_len);
1866 stack_offset += align_up (partial_len, 4);
1869 len -= partial_len;
1870 val += partial_len;
1874 regcache_cooked_write_signed (regcache, NIOS2_SP_REGNUM, sp);
1876 /* Return adjusted stack pointer. */
1877 return sp;
1880 /* Implement the unwind_pc gdbarch method. */
1882 static CORE_ADDR
1883 nios2_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1885 gdb_byte buf[4];
1887 frame_unwind_register (next_frame, NIOS2_PC_REGNUM, buf);
1888 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1891 /* Use prologue analysis to fill in the register cache
1892 *THIS_PROLOGUE_CACHE for THIS_FRAME. This function initializes
1893 *THIS_PROLOGUE_CACHE first. */
1895 static struct nios2_unwind_cache *
1896 nios2_frame_unwind_cache (struct frame_info *this_frame,
1897 void **this_prologue_cache)
1899 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1900 CORE_ADDR current_pc;
1901 struct nios2_unwind_cache *cache;
1903 if (*this_prologue_cache)
1904 return (struct nios2_unwind_cache *) *this_prologue_cache;
1906 cache = FRAME_OBSTACK_ZALLOC (struct nios2_unwind_cache);
1907 *this_prologue_cache = cache;
1909 /* Zero all fields. */
1910 nios2_init_cache (cache, get_frame_func (this_frame));
1912 /* Prologue analysis does the rest... */
1913 current_pc = get_frame_pc (this_frame);
1914 if (cache->pc != 0)
1915 nios2_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame);
1917 return cache;
1920 /* Implement the this_id function for the normal unwinder. */
1922 static void
1923 nios2_frame_this_id (struct frame_info *this_frame, void **this_cache,
1924 struct frame_id *this_id)
1926 struct nios2_unwind_cache *cache =
1927 nios2_frame_unwind_cache (this_frame, this_cache);
1929 /* This marks the outermost frame. */
1930 if (cache->base == 0)
1931 return;
1933 *this_id = frame_id_build (cache->cfa, cache->pc);
1936 /* Implement the prev_register function for the normal unwinder. */
1938 static struct value *
1939 nios2_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1940 int regnum)
1942 struct nios2_unwind_cache *cache =
1943 nios2_frame_unwind_cache (this_frame, this_cache);
1945 gdb_assert (regnum >= 0 && regnum < NIOS2_NUM_REGS);
1947 /* The PC of the previous frame is stored in the RA register of
1948 the current frame. Frob regnum so that we pull the value from
1949 the correct place. */
1950 if (regnum == NIOS2_PC_REGNUM)
1951 regnum = cache->return_regnum;
1953 if (regnum == NIOS2_SP_REGNUM && cache->cfa)
1954 return frame_unwind_got_constant (this_frame, regnum, cache->cfa);
1956 /* If we've worked out where a register is stored then load it from
1957 there. */
1958 if (cache->reg_saved[regnum].basereg == NIOS2_Z_REGNUM)
1959 return frame_unwind_got_memory (this_frame, regnum,
1960 cache->reg_saved[regnum].addr);
1962 return frame_unwind_got_register (this_frame, regnum, regnum);
1965 /* Implement the this_base, this_locals, and this_args hooks
1966 for the normal unwinder. */
1968 static CORE_ADDR
1969 nios2_frame_base_address (struct frame_info *this_frame, void **this_cache)
1971 struct nios2_unwind_cache *info
1972 = nios2_frame_unwind_cache (this_frame, this_cache);
1974 return info->base;
1977 /* Data structures for the normal prologue-analysis-based
1978 unwinder. */
1980 static const struct frame_unwind nios2_frame_unwind =
1982 "nios2 prologue",
1983 NORMAL_FRAME,
1984 default_frame_unwind_stop_reason,
1985 nios2_frame_this_id,
1986 nios2_frame_prev_register,
1987 NULL,
1988 default_frame_sniffer
1991 static const struct frame_base nios2_frame_base =
1993 &nios2_frame_unwind,
1994 nios2_frame_base_address,
1995 nios2_frame_base_address,
1996 nios2_frame_base_address
1999 /* Fill in the register cache *THIS_CACHE for THIS_FRAME for use
2000 in the stub unwinder. */
2002 static struct trad_frame_cache *
2003 nios2_stub_frame_cache (struct frame_info *this_frame, void **this_cache)
2005 CORE_ADDR pc;
2006 CORE_ADDR start_addr;
2007 CORE_ADDR stack_addr;
2008 struct trad_frame_cache *this_trad_cache;
2009 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2011 if (*this_cache != NULL)
2012 return (struct trad_frame_cache *) *this_cache;
2013 this_trad_cache = trad_frame_cache_zalloc (this_frame);
2014 *this_cache = this_trad_cache;
2016 /* The return address is in the link register. */
2017 trad_frame_set_reg_realreg (this_trad_cache,
2018 gdbarch_pc_regnum (gdbarch),
2019 NIOS2_RA_REGNUM);
2021 /* Frame ID, since it's a frameless / stackless function, no stack
2022 space is allocated and SP on entry is the current SP. */
2023 pc = get_frame_pc (this_frame);
2024 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2025 stack_addr = get_frame_register_unsigned (this_frame, NIOS2_SP_REGNUM);
2026 trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr));
2027 /* Assume that the frame's base is the same as the stack pointer. */
2028 trad_frame_set_this_base (this_trad_cache, stack_addr);
2030 return this_trad_cache;
2033 /* Implement the this_id function for the stub unwinder. */
2035 static void
2036 nios2_stub_frame_this_id (struct frame_info *this_frame, void **this_cache,
2037 struct frame_id *this_id)
2039 struct trad_frame_cache *this_trad_cache
2040 = nios2_stub_frame_cache (this_frame, this_cache);
2042 trad_frame_get_id (this_trad_cache, this_id);
2045 /* Implement the prev_register function for the stub unwinder. */
2047 static struct value *
2048 nios2_stub_frame_prev_register (struct frame_info *this_frame,
2049 void **this_cache, int regnum)
2051 struct trad_frame_cache *this_trad_cache
2052 = nios2_stub_frame_cache (this_frame, this_cache);
2054 return trad_frame_get_register (this_trad_cache, this_frame, regnum);
2057 /* Implement the sniffer function for the stub unwinder.
2058 This unwinder is used for cases where the normal
2059 prologue-analysis-based unwinder can't work,
2060 such as PLT stubs. */
2062 static int
2063 nios2_stub_frame_sniffer (const struct frame_unwind *self,
2064 struct frame_info *this_frame, void **cache)
2066 gdb_byte dummy[4];
2067 CORE_ADDR pc = get_frame_address_in_block (this_frame);
2069 /* Use the stub unwinder for unreadable code. */
2070 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
2071 return 1;
2073 if (in_plt_section (pc))
2074 return 1;
2076 return 0;
2079 /* Define the data structures for the stub unwinder. */
2081 static const struct frame_unwind nios2_stub_frame_unwind =
2083 "nios2 stub",
2084 NORMAL_FRAME,
2085 default_frame_unwind_stop_reason,
2086 nios2_stub_frame_this_id,
2087 nios2_stub_frame_prev_register,
2088 NULL,
2089 nios2_stub_frame_sniffer
2094 /* Determine where to set a single step breakpoint while considering
2095 branch prediction. */
2097 static CORE_ADDR
2098 nios2_get_next_pc (struct regcache *regcache, CORE_ADDR pc)
2100 struct gdbarch *gdbarch = regcache->arch ();
2101 nios2_gdbarch_tdep *tdep = (nios2_gdbarch_tdep *) gdbarch_tdep (gdbarch);
2102 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
2103 unsigned int insn;
2104 const struct nios2_opcode *op = nios2_fetch_insn (gdbarch, pc, &insn);
2105 int ra;
2106 int rb;
2107 int imm;
2108 unsigned int uimm;
2109 int wb, id, ret;
2110 enum branch_condition cond;
2112 /* Do something stupid if we can't disassemble the insn at pc. */
2113 if (op == NULL)
2114 return pc + NIOS2_OPCODE_SIZE;
2116 if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond))
2118 int ras = regcache_raw_get_signed (regcache, ra);
2119 int rbs = regcache_raw_get_signed (regcache, rb);
2120 unsigned int rau = regcache_raw_get_unsigned (regcache, ra);
2121 unsigned int rbu = regcache_raw_get_unsigned (regcache, rb);
2123 pc += op->size;
2124 switch (cond)
2126 case branch_none:
2127 pc += imm;
2128 break;
2129 case branch_eq:
2130 if (ras == rbs)
2131 pc += imm;
2132 break;
2133 case branch_ne:
2134 if (ras != rbs)
2135 pc += imm;
2136 break;
2137 case branch_ge:
2138 if (ras >= rbs)
2139 pc += imm;
2140 break;
2141 case branch_geu:
2142 if (rau >= rbu)
2143 pc += imm;
2144 break;
2145 case branch_lt:
2146 if (ras < rbs)
2147 pc += imm;
2148 break;
2149 case branch_ltu:
2150 if (rau < rbu)
2151 pc += imm;
2152 break;
2153 default:
2154 break;
2158 else if (nios2_match_jmpi (insn, op, mach, &uimm))
2159 pc = (pc & 0xf0000000) | uimm;
2160 else if (nios2_match_calli (insn, op, mach, &uimm))
2162 CORE_ADDR callto = (pc & 0xf0000000) | uimm;
2163 if (tdep->is_kernel_helper != NULL
2164 && tdep->is_kernel_helper (callto))
2165 /* Step over call to kernel helper, which we cannot debug
2166 from user space. */
2167 pc += op->size;
2168 else
2169 pc = callto;
2172 else if (nios2_match_jmpr (insn, op, mach, &ra))
2173 pc = regcache_raw_get_unsigned (regcache, ra);
2174 else if (nios2_match_callr (insn, op, mach, &ra))
2176 CORE_ADDR callto = regcache_raw_get_unsigned (regcache, ra);
2177 if (tdep->is_kernel_helper != NULL
2178 && tdep->is_kernel_helper (callto))
2179 /* Step over call to kernel helper. */
2180 pc += op->size;
2181 else
2182 pc = callto;
2185 else if (nios2_match_ldwm (insn, op, mach, &uimm, &ra, &imm, &wb, &id, &ret)
2186 && ret)
2188 /* If ra is in the reglist, we have to use the value saved in the
2189 stack frame rather than the current value. */
2190 if (uimm & (1 << NIOS2_RA_REGNUM))
2191 pc = nios2_unwind_pc (gdbarch, get_current_frame ());
2192 else
2193 pc = regcache_raw_get_unsigned (regcache, NIOS2_RA_REGNUM);
2196 else if (nios2_match_trap (insn, op, mach, &uimm) && uimm == 0)
2198 if (tdep->syscall_next_pc != NULL)
2199 return tdep->syscall_next_pc (get_current_frame (), op);
2202 else
2203 pc += op->size;
2205 return pc;
2208 /* Implement the software_single_step gdbarch method. */
2210 static std::vector<CORE_ADDR>
2211 nios2_software_single_step (struct regcache *regcache)
2213 CORE_ADDR next_pc = nios2_get_next_pc (regcache, regcache_read_pc (regcache));
2215 return {next_pc};
2218 /* Implement the get_longjump_target gdbarch method. */
2220 static int
2221 nios2_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2223 struct gdbarch *gdbarch = get_frame_arch (frame);
2224 nios2_gdbarch_tdep *tdep = (nios2_gdbarch_tdep *) gdbarch_tdep (gdbarch);
2225 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2226 CORE_ADDR jb_addr = get_frame_register_unsigned (frame, NIOS2_R4_REGNUM);
2227 gdb_byte buf[4];
2229 if (target_read_memory (jb_addr + (tdep->jb_pc * 4), buf, 4))
2230 return 0;
2232 *pc = extract_unsigned_integer (buf, 4, byte_order);
2233 return 1;
2236 /* Implement the type_align gdbarch function. */
2238 static ULONGEST
2239 nios2_type_align (struct gdbarch *gdbarch, struct type *type)
2241 switch (type->code ())
2243 case TYPE_CODE_PTR:
2244 case TYPE_CODE_FUNC:
2245 case TYPE_CODE_FLAGS:
2246 case TYPE_CODE_INT:
2247 case TYPE_CODE_RANGE:
2248 case TYPE_CODE_FLT:
2249 case TYPE_CODE_ENUM:
2250 case TYPE_CODE_REF:
2251 case TYPE_CODE_RVALUE_REF:
2252 case TYPE_CODE_CHAR:
2253 case TYPE_CODE_BOOL:
2254 case TYPE_CODE_DECFLOAT:
2255 case TYPE_CODE_METHODPTR:
2256 case TYPE_CODE_MEMBERPTR:
2257 type = check_typedef (type);
2258 return std::min<ULONGEST> (4, TYPE_LENGTH (type));
2259 default:
2260 return 0;
2264 /* Implement the gcc_target_options gdbarch method. */
2265 static std::string
2266 nios2_gcc_target_options (struct gdbarch *gdbarch)
2268 /* GCC doesn't know "-m32". */
2269 return {};
2272 /* Initialize the Nios II gdbarch. */
2274 static struct gdbarch *
2275 nios2_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2277 struct gdbarch *gdbarch;
2278 int i;
2279 tdesc_arch_data_up tdesc_data;
2280 const struct target_desc *tdesc = info.target_desc;
2282 if (!tdesc_has_registers (tdesc))
2283 /* Pick a default target description. */
2284 tdesc = tdesc_nios2;
2286 /* Check any target description for validity. */
2287 if (tdesc_has_registers (tdesc))
2289 const struct tdesc_feature *feature;
2290 int valid_p;
2292 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nios2.cpu");
2293 if (feature == NULL)
2294 return NULL;
2296 tdesc_data = tdesc_data_alloc ();
2298 valid_p = 1;
2300 for (i = 0; i < NIOS2_NUM_REGS; i++)
2301 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i,
2302 nios2_reg_names[i]);
2304 if (!valid_p)
2305 return NULL;
2308 /* Find a candidate among the list of pre-declared architectures. */
2309 arches = gdbarch_list_lookup_by_info (arches, &info);
2310 if (arches != NULL)
2311 return arches->gdbarch;
2313 /* None found, create a new architecture from the information
2314 provided. */
2315 nios2_gdbarch_tdep *tdep = new nios2_gdbarch_tdep;
2316 gdbarch = gdbarch_alloc (&info, tdep);
2318 /* longjmp support not enabled by default. */
2319 tdep->jb_pc = -1;
2321 /* Data type sizes. */
2322 set_gdbarch_ptr_bit (gdbarch, 32);
2323 set_gdbarch_addr_bit (gdbarch, 32);
2324 set_gdbarch_short_bit (gdbarch, 16);
2325 set_gdbarch_int_bit (gdbarch, 32);
2326 set_gdbarch_long_bit (gdbarch, 32);
2327 set_gdbarch_long_long_bit (gdbarch, 64);
2328 set_gdbarch_float_bit (gdbarch, 32);
2329 set_gdbarch_double_bit (gdbarch, 64);
2331 set_gdbarch_type_align (gdbarch, nios2_type_align);
2333 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2334 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2336 /* The register set. */
2337 set_gdbarch_num_regs (gdbarch, NIOS2_NUM_REGS);
2338 set_gdbarch_sp_regnum (gdbarch, NIOS2_SP_REGNUM);
2339 set_gdbarch_pc_regnum (gdbarch, NIOS2_PC_REGNUM); /* Pseudo register PC */
2341 set_gdbarch_register_name (gdbarch, nios2_register_name);
2342 set_gdbarch_register_type (gdbarch, nios2_register_type);
2344 /* Provide register mappings for stabs and dwarf2. */
2345 set_gdbarch_stab_reg_to_regnum (gdbarch, nios2_dwarf_reg_to_regnum);
2346 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nios2_dwarf_reg_to_regnum);
2348 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2350 /* Call dummy code. */
2351 set_gdbarch_frame_align (gdbarch, nios2_frame_align);
2353 set_gdbarch_return_value (gdbarch, nios2_return_value);
2355 set_gdbarch_skip_prologue (gdbarch, nios2_skip_prologue);
2356 set_gdbarch_stack_frame_destroyed_p (gdbarch, nios2_stack_frame_destroyed_p);
2357 set_gdbarch_breakpoint_kind_from_pc (gdbarch, nios2_breakpoint_kind_from_pc);
2358 set_gdbarch_sw_breakpoint_from_kind (gdbarch, nios2_sw_breakpoint_from_kind);
2360 set_gdbarch_unwind_pc (gdbarch, nios2_unwind_pc);
2362 /* The dwarf2 unwinder will normally produce the best results if
2363 the debug information is available, so register it first. */
2364 dwarf2_append_unwinders (gdbarch);
2365 frame_unwind_append_unwinder (gdbarch, &nios2_stub_frame_unwind);
2366 frame_unwind_append_unwinder (gdbarch, &nios2_frame_unwind);
2368 /* Single stepping. */
2369 set_gdbarch_software_single_step (gdbarch, nios2_software_single_step);
2371 /* Target options for compile. */
2372 set_gdbarch_gcc_target_options (gdbarch, nios2_gcc_target_options);
2374 /* Hook in ABI-specific overrides, if they have been registered. */
2375 gdbarch_init_osabi (info, gdbarch);
2377 if (tdep->jb_pc >= 0)
2378 set_gdbarch_get_longjmp_target (gdbarch, nios2_get_longjmp_target);
2380 frame_base_set_default (gdbarch, &nios2_frame_base);
2382 /* Enable inferior call support. */
2383 set_gdbarch_push_dummy_call (gdbarch, nios2_push_dummy_call);
2385 if (tdesc_data != nullptr)
2386 tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data));
2388 return gdbarch;
2391 void _initialize_nios2_tdep ();
2392 void
2393 _initialize_nios2_tdep ()
2395 gdbarch_register (bfd_arch_nios2, nios2_gdbarch_init, NULL);
2396 initialize_tdesc_nios2 ();
2398 /* Allow debugging this file's internals. */
2399 add_setshow_boolean_cmd ("nios2", class_maintenance, &nios2_debug,
2400 _("Set Nios II debugging."),
2401 _("Show Nios II debugging."),
2402 _("When on, Nios II specific debugging is enabled."),
2403 NULL,
2404 NULL,
2405 &setdebuglist, &showdebuglist);