gprofng/common/hwctable.c

   1 /* Copyright (C) 2021 Free Software Foundation, Inc.
   2    Contributed by Oracle.
   3
   4    This file is part of GNU Binutils.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <errno.h>
  24 #include <string.h>
  25 #include <limits.h>
  26
  27 #include "hwcdrv.h"
  28 #include "hwcfuncs.h"
  29
  30 /* TprintfT(<level>,...) definitions.  Adjust per module as needed */
  31 #define DBG_LT0 0 // for high-level configuration, unexpected errors/warnings
  32 #define DBG_LT1 1 // for configuration details, warnings
  33 #define DBG_LT2 2
  34 #define DBG_LT3 3
  35
  36 /*---------------------------------------------------------------------------*/
  37 /* compile options */
  38
  39 #define DISALLOW_USI_USII_6357446
  40 /* Solaris 9/libcpc1 allows cpc_bind() to work on US-IIe processors, even
  41    though this processor cannot generate profiling interrupts. */
  42
  43 #define DISALLOW_PENTIUM_PRO_MMX_7007575
  44 /* Solaris/libcpc2 defaults to "Pentium Pro with MMX, Pentium II"
  45    when it doesn't recognize an Intel processor.  As a result,
  46    when collect attempts to start Pentium Pro counters on a
  47    new machine (e.g. Westmere as of 1/2011), the OS may hang.  */
  48
  49 /* Register 0 counter doesn't work on Niagara T1 version (?) */
  50 #define WORKAROUND_6231196_NIAGARA1_NO_CTR_0
  51
  52 /*---------------------------------------------------------------------------*/
  53 /* consts, macros */
  54
  55 /* 10^N rates */
  56 #define PRELOADS_9      1001000001
  57 #define PRELOADS_85      320100001
  58 #define PRELOADS_8       100100001
  59 #define PRELOADS_75       32010001
  60 #define PRELOADS_7        10010001
  61 #define PRELOADS_65        3201001
  62 #define PRELOADS_6         1001001
  63 #define PRELOADS_55         320101
  64 #define PRELOADS_5          100101
  65 #define PRELOADS_45          32001
  66 #define PRELOADS_4           10001
  67 #define PRELOADS_35           3201
  68 #define PRELOADS_3            1001
  69 #define PRELOADS_25            301
  70
  71 #define ABST_TBD        ABST_NONE /* to be determined */
  72
  73 /*---------------------------------------------------------------------------*/
  74 /* prototypes */
  75 static void hwc_cb (uint_t cpc_regno, const char *name);
  76 static void attrs_cb (const char *attr);
  77 static int attr_is_valid (int forKernel, const char *attr);
  78
  79 /*---------------------------------------------------------------------------*/
  80 /* HWC definition tables */
  81
  82 /*
  83   comments on hwcentry tables
  84   ---------------------------
  85   name:          this field should not contain '~'.
  86   int_name:      actual name of register, may contain ~ attribute specifications.
  87   regnum:        assigned register.
  88   metric:        if non-NULL, is a 'standard' counter that will show up in help.
  89   timecvt:       >0: can convert to time, 'timecvt' CPU cycles per event
  90                  =0: counts events
  91                  <0: can convert to time, count reference-clock cycles at '-timecvt' MHz
  92   memop:         see description for ABST_type enum
  93  */
  94
  95 // PRELOAD(): generates an interval based on the cycles/event and CPU GHZ.
  96 // Note: the macro tweaks the interval so that it ends in decimal 001.
  97 #define CYC_PER_SAMPLE (1000ULL*1000*1000/100) // cycles per signal at 1ghz, 100 samples/second
  98 #define PRELOAD(min_cycles_per_event,ghz) (((ghz)*CYC_PER_SAMPLE/(min_cycles_per_event))/100*100+1)
  99
 100 // PRELOAD_DEF: initial value for uncalibrated events.
 101 // This value should be based on a rate that will work for the slowest changing
 102 // HWCs, HWCs where there are many CPU cycles between events.
 103 //
 104 // The interval needs to target the slowest HWCs so that
 105 // automatic adjustment of HWC overflow intervals can adapt.
 106 #define PRELOAD_DEF PRELOAD(1000,3)  // default interval targets 1000 cycles/event at 3ghz
 107 // For er_kernel, which HWC intervals cannot be adjusted automatically for ON/HI/LO,
 108 // The interval should target some safe interval for fast events
 109 #define PRELOAD_DEF_ERKERNEL PRELOAD(4,4)  // default interval targets 4 cycles/event at 4ghz
 110
 111 static const Hwcentry empty_ctr = {NULL, NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, 0};
 112
 113
 114 // --- use cycles counter to expose "system_time" on Linux ---
 115 #define SYSTIME_REGNOS REGNO_ANY // Linux: make sys_time/usr_time available for data collection
 116 // Note: For x86, Linux and Solaris use different ref-clock names
 117 #define USE_INTEL_REF_CYCLES(MHZ) \
 118     {"usr_time","unhalted-reference-cycles",                SYSTIME_REGNOS, STXT("User CPU"),   PRELOAD(900,MHZ),  -(MHZ), ABST_NONE}, \
 119     {"usr_time","cpu_clk_unhalted.ref_p",                   SYSTIME_REGNOS, STXT("User CPU"),   PRELOAD(900,MHZ),  -(MHZ), ABST_NONE}, \
 120     {"sys_time","unhalted-reference-cycles~system=1~user=0", SYSTIME_REGNOS, STXT("System CPU"), PRELOAD(900,MHZ), -(MHZ), ABST_NONE}, \
 121     {"sys_time","cpu_clk_unhalted.ref_p~system=1~user=0",   SYSTIME_REGNOS, STXT("System CPU"), PRELOAD( 900,MHZ), -(MHZ), ABST_NONE}, \
 122     {"cycles0", "unhalted-reference-cycles",                0,  NULL,   PRELOAD( 900,MHZ),  -(MHZ), ABST_NONE}, /*hidden*/ \
 123     {"cycles0", "cpu_clk_unhalted.ref_p",                   0,  NULL,   PRELOAD( 900,MHZ),  -(MHZ), ABST_NONE}, /*hidden*/ \
 124     {"cycles1", "unhalted-reference-cycles",                1,  NULL,   PRELOAD( 910,MHZ),  -(MHZ), ABST_NONE}, /*hidden*/ \
 125     {"cycles1", "cpu_clk_unhalted.ref_p",                   1,  NULL,   PRELOAD( 910,MHZ),  -(MHZ), ABST_NONE}, /*hidden*/ \
 126     /* end of list */
 127
 128 #define SPARC_CYCLES \
 129     {"usr_time","Cycles_user",                  SYSTIME_REGNOS, STXT("User CPU"),   PRELOADS_75,1, ABST_NONE}, \
 130     {"sys_time","Cycles_user~system=1~user=0",  SYSTIME_REGNOS, STXT("System CPU"), PRELOADS_75,1, ABST_NONE}, \
 131     /* end of list */
 132
 133
 134 /* --- PERF_EVENTS "software" definitions --- */
 135 #define PERF_EVENTS_SW_EVENT_ALIASES \
 136 // none supported for now
 137 #if 0
 138     {"usr",             "PERF_COUNT_SW_TASK_CLOCK",                     REGNO_ANY, STXT("User CPU"),                    PRELOADS_7, -(1000), ABST_NONE}, \
 139     {"sys",             "PERF_COUNT_SW_TASK_CLOCK~system=1~user=0",     REGNO_ANY, STXT("System CPU"),                  PRELOADS_7, -(1000), ABST_NONE}, \
 140     /* end of list */
 141 #endif
 142
 143 #define PERF_EVENTS_SW_EVENT_DEFS \
 144 // none supported for now
 145 #if 0
 146     {"PERF_COUNT_SW_TASK_CLOCK",                                        NULL, REGNO_ANY, NULL, PRELOADS_7, -(1000),ABST_NONE}, \
 147     /* end of list */
 148 #endif
 149
 150 /*
 151  * The PAPI descriptive strings used to be wrapped with STXT(),
 152  * a macro defined in perfan/include/i18n.h.  For the time being,
 153  * we want to demote the PAPI counters by omitting the
 154  * descriptions.  So we use a new macro PAPITXT() for this purpose.
 155  */
 156 #define PAPITXT(x)  NULL
 157
 158 /* Solaris "Generic" Counters */
 159 static Hwcentry papi_generic_list[] = {
 160   {"PAPI_l1_dcm", NULL, REGNO_ANY, PAPITXT ("L1 D-cache misses"), PRELOADS_65, 0, ABST_NONE},
 161   {"PAPI_l1_icm", NULL, REGNO_ANY, PAPITXT ("L1 I-cache misses"), PRELOADS_6, 0, ABST_NONE},
 162   {"PAPI_l2_dcm", NULL, REGNO_ANY, PAPITXT ("L2 D-cache misses"), PRELOADS_6, 0, ABST_NONE},
 163   {"PAPI_l2_icm", NULL, REGNO_ANY, PAPITXT ("L2 I-cache misses"), PRELOADS_6, 0, ABST_NONE},
 164   {"PAPI_l3_dcm", NULL, REGNO_ANY, PAPITXT ("L3 D-cache misses"), PRELOADS_5, 0, ABST_NONE},
 165   {"PAPI_l3_icm", NULL, REGNO_ANY, PAPITXT ("L3 I-cache misses"), PRELOADS_5, 0, ABST_NONE},
 166   {"PAPI_l1_tcm", NULL, REGNO_ANY, PAPITXT ("L1 misses"), PRELOADS_65, 0, ABST_NONE},
 167   {"PAPI_l2_tcm", NULL, REGNO_ANY, PAPITXT ("L2 misses"), PRELOADS_6, 0, ABST_NONE},
 168   {"PAPI_l3_tcm", NULL, REGNO_ANY, PAPITXT ("L3 misses"), PRELOADS_5, 0, ABST_NONE},
 169   {"PAPI_ca_snp", NULL, REGNO_ANY, PAPITXT ("Requests for a snoop"), PRELOADS_6, 0, ABST_NONE},
 170   {"PAPI_ca_shr", NULL, REGNO_ANY, PAPITXT ("Requests for exclusive access to shared cache line"), PRELOADS_6, 0, ABST_NONE},
 171   {"PAPI_ca_cln", NULL, REGNO_ANY, PAPITXT ("Requests for exclusive access to clean cache line"), PRELOADS_6, 0, ABST_NONE},
 172   {"PAPI_ca_inv", NULL, REGNO_ANY, PAPITXT ("Requests for cache line invalidation"), PRELOADS_6, 0, ABST_NONE},
 173   {"PAPI_ca_itv", NULL, REGNO_ANY, PAPITXT ("Requests for cache line intervention"), PRELOADS_6, 0, ABST_NONE},
 174   {"PAPI_l3_ldm", NULL, REGNO_ANY, PAPITXT ("L3 load misses"), PRELOADS_5, 0, ABST_NONE},
 175   {"PAPI_l3_stm", NULL, REGNO_ANY, PAPITXT ("L3 store misses"), PRELOADS_5, 0, ABST_NONE},
 176   {"PAPI_bru_idl", NULL, REGNO_ANY, PAPITXT ("Cycles branch units are idle"), PRELOADS_7, 1, ABST_NONE},
 177   {"PAPI_fxu_idl", NULL, REGNO_ANY, PAPITXT ("Cycles integer units are idle"), PRELOADS_7, 1, ABST_NONE},
 178   {"PAPI_fpu_idl", NULL, REGNO_ANY, PAPITXT ("Cycles FP units are idle"), PRELOADS_7, 1, ABST_NONE},
 179   {"PAPI_lsu_idl", NULL, REGNO_ANY, PAPITXT ("Cycles load/store units are idle"), PRELOADS_7, 1, ABST_NONE},
 180   {"PAPI_tlb_dm", NULL, REGNO_ANY, PAPITXT ("DTLB misses"), PRELOADS_6, 0, ABST_NONE},
 181   {"PAPI_tlb_im", NULL, REGNO_ANY, PAPITXT ("ITLB misses"), PRELOADS_6, 0, ABST_NONE},
 182   {"PAPI_tlb_tl", NULL, REGNO_ANY, PAPITXT ("Total TLB misses"), PRELOADS_6, 0, ABST_NONE},
 183   {"PAPI_tlb_tm", NULL, REGNO_ANY, PAPITXT ("Total TLB misses"), PRELOADS_6, 0, ABST_NONE},
 184   {"PAPI_l1_ldm", NULL, REGNO_ANY, PAPITXT ("L1 load misses"), PRELOADS_65, 0, ABST_NONE},
 185   {"PAPI_l1_stm", NULL, REGNO_ANY, PAPITXT ("L1 store misses"), PRELOADS_65, 0, ABST_NONE},
 186   {"PAPI_l2_ldm", NULL, REGNO_ANY, PAPITXT ("L2 load misses"), PRELOADS_6, 0, ABST_NONE},
 187   {"PAPI_l2_stm", NULL, REGNO_ANY, PAPITXT ("L2 store misses"), PRELOADS_6, 0, ABST_NONE},
 188   {"PAPI_btac_m", NULL, REGNO_ANY, PAPITXT ("Branch target address cache misses"), PRELOADS_5, 0, ABST_NONE},
 189   {"PAPI_prf_dm", NULL, REGNO_ANY, PAPITXT ("Data prefetch cache misses"), PRELOADS_65, 0, ABST_NONE},
 190   {"PAPI_l3_dch", NULL, REGNO_ANY, PAPITXT ("L3 D-cache hits"), PRELOADS_6, 0, ABST_NONE},
 191   {"PAPI_tlb_sd", NULL, REGNO_ANY, PAPITXT ("TLB shootdowns"), PRELOADS_6, 0, ABST_NONE},
 192   {"PAPI_csr_fal", NULL, REGNO_ANY, PAPITXT ("Failed store conditional instructions"), PRELOADS_6, 0, ABST_NONE},
 193   {"PAPI_csr_suc", NULL, REGNO_ANY, PAPITXT ("Successful store conditional instructions"), PRELOADS_7, 0, ABST_NONE},
 194   {"PAPI_csr_tot", NULL, REGNO_ANY, PAPITXT ("Total store conditional instructions"), PRELOADS_7, 0, ABST_NONE},
 195   {"PAPI_mem_scy", NULL, REGNO_ANY, PAPITXT ("Cycles Stalled Waiting for memory accesses"), PRELOADS_7, 1, ABST_NONE},
 196   {"PAPI_mem_rcy", NULL, REGNO_ANY, PAPITXT ("Cycles Stalled Waiting for memory reads"), PRELOADS_7, 1, ABST_NONE},
 197   {"PAPI_mem_wcy", NULL, REGNO_ANY, PAPITXT ("Cycles Stalled Waiting for memory writes"), PRELOADS_7, 1, ABST_NONE},
 198   {"PAPI_stl_icy", NULL, REGNO_ANY, PAPITXT ("Cycles with no instruction issue"), PRELOADS_7, 1, ABST_NONE},
 199   {"PAPI_ful_icy", NULL, REGNO_ANY, PAPITXT ("Cycles with maximum instruction issue"), PRELOADS_7, 1, ABST_NONE},
 200   {"PAPI_stl_ccy", NULL, REGNO_ANY, PAPITXT ("Cycles with no instructions completed"), PRELOADS_7, 1, ABST_NONE},
 201   {"PAPI_ful_ccy", NULL, REGNO_ANY, PAPITXT ("Cycles with maximum instructions completed"), PRELOADS_7, 1, ABST_NONE},
 202   {"PAPI_hw_int", NULL, REGNO_ANY, PAPITXT ("Hardware interrupts"), PRELOADS_5, 0, ABST_NONE},
 203   {"PAPI_br_ucn", NULL, REGNO_ANY, PAPITXT ("Unconditional branch instructions"), PRELOADS_7, 0, ABST_NONE},
 204   {"PAPI_br_cn", NULL, REGNO_ANY, PAPITXT ("Cond. branch instructions"), PRELOADS_7, 0, ABST_NONE},
 205   {"PAPI_br_tkn", NULL, REGNO_ANY, PAPITXT ("Cond. branch instructions taken"), PRELOADS_7, 0, ABST_NONE},
 206   {"PAPI_br_ntk", NULL, REGNO_ANY, PAPITXT ("Cond. branch instructions not taken"), PRELOADS_7, 0, ABST_NONE},
 207   {"PAPI_br_msp", NULL, REGNO_ANY, PAPITXT ("Cond. branch instructions mispredicted"), PRELOADS_6, 0, ABST_NONE},
 208   {"PAPI_br_prc", NULL, REGNO_ANY, PAPITXT ("Cond. branch instructions correctly predicted"), PRELOADS_7, 0, ABST_NONE},
 209   {"PAPI_fma_ins", NULL, REGNO_ANY, PAPITXT ("FMA instructions completed"), PRELOADS_65, 0, ABST_NONE},
 210   {"PAPI_tot_iis", NULL, REGNO_ANY, PAPITXT ("Instructions issued"), PRELOADS_7, 0, ABST_NONE},
 211   {"PAPI_tot_ins", NULL, REGNO_ANY, PAPITXT ("Instructions completed"), PRELOADS_7, 0, ABST_NONE},
 212   {"PAPI_int_ins", NULL, REGNO_ANY, PAPITXT ("Integer instructions"), PRELOADS_7, 0, ABST_NONE},
 213   {"PAPI_fp_ins", NULL, REGNO_ANY, PAPITXT ("Floating-point instructions"), PRELOADS_7, 0, ABST_NONE},
 214   {"PAPI_ld_ins", NULL, REGNO_ANY, PAPITXT ("Load instructions"), PRELOADS_7, 0, ABST_NONE},
 215   {"PAPI_sr_ins", NULL, REGNO_ANY, PAPITXT ("Store instructions"), PRELOADS_7, 0, ABST_NONE},
 216   {"PAPI_br_ins", NULL, REGNO_ANY, PAPITXT ("Branch instructions"), PRELOADS_7, 0, ABST_NONE},
 217   {"PAPI_vec_ins", NULL, REGNO_ANY, PAPITXT ("Vector/SIMD instructions"), PRELOADS_7, 0, ABST_NONE},
 218   {"PAPI_res_stl", NULL, REGNO_ANY, PAPITXT ("Cycles stalled on any resource"), PRELOADS_7, 1, ABST_NONE},
 219   {"PAPI_fp_stal", NULL, REGNO_ANY, PAPITXT ("Cycles the FP unit(s) are stalled"), PRELOADS_7, 1, ABST_NONE},
 220   {"PAPI_tot_cyc", NULL, REGNO_ANY, PAPITXT ("Total cycles"), PRELOADS_7, 1, ABST_NONE},
 221   {"PAPI_lst_ins", NULL, REGNO_ANY, PAPITXT ("Load/store instructions completed"), PRELOADS_7, 0, ABST_NONE},
 222   {"PAPI_syc_ins", NULL, REGNO_ANY, PAPITXT ("Sync instructions completed"), PRELOADS_65, 0, ABST_NONE},
 223   {"PAPI_l1_dch", NULL, REGNO_ANY, PAPITXT ("L1 D-cache hits"), PRELOADS_7, 0, ABST_NONE},
 224   {"PAPI_l2_dch", NULL, REGNO_ANY, PAPITXT ("L2 D-cache hits"), PRELOADS_65, 0, ABST_NONE},
 225   {"PAPI_l1_dca", NULL, REGNO_ANY, PAPITXT ("L1 D-cache accesses"), PRELOADS_7, 0, ABST_NONE},
 226   {"PAPI_l2_dca", NULL, REGNO_ANY, PAPITXT ("L2 D-cache accesses"), PRELOADS_65, 0, ABST_NONE},
 227   {"PAPI_l3_dca", NULL, REGNO_ANY, PAPITXT ("L3 D-cache accesses"), PRELOADS_6, 0, ABST_NONE},
 228   {"PAPI_l1_dcr", NULL, REGNO_ANY, PAPITXT ("L1 D-cache reads"), PRELOADS_7, 0, ABST_NONE},
 229   {"PAPI_l2_dcr", NULL, REGNO_ANY, PAPITXT ("L2 D-cache reads"), PRELOADS_65, 0, ABST_NONE},
 230   {"PAPI_l3_dcr", NULL, REGNO_ANY, PAPITXT ("L3 D-cache reads"), PRELOADS_6, 0, ABST_NONE},
 231   {"PAPI_l1_dcw", NULL, REGNO_ANY, PAPITXT ("L1 D-cache writes"), PRELOADS_7, 0, ABST_NONE},
 232   {"PAPI_l2_dcw", NULL, REGNO_ANY, PAPITXT ("L2 D-cache writes"), PRELOADS_65, 0, ABST_NONE},
 233   {"PAPI_l3_dcw", NULL, REGNO_ANY, PAPITXT ("L3 D-cache writes"), PRELOADS_6, 0, ABST_NONE},
 234   {"PAPI_l1_ich", NULL, REGNO_ANY, PAPITXT ("L1 I-cache hits"), PRELOADS_7, 0, ABST_NONE},
 235   {"PAPI_l2_ich", NULL, REGNO_ANY, PAPITXT ("L2 I-cache hits"), PRELOADS_65, 0, ABST_NONE},
 236   {"PAPI_l3_ich", NULL, REGNO_ANY, PAPITXT ("L3 I-cache hits"), PRELOADS_6, 0, ABST_NONE},
 237   {"PAPI_l1_ica", NULL, REGNO_ANY, PAPITXT ("L1 I-cache accesses"), PRELOADS_7, 0, ABST_NONE},
 238   {"PAPI_l2_ica", NULL, REGNO_ANY, PAPITXT ("L2 I-cache accesses"), PRELOADS_65, 0, ABST_NONE},
 239   {"PAPI_l3_ica", NULL, REGNO_ANY, PAPITXT ("L3 I-cache accesses"), PRELOADS_6, 0, ABST_NONE},
 240   {"PAPI_l1_icr", NULL, REGNO_ANY, PAPITXT ("L1 I-cache reads"), PRELOADS_7, 0, ABST_NONE},
 241   {"PAPI_l2_icr", NULL, REGNO_ANY, PAPITXT ("L2 I-cache reads"), PRELOADS_65, 0, ABST_NONE},
 242   {"PAPI_l3_icr", NULL, REGNO_ANY, PAPITXT ("L3 I-cache reads"), PRELOADS_6, 0, ABST_NONE},
 243   {"PAPI_l1_icw", NULL, REGNO_ANY, PAPITXT ("L1 I-cache writes"), PRELOADS_7, 0, ABST_NONE},
 244   {"PAPI_l2_icw", NULL, REGNO_ANY, PAPITXT ("L2 I-cache writes"), PRELOADS_65, 0, ABST_NONE},
 245   {"PAPI_l3_icw", NULL, REGNO_ANY, PAPITXT ("L3 I-cache writes"), PRELOADS_6, 0, ABST_NONE},
 246   {"PAPI_l1_tch", NULL, REGNO_ANY, PAPITXT ("L1 total hits"), PRELOADS_7, 0, ABST_NONE},
 247   {"PAPI_l2_tch", NULL, REGNO_ANY, PAPITXT ("L2 total hits"), PRELOADS_65, 0, ABST_NONE},
 248   {"PAPI_l3_tch", NULL, REGNO_ANY, PAPITXT ("L3 total hits"), PRELOADS_6, 0, ABST_NONE},
 249   {"PAPI_l1_tca", NULL, REGNO_ANY, PAPITXT ("L1 total accesses"), PRELOADS_7, 0, ABST_NONE},
 250   {"PAPI_l2_tca", NULL, REGNO_ANY, PAPITXT ("L2 total accesses"), PRELOADS_65, 0, ABST_NONE},
 251   {"PAPI_l3_tca", NULL, REGNO_ANY, PAPITXT ("L3 total accesses"), PRELOADS_6, 0, ABST_NONE},
 252   {"PAPI_l1_tcr", NULL, REGNO_ANY, PAPITXT ("L1 total reads"), PRELOADS_7, 0, ABST_NONE},
 253   {"PAPI_l2_tcr", NULL, REGNO_ANY, PAPITXT ("L2 total reads"), PRELOADS_65, 0, ABST_NONE},
 254   {"PAPI_l3_tcr", NULL, REGNO_ANY, PAPITXT ("L3 total reads"), PRELOADS_6, 0, ABST_NONE},
 255   {"PAPI_l1_tcw", NULL, REGNO_ANY, PAPITXT ("L1 total writes"), PRELOADS_7, 0, ABST_NONE},
 256   {"PAPI_l2_tcw", NULL, REGNO_ANY, PAPITXT ("L2 total writes"), PRELOADS_65, 0, ABST_NONE},
 257   {"PAPI_l3_tcw", NULL, REGNO_ANY, PAPITXT ("L3 total writes"), PRELOADS_6, 0, ABST_NONE},
 258   {"PAPI_fml_ins", NULL, REGNO_ANY, PAPITXT ("FP multiply instructions"), PRELOADS_7, 0, ABST_NONE},
 259   {"PAPI_fad_ins", NULL, REGNO_ANY, PAPITXT ("FP add instructions"), PRELOADS_7, 0, ABST_NONE},
 260   {"PAPI_fdv_ins", NULL, REGNO_ANY, PAPITXT ("FP divide instructions"), PRELOADS_7, 0, ABST_NONE},
 261   {"PAPI_fsq_ins", NULL, REGNO_ANY, PAPITXT ("FP square root instructions"), PRELOADS_65, 0, ABST_NONE},
 262   {"PAPI_fnv_ins", NULL, REGNO_ANY, PAPITXT ("FP inverse instructions"), PRELOADS_7, 0, ABST_NONE},
 263   {"PAPI_fp_ops", NULL, REGNO_ANY, PAPITXT ("FP operations"), PRELOADS_7, 0, ABST_NONE},
 264   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 265 };
 266
 267 static Hwcentry usIlist[] = {
 268   {"cycles", "Cycle_cnt", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
 269   {"insts", "Instr_cnt", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
 270   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 271 };
 272
 273 static Hwcentry usIIIlist[] = /* III, IIIi, IIIp.  Note that some counters are processor-specific */{
 274   {"cycles", "Cycle_cnt", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
 275   {"insts", "Instr_cnt", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
 276   {"icm", "IC_miss", REGNO_ANY, STXT ("I$ Misses"), PRELOADS_5, 0, ABST_NONE},
 277   {"dcrm", "DC_rd_miss", REGNO_ANY, STXT ("D$ Read Misses"), PRELOADS_5, 0, ABST_LOAD},
 278   {"dcwm", "DC_wr_miss", REGNO_ANY, STXT ("D$ Write Misses"), PRELOADS_5, 0, ABST_STORE},
 279   {"dcr", "DC_rd", REGNO_ANY, STXT ("D$ Read Refs"), PRELOADS_6, 0, ABST_LOAD},
 280   {"dcw", "DC_wr", REGNO_ANY, STXT ("D$ Write Refs"), PRELOADS_6, 0, ABST_STORE},
 281   {"ecref", "EC_ref", REGNO_ANY, STXT ("E$ Refs"), PRELOADS_6, 0, ABST_LDST},
 282   {"itlbm", "ITLB_miss", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE},
 283   {"dtlbm", "DTLB_miss", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_5, 0, ABST_US_DTLBM},
 284   {"ecm", "EC_misses", REGNO_ANY, STXT ("E$ Misses"), PRELOADS_5, 0, ABST_LDST},
 285   {"ecrm", "EC_rd_miss", REGNO_ANY, STXT ("E$ Read Misses"), PRELOADS_5, 0, ABST_LOAD},
 286   {"ecml", "EC_miss_local", REGNO_ANY, STXT ("E$ Local Misses"), PRELOADS_5, 0, ABST_LDST},
 287   {"ecmr", "EC_miss_remote", REGNO_ANY, STXT ("E$ Remote Misses"), PRELOADS_5, 0, ABST_LDST},
 288   {"ecim", "EC_ic_miss", REGNO_ANY, STXT ("E$ Instr. Misses"), PRELOADS_5, 0, ABST_NONE},
 289   {"icstall", "Dispatch0_IC_miss", REGNO_ANY, STXT ("I$ Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 290   {"dcstall", "Re_DC_miss", REGNO_ANY, STXT ("D$ and E$ Stall Cycles"), PRELOADS_6, 1, ABST_LOAD},
 291   {"ecstall", "Re_EC_miss", REGNO_ANY, STXT ("E$ Stall Cycles"), PRELOADS_6, 1, ABST_LOAD},
 292   {"sqstall", "Rstall_storeQ", REGNO_ANY, STXT ("StoreQ Stall Cycles"), PRELOADS_6, 1, ABST_STORE},
 293   {"rawstall", "Re_RAW_miss", REGNO_ANY, STXT ("RAW Stall Cycles"), PRELOADS_6, 1, ABST_LOAD},
 294   {"dcmissov", "Re_DC_missovhd", REGNO_ANY, STXT ("DC Miss Ovhd"), PRELOADS_6, 1, ABST_LOAD},
 295   {"fpustall", "Re_FPU_bypass", REGNO_ANY, STXT ("FPU Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 296   {"fpusestall", "Rstall_FP_use", REGNO_ANY, STXT ("FPU Use Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 297   {"iustall", "Rstall_IU_use", REGNO_ANY, STXT ("IU Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 298   {"fpadd", "FA_pipe_completion", REGNO_ANY, STXT ("FP Adds"), PRELOADS_6, 0, ABST_NONE},
 299   {"fpmul", "FM_pipe_completion", REGNO_ANY, STXT ("FP Muls"), PRELOADS_6, 0, ABST_NONE},
 300
 301   /* explicit definitions of (hidden) entries for proper counters */
 302   /*  Only counters that can be time converted, or are load-store need to be in this table */
 303   {"Cycle_cnt", NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
 304   {"EC_miss_mtag_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 305   {"DC_rd_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 306   {"DC_wr_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 307   {"DC_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 308   {"DC_wr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 309   {"EC_ref", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 310   {"EC_snoop_inv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/},
 311   {"EC_wb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 312   {"EC_wb_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 313   {"DTLB_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_US_DTLBM},
 314   {"EC_misses", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 315   {"EC_rd_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 316   {"PC_port0_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 317   {"EC_miss_local", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 318   {"EC_miss_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 319   {"EC_snoop_cb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/},
 320   {"WC_snoop_cb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/},
 321   {"WC_scrubbed", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 322   {"WC_wb_wo_read", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 323   {"PC_MS_misses", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 324   {"PC_soft_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 325   {"PC_hard_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 326   {"PC_port1_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 327   {"PC_snoop_inv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE /*?*/},
 328   {"SW_count_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_COUNT},
 329   {"SW_count_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_COUNT},
 330   {"Dispatch0_IC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 331   {"Dispatch0_mispred", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 332   {"Dispatch0_br_target", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 333   {"Dispatch0_2nd_br", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 334   {"Dispatch_rs_mispred", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 335   {"Rstall_storeQ", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_STORE},
 336   {"Rstall_FP_use", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 337   {"Rstall_IU_use", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 338   {"EC_write_hit_RTO", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 339   {"Re_RAW_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 340   {"Re_DC_missovhd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 341   {"Re_endian_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 342   {"Re_FPU_bypass", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 343   {"Re_DC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 344   {"Re_EC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 345   {"Re_PC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 346   {"SI_snoop", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 347   {"SI_ciq_flow", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 348   {"SI_owned", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 349   {"MC_msl_busy_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 350   {"MC_mdb_overflow_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 351   {"MC_page_close_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 352   {"MC_reads_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 353   {"MC_reads_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 354   {"MC_reads_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 355   {"MC_reads_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 356   {"MC_writes_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 357   {"MC_writes_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 358   {"MC_writes_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 359   {"MC_writes_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 360   {"MC_stalls_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 361   {"MC_stalls_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 362   {"MC_stalls_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 363   {"MC_stalls_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 364
 365   /* additional (hidden) aliases, for convenience */
 366   {"cycles0", "Cycle_cnt", 0, NULL, PRELOADS_75, 1, ABST_NONE},
 367   {"cycles1", "Cycle_cnt", 1, NULL, PRELOADS_75, 1, ABST_NONE},
 368   {"insts0", "Instr_cnt", 0, NULL, PRELOADS_75, 0, ABST_NONE},
 369   {"insts1", "Instr_cnt", 1, NULL, PRELOADS_75, 0, ABST_NONE},
 370   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 371 };
 372
 373 static Hwcentry usIVplist[] = {
 374   {"cycles", "Cycle_cnt", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
 375   {"insts", "Instr_cnt", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
 376   {"icm", "IC_fill", REGNO_ANY, STXT ("I$ Misses"), PRELOADS_5, 0, ABST_NONE},
 377   {"dcrm", "DC_rd_miss", REGNO_ANY, STXT ("D$ Read Misses"), PRELOADS_5, 0, ABST_LOAD},
 378   {"dcwm", "DC_wr_miss", REGNO_ANY, STXT ("D$ Write Misses"), PRELOADS_5, 0, ABST_STORE},
 379   {"dcr", "DC_rd", REGNO_ANY, STXT ("D$ Read Refs"), PRELOADS_6, 0, ABST_LOAD},
 380   {"dcw", "DC_wr", REGNO_ANY, STXT ("D$ Write Refs"), PRELOADS_6, 0, ABST_STORE},
 381   {"itlbm", "ITLB_miss", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE},
 382   {"dtlbm", "DTLB_miss", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_5, 0, ABST_US_DTLBM},
 383   {"l2ref", "L2_ref", REGNO_ANY, STXT ("L2$ Refs"), PRELOADS_5, 0, ABST_LDST},
 384   {"l2m", "L2_miss", REGNO_ANY, STXT ("L2$ Misses"), PRELOADS_5, 0, ABST_LDST},
 385   {"l2rm", "L2_rd_miss", REGNO_ANY, STXT ("L2$ Read Misses"), PRELOADS_5, 0, ABST_LOAD},
 386   {"l2im", "L2_IC_miss", REGNO_ANY, STXT ("L2$ Instr. Misses"), PRELOADS_5, 0, ABST_NONE},
 387   {"ecm", "L3_miss", REGNO_ANY, STXT ("E$ Misses"), PRELOADS_5, 0, ABST_LDST},
 388   {"ecrm", "L3_rd_miss", REGNO_ANY, STXT ("E$ Read Misses"), PRELOADS_5, 0, ABST_LOAD},
 389   {"ecml", "SSM_L3_miss_local", REGNO_ANY, STXT ("E$ Local Misses"), PRELOADS_5, 0, ABST_LDST},
 390   {"ecmr", "SSM_L3_miss_remote", REGNO_ANY, STXT ("E$ Remote Misses"), PRELOADS_5, 0, ABST_LDST},
 391   {"ecim", "L3_IC_miss", REGNO_ANY, STXT ("E$ Instr. Misses"), PRELOADS_5, 0, ABST_NONE},
 392   {"icstall", "Dispatch0_IC_miss", REGNO_ANY, STXT ("I$ Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 393   {"dcstall", "Re_DC_miss", REGNO_ANY, STXT ("D$ and E$ Stall Cycles"), PRELOADS_6, 1, ABST_LOAD},
 394   {"ecstall", "Re_L3_miss", REGNO_ANY, STXT ("E$ Stall Cycles"), PRELOADS_6, 1, ABST_LOAD},
 395   {"sqstall", "Rstall_storeQ", REGNO_ANY, STXT ("StoreQ Stall Cycles"), PRELOADS_6, 1, ABST_STORE},
 396   {"rawstall", "Re_RAW_miss", REGNO_ANY, STXT ("RAW Stall Cycles"), PRELOADS_6, 1, ABST_LOAD},
 397   {"dcmissov", "Re_DC_missovhd", REGNO_ANY, STXT ("DC Miss Ovhd"), PRELOADS_6, 1, ABST_LOAD},
 398   {"fpustall", "Re_FPU_bypass", REGNO_ANY, STXT ("FPU Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 399   {"fpusestall", "Rstall_FP_use", REGNO_ANY, STXT ("FPU Use Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 400   {"iustall", "Rstall_IU_use", REGNO_ANY, STXT ("IU Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 401   {"fpadd", "FA_pipe_completion", REGNO_ANY, STXT ("FP Adds"), PRELOADS_6, 0, ABST_NONE},
 402   {"fpmul", "FM_pipe_completion", REGNO_ANY, STXT ("FP Muls"), PRELOADS_6, 0, ABST_NONE},
 403
 404   /* explicit definitions of (hidden) entries for proper counters */
 405   /*  Only counters that can be time converted, or are load-store need to be in this table */
 406   {"Cycle_cnt", NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
 407   {"DC_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 408   {"DC_rd_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 409   {"DC_wr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 410   {"DC_wr_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 411   {"DTLB_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_US_DTLBM},
 412   {"Dispatch0_2nd_br", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 413   {"Dispatch0_IC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 414   {"Dispatch0_other", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 415   {"L2L3_snoop_cb_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/},
 416   {"L2L3_snoop_inv_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/},
 417   {"L2_hit_I_state_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST /*?*/},
 418   {"L2_hit_other_half", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 419   {"L2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 420   {"L2_rd_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 421   {"L2_ref", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 422   {"L2_snoop_cb_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/},
 423   {"L2_snoop_inv_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/},
 424   {"L2_wb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 425   {"L2_wb_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 426   {"L2_write_hit_RTO", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 427   {"L2_write_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 428   {"L3_hit_I_state_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 429   {"L3_hit_other_half", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 430   {"L3_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 431   {"L3_rd_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 432   {"L3_wb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 433   {"L3_wb_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 434   {"L3_write_hit_RTO", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 435   {"L3_write_miss_RTO", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 436   {"MC_reads_0_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 437   {"MC_reads_1_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 438   {"MC_reads_2_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 439   {"MC_reads_3_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 440   {"MC_stalls_0_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 441   {"MC_stalls_1_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 442   {"MC_stalls_2_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 443   {"MC_stalls_3_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 444   {"MC_writes_0_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 445   {"MC_writes_1_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 446   {"MC_writes_2_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 447   {"MC_writes_3_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 448   /*? {"PC_MS_misses",  NULL, REGNO_ANY, NULL, PRELOAD_DEF,     0, ABST_LOAD}, */
 449   {"PC_hard_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 450   {"PC_inv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE /*?*/},
 451   {"PC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 452   {"PC_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 453   {"PC_soft_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 454   {"Re_DC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 455   {"Re_DC_missovhd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 456   {"Re_FPU_bypass", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 457   {"Re_L2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 458   {"Re_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 459   {"Re_PFQ_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 460   {"Re_RAW_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 461   {"Rstall_FP_use", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 462   {"Rstall_IU_use", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 463   {"Rstall_storeQ", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_STORE},
 464   {"SI_RTO_src_data", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 465   {"SI_RTS_src_data", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 466   {"SI_ciq_flow_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 467   {"SI_owned_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 468   {"SI_snoop_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 469   {"ecml", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 470   {"ecmr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 471   {"SSM_L3_miss_local", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST /*?*/},
 472   {"SSM_L3_miss_mtag_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST /*?*/},
 473   {"SSM_L3_miss_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST /*?*/},
 474   {"SSM_L3_wb_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE /*?*/},
 475   {"SSM_new_transaction_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_TBD /*?*/},
 476
 477   /* additional (hidden) aliases, for convenience */
 478   {"cycles0", "Cycle_cnt", 0, NULL, PRELOADS_75, 1, ABST_NONE},
 479   {"cycles1", "Cycle_cnt", 1, NULL, PRELOADS_75, 1, ABST_NONE},
 480   {"insts0", "Instr_cnt", 0, NULL, PRELOADS_75, 0, ABST_NONE},
 481   {"insts1", "Instr_cnt", 1, NULL, PRELOADS_75, 0, ABST_NONE},
 482   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 483 };
 484
 485 static Hwcentry niagara1[] =
 486         /* CPC_ULTRA_T1              , "UltraSPARC T1" */{
 487   {"insts", "Instr_cnt", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
 488 #ifndef WORKAROUND_6231196_NIAGARA1_NO_CTR_0 /* since register 0 counter don't work XXX */
 489   {"icm", "IC_miss", REGNO_ANY, STXT ("I$ Misses"), PRELOADS_5, 0, ABST_NONE},
 490   {"itlbm", "ITLB_miss", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE},
 491   {"ecim", "L2_imiss", REGNO_ANY, STXT ("E$ Instr. Misses"), PRELOADS_4, 0, ABST_NONE},
 492   {"dcm", "DC_miss", REGNO_ANY, STXT ("D$ Misses"), PRELOADS_5, 0, ABST_EXACT},
 493   {"dtlbm", "DTLB_miss", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_5, 0, ABST_EXACT},
 494   {"ecdm", "L2_dmiss_ld", REGNO_ANY, STXT ("E$ Data Misses"), PRELOADS_4, 0, ABST_EXACT},
 495   {"flops", "FP_instr_cnt", REGNO_ANY, STXT ("Floating-point Ops"), PRELOADS_6, 0, ABST_NONE},
 496
 497   /* explicit definitions of (hidden) entries for proper counters */
 498   /*  Only counters that can be time converted, or are load-store need to be in this table */
 499   {"SB_full", NULL, REGNO_ANY, NULL, PRELOADS_6, 1, ABST_NONE},
 500   {"DC_miss", NULL, REGNO_ANY, NULL, PRELOADS_6, 0, ABST_EXACT},
 501   {"DTLB_miss", NULL, REGNO_ANY, NULL, PRELOADS_6, 0, ABST_EXACT},
 502   {"L2_dmiss_ld", NULL, REGNO_ANY, NULL, PRELOADS_6, 0, ABST_EXACT},
 503 #endif
 504
 505   /* additional (hidden) aliases, for convenience */
 506   {"insts1", "Instr_cnt", 1, NULL, PRELOADS_75, 0, ABST_NONE},
 507   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 508 };
 509
 510 static Hwcentry niagara2[] = {
 511   /* CPC_ULTRA_T2              , "UltraSPARC T2" */
 512   /* CPC_ULTRA_T2              , "UltraSPARC T2+" */
 513   {"insts", "Instr_cnt", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
 514   {"loads", "Instr_ld", REGNO_ANY, STXT ("Load Instructions"), PRELOADS_7, 0, ABST_EXACT},
 515   {"stores", "Instr_st", REGNO_ANY, STXT ("Store Instructions"), PRELOADS_6, 0, ABST_EXACT},
 516   {"dcm", "DC_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_6, 0, ABST_EXACT},
 517   {"dtlbm", "DTLB_miss", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_6, 0, ABST_NONE},
 518   {"l2drm", "L2_dmiss_ld", REGNO_ANY, STXT ("L2 D-cache Read Misses (See Bug 15664448)"), PRELOADS_5, 0, ABST_EXACT},
 519   {"icm", "IC_miss", REGNO_ANY, STXT ("L1 I-cache Misses"), PRELOADS_5, 0, ABST_NONE},
 520   {"itlbm", "ITLB_miss", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE},
 521   {"l2im", "L2_imiss", REGNO_ANY, STXT ("L2 I-cache Misses"), PRELOADS_4, 0, ABST_NONE},
 522
 523   /* explicit definitions of (hidden) entries for proper counters */
 524   /* Only counters that can be time converted, or are load-store need to be in this table */
 525   {"Instr_ld", NULL, REGNO_ANY, NULL, PRELOADS_7, 0, ABST_EXACT},
 526   {"Instr_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
 527   {"Atomics", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
 528   {"DC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
 529   {"L2_dmiss_ld", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
 530   {"DTLB_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
 531   {"DES_3DES_busy_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 532   {"AES_busy_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 533   {"Kasumi_busy_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 534   {"MD5_SHA-1_SHA-256_busy_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 535   {"MA_busy_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 536
 537   /* additional (hidden) aliases, for convenience */
 538   {"insts1", "Instr_cnt", 1, NULL, PRELOADS_75, 0, ABST_NONE},
 539   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 540 };
 541
 542 static Hwcentry sparc_t4[] = {
 543   // Identical to sparc_t5_m6 except for: l3m_spec
 544   // when updating this table, also update sparc_t5_m6[]
 545   // obsolete aliases marked with REGNO_INVALID (allows reading of older experiments)
 546   {"l2l3dh", "DC_miss_L2_L3_hit_nospec", REGNO_INVALID, STXT ("L2 or L3 D-cache Hits"), PRELOADS_6, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 547   {"l3m", "DC_miss_remote_L3_hit_nospec~emask=0x6", REGNO_INVALID, STXT ("L3 D-cache Misses"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 548   {"lmh", "DC_miss_local_hit_nospec", REGNO_INVALID, STXT ("Local Mem. Hits"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 549   {"rmh", "DC_miss_remote_L3_hit_nospec", REGNO_INVALID, STXT ("Remote Mem. Hits"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 550   {"pqs", "PQ_tag_wait", REGNO_INVALID, STXT ("Pick Queue Stalls"), PRELOADS_7, 1, ABST_NONE}, // old alias name
 551   {"raw_stb", "RAW_hit_st_buf", REGNO_INVALID, STXT ("RAW Hazard in Store Buffer"), PRELOADS_55, 0, ABST_NONE}, // 11@full hit, 60@partial hit (in future, combine w/st_q)
 552   {"raw_stq", "RAW_hit_st_q", REGNO_INVALID, STXT ("RAW Hazard in Store Queue"), PRELOADS_55, 0, ABST_NONE}, // 11@full hit, 60@partial hit (in future, combine w/st_buf)
 553   {"sel_stalls", "Sel_0_ready", REGNO_INVALID, STXT ("Stalls Another Thread Selected"), PRELOADS_7, 1, ABST_NONE},
 554   {"icm", "IC_miss", REGNO_INVALID, STXT ("L1 I-Cache Misses"), PRELOADS_55, 0, ABST_NONE}, // 20@ l2/l3 hit (guess)
 555   {"icm_stalls", "IC_miss", REGNO_INVALID, STXT ("L1 I-Cache Miss Est Stalls"), PRELOADS_55, 25, ABST_NONE}, // 25@ l2-20/l3-50
 556
 557   // current aliases
 558   SPARC_CYCLES
 559   {"cycles", "Cycles_user", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
 560   {"insts", "Instr_all", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
 561   {"c_stalls", "Commit_0", REGNO_ANY, STXT ("Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
 562   {"loads", "Instr_ld", REGNO_ANY, STXT ("Load Instructions"), PRELOADS_7, 0, ABST_EXACT},
 563   {"stores", "Instr_st", REGNO_ANY, STXT ("Store Instructions"), PRELOADS_7, 0, ABST_EXACT},
 564   {"dcm", "DC_miss_nospec", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_EXACT},
 565   {"l3m_spec", "DC_miss_local_hit~emask=0x6", REGNO_ANY, STXT ("L3 D-cache Speculative Misses"), PRELOADS_5, 0, ABST_NONE, STXT ("Loads that speculatively missed local L3")}, // T4 encoding (430 lm, 690 rm) ~5 misses overlap on t5/pico_ile
 566   //  {"l3m_spec",      "DC_miss_local_hit~emask=0x30",         REGNO_ANY, STXT("L3 D-cache Speculative Misses"),PRELOADS_5,0, ABST_NONE, STXT("Loads that speculatively missed local L3")}, // T5/M6 encoding (430 lm, 690 rm) ~5 misses overlap on t5/pico_ile
 567   {"lmh_spec", "DC_miss_local_hit", REGNO_ANY, STXT ("Local Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
 568   {"rmh_spec", "DC_miss_remote_L3_hit", REGNO_ANY, STXT ("Remote Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
 569   //
 570   {"dtlbm", "DTLB_miss_asynch", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_55, 0, ABST_NONE}, // 10@l1 hit, 24@l2 hit, 60@l3 hit, 500@l3 miss, 5000@trap  0.001 events/cycle
 571   {"dtlb_hwtw_stalls", "DTLB_HWTW_all", REGNO_ANY, STXT ("DTLB HWTW Est Stalls"), PRELOADS_55, 25, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss requiring a HW tablewalk")}, // l2-20, l3-50
 572   {"dtlb_trap_stalls", "DTLB_fill_trap", REGNO_ANY, STXT ("DTLB Trap Est Stalls"), PRELOADS_35, 5000, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss with HW tablewalk unsuccessful")}, // 5000@trap
 573   {"rawhaz", "RAW_hit_st_q~emask=0xf", REGNO_ANY, STXT ("Read-after-write Hazards"), PRELOADS_55, 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write hazards)")},
 574   {"br_msp_stalls", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict Stalls"), PRELOADS_6, 24, ABST_NONE, STXT ("Estimated time stalled on Branch mispredictions")}, // 24@miss, %5 of branches is bad
 575   {"br_msp", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict"), PRELOADS_6, 0, ABST_NONE}, // 24@miss, %5 of branches is bad
 576   {"br_tkn", "Br_taken", REGNO_ANY, STXT ("Branch Taken"), PRELOADS_7, 0, ABST_NONE}, // 2 cycles minimum
 577   {"br_ins", "Branches", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE}, // 24@miss, %5 of branches is bad
 578   {"fgu", "Instr_FGU_crypto", REGNO_ANY, STXT ("FP/VIS/Crypto Instructions"), PRELOADS_7, 0, ABST_NONE}, // 1 cycle/event
 579
 580   /* explicit definitions of (hidden) entries for proper counters */
 581   /* Counters that can be time converted, support memspace, or have a short_desc need to be in this table */
 582
 583   {"Sel_pipe_drain_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting with correct instructions when pipeline has to drain after branch misprediction")},
 584   {"Sel_0_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting for various conditions to be resolved")},
 585   {"Sel_0_ready", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread was ready to have its instructions selected but another hardware thread was selected instead")},
 586   {"Sel_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that only 1 instruction or uop was selected")},
 587   {"Sel_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that 2 instructions or uops were selected")},
 588
 589   {"Pick_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 590   {"Pick_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 591   {"Pick_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 592   {"Pick_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 593   {"Pick_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 594
 595   {"Branches", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Control transfer instructions completed, excluding trap-related transfers")},
 596   {"Instr_FGU_crypto", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("FP and VIS instructions completed by the Floating Point and Graphics Unit")},
 597   {"Instr_ld", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Load instructions completed")},
 598   {"Instr_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Store instructions completed")},
 599   {"SPR_ring_ops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Specialized instructions that require internal use of SPR ring completed")},
 600   {"Instr_other", NULL, REGNO_ANY, NULL, PRELOAD (2, 4), 0, ABST_NONE, STXT ("Basic arithmetic and logical instructions completed")},
 601   {"Instr_all", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 0, ABST_NONE, STXT ("Total instructions completed")},
 602
 603   {"Br_taken", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branch instructions taken and completed")},
 604   {"Sw_count_intr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("SW Count instructions completed")},
 605   {"Atomics", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Atomic instructions, including CASA/XA, completed")},
 606   {"SW_prefetch", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("PREFETCH and PREFETCHA instructions completed")},
 607   {"Block_ld_st", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Block load/store instructions completed")},
 608
 609   {"BTC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branches delayed a few extra cycles because branch target not found in Branch Target Cache")},
 610
 611   {"ITLB_fill_8KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 8K page")},
 612   {"ITLB_fill_64KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 64K page")},
 613   {"ITLB_fill_4MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 4M page")},
 614   {"ITLB_fill_256MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 256M page")},
 615   {"ITLB_fill_2GB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")},
 616   {"ITLB_fill_trap", NULL, REGNO_ANY, NULL, PRELOAD (1000, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk unsuccessful")},
 617   {"ITLB_miss_asynch", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk search done")},
 618
 619   {"Fetch_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 620   {"Fetch_0_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 621
 622   {"Instr_buffer_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 623
 624   {"PQ_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 625   {"ROB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 626   {"LB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 627   {"ROB_LB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 628   {"SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 629   {"ROB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 630   {"LB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 631   {"ROB_LB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 632   {"DTLB_miss_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 633
 634   {"ITLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L2D")},
 635   {"ITLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L3 or neighbor L2D")},
 636   {"ITLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk missed all local caches")},
 637   {"DTLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L2D")},
 638   {"DTLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L3 or neighbor L2D")},
 639   {"DTLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk missed all local caches")},
 640   {"DTLB_HWTW_all", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss requiring HW tablewalk")},
 641
 642   {"DC_miss_L2_L3_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT},
 643   {"DC_miss_local_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_EXACT},
 644   {"DC_miss_remote_L3_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_EXACT},
 645   {"DC_miss_nospec", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT, STXT ("Loads that missed local L1D")},
 646
 647   {"DTLB_fill_8KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 8K page")},
 648   {"DTLB_fill_64KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 64K page")},
 649   {"DTLB_fill_4MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 4M page")},
 650   {"DTLB_fill_256MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 256M page")},
 651   {"DTLB_fill_2GB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")},
 652   {"DTLB_fill_trap", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk unsuccessful")},
 653   {"DTLB_miss_asynch", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk search done")},
 654   {"RAW_hit_st_buf", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) still in store buffer not yet committed")},
 655   {"RAW_hit_st_q", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) committed but in store queue not yet written to L2D")},
 656
 657   {"St_q_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 658
 659   {"St_hit_L2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L2D")},
 660   {"St_hit_L3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L3")},
 661
 662   {"DC_miss_L2_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local L2D or L3")},
 663   {"DC_miss_local_hit", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local memory")},
 664   {"DC_miss_remote_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit remote cache or remote memory")},
 665   {"DC_miss", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed L1D")},
 666
 667   {"L2_pipe_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 668
 669   {"Br_dir_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction was mispredicted")},
 670   {"Br_trg_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose target was mispredicted")},
 671   {"Br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction or target was mispredicted")},
 672
 673   {"Cycles_user", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 1, ABST_NONE, STXT ("Cycles hardware thread is active in specified mode(s)")},
 674   //
 675   {"Commit_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from this hardware thread")},
 676   {"Commit_0_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from any hardware thread on this core")},
 677   {"Commit_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 uop commits from this hardware thread")},
 678   {"Commit_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 2 uops commit from this hardware thread")},
 679   {"Commit_1_or_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 or 2 uops commit from this hardware thread")},
 680
 681   /* additional (hidden) aliases, for convenience */
 682   {"cycles0", "Cycles_user", 0, NULL, PRELOADS_8, 1, ABST_NONE},
 683   {"cycles1", "Cycles_user", 1, NULL, PRELOADS_8, 1, ABST_NONE},
 684   {"insts0", "Instr_all", 0, NULL, PRELOADS_8, 0, ABST_NONE},
 685   {"insts1", "Instr_all", 1, NULL, PRELOADS_8, 0, ABST_NONE},
 686   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 687 };
 688
 689 static Hwcentry sparc_t5_m6[] = {
 690   // Identical to sparc_t4 except for: l3m_spec
 691   // when updating this table, also update sparc_t4[]
 692   // obsolete aliases marked with REGNO_INVALID (allows reading of older experiments)
 693   {"l2l3dh", "DC_miss_L2_L3_hit_nospec", REGNO_INVALID, STXT ("L2 or L3 D-cache Hits"), PRELOADS_6, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 694   {"l3m", "DC_miss_remote_L3_hit_nospec~emask=0x6", REGNO_INVALID, STXT ("L3 D-cache Misses"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 695   {"lmh", "DC_miss_local_hit_nospec", REGNO_INVALID, STXT ("Local Mem. Hits"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 696   {"rmh", "DC_miss_remote_L3_hit_nospec", REGNO_INVALID, STXT ("Remote Mem. Hits"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 697   {"pqs", "PQ_tag_wait", REGNO_INVALID, STXT ("Pick Queue Stalls"), PRELOADS_7, 1, ABST_NONE}, // old alias name
 698   {"raw_stb", "RAW_hit_st_buf", REGNO_INVALID, STXT ("RAW Hazard in Store Buffer"), PRELOADS_55, 0, ABST_NONE}, // 11@full hit, 60@partial hit (in future, combine w/st_q)
 699   {"raw_stq", "RAW_hit_st_q", REGNO_INVALID, STXT ("RAW Hazard in Store Queue"), PRELOADS_55, 0, ABST_NONE}, // 11@full hit, 60@partial hit (in future, combine w/st_buf)
 700   {"sel_stalls", "Sel_0_ready", REGNO_INVALID, STXT ("Stalls Another Thread Selected"), PRELOADS_7, 1, ABST_NONE},
 701   {"icm", "IC_miss", REGNO_INVALID, STXT ("L1 I-Cache Misses"), PRELOADS_55, 0, ABST_NONE}, // 20@ l2/l3 hit (guess)
 702   {"icm_stalls", "IC_miss", REGNO_INVALID, STXT ("L1 I-Cache Miss Est Stalls"), PRELOADS_55, 25, ABST_NONE}, // 25@ l2-20/l3-50
 703
 704   // current aliases
 705   SPARC_CYCLES
 706   {"cycles", "Cycles_user", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
 707   {"insts", "Instr_all", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
 708   {"c_stalls", "Commit_0", REGNO_ANY, STXT ("Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
 709
 710   {"loads", "Instr_ld", REGNO_ANY, STXT ("Load Instructions"), PRELOADS_7, 0, ABST_EXACT},
 711   {"stores", "Instr_st", REGNO_ANY, STXT ("Store Instructions"), PRELOADS_7, 0, ABST_EXACT},
 712   {"dcm", "DC_miss_nospec", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_EXACT},
 713   //  {"l3m_spec",      "DC_miss_local_hit~emask=0x6",          REGNO_ANY, STXT("L3 D-cache Speculative Misses"),PRELOADS_5,0, ABST_NONE, STXT("Loads that speculatively missed local L3")}, // T4 encoding (430 lm, 690 rm) ~5 misses overlap on t5/pico_ile
 714   {"l3m_spec", "DC_miss_local_hit~emask=0x30", REGNO_ANY, STXT ("L3 D-cache Speculative Misses"), PRELOADS_5, 0, ABST_NONE, STXT ("Loads that speculatively missed local L3")}, // T5/M6 encoding (430 lm, 690 rm) ~5 misses overlap on t5/pico_ile
 715   {"lmh_spec", "DC_miss_local_hit", REGNO_ANY, STXT ("Local Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
 716   {"rmh_spec", "DC_miss_remote_L3_hit", REGNO_ANY, STXT ("Remote Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
 717   //
 718   {"dtlbm", "DTLB_miss_asynch", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_55, 0, ABST_NONE}, // 10@l1 hit, 24@l2 hit, 60@l3 hit, 500@l3 miss, 5000@trap  0.001 events/cycle
 719   {"dtlb_hwtw_stalls", "DTLB_HWTW_all", REGNO_ANY, STXT ("DTLB HWTW Est Stalls"), PRELOADS_55, 25, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss requiring a HW tablewalk")}, // l2-20, l3-50
 720   {"dtlb_trap_stalls", "DTLB_fill_trap", REGNO_ANY, STXT ("DTLB Trap Est Stalls"), PRELOADS_35, 5000, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss with HW tablewalk unsuccessful")}, // 5000@trap
 721   {"rawhaz", "RAW_hit_st_q~emask=0xf", REGNO_ANY, STXT ("Read-after-write Hazards"), PRELOADS_55, 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write hazards)")},
 722   {"br_msp_stalls", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict Stalls"), PRELOADS_6, 24, ABST_NONE, STXT ("Estimated time stalled on Branch mispredictions")}, // 24@miss, %5 of branches is bad
 723   {"br_msp", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict"), PRELOADS_6, 0, ABST_NONE}, // 24@miss, %5 of branches is bad
 724   {"br_tkn", "Br_taken", REGNO_ANY, STXT ("Branch Taken"), PRELOADS_7, 0, ABST_NONE}, // 2 cycles minimum
 725   {"br_ins", "Branches", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE}, // 24@miss, %5 of branches is bad
 726   {"fgu", "Instr_FGU_crypto", REGNO_ANY, STXT ("FP/VIS/Crypto Instructions"), PRELOADS_7, 0, ABST_NONE}, // 1 cycle/event
 727
 728   /* explicit definitions of (hidden) entries for proper counters */
 729   /* Counters that can be time converted, support memspace, or have a short_desc need to be in this table */
 730
 731   {"Sel_pipe_drain_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting with correct instructions when pipeline has to drain after branch misprediction")},
 732   {"Sel_0_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting for various conditions to be resolved")},
 733   {"Sel_0_ready", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread was ready to have its instructions selected but another hardware thread was selected instead")},
 734   {"Sel_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that only 1 instruction or uop was selected")},
 735   {"Sel_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that 2 instructions or uops were selected")},
 736
 737   {"Pick_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 738   {"Pick_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 739   {"Pick_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 740   {"Pick_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 741   {"Pick_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 742
 743   {"Branches", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Control transfer instructions completed, excluding trap-related transfers")},
 744   {"Instr_FGU_crypto", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("FP and VIS instructions completed by the Floating Point and Graphics Unit")},
 745   {"Instr_ld", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Load instructions completed")},
 746   {"Instr_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Store instructions completed")},
 747   {"SPR_ring_ops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Specialized instructions that require internal use of SPR ring completed")},
 748   {"Instr_other", NULL, REGNO_ANY, NULL, PRELOAD (2, 4), 0, ABST_NONE, STXT ("Basic arithmetic and logical instructions completed")},
 749   {"Instr_all", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 0, ABST_NONE, STXT ("Total instructions completed")},
 750
 751   {"Br_taken", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branch instructions taken and completed")},
 752   {"Sw_count_intr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("SW Count instructions completed")},
 753   {"Atomics", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Atomic instructions, including CASA/XA, completed")},
 754   {"SW_prefetch", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("PREFETCH and PREFETCHA instructions completed")},
 755   {"Block_ld_st", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Block load/store instructions completed")},
 756
 757   {"BTC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branches delayed a few extra cycles because branch target not found in Branch Target Cache")},
 758
 759   {"ITLB_fill_8KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 8K page")},
 760   {"ITLB_fill_64KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 64K page")},
 761   {"ITLB_fill_4MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 4M page")},
 762   {"ITLB_fill_256MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 256M page")},
 763   {"ITLB_fill_2GB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")},
 764   {"ITLB_fill_trap", NULL, REGNO_ANY, NULL, PRELOAD (1000, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk unsuccessful")},
 765   {"ITLB_miss_asynch", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk search done")},
 766
 767   {"Fetch_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 768   {"Fetch_0_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 769
 770   {"Instr_buffer_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 771
 772   {"PQ_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 773   {"ROB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 774   {"LB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 775   {"ROB_LB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 776   {"SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 777   {"ROB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 778   {"LB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 779   {"ROB_LB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 780   {"DTLB_miss_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 781
 782   {"ITLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L2D")},
 783   {"ITLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L3 or neighbor L2D")},
 784   {"ITLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk missed all local caches")},
 785   {"DTLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L2D")},
 786   {"DTLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L3 or neighbor L2D")},
 787   {"DTLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk missed all local caches")},
 788   {"DTLB_HWTW_all", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss requiring HW tablewalk")},
 789
 790   {"DC_miss_L2_L3_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT},
 791   {"DC_miss_local_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_EXACT},
 792   {"DC_miss_remote_L3_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_EXACT},
 793   {"DC_miss_nospec", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT, STXT ("Loads that missed local L1D")},
 794
 795   {"DTLB_fill_8KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 8K page")},
 796   {"DTLB_fill_64KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 64K page")},
 797   {"DTLB_fill_4MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 4M page")},
 798   {"DTLB_fill_256MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 256M page")},
 799   {"DTLB_fill_2GB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")},
 800   {"DTLB_fill_trap", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk unsuccessful")},
 801   {"DTLB_miss_asynch", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk search done")},
 802   {"RAW_hit_st_buf", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) still in store buffer not yet committed")},
 803   {"RAW_hit_st_q", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) committed but in store queue not yet written to L2D")},
 804
 805   {"St_q_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 806
 807   {"St_hit_L2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L2D")},
 808   {"St_hit_L3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L3")},
 809
 810   {"DC_miss_L2_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local L2D or L3")},
 811   {"DC_miss_local_hit", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local memory")},
 812   {"DC_miss_remote_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit remote cache or remote memory")},
 813   {"DC_miss", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed L1D")},
 814
 815   {"L2_pipe_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 816
 817   {"Br_dir_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction was mispredicted")},
 818   {"Br_trg_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose target was mispredicted")},
 819   {"Br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction or target was mispredicted")},
 820
 821   {"Cycles_user", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 1, ABST_NONE, STXT ("Cycles hardware thread is active in specified mode(s)")},
 822   //
 823   {"Commit_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from this hardware thread")},
 824   {"Commit_0_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from any hardware thread on this core")},
 825   {"Commit_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 uop commits from this hardware thread")},
 826   {"Commit_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 2 uops commit from this hardware thread")},
 827   {"Commit_1_or_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 or 2 uops commit from this hardware thread")},
 828
 829   /* additional (hidden) aliases, for convenience */
 830   {"cycles0", "Cycles_user", 0, NULL, PRELOADS_8, 1, ABST_NONE},
 831   {"cycles1", "Cycles_user", 1, NULL, PRELOADS_8, 1, ABST_NONE},
 832   {"insts0", "Instr_all", 0, NULL, PRELOADS_8, 0, ABST_NONE},
 833   {"insts1", "Instr_all", 1, NULL, PRELOADS_8, 0, ABST_NONE},
 834   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 835 };
 836
 837 static Hwcentry sparc_m7[] = {
 838   // obsolete aliases marked with REGNO_INVALID (allows reading of older experiments)
 839   {"icm", "IC_miss_commit", REGNO_INVALID, STXT ("L1 I-Cache Misses"), PRELOADS_6, 0, ABST_EXACT},
 840   {"raw_stb", "RAW_hit_st_buf", REGNO_INVALID, STXT ("RAW Hazard in Store Buffer"), PRELOADS_55, 0, ABST_NONE},
 841   {"raw_stq", "RAW_hit_st_q", REGNO_INVALID, STXT ("RAW Hazard in Store Queue"), PRELOADS_55, 0, ABST_NONE},
 842   {"pqs", "PQ_tag_wait_cyc", REGNO_INVALID, STXT ("Pick Queue Stalls"), PRELOADS_7, 1, ABST_NONE},
 843   {"sel_stalls", "Sel_0_ready_cyc", REGNO_INVALID, STXT ("Stalls Another Thread Selected"), PRELOADS_7, 1, ABST_NONE},
 844
 845   // current aliases
 846   SPARC_CYCLES
 847   {"cycles", "Cycles_user", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
 848   {"insts", "Instr_all", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
 849   {"c_stalls", "Commit_0_cyc", REGNO_ANY, STXT ("Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
 850
 851   {"loads", "Instr_ld", REGNO_ANY, STXT ("Load Instructions"), PRELOADS_7, 0, ABST_EXACT},
 852   {"stores", "Instr_st", REGNO_ANY, STXT ("Store Instructions"), PRELOADS_6, 0, ABST_EXACT},
 853   {"dcm", "DC_miss_commit", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_6, 0, ABST_EXACT},
 854
 855   {"l3m_spec", "DC_miss_L3_miss", REGNO_ANY, STXT ("L3 D-cache Speculative Misses"), PRELOADS_5, 0, ABST_NONE},
 856   {"lmh_spec", "DC_miss_local_mem_hit", REGNO_ANY, STXT ("Local Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
 857   {"rmh_spec", "DC_miss_remote_mem_hit", REGNO_ANY, STXT ("Remote Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
 858   //
 859   {"dtlbm", "DTLB_HWTW_search", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_55, 0, ABST_NONE}, // 10@l1 hit, 24@l2 hit, 60@l3 hit, 500@l3 miss, 5000@trap  0.001 events/cycle
 860   {"dtlb_hwtw_stalls", "DTLB_HWTW_ref", REGNO_ANY, STXT ("DTLB HWTW Est Stalls"), PRELOADS_55, 25, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss requiring a HW tablewalk")}, // l2-20, l3-50
 861   {"dtlb_trap_stalls", "DTLB_HWTW_miss_trap", REGNO_ANY, STXT ("DTLB Trap Est Stalls"), PRELOADS_35, 5000, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss with HW tablewalk unsuccessful")}, // 5000@trap
 862   {"rawhaz", "RAW_hit_st_q~emask=0xf", REGNO_ANY, STXT ("Read-after-write Hazards"), PRELOADS_55, 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write hazards)")},
 863   {"br_msp_stalls", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict Stalls"), PRELOADS_6, 24, ABST_NONE, STXT ("Estimated time stalled on Branch mispredictions")}, // 24@miss, %5 of branches is bad
 864   {"br_msp", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict"), PRELOADS_6, 0, ABST_NONE},
 865   {"br_tkn", "Br_taken", REGNO_ANY, STXT ("Branch Taken"), PRELOADS_7, 0, ABST_NONE},
 866   {"br_ins", "Branches", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE},
 867   {"fgu", "Instr_FGU_crypto", REGNO_ANY, STXT ("FP/VIS/Crypto Instructions"), PRELOADS_7, 0, ABST_NONE},
 868   {"spill_fill", "Flush_arch_exception", REGNO_ANY, STXT ("Reg Window Spill/Fill Est Stalls"), PRELOAD (100, 4), 80, ABST_NONE, STXT ("Estimated time stalled on flushing pipeline due to register window spill/fill")},
 869
 870   /* explicit definitions of (hidden) entries for proper counters */
 871   /*  Counters that can be time converted, support memspace, or have a short_desc need to be in this table */
 872   {"Sel_pipe_drain_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting with correct instructions when pipeline has to drain after branch misprediction")},
 873   {"Sel_0_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting for various conditions to be resolved")},
 874   {"Sel_0_ready_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread was ready to have its instructions selected but another hardware thread was selected instead")},
 875   {"Sel_1_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that only 1 instruction or uop was selected")},
 876   {"Sel_2_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that 2 instructions or uops were selected")},
 877
 878   {"Pick_0_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 879   {"Pick_1_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 880   {"Pick_2_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 881   {"Pick_3_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 882   {"Pick_any_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 883
 884   {"Branches", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Control transfer instructions completed, excluding trap-related transfers")},
 885   {"Instr_FGU_crypto", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("FP and VIS instructions completed by the Floating Point and Graphics Unit")},
 886   {"Instr_ld", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Load instructions completed")},
 887   {"Instr_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Store instructions completed")},
 888   {"Instr_SPR_ring_ops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Specialized instructions that require internal use of SPR ring completed")},
 889   {"Instr_other", NULL, REGNO_ANY, NULL, PRELOAD (2, 4), 0, ABST_NONE, STXT ("Basic arithmetic and logical instructions completed")},
 890   {"Instr_all", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 0, ABST_NONE, STXT ("Total instructions completed")},
 891
 892   {"Br_taken", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branch instructions taken and completed")},
 893   {"Instr_SW_count", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("SW Count instructions completed")},
 894   {"Instr_atomic", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Atomic instructions, including CASA/XA, completed")},
 895   {"Instr_SW_prefetch", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("PREFETCH and PREFETCHA instructions completed")},
 896   {"Instr_block_ld_st", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Block load/store instructions completed")},
 897
 898   {"Br_BTC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branches delayed a few extra cycles because branch target not found in Branch Target Cache")},
 899
 900   {"ITLB_HWTW_hit_8K", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 8K page")},
 901   {"ITLB_HWTW_hit_64K", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 64K page")},
 902   {"ITLB_HWTW_hit_4M", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 4M page")},
 903   {"ITLB_HWTW_hit_256M", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 256M page")},
 904   {"ITLB_HWTW_hit_2G_16G", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")},
 905   {"ITLB_HWTW_miss_trap", NULL, REGNO_ANY, NULL, PRELOAD (1000, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk unsuccessful")},
 906   {"ITLB_HWTW_search", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk search done")},
 907
 908   {"Fetch_0_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 909   {"Fetch_0_all_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 910
 911   {"Instr_buffer_full_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 912
 913   {"PQ_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 914   {"ROB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 915   {"LB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 916   {"SB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 917   {"ROB_LB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 918   {"ROB_SB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 919   {"LB_SB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 920   {"ROB_LB_SB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 921   {"DTLB_miss_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 922
 923   {"ITLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L2D")},
 924   {"ITLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L3 or neighbor L2D")},
 925   {"ITLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk missed all local caches")},
 926   {"DTLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L2D")},
 927   {"DTLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L3 or neighbor L2D")},
 928   {"DTLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk missed all local caches")},
 929   {"DTLB_HWTW_ref", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss requiring HW tablewalk")},
 930
 931   {"DC_miss_L2_L3_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT},
 932   {"DC_miss_nbr_scc_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_EXACT},
 933   {"DC_miss_nbr_scc_miss_commit", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_EXACT},
 934   {"DC_miss_commit", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT, STXT ("Loads that missed local L1D")},
 935
 936   {"DTLB_HWTW_hit_8K", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 8K page")},
 937   {"DTLB_HWTW_hit_64K", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 64K page")},
 938   {"DTLB_HWTW_hit_4M", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 4M page")},
 939   {"DTLB_HWTW_hit_256M", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 256M page")},
 940   {"DTLB_HWTW_hit_2G_16G", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")},
 941   {"DTLB_HWTW_miss_trap", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk unsuccessful")},
 942   {"DTLB_HWTW_search", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk search done")},
 943   {"RAW_hit_st_buf", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) still in store buffer not yet committed")},
 944   {"RAW_hit_st_q", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) committed but in store queue not yet written to L2D")},
 945
 946   {"St_q_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 947
 948   {"St_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L2D")},
 949   {"St_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L3")},
 950
 951   {"DC_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Loads that speculatively hit local L1D")},
 952   {"DC_miss_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local L2D")},
 953   {"DC_miss_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local L3")},
 954   {"DC_miss_nbr_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (100, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit neighbor L2D via local L3")},
 955   {"DC_miss_nbr_scc_hit", NULL, REGNO_ANY, NULL, PRELOAD (100, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit neighbor L3 on same socket")},
 956   {"DC_miss_nbr_scc_miss", NULL, REGNO_ANY, NULL, PRELOAD (400, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed all caches on same socket")},
 957   {"DC_miss", NULL, REGNO_ANY, NULL, PRELOAD (10, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed local L1D")},
 958   {"DC_miss_L2_miss", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed local L2D")},
 959   {"DC_miss_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (200, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed local L3")},
 960
 961   {"DC_miss_remote_scc_hit", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit remote cache on different socket")},
 962   {"DC_miss_local_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local memory")},
 963   {"DC_miss_remote_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (1000, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit remote memory")},
 964   {"Br_dir_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction was mispredicted")},
 965   {"Br_tgt_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose target was mispredicted")},
 966   {"Br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction or target was mispredicted")},
 967
 968   {"Cycles_user", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 1, ABST_NONE, STXT ("Cycles hardware thread is active in specified mode(s)")},
 969
 970   {"Flush_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Pipeline flushes due to a load that misses L3 when more than 1 hardware thread is active on the core")},
 971   {"Flush_br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Pipeline flushes due to a branch misprediction")},
 972   {"Flush_arch_exception", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Pipeline flushes due to SPARC architecture exceptions and trap entry/return")},
 973   {"Flush_other", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Pipeline flushes due to hardware thread state change to/from halted/paused state")},
 974   //
 975   {"Commit_0_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from this hardware thread")},
 976   {"Commit_0_all_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from any hardware thread on this core")},
 977   {"Commit_1_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 uop commits from this hardware thread")},
 978   {"Commit_2_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 2 uops commit from this hardware thread")},
 979   {"Commit_1_or_2_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 or 2 uops commit from this hardware thread")},
 980
 981
 982   /* additional (hidden) aliases, for convenience */
 983   {"cycles0", "Cycles_user", 0, NULL, PRELOADS_8, 1, ABST_NONE},
 984   {"cycles1", "Cycles_user", 1, NULL, PRELOADS_8, 1, ABST_NONE},
 985   {"insts0", "Instr_all", 0, NULL, PRELOADS_8, 0, ABST_NONE},
 986   {"insts1", "Instr_all", 1, NULL, PRELOADS_8, 0, ABST_NONE},
 987   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 988 };
 989
 990 static Hwcentry sparc_m8[] = {
 991   // current aliases
 992   SPARC_CYCLES
 993   {"cycles", "Cycles_user", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
 994   {"insts", "Instr_all", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
 995   {"c_stalls", "Commit_0_cyc", 3, STXT ("Stall Cycles"), PRELOADS_7, 1, ABST_NONE}, // 22825776: limit to reg 3
 996   {"Sel_0_wait_cyc", "Sel_0_cyc~emask=0x3f", REGNO_ANY, STXT ("Select Stall Cycles"), PRELOADS_7, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting for various conditions to be resolved that prevent it being selected")},
 997
 998   {"loads", "Instr_ld", REGNO_ANY, STXT ("Load Instructions"), PRELOADS_7, 0, ABST_EXACT},
 999   {"stores", "Instr_st", REGNO_ANY, STXT ("Store Instructions"), PRELOADS_6, 0, ABST_EXACT},
1000   {"dcm", "DC_miss_commit", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_6, 0, ABST_EXACT},
1001
1002   {"lmh_spec", "DC_miss_local_mem_hit", REGNO_ANY, STXT ("Local Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
1003   {"rmh_spec", "DC_miss_remote_mem_hit", REGNO_ANY, STXT ("Remote Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
1004
1005   {"dtlbm", "DTLB_HWTW", REGNO_ANY, STXT ("DTLB Misses"), PRELOAD (40, 5), 0, ABST_NONE}, // 10@l1 hit, 24@l2 hit, 60@l3 hit, 500@l3 miss, 5000@trap  0.001 events/cycle
1006   {"dtlb_hwtw_stalls", "DTLB_HWTW", REGNO_ANY, STXT ("DTLB HWTW Est Stalls"), PRELOAD (40, 5), 25, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss requiring a HW tablewalk")}, // l2-20, l3-50
1007   {"dtlb_trap_stalls", "DTLB_HWTW_miss_trap", REGNO_ANY, STXT ("DTLB Trap Est Stalls"), PRELOAD (800, 5), 5000, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss with HW tablewalk unsuccessful")}, // 5000@trap
1008   {"rawhaz", "RAW_hit", REGNO_ANY, STXT ("Read-after-write Hazards"), PRELOAD (40, 5), 0, ABST_NONE},
1009   {"br_msp_stalls", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict Stalls"), PRELOAD (40, 5), 24, ABST_NONE, STXT ("Estimated time stalled on Branch mispredictions")}, // 24@miss, %5 of branches is bad
1010   {"br_msp", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict"), PRELOAD (40, 5), 0, ABST_NONE},
1011   {"br_tkn", "Br_taken", REGNO_ANY, STXT ("Branch Taken"), PRELOADS_7, 0, ABST_NONE},
1012   {"br_ins", "Branches", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE},
1013   {"fgu", "Instr_FGU_crypto", REGNO_ANY, STXT ("FP/VIS/Crypto Instructions"), PRELOADS_7, 0, ABST_NONE},
1014   {"spill_fill", "Flush_spill_fill", REGNO_ANY, STXT ("Reg Window Spill/Fill Est Stalls"), PRELOAD (100, 5), 80, ABST_NONE, STXT ("Estimated time stalled on flushing pipeline due to register window spill/fill")},
1015
1016   /* explicit definitions of (hidden) entries for proper counters */
1017   /*  Counters that can be time converted, support memspace, or have a short_desc need to be in this table */
1018   //0x01
1019   {"Fetch_stall_IFU_reset_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1020   {"Fetch_stall_IC_miss_MB_full_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1021   {"Fetch_stall_IC_miss_MB_avail_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1022   {"Fetch_stall_IC_miss_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1023   {"Fetch_stall_ITLB_miss_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1024   {"Fetch_stall_SEL_buf_full_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1025   {"Fetch_ready_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1026   {"Fetch_0_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1027   {"Fetch_0_all_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1028   //0x02
1029   {"Fetch_1_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1030   {"Fetch_2_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1031   {"Fetch_3_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1032   {"Fetch_4_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1033   {"Fetch_5_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1034   {"Fetch_6_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1035   {"Fetch_7_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1036   {"Fetch_8_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1037   {"Fetch_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1038   //0x07
1039   {"ITLB_HWTW_hit_8K", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 8K page")},
1040   {"ITLB_HWTW_hit_64K", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 64K page")},
1041   {"ITLB_HWTW_hit_4M", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 4M page")},
1042   {"ITLB_HWTW_hit_256M", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 256M page")},
1043   {"ITLB_HWTW_hit_16G", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 16G page")},
1044   {"ITLB_HWTW_hit_1T", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 1T page")},
1045   //  { "ITLB_HWTW_miss_RA2PAC",                0x0740, 0xf07ff },
1046   //  { "ITLB_HWTW_miss_not_RA2PAC",            0x0780, 0xf07ff },
1047   {"ITLB_HWTW_miss_trap", NULL, REGNO_ANY, NULL, PRELOAD (1000, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk unsuccessful")},
1048   {"ITLB_HWTW", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk search done")},
1049   //0x08
1050   {"Br_BTC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branches delayed a few extra cycles because branch target not found in Branch Target Cache")},
1051   //0x09
1052   {"Sel_0_no_instr_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select because no instructions are available")},
1053   {"Sel_0_pipe_drain_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting with correct instructions when pipeline has to drain after branch misprediction")},
1054   {"Sel_0_postsync_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting for prior instructions to commit")},
1055   {"Sel_0_presync_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select with instruction that cannot decode until prior instructions have committed")},
1056   {"Sel_0_thread_hog_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select to prevent strand monopolizing resources")},
1057   {"Sel_0_tag_stall_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select because no required tags are available")},
1058   {"Sel_0_ready_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread was ready to have its instructions selected but another hardware thread was selected instead")},
1059   {"Sel_0_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread is not selected")},
1060   // No direct equivalent Sel_1/2_cyc. Nearest is Decode_uop, which increments by 0-4 each cycle according to how many uops were decoded.
1061   //0x13
1062   {"ITLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L2D")},
1063   {"ITLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L3 or neighbor L2D")},
1064   {"ITLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk missed all local caches")},
1065   {"DTLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L2D")},
1066   {"DTLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L3 or neighbor L2D")},
1067   {"DTLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk missed all local caches")},
1068   {"DTLB_HWTW_ref", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss requiring HW tablewalk")},
1069   //0x0E
1070   {"Instr_FGU_crypto", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("FP and VIS instructions completed by the Floating Point and Graphics Unit")},
1071   {"Instr_ld", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Load instructions completed")},
1072   {"Instr_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Store instructions completed")},
1073   {"Instr_block_ld_st", NULL, REGNO_ANY, NULL, PRELOAD (20, 5), 0, ABST_EXACT, STXT ("Block load/store instructions completed")},
1074   {"Instr_SPR_ring_ops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Specialized instructions that require internal use of SPR ring completed")},
1075   {"Instr_atomic", NULL, REGNO_ANY, NULL, PRELOAD (20, 5), 0, ABST_EXACT, STXT ("Atomic instructions, including CASA/XA, completed")},
1076   {"Instr_SW_prefetch", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("PREFETCH and PREFETCHA instructions completed")},
1077   {"Instr_other", NULL, REGNO_ANY, NULL, PRELOAD (2, 5), 0, ABST_NONE, STXT ("Basic arithmetic and logical instructions completed")},
1078   {"Instr_all", NULL, REGNO_ANY, NULL, PRELOAD (1, 5), 0, ABST_NONE, STXT ("Total instructions completed")},
1079   //0x0F
1080   {"Branches", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Control transfer instructions completed, excluding trap-related transfers")},
1081   //0x10
1082   {"Br_taken", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branch instructions taken and completed")},
1083   //0x11
1084   {"Rename_tag_wait_PQ_1_EXU_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1085   {"Rename_tag_wait_PQ_0_LSU_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1086   {"Rename_wait_crypto_diag_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1087   {"Sel_0_wait_ROB_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1088   {"Sel_0_wait_WRF_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1089   {"Sel_0_wait_LB_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1090   {"Sel_0_wait_SB_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1091   //0x12
1092   {"Fetch_stall_BDA_tag_unavail_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1093   {"Fetch_stall_BTA_tag_unavail_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1094   {"Fetch_stall_misc_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1095   {"Fetch_stall_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1096   {"MMU_TTE_buffer_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1097   {"MMU_PRQ_pool_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1098   //0x15
1099   {"L2I_request_block_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1100   {"L2I_thread_hog_stall_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1101   {"L2I_MB_full_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1102   {"L2I_snoop_eviction", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1103   {"L2I_stall_no_request_credit_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1104   {"L2I_stall_no_response_credit_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1105   //0x16
1106   {"Flush_thread_hog", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes to prevent thread from monopolizing resources")},
1107   {"Flush_br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to a branch misprediction")},
1108   {"Flush_arch_exception", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to SPARC architecture exceptions and trap entry/return")},
1109   {"Flush_evil_twin", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to detecting floating point evil twin condition")},
1110   {"Flush_LSU_trap", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes to refetch Next-PC")},
1111   {"Flush_mode_change", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to strand mode change")},
1112   {"Flush_misalign", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to detecting misaligned load/store requiring transition to misaligned mitigation mode")},
1113   {"Flush_other", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to hardware thread state change to/from halted/paused state")},
1114   {"Flush_all", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to any reason")},
1115   //0x17
1116   {"Flush_spill_n_normal", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to spill_n_normal exception")},
1117   {"Flush_spill_n_other", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to spill_n_other exception")},
1118   {"Flush_fill_n_normal", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to fill_n_normal exception")},
1119   {"Flush_fill_n_other", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to fill_n_other exception")},
1120   {"Flush_spill_fill", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to spill/fill exceptions")},
1121   {"Flush_lost_load", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to speculatively executed load violating memory order")},
1122   //0x21
1123   {"Br_dir_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Branch instructions completed whose direction was mispredicted")},
1124   {"Br_tgt_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Branch instructions completed whose target was mispredicted")},
1125   {"Br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Branch instructions completed whose direction or target was mispredicted")},
1126   //0x23
1127   {"LSU_st_q_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1128   {"LSU_st_q_tag_wait_all_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1129   {"L2D_stall_no_request_credit_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1130   {"L2D_stall_no_response_credit_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1131   //0x27
1132   {"DC_miss_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (20, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit local L2D")},
1133   {"DC_miss_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit local L3")},
1134   {"DC_miss_L3_dirty_copyback", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit local L3 but require copyback from L2D within same CPC")},
1135   {"DC_miss_nbr_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (100, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit neighbor L3 on same socket")},
1136   {"DC_miss_remote_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (400, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit remote cache on different socket")},
1137   {"DC_miss_local_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (500, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit local memory")},
1138   {"DC_miss_remote_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (1000, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit remote memory")},
1139   {"DC_miss", NULL, REGNO_ANY, NULL, PRELOAD (10, 5), 0, ABST_NONE, STXT ("Loads that speculatively missed local L1D")},
1140   //0x28
1141   {"DC_sec_miss_L2_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1142   {"DC_miss_L2_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1143   {"DC_miss_L3_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1144   {"DC_miss_L3_dirty_copyback_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1145   {"DC_miss_nbr_L3_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1146   {"DC_miss_remote_L3_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1147   {"DC_miss_local_mem_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1148   {"DC_miss_remote_mem_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1149   {"DC_miss_commit", NULL, REGNO_ANY, NULL, PRELOAD (25, 5), 0, ABST_EXACT, STXT ("Loads that missed local L1D")},
1150   //0x29
1151   //  {"Store_DC_sec_miss_L2_hit",       NULL, REGNO_ANY, NULL, PRELOAD_DEF,     0, ABST_NONE,  STXT("")},
1152   {"Store_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (20, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L2D")},
1153   {"Store_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L3")},
1154   {"Store_nbr_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (100, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in neighbor L2 on same socket")},
1155   {"Store_nbr_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (100, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in neighbor L3 on same socket")},
1156   {"Store_remote_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (400, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in remote cache on different socket")},
1157   {"Store_local_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (500, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local memory")},
1158   {"Store_remote_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (1000, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in remote memory")},
1159   {"Store_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was observed to be somewhere in the memory hierarchy")},
1160   //0x2d
1161   {"RAW_hit_st_buf", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) still in store buffer not yet committed")},
1162   {"RAW_hit_st_q", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) committed but in store queue not yet written to L2D")},
1163   {"RAW_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write hazards)")},
1164   //0x2f
1165   {"Cycles_user_non_MLA", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1166   {"Cycles_user_MLA", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1167   {"Cycles_user", NULL, REGNO_ANY, NULL, PRELOAD (1, 5), 1, ABST_NONE, STXT ("Cycles hardware thread is active in specified mode(s)")},
1168   //0x37
1169   {"DTLB_HWTW_hit_8K", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 8K page")},
1170   {"DTLB_HWTW_hit_64K", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 64K page")},
1171   {"DTLB_HWTW_hit_4M", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 4M page")},
1172   {"DTLB_HWTW_hit_256M", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 256M page")},
1173   {"DTLB_HWTW_hit_16G", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 16G page")},
1174   {"DTLB_HWTW_hit_1T", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 1T page")},
1175   {"DTLB_HWTW_miss_trap", NULL, REGNO_ANY, NULL, PRELOAD (800, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk unsuccessful")},
1176   {"DTLB_HWTW", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk search done")},
1177   //0x3f
1178   {"Commit_0_cyc", /*22825776*/ NULL, 3, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from this hardware thread")},
1179   {"Commit_0_all_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from any hardware thread on this core")},
1180   // Similar situation to Sel_1_cyc etc. No direct equivalent, nearest is Commit_uop, which increments by 0-4 each cycle according to how many uops were committed.
1181
1182   /* additional (hidden) aliases, for convenience */
1183   {"cycles0", "Cycles_user", 0, NULL, PRELOADS_8, 1, ABST_NONE},
1184   {"cycles1", "Cycles_user", 1, NULL, PRELOADS_8, 1, ABST_NONE},
1185   {"insts0", "Instr_all", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1186   {"insts1", "Instr_all", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1187   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1188 };
1189
1190 static Hwcentry usfuji_V_list[] = {
1191   {"cycles", "cycle_counts", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
1192   {"insts", "instruction_counts", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
1193   {"flops", "floating_instructions", REGNO_ANY, STXT ("Floating-point Ops"), PRELOADS_6, 0, ABST_NONE},
1194
1195   /* explicit definitions of (hidden) entries for proper counters */
1196   /*  Only counters that can be time converted, or are load-store need to be in this table */
1197   {"cycle_counts", NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
1198   {"load_store_instructions", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1199
1200   /* additional (hidden) aliases for convenience */
1201   {"cycles0", "cycle_counts", 0, NULL, PRELOADS_75, 1, ABST_NONE},
1202   {"cycles1", "cycle_counts", 1, NULL, PRELOADS_75, 1, ABST_NONE},
1203   {"insts0", "instruction_counts", 0, NULL, PRELOADS_75, 0, ABST_NONE},
1204   {"insts1", "instruction_counts", 1, NULL, PRELOADS_75, 0, ABST_NONE},
1205   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1206 };
1207
1208 static Hwcentry usfuji_VI_VII_list[] = {
1209   {"cycles", "cycle_counts", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1210   {"insts", "instruction_counts", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1211   {"dcm", "op_r_iu_req_mi_go", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_6, 0, ABST_NONE},
1212   {"dcstall", "op_wait_all", REGNO_ANY, STXT ("L1 D-cache Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
1213   {"dtlbm", "write_op_uTLB", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_5, 0, ABST_NONE},
1214   // l2m: mem_cache_load test shows undercount of 3x, however, we don't care too much about this chip, keeping the alias for now
1215   {"l2m", "sx_miss_count_dm", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_5, 0, ABST_NONE}, /*YXXX undercounts?*/
1216   {"l2wm", "dvp_count_dm", REGNO_ANY, STXT ("L2 Cache Writeback Misses"), PRELOADS_5, 0, ABST_NONE},
1217   {"l2ref", "sx_read_count_dm", REGNO_ANY, STXT ("L2 Cache Refs"), PRELOADS_6, 0, ABST_NONE},
1218   {"l2stall", "sx_miss_wait_dm", REGNO_ANY, STXT ("L2 Cache Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
1219   {"icm", "if_r_iu_req_mi_go", REGNO_ANY, STXT ("L1 I-cache Misses"), PRELOADS_6, 0, ABST_NONE},
1220   {"icstall", "if_wait_all", REGNO_ANY, STXT ("L1 I-cache Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
1221   {"itlbm", "write_if_uTLB", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE},
1222   {"flops", "floating_instructions", REGNO_ANY, STXT ("Floating-point Ops"), PRELOADS_7, 0, ABST_NONE},
1223
1224   /* explicit definitions of (hidden) entries for proper counters */
1225   /*  Only counters that can be time converted, or are load-store need to be in this table */
1226   {"cycle_counts", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1227   {"op_stv_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1228   {"load_store_instructions", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1229   {"active_cycle_count", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1230   {"op_stv_wait_sxmiss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1231   {"branch_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1232   {"write_op_uTLB", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1233   {"sx_miss_wait_pf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1234   {"sx_miss_wait_dm", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1235   {"op_stv_wait_nc_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1236   {"op_stv_wait_sxmiss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1237   {"eu_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1238   {"sx_miss_count_dm", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1239   {"fl_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1240   {"op_r_iu_req_mi_go", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1241   {"sx_miss_count_dm_if", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1242   {"op_stv_wait_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1243   {"swpf_lbs_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1244   {"sx_read_count_dm", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1245   {"trap_DMMU_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1246   {"op_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1247   {"sx_miss_count_dm_opex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1248   {"if_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1249   {"dvp_count_dm", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1250   {"sx_miss_count_dm_opsh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1251
1252   /* additional (hidden) aliases for convenience */
1253   {"cycles0", "cycle_counts", 0, NULL, PRELOADS_8, 1, ABST_NONE},
1254   {"cycles1", "cycle_counts", 1, NULL, PRELOADS_8, 1, ABST_NONE},
1255   {"insts0", "instruction_counts", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1256   {"insts1", "instruction_counts", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1257   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1258 };
1259
1260
1261 static Hwcentry usfuji_X_list[] = {
1262   {"cycles", "cycle_counts", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1263   {"insts", "instruction_counts", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1264   {"dcm", "L1D_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE},
1265   {"dcstall", "L1D_wait_all", REGNO_ANY, STXT ("L1 D-cache Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
1266
1267   /* explicit definitions of (hidden) entries for proper counters */
1268   /*  Only counters that can be time converted, or are load-store need to be in this table */
1269   {"cycle_counts", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1270   {"w_op_stv_wait_nc_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1271   {"op_stv_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1272   {"eu_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1273   {"L2_miss_wait_pf_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1274   {"op_stv_wait_pfp_busy_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1275   {"L2_miss_wait_dm_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1276   {"w_branch_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1277   {"w_op_stv_wait_sxmiss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1278   {"op_stv_wait_nc_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1279   {"L2_miss_wait_pf_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1280   {"w_eu_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1281   {"w_op_stv_wait_sxmiss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1282   {"op_stv_wait_sxmiss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1283   {"branch_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1284   {"L2_miss_wait_dm_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1285   {"d_move_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1286   {"w_op_stv_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1287   {"w_fl_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1288   {"op_stv_wait_pfp_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1289   {"fl_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1290   {"L2_miss_wait_pf_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1291   {"op_stv_wait_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1292   {"L2_miss_wait_dm_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1293   {"w_op_stv_wait_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1294   {"op_stv_wait_sxmiss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1295   {"op_stv_wait_swpf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1296   {"L1D_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1297   {"L2_miss_wait_pf_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1298   {"cse_priority_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1299   {"op_stv_wait_pfp_busy_swpf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1300   {"L1I_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1301   {"L2_miss_wait_dm_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1302
1303   {"single_mode_cycle_counts", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1304   {"suspend_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1305   {"sleep_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1306
1307   /* additional (hidden) aliases for convenience */
1308   {"cycles0", "cycle_counts", 0, NULL, PRELOADS_8, 1, ABST_NONE},
1309   {"cycles1", "cycle_counts", 1, NULL, PRELOADS_8, 1, ABST_NONE},
1310   {"insts0", "instruction_counts", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1311   {"insts1", "instruction_counts", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1312   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1313 };
1314
1315 static Hwcentry usfuji_XII_list[] = {
1316   {"cycles", "cycle_counts", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1317   {"insts", "instruction_counts", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1318   {"dcm", "L1D_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE},
1319   {"dcstall", "L1D_wait_all", REGNO_ANY, STXT ("L1 D-cache Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
1320
1321   /* explicit definitions of (hidden) entries for proper counters */
1322   /*  Only counters that can be time converted, or are load-store need to be in this table */
1323   {"cycle_counts", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1324   {"L1D_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1325   {"L1I_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1326   {"L2_miss_wait_dm_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1327   {"L2_miss_wait_dm_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1328   {"L2_miss_wait_dm_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1329   {"L2_miss_wait_dm_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1330   {"L2_miss_wait_pf_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1331   {"L2_miss_wait_pf_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1332   {"L2_miss_wait_pf_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1333   {"L2_miss_wait_pf_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1334   {"LL_miss_wait_dm_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1335   {"LL_miss_wait_dm_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1336   {"LL_miss_wait_dm_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1337   {"LL_miss_wait_dm_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1338   {"LL_miss_wait_pf_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1339   {"LL_miss_wait_pf_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1340   {"LL_miss_wait_pf_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1341   {"LL_miss_wait_pf_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1342   {"branch_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1343   {"cse_priority_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1344   {"d_move_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1345   {"eu_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1346   {"fl_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1347   {"l2_sy_miss_wait_dm_part1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1348   {"l2_sy_miss_wait_dm_part2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1349   {"msgr_reqp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1350   {"msgr_rtnp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1351   {"msgs_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1352   {"op_stv_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1353   {"op_stv_wait_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1354   {"op_stv_wait_l1d_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1355   {"op_stv_wait_l1d_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1356   {"op_stv_wait_l2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1357   {"op_stv_wait_l2_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1358   {"op_stv_wait_ll_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1359   {"op_stv_wait_ll_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1360   {"op_stv_wait_nc_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1361   {"op_stv_wait_pfp_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1362   {"op_stv_wait_pfp_busy_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1363   {"op_stv_wait_pfp_busy_swpf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1364   {"op_stv_wait_swpf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1365   {"op_stv_wait_sxmiss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1366   {"op_stv_wait_sxmiss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1367   {"w_branch_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1368   {"w_eu_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1369   {"w_fl_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1370   {"w_op_stv_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1371   {"w_op_stv_wait_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1372   {"w_op_stv_wait_l1d_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1373   {"w_op_stv_wait_l1d_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1374   {"w_op_stv_wait_l2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1375   {"w_op_stv_wait_l2_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1376   {"w_op_stv_wait_ll_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1377   {"w_op_stv_wait_ll_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1378   {"w_op_stv_wait_nc_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1379   {"w_op_stv_wait_pfp_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1380   {"w_op_stv_wait_pfp_busy_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1381   {"w_op_stv_wait_pfp_busy_swpf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1382   {"w_op_stv_wait_sxmiss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1383   {"w_op_stv_wait_sxmiss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1384
1385   {"single_mode_cycle_counts", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1386   {"suspend_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1387   {"sleep_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1388
1389   /* additional (hidden) aliases for convenience */
1390   {"cycles0", "cycle_counts", 0, NULL, PRELOADS_8, 1, ABST_NONE},
1391   {"cycles1", "cycle_counts", 1, NULL, PRELOADS_8, 1, ABST_NONE},
1392   {"insts0", "instruction_counts", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1393   {"insts1", "instruction_counts", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1394   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1395 };
1396
1397 /* Kernel profiling pseudo-chip, OBSOLETE (To support 12.3 and earlier, TBR) */
1398 static Hwcentry kproflist[] = {
1399   {"kcycles", "kcycles", 0, STXT ("KCPU Cycles"), PRELOADS_5, 1, ABST_NONE},
1400   {"kucycles", "kucycles", 0, STXT ("KUCPU Cycles"), PRELOADS_5, 1, ABST_NONE},
1401   {"kthr", "kthr", 0, STXT ("KTHR Cycles"), PRELOADS_5, 1, ABST_NONE},
1402   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1403 };
1404
1405 static Hwcentry pentiumIIlist[] = {
1406   /*  note -- missing entries for dtlbm, ecm */
1407   {"cycles", "cpu_clk_unhalted", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
1408   {"insts", "inst_retired", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
1409   {"icm", "ifu_ifetch_miss", REGNO_ANY, STXT ("I$ Misses"), PRELOADS_5, 0, ABST_NONE},
1410   {"dcrm", "dcu_m_lines_in", REGNO_ANY, STXT ("D$ Read Misses"), PRELOADS_5, 0, ABST_NONE},
1411   {"dcwm", "dcu_m_lines_out", REGNO_ANY, STXT ("D$ Write Misses"), PRELOADS_5, 0, ABST_NONE},
1412   {"flops", "flops", REGNO_ANY, STXT ("Floating-point Ops"), PRELOADS_7, 0, ABST_NONE},
1413   {"itlbm", "itlb_miss", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE},
1414   {"ecim", "l2_ifetch", REGNO_ANY, STXT ("E$ Instr. Misses"), PRELOADS_5, 0, ABST_NONE},
1415
1416   /* explicit definitions of (hidden) entries for proper counters */
1417   /*  Only counters that can be time converted, or are load-store need to be in this table */
1418   {"cpu_clk_unhalted", NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
1419
1420   /* additional (hidden) aliases for convenience */
1421   {"cycles0", "cpu_clk_unhalted", 0, NULL, PRELOADS_75, 1, ABST_NONE},
1422   {"cycles1", "cpu_clk_unhalted", 1, NULL, PRELOADS_75, 1, ABST_NONE},
1423   {"insts0", "inst_retired", 0, NULL, PRELOADS_75, 0, ABST_NONE},
1424   {"insts1", "inst_retired", 1, NULL, PRELOADS_75, 0, ABST_NONE},
1425   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1426 };
1427
1428 static Hwcentry pentiumIIIlist[] = {
1429   /*  note -- many missing entries; no reference machine to try */
1430   {"cycles", "cpu_clk_unhalted", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
1431   {"insts", "inst_retired", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
1432
1433   /* explicit definitions of (hidden) entries for proper counters */
1434   /*  Only counters that can be time converted, or are load-store need to be in this table */
1435   {"cpu_clk_unhalted", NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
1436
1437   /* additional (hidden) aliases for convenience */
1438   {"cycles0", "cpu_clk_unhalted", 0, NULL, PRELOADS_75, 1, ABST_NONE},
1439   {"cycles1", "cpu_clk_unhalted", 1, NULL, PRELOADS_75, 1, ABST_NONE},
1440   {"insts0", "inst_retired", 0, NULL, PRELOADS_75, 0, ABST_NONE},
1441   {"insts1", "inst_retired", 1, NULL, PRELOADS_75, 0, ABST_NONE},
1442   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1443 };
1444
1445 static Hwcentry pentium4[] = {
1446   {"cycles", "TC_deliver_mode~threshold=0xf~complement=1~compare=1", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
1447   {"insts", "instr_retired~emask=0x3", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
1448   {"l1m", "BSQ_cache_reference~emask=0x0507", REGNO_ANY, STXT ("L1 Cache Misses"), PRELOADS_7, 0, ABST_NONE},
1449   {"l2h", "BSQ_cache_reference~emask=0x0007", REGNO_ANY, STXT ("L2 Cache Hits"), PRELOADS_7, 0, ABST_NONE},
1450   {"l2m", "BSQ_cache_reference~emask=0x0500", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_6, 0, ABST_NONE},
1451
1452   /* explicit definitions of (hidden) entries for proper counters */
1453   /*  Only counters that can be time converted, or are load-store need to be in this table */
1454   {"TC_deliver_mode", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1455   {"machine_clear", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1456
1457   /* additional (hidden) aliases, for convenience */
1458   {"cycles0", "TC_deliver_mode~threshold=0xf~complement=1~compare=1", 5, NULL, PRELOADS_75, 1, ABST_NONE},
1459   {"cycles1", "TC_deliver_mode~threshold=0xf~complement=1~compare=1", 6, NULL, PRELOADS_75, 1, ABST_NONE},
1460   {"insts0", "instr_retired~emask=0x3", 15, NULL, PRELOADS_75, 0, ABST_NONE},
1461   {"insts1", "instr_retired~emask=0x3", 16, NULL, PRELOADS_75, 0, ABST_NONE},
1462   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1463 };
1464
1465 static Hwcentry intelCore2list[] = {
1466   // For post-processing, both Linux and Solaris definitions need to be "live".
1467   // However, for data collection, OS-specific definitions may need to be hidden.
1468   // Use REGNO_INVALID for definitions that should be hidden for data collection.
1469 #define LINUX_ONLY   REGNO_ANY
1470 #define SOLARIS_ONLY REGNO_INVALID /* hidden for Linux data collection */
1471
1472   {"cycles", "cpu_clk_unhalted.core", /*6759307*/ SOLARIS_ONLY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1473   {"cycles", "cpu_clk_unhalted.thread", /*6759307*/ SOLARIS_ONLY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1474   /* Linux Note: 7046312 Many HWC tests fail on system Core2 system with perf_events if above alias used */
1475   {"cycles", "cpu_clk_unhalted", LINUX_ONLY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1476
1477   {"insts", "instr_retired.any", SOLARIS_ONLY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1478   /* Linux Note: 7046312 Many HWC tests fail on system Core2 system with perf_events if above alias used */
1479   {"insts", "inst_retired", LINUX_ONLY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1480
1481   // The following counters were identified in "Cycle Accounting Analysis on Intel Core2 Processors" by David Levinthal
1482   {"uops_stalled", "rs_uops_dispatched~cmask=1~inv=1", REGNO_ANY, STXT ("uOps Stalled"), PRELOADS_7, 1, ABST_NONE},
1483   {"l2m", "mem_load_retired~umask=0x08", REGNO_ANY, STXT ("L2 Line Misses"), PRELOADS_5, 0, ABST_NONE},
1484   {"dtlbm", "mem_load_retired~umask=0x10", REGNO_ANY, STXT ("L1 DTLB Misses"), PRELOADS_5, 0, ABST_NONE},
1485   {"l1m", "mem_load_retired~umask=0x02", REGNO_ANY, STXT ("L1 Line Misses"), PRELOADS_6, 0, ABST_NONE},
1486   // {"stalls_resources","resource_stalls~umask=0x1f",          REGNO_ANY, STXT("Resource Stalls"),             PRELOADS_6, 1, ABST_NONE},
1487   {"rs_full", "resource_stalls~umask=0x02", REGNO_ANY, STXT ("Reservation Station Full"), PRELOADS_6, 1, ABST_NONE},
1488   {"br_miss_flush", "resource_stalls~umask=0x10", REGNO_ANY, STXT ("Mispredicted Branch Flushes"), PRELOADS_6, 1, ABST_NONE},
1489   {"ld_st_full", "resource_stalls~umask=0x04", REGNO_ANY, STXT ("Load/Store Buffers Full"), PRELOADS_6, 1, ABST_NONE},
1490   {"rob_full", "resource_stalls~umask=0x01", REGNO_ANY, STXT ("Reorder Buffer Full"), PRELOADS_6, 1, ABST_NONE},
1491   {"slow_decode", "ild_stall", REGNO_ANY, STXT ("Slow Instruction Decode"), PRELOADS_6, 1, ABST_NONE},
1492   {"br_miss", "br_cnd_missp_exec", REGNO_ANY, STXT ("Mispredicted Branches"), PRELOADS_5, 0, ABST_NONE},
1493   {"ret_miss", "br_call_missp_exec", REGNO_ANY, STXT ("Mispredicted Return Calls"), PRELOADS_5, 0, ABST_NONE},
1494   {"div_busy", "idle_during_div", REGNO_ANY, STXT ("Divider Unit Busy"), PRELOADS_5, 1, ABST_NONE},
1495   {"fp_assists", "fp_assist", REGNO_ANY, STXT ("FP Microcode Assists"), PRELOADS_5, 0, ABST_NONE},
1496   {"bus_busy", "bus_drdy_clocks~umask=0x60", REGNO_ANY, STXT ("Busy Data Bus"), PRELOADS_5, 1, ABST_NONE},
1497
1498   /* explicit definitions of (hidden) entries for proper counters */
1499   /*  Only counters that can be time converted, or are load-store need to be in this table */
1500   {/*30a*/"cpu_clk_unhalted.core", /*6759307*/ NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1501   {/*30a*/"cpu_clk_unhalted.thread", /*6759307*/ NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1502   {/*03*/"store_block", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1503   {/*03*/"store_block.drain_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1504   {/*03*/"store_block.order", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1505   {/*03*/"store_block.snoop", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1506   {/*09*/"memory_disambiguation.reset", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1507   {/*0c*/"page_walks.cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1508   {/*14*/"cycles_div_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1509   {/*18*/"idle_during_div", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1510   {/*19*/"delayed_bypass.load", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1511   {/*21*/"l2_ads", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1512   {/*23*/"l2_dbus_busy_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1513   {/*32*/"l2_no_req", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1514   {/*3c*/"cpu_clk_unhalted", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1515   {/*3c*/"cpu_clk_unhalted.core_p", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1516   {/*3c*/"cpu_clk_unhalted.bus", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1517   {/*3c*/"cpu_clk_unhalted.no_other", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1518   {/*42*/"l1d_cache_lock.duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1519   {/*62*/"bus_drdy_clocks", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1520   {/*63*/"bus_lock_clocks", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1521   {/*64*/"bus_data_rcv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1522   {/*7a*/"bus_hit_drv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1523   {/*7b*/"bus_hitm_drv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1524   {/*7d*/"busq_empty", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1525   {/*7e*/"snoop_stall_drv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1526   {/*7f*/"bus_io_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1527   {/*83*/"inst_queue", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1528   {/*83*/"inst_queue.full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1529   {/*86*/"cycles_l1i_mem_stalled", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1530   {/*87*/"ild_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1531   {/*a1*/"rs_uops_dispatched", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1532   {/*a1*/"rs_uops_dispatched_port", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1533   {/*a1*/"rs_uops_dispatched_port.0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1534   {/*a1*/"rs_uops_dispatched_port.1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1535   {/*a1*/"rs_uops_dispatched_port.2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1536   {/*a1*/"rs_uops_dispatched_port.3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1537   {/*a1*/"rs_uops_dispatched_port.4", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1538   {/*a1*/"rs_uops_dispatched_port.5", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1539   {/*6c*/"cycles_int", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1540   {/*6c*/"cycles_int.masked", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1541   {/*6c*/"cycles_int.pending_and_masked", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1542   {/*d2*/"rat_stalls", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1543   {/*d2*/"rat_stalls.rob_read_port", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1544   {/*d2*/"rat_stalls.partial_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1545   {/*d2*/"rat_stalls.flags", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1546   {/*d2*/"rat_stalls.fpsw", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1547   {/*d2*/"rat_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1548   {/*d2*/"rat_stalls.other_serialization_stalls", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1549   {/*d4*/"seg_rename_stalls", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1550   {/*d4*/"seg_rename_stalls.es", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1551   {/*d4*/"seg_rename_stalls.ds", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1552   {/*d4*/"seg_rename_stalls.fs", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1553   {/*d4*/"seg_rename_stalls.gs", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1554   {/*d4*/"seg_rename_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1555   {/*dc*/"resource_stalls", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1556   {/*dc*/"resource_stalls.rob_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1557   {/*dc*/"resource_stalls.rs_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1558   {/*dc*/"resource_stalls.ld_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1559   {/*dc*/"resource_stalls.fpcw", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1560   {/*dc*/"resource_stalls.br_miss_clear", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1561   {/*dc*/"resource_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1562   /* "Architectural" events: */
1563   {/*3c*/"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1564
1565   /* additional (hidden) aliases for convenience */
1566   {"cycles0", "cpu_clk_unhalted", 0, NULL, PRELOADS_8, 1, ABST_NONE},
1567   {"cycles1", "cpu_clk_unhalted", 1, NULL, PRELOADS_8, 1, ABST_NONE},
1568   {"insts0", "inst_retired", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1569   {"insts1", "inst_retired", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1570   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1571 };
1572
1573
1574 static Hwcentry intelNehalemList[] = {
1575   /* 6832635: on Linux, we're not seeing consistent overflows on FFCs */
1576   /* 15634344==6940930: HWC overflow profiling can cause system hang on Solaris/core-i7 systems */
1577   /* 17578620: counter overflow for fixed-function counters hangs systems */
1578   /* same issues for intelSandyBridgeList and intelHaswellList */
1579   PERF_EVENTS_SW_EVENT_ALIASES
1580   USE_INTEL_REF_CYCLES (133)
1581   {"cycles", "cpu_clk_unhalted.thread_p", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1582   {"insts", "inst_retired.any_p", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1583   // cpu_clk_unhalted.ref: at the ref requency of the cpu. Should not be affected by Speedstep or Turbo.
1584   // cpu_clk_unhalted.thread_p: with HT & 2 threads, 2x cycles.  Affected by Speedstep and Turbo.
1585
1586   // PEBs (Sampling)
1587   {"l2m_latency", "mem_inst_retired.latency_above_threshold", REGNO_ANY, STXT ("L2 Cache Miss Est. Latency"), PRELOADS_4, 33, ABST_EXACT_PEBS_PLUS1},
1588
1589   // See file hwctable.README.corei7
1590   {"dch", "mem_load_retired.l1d_hit", REGNO_ANY, STXT ("L1 D-cache Hits"), PRELOADS_7, 0, ABST_NONE},
1591   {"dcm", "0xCB~umask=0x1e", REGNO_ANY, STXT ("L1 D-Cache Misses"), PRELOADS_65, 0, ABST_NONE}, /*mem_load_retired*/
1592   {"lfbdh", "mem_load_retired.hit_lfb", REGNO_ANY, STXT ("LFB D-cache Hits"), PRELOADS_65, 0, ABST_NONE},
1593   {"l2h", "mem_load_retired.l2_hit", REGNO_ANY, STXT ("L2 Cache Hits"), PRELOADS_65, 0, ABST_NONE},
1594   {"l2m", "0xCB~umask=0x1c", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_6, 0, ABST_NONE}, /*mem_load_retired*/
1595   {"l3h", "mem_load_retired.llc_unshared_hit", REGNO_ANY, STXT ("L3 Cache Hit w/o Snoop"), PRELOADS_6, 0, ABST_NONE},
1596   {"l3h_stall", "mem_load_retired.llc_unshared_hit", REGNO_ANY, STXT ("L3 Cache Hit w/o Snoop x 35: Est. Stalls"), PRELOADS_6, 35, ABST_NONE},
1597   {"l3hsnoop", "mem_load_retired.other_core_l2_hit_hitm", REGNO_ANY, STXT ("L3 Cache Hit w/Snoop"), PRELOADS_6, 0, ABST_NONE},
1598   {"l3hsnoop_stall", "mem_load_retired.other_core_l2_hit_hitm", REGNO_ANY, STXT ("L3 Cache Hit w/Snoop x 74: Est. Stalls"), PRELOADS_6, 74, ABST_NONE},
1599   {"l3m", "mem_load_retired.llc_miss", REGNO_ANY, STXT ("L3 Cache Misses"), PRELOADS_5, 0, ABST_NONE},
1600   {"l3m_stall", "mem_load_retired.llc_miss", REGNO_ANY, STXT ("L3 Cache Misses x 180: Estimated Stalls"), PRELOADS_5, 180, ABST_NONE},
1601   {"dtlbm", "dtlb_load_misses.walk_completed", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_6, 0, ABST_NONE},
1602   {"dtlbm_stall", "dtlb_load_misses.walk_completed", REGNO_ANY, STXT ("DTLB Misses x 30: Estimated Stalls"), PRELOADS_6, 30, ABST_NONE},
1603   {"addr_alias_stall", "partial_address_alias", REGNO_ANY, STXT ("Partial Address Aliases x 3: Est. Stalls"), PRELOADS_6, 3, ABST_NONE},
1604   {"uope_stall", "uops_executed.port234~cmask=1~inv=1", REGNO_ANY, STXT ("UOP Execute Stalls per Core"), PRELOADS_7, 1, ABST_NONE},
1605   {"uopr_stall", "uops_retired.any~cmask=1~inv=1", REGNO_ANY, STXT ("UOP Retired Stalls"), PRELOADS_7, 1, ABST_NONE},
1606   {"itlbm", "itlb_miss_retired", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_6, 0, ABST_NONE},
1607   {"l1i_stall", "l1i.cycles_stalled", REGNO_ANY, STXT ("L1 I-cache Stalls"), PRELOADS_6, 1, ABST_NONE},
1608   {"br_rets", "br_inst_retired.all_branches", REGNO_ANY, STXT ("Branch Instruction Retires"), PRELOADS_7, 0, ABST_NONE},
1609   {"br_misp", "br_misp_exec.any", REGNO_ANY, STXT ("Branch Mispredicts"), PRELOADS_6, 0, ABST_NONE},
1610   {"mach_clear", "machine_clears.cycles", REGNO_ANY, STXT ("Machine Clear Asserted"), PRELOADS_6, 1, ABST_NONE},
1611   {"fp_mmx", "fp_mmx_trans.any", REGNO_ANY, STXT ("FP-MMX Transistions"), PRELOADS_6, 0, ABST_NONE},
1612   {"div_busy", "arith.cycles_div_busy", REGNO_ANY, STXT ("Divider Busy Cycles"), PRELOADS_6, 1, ABST_NONE},
1613
1614   /* explicit definitions of (hidden) entries for proper counters */
1615   /*  Only counters that can be time converted, or are load-store need to be in this table */
1616   {/*30a*/"cpu_clk_unhalted.core", /*6759307*/ NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1617   {/*30a*/"cpu_clk_unhalted.thread", /*6759307*/ NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1618   {/*04*/"sb_drain.cycles", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1619   {/*08.04*/"dtlb_load_misses.walk_cycles", /*westmere*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1620   //{/*0e*/"uops_issued.stalled_cycles",/*future, multibit*/            NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1621   {/*09*/"memory_disambiguation.reset", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1622   {/*09*/"memory_disambiguation.watch_cycles", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1623   {/*0b*/"mem_inst_retired.latency_above_threshold", /*PEBS*/ NULL, REGNO_ANY, NULL, PRELOADS_4, 33, ABST_EXACT_PEBS_PLUS1}, //non-standard overflow
1624   {/*14*/"arith.cycles_div_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1625   {/*17*/"inst_queue_write_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1626   {/*1d*/"hw_int.cycles_masked", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1627   {/*1d*/"hw_int.cycles_pending_and_masked", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1628   {/*3c*/"cpu_clk_unhalted.thread_p", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1629   {/*48*/"l1d_pend_miss.load_buffers_full", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1630   {/*49.04*/"dtlb_misses.walk_cycles", /*westmere*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1631   {/*4e*/"sfence_cycles", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1632   {/*4f.10*/"ept.walk_cycles", /*westmere*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1633   {/*60*/"offcore_requests_outstanding.demand.read_data", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1634   {/*60*/"offcore_requests_outstanding.demand.read_code", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1635   {/*60*/"offcore_requests_outstanding.demand.rfo", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1636   {/*60*/"offcore_requests_outstanding.any.read", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1637   {/*63*/"cache_lock_cycles.l1d", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1638   {/*63*/"cache_lock_cycles.l1d_l2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1639   {/*80*/"l1i.cycles_stalled", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1640   {/*85*/"itlb_misses.walk_cycles", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1641   {/*85*/"itlb_misses.pmh_busy_cycles", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1642   {/*87*/"ild_stall.lcp", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1643   {/*87*/"ild_stall.mru", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1644   {/*87*/"ild_stall.iq_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1645   {/*87*/"ild_stall.regen", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1646   {/*87*/"ild_stall.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1647   {/*a2*/"resource_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1648   {/*a2*/"resource_stalls.load", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1649   {/*a2*/"resource_stalls.rs_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1650   {/*a2*/"resource_stalls.store", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1651   {/*a2*/"resource_stalls.rob_full", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1652   {/*a2*/"resource_stalls.fpcw", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1653   {/*a2*/"resource_stalls.mxcsr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1654   {/*a2*/"resource_stalls.other", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1655   {/*b0*/"offcore_requests_sq_full", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1656   {/*b3*/"snoopq_requests_outstanding.data", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1657   {/*b3*/"snoopq_requests_outstanding.invalidate", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1658   {/*b3*/"snoopq_requests_outstanding.code", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1659   //{/*c2*/"uops_retired.stalled_cycles",/*future, multibit*/           NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1660   {/*c3*/"machine_clears.cycles", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1661   {/*d2*/"rat_stalls.flags", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1662   {/*d2*/"rat_stalls.registers", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1663   {/*d2*/"rat_stalls.rob_read_port", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1664   {/*d2*/"rat_stalls.scoreboard", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1665   {/*d2*/"rat_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1666   {/*d4*/"seg_rename_stalls", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1667   {/*f6*/"sq_full_stall_cycles", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1668   /* "Architectural" events: */
1669   {/*3c*/"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1670   PERF_EVENTS_SW_EVENT_DEFS
1671
1672   /* additional (hidden) aliases for convenience */
1673 #if 0
1674   USE_INTEL_REF_CYCLES (133),
1675 #endif
1676   {"insts0", "inst_retired.any_p", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1677   {"insts1", "inst_retired.any_p", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1678   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1679 };
1680
1681
1682 static Hwcentry intelSandyBridgeList[] = {
1683   /* see comments for "cycles" and "insts" for intelNehalemList */
1684   PERF_EVENTS_SW_EVENT_ALIASES
1685   USE_INTEL_REF_CYCLES (100)
1686   {"cycles", "cpu_clk_unhalted.thread_p", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1687   {"insts", "inst_retired.any_p", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1688
1689   // PEBS (sampling)
1690   {"l2m_latency", "mem_trans_retired.load_latency", REGNO_ANY, STXT ("L2 Cache Miss Est. Latency"), PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1},
1691
1692   // See file hwctable.README.sandybridge
1693   {"dch", "mem_load_uops_retired.l1_hit", REGNO_ANY, STXT ("L1 D-cache Hits"), PRELOADS_7, 0, ABST_NONE},
1694   {"dcm", "mem_load_uops_retired.l1_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE}, /*mem_load_uops_retired*/
1695   {"l2h", "mem_load_uops_retired.l2_hit", REGNO_ANY, STXT ("L2 Cache Hits"), PRELOADS_65, 0, ABST_NONE},
1696   {"l2m", "mem_load_uops_retired.l2_miss", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_6, 0, ABST_NONE}, /*mem_load_uops_retired*/
1697   // Intel errata:  BT241 and BT243 says the mem_load_uops_retired.llc* counters may not be reliable on some CPU variants
1698   {"l3h", "mem_load_uops_retired.llc_hit", REGNO_ANY, STXT ("L3 Cache Hit w/o Snoop"), PRELOADS_6, 0, ABST_NONE}, // may undercount
1699   {"l3m", "longest_lat_cache.miss", REGNO_ANY, STXT ("L3 Cache Misses"), PRELOADS_5, 0, ABST_NONE},
1700
1701   /* dtlbm has not been confirmed via Intel white paper */
1702   {"dtlbm", "dtlb_load_misses.walk_completed", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_6, 0, ABST_NONE},
1703   {"dtlbm_stall", "dtlb_load_misses.walk_completed", REGNO_ANY, STXT ("DTLB Misses x 30: Estimated Stalls"), PRELOADS_6, 30, ABST_NONE},
1704   {"dtlbm", "dtlb_load_misses.demand_ld_walk_completed", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_6, 0, ABST_NONE},
1705   {"dtlbm_stall", "dtlb_load_misses.demand_ld_walk_completed", REGNO_ANY, STXT ("DTLB Misses x 30: Estimated Stalls"), PRELOADS_6, 30, ABST_NONE},
1706
1707   /* explicit definitions of (hidden) entries for proper counters */
1708   /*  Only counters that can be time converted, or are load-store need to be in this table */
1709   {/* 30a */"cpu_clk_unhalted.thread", /*15634344==6940930*/ NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1710   //{/* 30a */"cpu_clk_unhalted.core",  /*6759307*/                     NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1711   {/*08.04*/"dtlb_load_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1712   {/*08.84*/"dtlb_load_misses.demand_ld_walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1713   {/*0d.03*/"int_misc.recovery_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1714   {/*0d.40*/"int_misc.rat_stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1715   {/*0e.01*/"uops_issued.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1716   {/*0e.01*/"uops_issued.core_stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1717   {/*14.01*/"arith.fpu_div_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1718   {/*3c.00*/"cpu_clk_unhalted.thread_p", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1719   {/*48.01*/"l1d_pend_miss.pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1720   {/*49.04*/"dtlb_store_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1721   {/*59.20*/"partial_rat_stalls.flags_merge_uop", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1722   {/*59.20*/"partial_rat_stalls.flags_merge_uop_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1723   {/*59.40*/"partial_rat_stalls.slow_lea_window", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1724   //{/*59.80*/"partial_rat_stalls.mul_single_uop",                      NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1725   {/*5b.0c*/"resource_stalls2.all_fl_empty", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1726   {/*5b.0f*/"resource_stalls2.all_prf_control", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1727   {/*5b.40*/"resource_stalls2.bob_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1728   {/*5b.4f*/"resource_stalls2.ooo_rsrc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1729   {/*5c.01*/"cpl_cycles.ring0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1730   {/*5c.02*/"cpl_cycles.ring123", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1731   {/*5c.xx*/"cpl_cycles.ring0_trans", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1732   {/*5c.xx*/"cpl_cycles.ring0_transition", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1733   {/*5e.01*/"rs_events.empty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1734   {/*60.01*/"offcore_requests_outstanding.cycles_with_demand_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1735   {/*60.01*/"offcore_requests_outstanding.demand_data_rd_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1736   {/*60.04*/"offcore_requests_outstanding.cycles_with_demand_rfo", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1737   {/*60.04*/"offcore_requests_outstanding.demand_rfo_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1738   {/*60.08*/"offcore_requests_outstanding.cycles_with_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1739   {/*60.08*/"offcore_requests_outstanding.all_data_rd_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1740   {/*60.02*/"offcore_requests_outstanding.demand_code_rd_cycles", /*?*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1741   {/*63.01*/"lock_cycles.split_lock_uc_lock_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1742   {/*63.02*/"lock_cycles.cache_lock_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1743   {/*79.00*/"idq.empty", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1744   {/*79.04*/"idq.mite_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1745   {/*79.08*/"idq.dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1746   {/*79.10*/"idq.ms_dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1747   {/*79.20*/"idq.ms_mite_uops_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1748   {/*79.20*/"idq.ms_mite_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1749   {/*79.30*/"idq.ms_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1750   {/*79.18*/"idq.all_dsb_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1751   {/*79.18*/"idq.all_dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1752   {/*79.18*/"idq.all_dsb_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1753   {/*79.24*/"idq.all_mite_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1754   {/*79.24*/"idq.all_mite_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1755   {/*79.24*/"idq.all_mite_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1756   {/*79.3c*/"idq.mite_all_cycles", /* Linux, but not in docs? */ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1757   {/*80.04*/"icache.ifetch_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1758   {/*85.04*/"itlb_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1759   {/*87.01*/"ild_stall.lcp", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1760   {/*87.04*/"ild_stall.iq_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1761   {/*9c.xx*/"idq_uops_not_delivered.cycles_0_uops_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1762   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_1_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1763   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_2_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1764   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_3_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1765   {/*9c.01*/"idq_uops_not_delivered.cycles_ge_1_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1766   {/*9c.01*/"idq_uops_not_delivered.cycles_fe_was_ok", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1767   {/*a1.01*/"uops_executed_port.port_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1768   {/*a1.02*/"uops_executed_port.port_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1769   {/*a1.04*/"uops_executed_port.port_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1770   {/*a1.08*/"uops_executed_port.port_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1771   {/*a1.10*/"uops_executed_port.port_4", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1772   {/*a1.20*/"uops_executed_port.port_5", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1773   {/*a2.01*/"resource_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1774   {/*a2.02*/"resource_stalls.lb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1775   {/*a2.04*/"resource_stalls.rs", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1776   {/*a2.08*/"resource_stalls.sb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1777   {/*a2.0a*/"resource_stalls.lb_sb", /*sb-ep*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1778   {/*a2.0e*/"resource_stalls.mem_rs", /*sb-ep*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1779   {/*a2.10*/"resource_stalls.rob", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1780   {/*a2.20*/"resource_stalls.fcsw", /*sb*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1781   {/*a2.40*/"resource_stalls.mxcsr", /*sb*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1782   {/*a2.80*/"resource_stalls.other", /*sb*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1783   {/*a2.F0*/"resource_stalls.ooo_rsrc", /*sb-ep*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1784
1785   {/*a3.01*/"cycle_activity.cycles_l2_pending", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1786   {/*??.??*/"cycle_activity.stalls_l2_pending", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1787   {/*a3.02*/"cycle_activity.cycles_ldm_pending", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1788   {/*??.??*/"cycle_activity.stalls_ldm_pending", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1789   {/*a3.04*/"cycle_activity.cycles_no_execute", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1790   {/*a3.04*/"cycle_activity.cycles_no_dispatch", /*sandybridge*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1791   {/*a3.08*/"cycle_activity.cycles_l1d_pending", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1792   {/*??.??*/"cycle_activity.stalls_l1d_pending", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1793
1794   {/*ab.02*/"dsb2mite_switches.penalty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1795   {/*b1.??*/"uops_executed.stall_cycles", /*? not in PRM*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1796   {/*b1.01*/"uops_dispatched.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1797   {/*b1.01*/"uops_executed.stall_cycles", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1798   {/*b1.01*/"uops_executed.cycles_ge_1_uop_exec", /*F6M62,not doc'd*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1799   {/*b1.01*/"uops_executed.cycles_ge_2_uops_exec", /*F6M62,not doc'd*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1800   {/*b1.01*/"uops_executed.cycles_ge_3_uops_exec", /*F6M62,not doc'd*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1801   {/*b1.01*/"uops_executed.cycles_ge_4_uops_exec", /*F6M62,not doc'd*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1802
1803   {/*bf.05*/"l1d_blocks.bank_conflict_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1804   {/*c2.01*/"uops_retired.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1805   {/*c2.01*/"uops_retired.total_cycles", /*cmask==0x10*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1806   {/*c2.01*/"uops_retired.core_stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1807   {/*c2.01*/"uops_retired.active_cycles", /*cmask==0x1*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1808 #if 0 // need to see documentation on the following before marking them as cycles
1809   uops_executed.cycles_ge_1_uop_exec[ / {0 | 1 | 2 | 3}], 1000003 (events)
1810   uops_executed.cycles_ge_2_uops_exec[ /
1811   {0 | 1 | 2 | 3}
1812   ], 1000003 (events)
1813   uops_executed.cycles_ge_3_uops_exec[ /
1814   {0 | 1 | 2 | 3}
1815   ], 1000003 (events)
1816   uops_executed.cycles_ge_4_uops_exec[ /
1817   {0 | 1 | 2 | 3}
1818   ], 1000003 (events)
1819 #endif
1820   {/*cd.01*/"mem_trans_retired.load_latency", /*PEBS*/ NULL, REGNO_ANY, NULL, PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1}, //non-standard overflow
1821
1822   /* "Architectural" events: */
1823   {/*3c*/"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1824   PERF_EVENTS_SW_EVENT_DEFS
1825
1826   /* additional (hidden) aliases for convenience */
1827 #if 0
1828   USE_INTEL_REF_CYCLES (100),
1829 #endif
1830   {"insts0", "inst_retired.any_p", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1831   {"insts1", "inst_retired.any_p", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1832   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1833 };
1834
1835
1836 static Hwcentry intelHaswellList[] = {
1837   /* see comments for "cycles" and "insts" for intelNehalemList */
1838   PERF_EVENTS_SW_EVENT_ALIASES
1839   USE_INTEL_REF_CYCLES (100)
1840   {"cycles", "cpu_clk_unhalted.thread_p", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1841   {"insts", "inst_retired.any_p", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1842
1843   // PEBS (sampling)
1844   {"l2m_latency", "mem_trans_retired.load_latency", REGNO_ANY, STXT ("L2 Cache Miss Est. Latency"), PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1},
1845
1846   {"dch", "mem_load_uops_retired.l1_hit", REGNO_ANY, STXT ("L1 D-cache Hits"), PRELOADS_7, 0, ABST_NONE},
1847   {"dcm", "mem_load_uops_retired.l1_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE}, //mem_load_uops_retired
1848   {"dcm", "0xd1~umask=0x08", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE}, //mem_load_uops_retired
1849   {"l2h", "mem_load_uops_retired.l2_hit", REGNO_ANY, STXT ("L2 Cache Hits"), PRELOADS_65, 0, ABST_NONE},
1850   {"l2m", "mem_load_uops_retired.l2_miss", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_6, 0, ABST_NONE}, //mem_load_uops_retired
1851   {"l2m", "0xd1~umask=0x10", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_6, 0, ABST_NONE}, //mem_load_uops_retired
1852   {"l3h", "mem_load_uops_retired.l3_hit", REGNO_ANY, STXT ("L3 Cache Hit w/o Snoop"), PRELOADS_6, 0, ABST_NONE},
1853   {"l3m", "mem_load_uops_retired.l3_miss", REGNO_ANY, STXT ("L3 Cache Misses"), PRELOADS_5, 0, ABST_NONE}, //mem_load_uops_retired
1854   {"l3m", "0xd1~umask=0x20", REGNO_ANY, STXT ("L3 Cache Misses"), PRELOADS_5, 0, ABST_NONE}, //mem_load_uops_retired
1855
1856   /* dtlbm has not been confirmed via Intel white paper */
1857   {"dtlbm", "dtlb_load_misses.walk_completed", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_6, 0, ABST_NONE},
1858   {"dtlbm_stall", "dtlb_load_misses.walk_completed", REGNO_ANY, STXT ("DTLB Misses x 30: Estimated Stalls"), PRELOADS_6, 30, ABST_NONE},
1859
1860   /* explicit definitions of (hidden) entries for proper counters */
1861   /*  Only counters that can be time converted, or are load-store need to be in this table */
1862   {/* 30a */"cpu_clk_unhalted.thread", /*15634344==6940930*/ NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1863   //{/* 30a */"cpu_clk_unhalted.core",  /*6759307*/                     NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1864   {/*08.10*/"dtlb_load_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1865   {/*0d.03*/"int_misc.recovery_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1866   {/*0e.01*/"uops_issued.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1867   {/*0e.01*/"uops_issued.core_stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1868   {/*3c.00*/"cpu_clk_unhalted.thread_p", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1869   {/*48.01*/"l1d_pend_miss.pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1870   {/*49.04*/"dtlb_store_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1871   {/*5c.01*/"cpl_cycles.ring0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1872   {/*5c.02*/"cpl_cycles.ring123", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1873   {/*5c.xx*/"cpl_cycles.ring0_trans", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1874   {/*5e.01*/"rs_events.empty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1875   {/*60.01*/"offcore_requests_outstanding.cycles_with_demand_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1876   {/*60.02*/"offcore_requests_outstanding.demand_code_rd_cycles", /*?*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1877   {/*60.04*/"offcore_requests_outstanding.demand_rfo_cycles", /*?*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1878   {/*60.08*/"offcore_requests_outstanding.cycles_with_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1879   {/*63.01*/"lock_cycles.split_lock_uc_lock_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1880   {/*63.02*/"lock_cycles.cache_lock_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1881   {/*79.00*/"idq.empty", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1882   {/*79.04*/"idq.mite_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1883   {/*79.08*/"idq.dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1884   {/*79.10*/"idq.ms_dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1885   {/*79.20*/"idq.ms_mite_uops_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1886   {/*79.20*/"idq.ms_mite_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1887   {/*79.30*/"idq.ms_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1888   {/*79.18*/"idq.all_dsb_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1889   {/*79.18*/"idq.all_dsb_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1890   {/*79.24*/"idq.all_mite_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1891   {/*79.24*/"idq.all_mite_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1892   {/*80.04*/"icache.ifetch_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1893   {/*85.04*/"itlb_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1894   {/*87.01*/"ild_stall.lcp", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, // Intel SDM says these are stalls, not cycles
1895   {/*87.04*/"ild_stall.iq_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1896   {/*9c.xx*/"idq_uops_not_delivered.cycles_0_uops_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1897   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_1_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1898   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_2_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1899   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_3_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1900   //  {/*9c.01*/"idq_uops_not_delivered.cycles_ge_1_uop_deliv.core",    NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1901   {/*9c.01*/"idq_uops_not_delivered.cycles_fe_was_ok", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1902
1903   {/*a1.01*/"uops_executed_port.port_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1904   {/*a1.02*/"uops_executed_port.port_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1905   {/*a1.04*/"uops_executed_port.port_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1906   {/*a1.08*/"uops_executed_port.port_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1907   {/*a1.10*/"uops_executed_port.port_4", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1908   {/*a1.20*/"uops_executed_port.port_5", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1909   {/*a1.40*/"uops_executed_port.port_6", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1910   {/*a1.80*/"uops_executed_port.port_7", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1911   {/*a1.01*/"uops_executed_port.port_0_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1912   {/*a1.02*/"uops_executed_port.port_1_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1913   {/*a1.04*/"uops_executed_port.port_2_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1914   {/*a1.08*/"uops_executed_port.port_3_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1915   {/*a1.10*/"uops_executed_port.port_4_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1916   {/*a1.20*/"uops_executed_port.port_5_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1917   {/*a1.40*/"uops_executed_port.port_6_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1918   {/*a1.80*/"uops_executed_port.port_7_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1919
1920   {/*a2.01*/"resource_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1921   {/*a2.04*/"resource_stalls.rs", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1922   {/*a2.08*/"resource_stalls.sb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1923   {/*a2.10*/"resource_stalls.rob", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1924
1925   {/*a3.01*/"cycle_activity.cycles_l2_pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1926   //  {/*a3.01*/"cycle_activity.cycles_l2_pending",                     NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1927   {/*a3.02*/"cycle_activity.cycles_ldm_pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1928   //  {/*a3.05*/"cycle_activity.stalls_l2_pending",                     NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1929   {/*a3.08*/"cycle_activity.cycles_l1d_pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1930   //  {/*a3.??*/"cycle_activity.cycles_no_execute",                     NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1931   //  {/*a3.??*/"cycle_activity.stalls_ldm_pending",/*?*/                       NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1932
1933   {/*ab.02*/"dsb2mite_switches.penalty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1934
1935   {/*b1.??*/"uops_executed.stall_cycles", /*? not in PRM*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1936   {/*b1.??*/"uops_executed.cycles_ge_1_uop_exec", /*?*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1937   {/*b1.??*/"uops_executed.cycles_ge_2_uops_exec", /*?*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1938   {/*b1.??*/"uops_executed.cycles_ge_3_uops_exec", /*?*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1939   {/*b1.??*/"uops_executed.cycles_ge_4_uops_exec", /*?*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1940
1941   {/*c2.01*/"uops_retired.stall_cycles", /*cmask==1 + INV*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1942   {/*c2.01*/"uops_retired.total_cycles", /*cmask==0x1*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1943   {/*c2.01*/"uops_retired.core_stall_cycles", /*PEBS Any==1*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1944
1945   {/*c3.01*/"machine_clears.cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1946
1947   {/*ca.1e*/"fp_assist.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1948
1949   {/*cd.01*/"mem_trans_retired.load_latency", /*PEBS*/ NULL, REGNO_ANY, NULL, PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1}, //non-standard overflow
1950
1951   /* "Architectural" events: */
1952   {/*3c*/"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1953   PERF_EVENTS_SW_EVENT_DEFS
1954
1955   /* additional (hidden) aliases for convenience */
1956 #if 0
1957   USE_INTEL_REF_CYCLES (100),
1958 #endif
1959   {"insts0", "inst_retired.any_p", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1960   {"insts1", "inst_retired.any_p", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1961   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1962 };
1963
1964
1965 static Hwcentry intelBroadwellList[] = {
1966   /* see comments for "cycles" and "insts" for intelNehalemList */
1967   PERF_EVENTS_SW_EVENT_ALIASES
1968   USE_INTEL_REF_CYCLES (100)
1969   {"cycles", "cpu_clk_unhalted.thread_p", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1970   {"insts", "inst_retired.any_p", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1971
1972   // PEBS (sampling)
1973   {"l2m_latency", "mem_trans_retired.load_latency", REGNO_ANY, STXT ("L2 Cache Miss Est. Latency"), PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1},
1974   {/*cd.01*/"mem_trans_retired.load_latency", NULL, REGNO_ANY, NULL, PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1},
1975
1976   // aliases (the first set are PEBS, but on Intel the only precise counter we support is l2m_latency)
1977   {"dch", "mem_load_uops_retired.l1_hit", REGNO_ANY, STXT ("L1 D-cache Hits"), PRELOADS_7, 0, ABST_NONE},
1978   {"dcm", "mem_load_uops_retired.l1_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE},
1979   {"l2h", "mem_load_uops_retired.l2_hit", REGNO_ANY, STXT ("L2 Cache Hits"), PRELOADS_65, 0, ABST_NONE},
1980   {"l2m", "mem_load_uops_retired.l2_miss", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_6, 0, ABST_NONE},
1981   {"l3h", "mem_load_uops_retired.l3_hit", REGNO_ANY, STXT ("L3 Cache Hits"), PRELOADS_6, 0, ABST_NONE},
1982   {"l3m", "mem_load_uops_retired.l3_miss", REGNO_ANY, STXT ("L3 Cache Misses"), PRELOADS_5, 0, ABST_NONE},
1983   {"dtlbm", "dtlb_load_misses.walk_completed", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_6, 0, ABST_NONE},
1984
1985   // counters that can be time converted (add FFCs if we decide to support them)
1986   // counters that are load-store (did not include any... do we want to?)
1987   {/*08.10*/"dtlb_load_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1988   {/*0d.03*/"int_misc.recovery_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1989   {/*0e.01*/"uops_issued.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1990   {/*0e.01*/"uops_issued.core_stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1991   {/*14.01*/"arith.fpu_div_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1992   {/*3c.00*/"cpu_clk_unhalted.thread_p_any", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1993   {/*3c.00*/"cpu_clk_unhalted.thread_p", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1994   {/*3c.02*/"cpu_clk_thread_unhalted.one_thread_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1995   {/*48.01*/"l1d_pend_miss.pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1996   {/*48.01*/"l1d_pend_miss.pending_cycles_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1997   {/*49.10*/"dtlb_store_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1998   {/*4f.10*/"ept.walk_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1999   {/*5c.01*/"cpl_cycles.ring0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2000   {/*5c.01*/"cpl_cycles.ring0_trans", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2001   {/*5c.02*/"cpl_cycles.ring123", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2002   {/*5e.01*/"rs_events.empty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2003   {/*60.01*/"offcore_requests_outstanding.cycles_with_demand_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2004   {/*60.02*/"offcore_requests_outstanding.demand_code_rd_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2005   {/*60.04*/"offcore_requests_outstanding.demand_rfo_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2006   {/*60.08*/"offcore_requests_outstanding.cycles_with_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2007   {/*63.01*/"lock_cycles.split_lock_uc_lock_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2008   {/*63.02*/"lock_cycles.cache_lock_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2009   {/*79.02*/"idq.empty", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2010   {/*79.04*/"idq.mite_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2011   {/*79.08*/"idq.dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2012   {/*79.10*/"idq.ms_dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2013   {/*79.18*/"idq.all_dsb_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2014   {/*79.18*/"idq.all_dsb_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2015   {/*79.24*/"idq.all_mite_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2016   {/*79.24*/"idq.all_mite_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2017   {/*79.30*/"idq.ms_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2018   {/*85.10*/"itlb_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2019   {/*9c.xx*/"idq_uops_not_delivered.cycles_0_uops_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2020   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_1_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2021   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_2_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2022   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_3_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2023   {/*9c.01*/"idq_uops_not_delivered.cycles_fe_was_ok", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2024   {/*a1.01*/"uops_executed_port.port_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2025   {/*a1.02*/"uops_executed_port.port_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2026   {/*a1.04*/"uops_executed_port.port_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2027   {/*a1.08*/"uops_executed_port.port_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2028   {/*a1.10*/"uops_executed_port.port_4", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2029   {/*a1.20*/"uops_executed_port.port_5", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2030   {/*a1.40*/"uops_executed_port.port_6", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2031   {/*a1.80*/"uops_executed_port.port_7", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2032   {/*a1.01*/"uops_executed_port.port_0_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2033   {/*a1.02*/"uops_executed_port.port_1_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2034   {/*a1.04*/"uops_executed_port.port_2_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2035   {/*a1.08*/"uops_executed_port.port_3_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2036   {/*a1.10*/"uops_executed_port.port_4_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2037   {/*a1.20*/"uops_executed_port.port_5_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2038   {/*a1.40*/"uops_executed_port.port_6_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2039   {/*a1.80*/"uops_executed_port.port_7_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2040   {/*a2.01*/"resource_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2041   {/*a2.04*/"resource_stalls.rs", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2042   {/*a2.08*/"resource_stalls.sb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2043   {/*a2.10*/"resource_stalls.rob", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2044   {/*a3.01*/"cycle_activity.cycles_l2_pending", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2045   {/*a3.02*/"cycle_activity.cycles_ldm_pending", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2046   {/*a3.04*/"cycle_activity.cycles_no_execute", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2047   {/*a3.08*/"cycle_activity.cycles_l1d_pending", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2048   {/*a8.01*/"lsd.cycles_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2049   {/*a8.01*/"lsd.cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2050   {/*ab.02*/"dsb2mite_switches.penalty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2051   {/*b1.01*/"uops_executed.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2052   {/*c2.01*/"uops_retired.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2053   {/*c2.01*/"uops_retired.total_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2054   {/*c2.01*/"uops_retired.core_stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2055   {/*c3.01*/"machine_clears.cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2056   {/*ca.1e*/"fp_assist.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2057
2058   /* "Architectural" events: */
2059   {/*3c*/"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2060   PERF_EVENTS_SW_EVENT_DEFS
2061
2062   /* additional (hidden) aliases for convenience */
2063 #if 0
2064   USE_INTEL_REF_CYCLES (100),
2065 #endif
2066   {"insts0", "inst_retired.any_p", 0, NULL, PRELOADS_8, 0, ABST_NONE},
2067   {"insts1", "inst_retired.any_p", 1, NULL, PRELOADS_8, 0, ABST_NONE},
2068   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
2069 };
2070
2071 static Hwcentry intelSkylakeList[] = {
2072   /* see comments for "cycles" and "insts" for intelNehalemList */
2073   PERF_EVENTS_SW_EVENT_ALIASES
2074   USE_INTEL_REF_CYCLES (25)
2075   {"cycles", "cpu_clk_unhalted.thread_p", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
2076   {"insts", "inst_retired.any_p", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
2077
2078   // PEBS (sampling)
2079   {"l2m_latency", "mem_trans_retired.load_latency", REGNO_ANY, STXT ("L2 Cache Miss Est. Latency"), PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1},
2080   {/*cd.01*/"mem_trans_retired.load_latency", NULL, REGNO_ANY, NULL, PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1},
2081
2082   // aliases (the first set are PEBS, but on Intel the only precise counter we support is l2m_latency)
2083   {"dch", "mem_load_retired.l1_hit", REGNO_ANY, STXT ("L1 D-cache Hits"), PRELOADS_7, 0, ABST_NONE},
2084   {"dcm", "mem_load_retired.l1_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE},
2085   {"l2h", "mem_load_retired.l2_hit", REGNO_ANY, STXT ("L2 Cache Hits"), PRELOADS_65, 0, ABST_NONE},
2086   {"l2m", "mem_load_retired.l2_miss", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_6, 0, ABST_NONE},
2087   {"l2m_stall", "cycle_activity.stalls_l2_miss", REGNO_ANY, STXT ("L2 Cache Miss Stall"), PRELOADS_7, 1, ABST_NONE}, // needs validation
2088   {"l3h", "mem_load_retired.l3_hit", REGNO_ANY, STXT ("L3 Cache Hits"), PRELOADS_6, 0, ABST_NONE},
2089   {"l3m", "mem_load_retired.l3_miss", REGNO_ANY, STXT ("L3 Cache Misses"), PRELOADS_5, 0, ABST_NONE},
2090   {"l3m_stall", "cycle_activity.stalls_l3_miss", REGNO_ANY, STXT ("L3 Cache Miss Stall"), PRELOADS_7, 1, ABST_NONE}, // needs validation
2091   {"dtlbm_stall", "dtlb_load_misses.walk_active", REGNO_ANY, STXT ("DTLB Miss Est Stall"), PRELOADS_7, 1, ABST_NONE, STXT ("Estimated time stalled on DTLB misses requiring a tablewalk.  Does not include time related to STLB hits.")}, // needs validation
2092   // PEBS mem_inst_retired.stlb_miss_loads for finding location of DTLB issues
2093   // what about: dtlb_load_misses.walk_completed, dtlb_load_misses.walk_pending, dtlb_load_misses.stlb_hit
2094
2095   {"fp_scalar", "fp_arith_inst_retired.scalar_double~umask=0x3", REGNO_ANY, STXT ("FP Scalar uOps"), PRELOADS_7, 0, ABST_NONE, STXT ("Floating-point scalar micro-ops that retired")},
2096   {"fp_vector", "fp_arith_inst_retired.128b_packed_double~umask=0x3c", REGNO_ANY, STXT ("FP Vector uOps"), /*needs test*/ PRELOADS_7, 0, ABST_NONE, STXT ("Floating-point vector micro-ops that retired")},
2097
2098   // counters that can be time converted (add FFCs if we decide to support them)
2099   // counters that are load-store (did not include any... do we want to?)
2100   {/*08.10*/"dtlb_load_misses.walk_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2101   {/*08.10*/"dtlb_load_misses.walk_pending", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2102   {/*0d.01*/"int_misc.recovery_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2103   {/*0d.01*/"int_misc.recovery_cycles_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2104   {/*0d.80*/"int_misc.clear_resteer_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2105   {/*0e.01*/"uops_issued.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2106   {/*14.01*/"arith.divider_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2107   {/*3c.00*/"cpu_clk_unhalted.ring0_trans", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2108   {/*3c.00*/"cpu_clk_unhalted.thread_p_any", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2109   {/*3c.00*/"cpu_clk_unhalted.thread_p", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2110   {/*3c.00*/"cpu_clk_unhalted.core", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2111   {/*48.01*/"l1d_pend_miss.pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2112   {/*48.01*/"l1d_pend_miss.pending_cycles_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2113   {/*49.10*/"dtlb_store_misses.walk_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2114   {/*49.10*/"dtlb_store_misses.walk_pending", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2115   {/*4f.10*/"ept.walk_pending", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2116   {/*5e.01*/"rs_events.empty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2117   {/*60.01*/"offcore_requests_outstanding.cycles_with_demand_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2118   {/*60.01*/"offcore_requests_outstanding.demand_data_rd_ge_6", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2119   {/*60.02*/"offcore_requests_outstanding.cycles_with_demand_code_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2120   {/*60.04*/"offcore_requests_outstanding.cycles_with_demand_rfo", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2121   {/*60.08*/"offcore_requests_outstanding.cycles_with_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2122   {/*60.10*/"offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2123   {/*60.10*/"offcore_requests_outstanding.l3_miss_demand_data_rd_ge_6", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2124   {/*63.02*/"lock_cycles.cache_lock_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2125   {/*79.04*/"idq.mite_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2126   {/*79.08*/"idq.dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2127   {/*79.10*/"idq.ms_dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2128   {/*79.18*/"idq.all_dsb_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2129   {/*79.18*/"idq.all_dsb_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2130   {/*79.24*/"idq.all_mite_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2131   {/*79.24*/"idq.all_mite_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2132   {/*79.30*/"idq.ms_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2133   {/*80.04*/"icache_16b.ifdata_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2134   {/*83.04*/"icache_64b.iftag_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2135   {/*85.10*/"itlb_misses.walk_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2136   {/*85.10*/"itlb_misses.walk_pending", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2137   {/*87.01*/"ild_stall.lcp", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2138   {/*9c.01*/"idq_uops_not_delivered.cycles_0_uops_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2139   {/*9c.01*/"idq_uops_not_delivered.cycles_le_1_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2140   {/*9c.01*/"idq_uops_not_delivered.cycles_le_2_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2141   {/*9c.01*/"idq_uops_not_delivered.cycles_le_3_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2142   {/*9c.01*/"idq_uops_not_delivered.cycles_fe_was_ok", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2143   {/*a1.01*/"uops_dispatched_port.port_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2144   {/*a1.02*/"uops_dispatched_port.port_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2145   {/*a1.04*/"uops_dispatched_port.port_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2146   {/*a1.08*/"uops_dispatched_port.port_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2147   {/*a1.10*/"uops_dispatched_port.port_4", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2148   {/*a1.20*/"uops_dispatched_port.port_5", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2149   {/*a1.40*/"uops_dispatched_port.port_6", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2150   {/*a1.80*/"uops_dispatched_port.port_7", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2151   {/*a2.01*/"resource_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2152   {/*a2.08*/"resource_stalls.sb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2153   {/*a3.01*/"cycle_activity.cycles_l2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2154   {/*a3.02*/"cycle_activity.cycles_l3_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2155   {/*a3.04*/"cycle_activity.stalls_total", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2156   {/*a3.05*/"cycle_activity.stalls_l2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2157   {/*a3.06*/"cycle_activity.stalls_l3_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2158   {/*a3.08*/"cycle_activity.cycles_l1d_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2159   {/*a3.0c*/"cycle_activity.stalls_l1d_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2160   {/*a3.10*/"cycle_activity.cycles_mem_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2161   {/*a3.14*/"cycle_activity.stalls_mem_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2162   {/*a6.01*/"exe_activity.exe_bound_0_ports", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2163   {/*a6.02*/"exe_activity.1_ports_util", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2164   {/*a6.04*/"exe_activity.2_ports_util", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2165   {/*a6.08*/"exe_activity.3_ports_util", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2166   {/*a6.10*/"exe_activity.4_ports_util", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2167   {/*a6.40*/"exe_activity.bound_on_stores", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2168   {/*a8.01*/"lsd.cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2169   {/*a8.01*/"lsd.cycles_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2170   {/*ab.02*/"dsb2mite_switches.penalty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2171   {/*b1.01*/"uops_executed.cycles_ge_1_uop_exec", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2172   {/*b1.01*/"uops_executed.cycles_ge_2_uops_exec", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2173   {/*b1.01*/"uops_executed.cycles_ge_3_uops_exec", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2174   {/*b1.01*/"uops_executed.cycles_ge_4_uops_exec", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2175   {/*b1.01*/"uops_executed.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2176   {/*b1.02*/"uops_executed.core_cycles_ge_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2177   {/*b1.02*/"uops_executed.core_cycles_ge_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2178   {/*b1.02*/"uops_executed.core_cycles_ge_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2179   {/*b1.02*/"uops_executed.core_cycles_ge_4", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2180   {/*b1.02*/"uops_executed.core_cycles_none", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2181   {/*c0.1*/"inst_retired.total_cycles_ps", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2182   {/*c2.01*/"uops_retired.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2183   {/*c2.01*/"uops_retired.total_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2184   {/*ca.1e*/"fp_assist.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2185
2186   /* "Architectural" events: */
2187   {/* FFC */"cpu_clk_unhalted.thread", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2188   {/* FFC */"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2189   PERF_EVENTS_SW_EVENT_DEFS
2190
2191   /* additional (hidden) aliases for convenience */
2192 #if 0
2193   USE_INTEL_REF_CYCLES (25),
2194 #endif
2195   {"insts0", "inst_retired.any_p", 0, NULL, PRELOADS_8, 0, ABST_NONE},
2196   {"insts1", "inst_retired.any_p", 1, NULL, PRELOADS_8, 0, ABST_NONE},
2197   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
2198 };
2199
2200 static Hwcentry intelLinuxUnknown[] = {
2201   PERF_EVENTS_SW_EVENT_ALIASES
2202   //    USE_INTEL_REF_CYCLES(100) // freq is unknown
2203   {"cycles", "unhalted-core-cycles", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
2204   {"cycles", "PERF_COUNT_HW_CPU_CYCLES", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
2205   {"insts", "instruction-retired", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
2206   {"insts", "PERF_COUNT_HW_INSTRUCTIONS", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
2207
2208   {"dcm", "PERF_COUNT_HW_CACHE_MISSES.L1D", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE},
2209   {"llm", "llc-misses", REGNO_ANY, STXT ("Last-Level Cache Misses"), PRELOADS_5, 0, ABST_NONE},
2210   {"llm", "PERF_COUNT_HW_CACHE_MISSES.LL", REGNO_ANY, STXT ("Last-Level Cache Misses"), PRELOADS_5, 0, ABST_NONE},
2211
2212   {"br_msp", "branch-misses-retired", REGNO_ANY, STXT ("Branch Mispredict"), PRELOADS_6, 0, ABST_NONE},
2213   {"br_msp", "PERF_COUNT_HW_BRANCH_MISSES", REGNO_ANY, STXT ("Branch Mispredict"), PRELOADS_6, 0, ABST_NONE},
2214   {"br_ins", "branch-instruction-retired", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE},
2215   {"br_ins", "PERF_COUNT_HW_BRANCH_INSTRUCTIONS", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE},
2216
2217   // counters that can be time converted (add FFCs if we decide to support them)
2218   // counters that are load-store (did not include any... do we want to?)
2219   /* "Architectural" events: */
2220   {/* FFC */"cpu_clk_unhalted.thread", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2221   {/* FFC */"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2222   PERF_EVENTS_SW_EVENT_DEFS
2223
2224   /* additional (hidden) aliases for convenience */
2225   {"cycles0", "unhalted-reference-cycles", 0, NULL, PRELOADS_6, -(25), ABST_NONE}, //YXXX -can't do with ref cycles #
2226   {"cycles0", "PERF_COUNT_HW_BUS_CYCLES", 0, NULL, PRELOADS_6, -(25), ABST_NONE}, //YXXX -can't do with ref cycles #
2227   {"cycles1", "unhalted-reference-cycles", 1, NULL, PRELOADS_65, -(25), ABST_NONE}, //YXXX - can't do with ref cycles #
2228   {"cycles1", "PERF_COUNT_HW_BUS_CYCLES", 1, NULL, PRELOADS_65, -(25), ABST_NONE}, //YXXX - can't do with ref cycles #
2229   {"insts0", "instruction-retired", 0, NULL, PRELOADS_8, 0, ABST_NONE},
2230   {"insts0", "PERF_COUNT_HW_INSTRUCTIONS", 0, NULL, PRELOADS_8, 0, ABST_NONE},
2231   {"insts1", "instruction-retired", 1, NULL, PRELOADS_8, 0, ABST_NONE},
2232   {"insts1", "PERF_COUNT_HW_INSTRUCTIONS", 1, NULL, PRELOADS_8, 0, ABST_NONE},
2233   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
2234 };
2235
2236 static Hwcentry intelAtomList[] = {
2237   {"cycles", "cpu_clk_unhalted.core", /*6759307*/ REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
2238   {"cycles", "cpu_clk_unhalted.thread", /*6759307*/ REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
2239   {"insts", "instr_retired.any", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
2240
2241   /* explicit definitions of (hidden) entries for proper counters */
2242   /*  Only counters that can be time converted, or are load-store need to be in this table */
2243   /* XXXX add core2-related entries if appropriate */
2244   {/*30A*/"cpu_clk_unhalted.core", /*6759307*/ NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
2245   {/*30A*/"cpu_clk_unhalted.thread", /*6759307*/ NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
2246   {/*0c*/"page_walks.cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2247   {/*14*/"cycles_div_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2248   {/*21*/"l2_ads", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2249   {/*22*/"l2_dbus_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2250   {/*32*/"l2_no_req", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2251   {/*3c*/"cpu_clk_unhalted.core_p", NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
2252   {/*3c*/"cpu_clk_unhalted.bus", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2253   {/*3c*/"cpu_clk_unhalted.no_other", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2254   {/*62*/"bus_drdy_clocks", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2255   {/*63*/"bus_lock_clocks", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2256   {/*64*/"bus_data_rcv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2257   {/*7a*/"bus_hit_drv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2258   {/*7b*/"bus_hitm_drv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2259   {/*7d*/"busq_empty", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2260   {/*7e*/"snoop_stall_drv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2261   {/*7f*/"bus_io_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2262   {/*c6*/"cycles_int_masked.cycles_int_masked", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2263   {/*c6*/"cycles_int_masked.cycles_int_pending_and_masked", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2264
2265   /* "Architectural" events: */
2266   {/*3c*/"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2267
2268   /* additional (hidden) aliases for convenience */
2269   {"cycles0", "cpu_clk_unhalted.core_p", 0, NULL, PRELOADS_75, 1, ABST_NONE},
2270   {"cycles1", "cpu_clk_unhalted.core_p", 1, NULL, PRELOADS_75, 1, ABST_NONE},
2271   {"insts0", "inst_retired.any_p", 0, NULL, PRELOADS_75, 0, ABST_NONE},
2272   {"insts1", "inst_retired.any_p", 1, NULL, PRELOADS_75, 0, ABST_NONE},
2273   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
2274 };
2275
2276 static Hwcentry amd_opteron_10h_11h[] = {
2277   {"cycles", "BU_cpu_clk_unhalted", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
2278   {"insts", "FR_retired_x86_instr_w_excp_intr", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
2279   {"icr", "IC_fetch", REGNO_ANY, STXT ("L1 I-cache Refs"), PRELOADS_7, 0, ABST_NONE}, /* new */
2280   {"icm", "IC_miss", REGNO_ANY, STXT ("L1 I-cache Misses"), PRELOADS_6, 0, ABST_NONE},
2281   {"l2itlbh", "IC_itlb_L1_miss_L2_hit", REGNO_ANY, STXT ("L2 ITLB Hits"), PRELOADS_6, 0, ABST_NONE}, /* new */
2282   {"l2itlbm", "IC_itlb_L1_miss_L2_miss", REGNO_ANY, STXT ("L2 ITLB Misses"), PRELOADS_5, 0, ABST_NONE}, /* new */
2283   {"l2ir", "BU_internal_L2_req~umask=0x1", REGNO_ANY, STXT ("L2 I-cache Refs"), PRELOADS_6, 0, ABST_NONE},
2284   {"l2im", "BU_fill_req_missed_L2~umask=0x1", REGNO_ANY, STXT ("L2 I-cache Misses"), PRELOADS_4, 0, ABST_NONE},
2285   {"dcr", "DC_access", REGNO_ANY, STXT ("L1 D-cache Refs"), PRELOADS_7, 0, ABST_NONE}, /* new */
2286   {"dcm", "DC_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE}, /* new */
2287   {"l2dtlbh", "DC_dtlb_L1_miss_L2_hit", REGNO_ANY, STXT ("L2 DTLB Hits"), PRELOADS_6, 0, ABST_NONE}, /* new */
2288   {"l2dtlbm", "DC_dtlb_L1_miss_L2_miss", REGNO_ANY, STXT ("L2 DTLB Misses"), PRELOADS_5, 0, ABST_NONE}, /* new */
2289   {"l2dr", "BU_internal_L2_req~umask=0x2", REGNO_ANY, STXT ("L2 D-cache Refs"), PRELOADS_65, 0, ABST_NONE}, /* hwc_cache_load: 1.6x overcount on shanghai01 */
2290   {"l2dm", "BU_fill_req_missed_L2~umask=0x2", REGNO_ANY, STXT ("L2 D-cache Misses"), PRELOADS_6, 0, ABST_NONE}, /* new */
2291   {"fpadd", "FP_dispatched_fpu_ops~umask=0x1", REGNO_ANY, STXT ("FP Adds"), PRELOADS_7, 0, ABST_NONE},
2292   {"fpmul", "FP_dispatched_fpu_ops~umask=0x2", REGNO_ANY, STXT ("FP Muls"), PRELOADS_7, 0, ABST_NONE},
2293   {"fpustall", "FR_dispatch_stall_fpu_full", REGNO_ANY, STXT ("FPU Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
2294   {"memstall", "FR_dispatch_stall_ls_full", REGNO_ANY, STXT ("Memory Unit Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
2295   // For PAPI mappings, see hwctable.README.family10h
2296   // For PAPI mappings, see hwctable.README.opteron
2297
2298   /* explicit definitions of (hidden) entries for proper counters */
2299   /*  Only counters that can be time converted, or are load-store need to be in this table */
2300   {"BU_cpu_clk_unhalted", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2301   {"FP_cycles_no_fpu_ops_retired", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2302   {"FP_serialize_ops_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2303   {"FR_dispatch_stall_branch_abort_to_retire", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2304   {"FR_dispatch_stall_far_ctl_trsfr_resync_branch_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2305   {"FR_dispatch_stall_fpu_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2306   {"FR_dispatch_stall_ls_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2307   {"FR_dispatch_stall_reorder_buffer_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2308   {"FR_dispatch_stall_resv_stations_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2309   {"FR_dispatch_stall_segment_load", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2310   {"FR_dispatch_stall_serialization", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2311   {"FR_dispatch_stall_waiting_all_quiet", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2312   {"FR_dispatch_stalls", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2313   {"FR_intr_masked_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2314   {"FR_intr_masked_while_pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2315   {"FR_nothing_to_dispatch", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2316   {"IC_instr_fetch_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2317   {"LS_buffer_2_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2318   {"NB_mem_ctrlr_dram_cmd_slots_missed", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2319   {"NB_mem_ctrlr_turnaround", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2320
2321   /* additional (hidden) aliases, for convenience */
2322   {"cycles0", "BU_cpu_clk_unhalted", 0, NULL, PRELOADS_8, 1, ABST_NONE},
2323   {"cycles1", "BU_cpu_clk_unhalted", 1, NULL, PRELOADS_8, 1, ABST_NONE},
2324   {"insts0", "FR_retired_x86_instr_w_excp_intr", 0, NULL, PRELOADS_8, 0, ABST_NONE},
2325   {"insts1", "FR_retired_x86_instr_w_excp_intr", 1, NULL, PRELOADS_8, 0, ABST_NONE},
2326   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
2327 };
2328
2329 static Hwcentry amd_15h[] = {
2330   {"cycles", "CU_cpu_clk_unhalted", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
2331   {"insts", "EX_retired_instr_w_excp_intr", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
2332   {"icr", "IC_fetch", REGNO_ANY, STXT ("L1 I-cache Refs"), PRELOADS_7, 0, ABST_NONE}, /* new */
2333   {"icm", "IC_miss", REGNO_ANY, STXT ("L1 I-cache Misses"), PRELOADS_6, 0, ABST_NONE},
2334   {"l2im", "IC_refill_from_system", REGNO_ANY, STXT ("L2 I-cache Misses"), PRELOADS_6, 0, ABST_NONE},
2335   {"dcr", "DC_access", REGNO_ANY, STXT ("L1 D-cache Refs"), PRELOADS_7, 0, ABST_NONE}, /* new */
2336   {"dcm", "DC_miss~umask=0x3", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE}, /* new */
2337   {"l2dm", "DC_refill_from_system", REGNO_ANY, STXT ("L2 D-cache Misses"), PRELOADS_6, 0, ABST_NONE}, /* new */
2338   {"dtlbm", "DC_unified_tlb_miss~umask=0x7", REGNO_ANY, STXT ("L2 DTLB Misses"), PRELOADS_5, 0, ABST_NONE}, /* new */
2339   // For PAPI mappings, see hwctable.README.family15h
2340
2341   /* explicit definitions of (hidden) entries for proper counters */
2342   /*  Only counters that can be time converted, or are load-store need to be in this table */
2343   {/*001.xx*/"FP_scheduler_empty", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2344   {/*006.xx*/"FP_bottom_execute_uops_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2345   {/*023.xx*/"LS_ldq_stq_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2346   {/*024.xx*/"LS_locked_operation", /*umask!=0*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2347   {/*069.xx*/"CU_mab_wait_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2348   {/*076.xx*/"CU_cpu_clk_unhalted", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2349   {/*087.xx*/"IC_instr_fetch_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2350   {/*0cd.xx*/"EX_intr_masked_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2351   {/*0ce.xx*/"EX_intr_masked_while_pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2352   {/*0d0.xx*/"DE_nothing_to_dispatch", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2353   {/*0d1.xx*/"DE_dispatch_stalls", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2354   {/*0d3.xx*/"DE_dispatch_stall_serialization", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2355   {/*0d5.xx*/"DE_dispatch_stall_instr_retire_q_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2356   {/*0d6.xx*/"DE_dispatch_stall_int_scheduler_q_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2357   {/*0d7.xx*/"DE_dispatch_stall_fp_scheduler_q_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2358   {/*0d8.xx*/"DE_dispatch_stall_ldq_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2359   {/*0d9.xx*/"DE_dispatch_stall_waiting_all_quiet", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2360   {/*1d8.xx*/"EX_dispatch_stall_stq_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2361
2362   /* additional (hidden) aliases, for convenience */
2363   {"cycles0", "CU_cpu_clk_unhalted", 0, NULL, PRELOADS_8, 1, ABST_NONE},
2364   {"cycles1", "CU_cpu_clk_unhalted", 1, NULL, PRELOADS_8, 1, ABST_NONE},
2365   {"insts0", "EX_retired_instr_w_excp_intr", 0, NULL, PRELOADS_8, 0, ABST_NONE},
2366   {"insts1", "EX_retired_instr_w_excp_intr", 1, NULL, PRELOADS_8, 0, ABST_NONE},
2367   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
2368 };
2369
2370 #define USE_ARM_REF_CYCLES \
2371     {"usr_time","cycles",                 REGNO_ANY, STXT("User CPU"),   PRELOADS_85, 1, ABST_NONE}, \
2372     {"sys_time","cycles~system=1~user=0", REGNO_ANY, STXT("System CPU"), PRELOADS_85, 1, ABST_NONE}, \
2373
2374 static Hwcentry armlist[] = {
2375   USE_ARM_REF_CYCLES
2376 // Hardware event:
2377   {"branch-instructions",     NULL, REGNO_ANY, STXT("Branch-instructions"), PRELOADS_35, 0, ABST_NONE},
2378   {"branch-misses",           NULL, REGNO_ANY, STXT("Branch-misses"), PRELOADS_35, 0, ABST_NONE},
2379   {"bus-cycles",              NULL, REGNO_ANY, STXT("Bus Cycles"), PRELOADS_35, 1, ABST_NONE},
2380   {"cache-misses",            NULL, REGNO_ANY, STXT("Cache-misses"), PRELOADS_35, 0, ABST_NONE},
2381   {"cache-references",        NULL, REGNO_ANY, STXT("Cache-references"), PRELOADS_35, 0, ABST_NONE},
2382   {"cycles",                  NULL, REGNO_ANY, STXT("CPU Cycles"), PRELOADS_85, 1, ABST_NONE},
2383   {"insts",         "instructions", REGNO_ANY, STXT("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
2384   {"ref-cycles",              NULL, REGNO_ANY, STXT("Total Cycles"), PRELOADS_85, 1, ABST_NONE},
2385   {"stalled-cycles-backend",  NULL, REGNO_ANY, STXT("Stalled Cycles during issue."), PRELOADS_85, 1, ABST_NONE},
2386   {"stalled-cycles-frontend", NULL, REGNO_ANY, STXT("Stalled Cycles during retirement."), PRELOADS_85, 1, ABST_NONE},
2387
2388 // Software event:
2389   {"alignment-faults",        NULL, REGNO_ANY, STXT("Alignment Faults"), PRELOADS_85, 0, ABST_NONE},
2390   {"context-switches",        NULL, REGNO_ANY, STXT("Context Switches"), PRELOADS_85, 0, ABST_NONE},
2391   {"cpu-clock",               NULL, REGNO_ANY, STXT("CPU Clock"), PRELOADS_85, 1, ABST_NONE},
2392   {"cpu-migrations",          NULL, REGNO_ANY, STXT("CPU Migrations"), PRELOADS_85, 0, ABST_NONE},
2393   {"emulation-faults",        NULL, REGNO_ANY, STXT("Emulation Faults"), PRELOADS_85, 0, ABST_NONE},
2394   {"major-faults",            NULL, REGNO_ANY, STXT("Major Page Faults"), PRELOADS_85, 0, ABST_NONE},
2395   {"minor-faults",            NULL, REGNO_ANY, STXT("Minor Page Faults"), PRELOADS_85, 0, ABST_NONE},
2396   {"page-faults",             NULL, REGNO_ANY, STXT("Page Faults"), PRELOADS_85, 0, ABST_NONE},
2397   {"task-clock",              NULL, REGNO_ANY, STXT("Clock Count Specific"), PRELOADS_85, 1, ABST_NONE},
2398
2399 // Hardware cache event
2400   {"L1-dcache-load-misses",   NULL, REGNO_ANY, STXT("L1 D-cache Load Misses"), PRELOADS_35, 0, ABST_NONE},
2401   {"L1-dcache-loads",         NULL, REGNO_ANY, STXT("L1 D-cache Loads"), PRELOADS_35, 0, ABST_NONE},
2402   {"L1-dcache-store-misses",  NULL, REGNO_ANY, STXT("L1 D-cache Store Misses"), PRELOADS_35, 0, ABST_NONE},
2403   {"L1-dcache-stores",        NULL, REGNO_ANY, STXT("L1 D-cache Store Stores"), PRELOADS_35, 0, ABST_NONE},
2404   {"L1-icache-load-misses",   NULL, REGNO_ANY, STXT("L1 Instructions Load Misses"), PRELOADS_35, 0, ABST_NONE},
2405   {"L1-icache-load-misses",   NULL, REGNO_ANY, STXT("L1 Instructions Loads"), PRELOADS_35, 0, ABST_NONE},
2406   {"dTLB-load-misses",        NULL, REGNO_ANY, STXT("D-TLB Load Misses"), PRELOADS_35, 0, ABST_NONE},
2407   {"dTLB-loads",              NULL, REGNO_ANY, STXT("D-TLB Loads"), PRELOADS_35, 0, ABST_NONE},
2408   {"iTLB-load-misses",        NULL, REGNO_ANY, STXT("The Instruction TLB Load Misses"), PRELOADS_35, 0, ABST_NONE},
2409   {"iTLB-loads",              NULL, REGNO_ANY, STXT("The Instruction TLB Loads"), PRELOADS_35, 0, ABST_NONE},
2410
2411   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
2412 };
2413
2414 static Hwcentry unknownlist[] =
2415         /*  used for unrecognized CPU type */{
2416   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
2417 };
2418
2419 /* structure defining the counters for a CPU type */
2420 typedef struct
2421 {
2422   int cputag;
2423   Hwcentry *stdlist_table;
2424 #define MAX_DEFAULT_HWC_DEFS 4 // allows multiple defs to handle OS variations; extend as needed
2425   char *default_exp_p[MAX_DEFAULT_HWC_DEFS + 1]; // end of list MUST be marked with NULL
2426 } cpu_list_t;
2427
2428 /*  IMPORTANT NOTE:
2429  *
2430  *  Any default HWC string must consist of counter names separated by -TWO- commas,
2431  *  with a no trailing comma/value after the last counter name
2432  *
2433  *  Only aliased counters should be specified; non-aliased counters will
2434  *  not get the right overflow values set.
2435  *  If the string is not formatted that way, -h hi and -h lo will fail
2436  */
2437 static cpu_list_t cputabs[] = {
2438   {CPC_ULTRA1, usIlist, {NULL}}, /* bind will fail */
2439   {CPC_ULTRA2, usIlist, {NULL}}, /* bind will fail */
2440   {CPC_ULTRA3, usIIIlist, {"insts,,ecstall", 0}},
2441   {CPC_ULTRA3_PLUS, usIIIlist, {"insts,,ecstall", 0}},
2442   {CPC_ULTRA3_I, usIIIlist, {"insts,,ecstall", 0}},
2443   {CPC_ULTRA4_PLUS, usIVplist, {"insts,,ecstall", 0}},
2444   {CPC_ULTRA_T1, niagara1, {"insts", 0}},
2445   {CPC_ULTRA_T2, niagara2, {"insts,,+l2drm", 0}},
2446   {CPC_ULTRA_T2P, niagara2, {"insts,,+l2drm", 0}},
2447   {CPC_ULTRA_T3, niagara2, {"insts,,+l2drm", 0}},
2448   {CPC_SPARC_T4, sparc_t4, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}},
2449   {CPC_SPARC_M4, sparc_t5_m6, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}}, // renamed to m5
2450   {CPC_SPARC_T5, sparc_t5_m6, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}},
2451   {CPC_SPARC_M5, sparc_t5_m6, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}},
2452   {CPC_SPARC_T6, sparc_t5_m6, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}}, // no such processor
2453   {CPC_SPARC_M6, sparc_t5_m6, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}},
2454   {CPC_SPARC_M7, sparc_m7, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}}, // includes T7
2455   {CPC_SPARC_M8, sparc_m8, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}},
2456   {CPC_PENTIUM_PRO_MMX, pentiumIIlist, {"insts", 0}},
2457   {CPC_PENTIUM_PRO, pentiumIIIlist, {"insts", 0}},
2458   {CPC_PENTIUM_4, pentium4, {"insts", 0}},
2459   {CPC_PENTIUM_4_HT, pentium4, {"insts", 0}},
2460   {CPC_INTEL_CORE2, intelCore2list, {"insts,,cycles", 0}},
2461   {CPC_INTEL_NEHALEM, intelNehalemList, {"insts,,cycles,,+l2m_latency,,dtlbm_stall",
2462       "insts,,cycles,,l3m_stall,,dtlbm_stall", 0}},
2463   {CPC_INTEL_WESTMERE, intelNehalemList, {"insts,,cycles,,+l2m_latency,,dtlbm_stall",
2464       "insts,,cycles,,l3m_stall,,dtlbm_stall", 0}},
2465   {CPC_INTEL_SANDYBRIDGE, intelSandyBridgeList, {"insts,,cycles,,+l2m_latency,,dtlbm_stall",
2466       "insts,,cycles,,l3m,,dtlbm", 0}},
2467   {CPC_INTEL_IVYBRIDGE, intelSandyBridgeList, {"insts,,cycles,,+l2m_latency,,dtlbm_stall",
2468       "insts,,cycles,,l3m,,dtlbm", 0}},
2469   {CPC_INTEL_HASWELL, intelHaswellList, {"insts,,cycles,,+l2m_latency,,dtlbm_stall",
2470       "insts,,cycles,,l3m,,dtlbm", 0}},
2471   {CPC_INTEL_BROADWELL, intelBroadwellList, {"insts,,cycles,,+l2m_latency,,dtlbm",
2472       "insts,,cycles,,l3m,,dtlbm", 0}},
2473   {CPC_INTEL_SKYLAKE, intelSkylakeList, {"insts,,cycles,,+l2m_latency,,dtlbm_stall",
2474       "insts,,cycles,,l2m_stall,,dtlbm_stall", 0}},
2475   {CPC_INTEL_UNKNOWN, intelLinuxUnknown, {"cycles,,insts,,llm",
2476       "user_time,,system_time,,cycles,,insts,,llm", 0}},
2477   {CPC_INTEL_ATOM, intelAtomList, {"insts", 0}},
2478   {CPC_AMD_K8C, amd_opteron_10h_11h, {"insts,,cycles,,l2dm,,l2dtlbm", 0}},
2479   {CPC_AMD_FAM_10H, amd_opteron_10h_11h, {"insts,,cycles,,l2dm,,l2dtlbm", 0}},
2480   {CPC_AMD_FAM_11H, amd_opteron_10h_11h, {"insts,,cycles,,l2dm,,l2dtlbm", 0}},
2481   {CPC_AMD_FAM_15H, amd_15h, {"insts,,cycles", 0}},
2482   {CPC_SPARC64_V, usfuji_V_list, {"insts,,cycles", 0}},
2483   {CPC_SPARC64_VI, usfuji_VI_VII_list, {"insts,,cycles,,dcstall", 0}},
2484   {CPC_SPARC64_VII, usfuji_VI_VII_list, {"insts,,cycles,,dcstall", 0}},
2485   {CPC_SPARC64_X, usfuji_X_list, {"insts,,cycles,,dcstall", 0}},
2486   {CPC_SPARC64_XII, usfuji_XII_list, {"insts,,cycles,,dcstall", 0}},
2487   {CPC_KPROF, kproflist, {NULL}}, // OBSOLETE (To support 12.3 and earlier, TBR)
2488   {ARM_CPU_IMP_APM, armlist, {"insts,,cycles", 0}},
2489   {0, unknownlist, {NULL}} /* processor is unknown, but experiment is allowed */
2490 };
2491
2492 /*---------------------------------------------------------------------------*/
2493 /* state variables */
2494 static int initialized;
2495 static int signals_disabled;
2496
2497 // Simple array list
2498 typedef struct
2499 {
2500   void** array;     // array of ptrs, last item set to null
2501   int sz;           // num live elements in array
2502   int max;          // array allocation size
2503 } ptr_list;
2504
2505 static void
2506 ptr_list_init (ptr_list *lst)
2507 {
2508   lst->sz = 0;
2509   lst->max = 0;
2510   lst->array = 0;
2511 }
2512
2513 static void
2514 ptr_list_add (ptr_list *lst, char* ptr)
2515 { // ptr must be freeable
2516   if (lst->sz >= lst->max - 1)
2517     {
2518       void * * new;
2519       int newmax = lst->max ? lst->max * 2 : 16;
2520       new = (void**) realloc (lst->array, newmax * sizeof (void*));
2521       if (!new) return; // failed, discard add
2522       lst->max = newmax;
2523       lst->array = new;
2524     }
2525   lst->array[lst->sz++] = ptr;
2526   lst->array[lst->sz] = NULL; // mark new end-of-list
2527 }
2528
2529 static void
2530 ptr_list_free (ptr_list *lst)
2531 { // includes shallow free of all elements
2532   if (lst->array)
2533     {
2534       for (int ii = 0; lst->array[ii]; ii++)
2535         free (lst->array[ii]);
2536       free (lst->array);
2537     }
2538   lst->sz = 0;
2539   lst->max = 0;
2540   lst->array = 0;
2541 }
2542
2543 // Capabilities of this machine (initialized by setup_cpc())
2544 static int cpcx_cpuver = CPUVER_UNDEFINED;
2545 static uint_t cpcx_npics;
2546 static const char *cpcx_cciname;
2547 static const char *cpcx_docref;
2548 static uint64_t cpcx_support_bitmask;
2549
2550 // cpcx_*[0]: collect lists
2551 // cpcx_*[1]: er_kernel lists
2552 // Each cpcx_*[] list is an array of ptrs with null ptr marking end of list
2553 static char **cpcx_attrs[2];
2554
2555 static Hwcentry **cpcx_std[2];
2556 static Hwcentry **cpcx_raw[2];
2557 static Hwcentry **cpcx_hidden[2];
2558
2559 static uint_t cpcx_max_concurrent[2];
2560 static char *cpcx_default_hwcs[2];
2561 static char *cpcx_orig_default_hwcs[2];
2562 static int cpcx_has_precise[2];
2563
2564 #define VALID_FOR_KERNEL(forKernel) ((forKernel)>=0 && (forKernel)<=1)
2565 #define IS_KERNEL(forKernel) ((forKernel)==1)
2566
2567 // used to build lists:
2568 static ptr_list unfiltered_attrs;
2569 static ptr_list unfiltered_raw;
2570
2571 /*---------------------------------------------------------------------------*/
2572 /* misc internal utilities */
2573
2574 /* compare 2 strings to either \0 or <termchar> */
2575 #define IS_EOL(currchar, termchar) ((currchar)==(termchar) || (currchar)==0)
2576
2577 static int
2578 is_same (const char * regname, const char * int_name, char termchar)
2579 {
2580   do
2581     {
2582       char a = *regname;
2583       char b = *int_name;
2584       if (IS_EOL (a, termchar))
2585         {
2586           if (IS_EOL (b, termchar))
2587             return 1; /* strings are the same up to terminating char */
2588           else
2589             break; /* strings differ */
2590         }
2591       if (a != b)
2592         break;      /* strings differ */
2593       regname++;
2594       int_name++;
2595     }
2596   while (1);
2597   return 0;
2598 }
2599
2600 static int
2601 is_numeric (const char *name, uint64_t *pval)
2602 {
2603   char *endptr;
2604   uint64_t val = strtoull (name, &endptr, 0);
2605   if (!*name || *endptr)
2606     return 0; /* name does not specify a numeric value */
2607   if (pval)
2608     *pval = val;
2609   return 1;
2610 }
2611
2612 static int
2613 is_visible_alias (Hwcentry* pctr)
2614 {
2615   if (!pctr)
2616     return 0;
2617   if (pctr->name && pctr->int_name && pctr->metric)
2618     return 1;
2619   return 0;
2620 }
2621
2622 static int
2623 is_hidden_alias (Hwcentry* pctr)
2624 {
2625   if (!pctr)
2626     return 0;
2627   if (pctr->name && pctr->int_name && pctr->metric == NULL)
2628     return 1;
2629   return 0;
2630 }
2631
2632 static int
2633 is_numeric_alias (Hwcentry* pctr)
2634 {
2635   int is_numeric_alias = 0;
2636   regno_t regno;
2637   char *nameOnly = NULL;
2638   hwcfuncs_parse_ctr (pctr->int_name, NULL, &nameOnly, NULL, NULL, &regno);
2639   if (is_numeric (nameOnly, NULL))
2640     is_numeric_alias = 1;
2641   free (nameOnly);
2642   return is_numeric_alias;
2643 }
2644
2645 /* print list of register to a buffer */
2646 /*
2647  *  style      e x a m p l e s
2648  *    0        NONE    2       {0|1|2|3}
2649  *    1        NONE    2       : 0, 1, 2, or 3
2650  *    2                        0 1 2 3     6
2651  */
2652 static char *
2653 get_regnolist (char *buf, size_t sz, const regno_t *reg_list, int style)
2654 {
2655   if (!buf || !sz)
2656     return "INTERNAL ERROR";
2657   buf[0] = 0;
2658   if (style == 2)
2659     {
2660       int ii;
2661       // width should be consistent with that in format_columns()
2662       // the format will accommodate cpcx_npics regs
2663       if (cpcx_npics < 1)
2664         return "INTERNAL ERROR";
2665       // clear out the buffer
2666       for (ii = 0; ii < sz; ii++)
2667         buf[ii] = '_';
2668       if (cpcx_npics <= 9)
2669         {
2670           // one char per reg, plus terminating null char
2671           if (cpcx_npics + 1 > sz)
2672             return "INTERNAL ERROR";
2673           buf[cpcx_npics] = '\0';
2674
2675           // fill buf with regnos
2676           for (ii = 0; ii < MAX_PICS; ii++)
2677             {
2678               regno_t regno = reg_list[ii];
2679               if (REG_LIST_EOL (regno))
2680                 break;
2681               if (regno < 0 || regno >= cpcx_npics)
2682                 return "INTERNAL ERROR";
2683               buf[regno] = '0' + regno;
2684             }
2685         }
2686       else
2687         {
2688           /* space between regs, which may be 1 or 2 digits each
2689            *   1 char  for reg 0
2690            *   2 chars for regs 1-9 each
2691            *   3 chars for regs 10- each
2692            *   1 char  for terminating null char
2693            */
2694           int nchars = 17 + 3 * (cpcx_npics - 9);
2695           if (nchars > sz)
2696             return "INTERNAL ERROR";
2697           buf[nchars - 1] = '\0';
2698
2699           // fill buf with regnos
2700           for (ii = 0; ii < MAX_PICS; ii++)
2701             {
2702               regno_t regno = reg_list[ii];
2703               if (REG_LIST_EOL (regno))
2704                 break;
2705               if (regno <= 9)
2706                 buf[2 * regno ] = '0' + regno;
2707               else
2708                 {
2709                   buf[3 * (regno - 9) + 17] = '0' + (regno / 10);
2710                   buf[3 * (regno - 9) + 18] = '0' + (regno % 10);
2711                 }
2712             }
2713         }
2714       return buf;
2715     }
2716   if (REG_LIST_IS_EMPTY (reg_list))
2717     {
2718       snprintf (buf, sz, GTXT ("NONE"));
2719       return buf;
2720     }
2721   else if (REG_LIST_EOL (reg_list[1]))
2722     {
2723       /* 1 item in list */
2724       snprintf (buf, sz, "%d", reg_list[0]);
2725       return buf;
2726     }
2727   else
2728     {
2729       /* 2 more items in list */
2730       int ii, num_regs;
2731       for (ii = 0; ii < MAX_PICS; ii++)
2732         {
2733           regno_t regno = reg_list[ii];
2734           if (REG_LIST_EOL (regno))
2735             break;
2736         }
2737       num_regs = ii;
2738       buf[0] = 0;
2739       for (ii = 0; ii < num_regs; ii++)
2740         {
2741           regno_t regno = reg_list[ii];
2742           if (style == 0)
2743             snprintf (buf + strlen (buf), sz - strlen (buf),
2744                       "%c%d", ii ? '|' : '{', regno);
2745           else
2746             {
2747               if (num_regs == 2)
2748                 snprintf (buf + strlen (buf), sz - strlen (buf),
2749                           "%d%s", regno, !ii ? " or " : "");
2750               else
2751                 {
2752                   /* 3 or more items in list */
2753                   if (ii < num_regs - 2)
2754                     snprintf (buf + strlen (buf), sz - strlen (buf),
2755                               "%d, ", regno);
2756                   else if (ii == num_regs - 2)
2757                     snprintf (buf + strlen (buf), sz - strlen (buf),
2758                               "%d, or ", regno);
2759                   else
2760                     snprintf (buf + strlen (buf), sz - strlen (buf),
2761                               "%d", regno);
2762                 }
2763             }
2764         }
2765       if (style == 0)
2766         snprintf (buf + strlen (buf), sz - strlen (buf), "}");
2767     }
2768   return buf;
2769 }
2770
2771 #if !HWC_DEBUG
2772 #define hwcentry_print(lvl,x1,x2)
2773 #else
2774
2775 /* print a Hwcentry */
2776 static void
2777 hwcentry_print (int lvl, const char * header, const Hwcentry *pentry)
2778 {
2779   char buf[1024];
2780   Tprintf (lvl, "%s '%s', '%s', %d, '%s', %d, %d, %d, %d, %d, %d, /",
2781            header,
2782            pentry->name ? pentry->name : "NULL",
2783            pentry->int_name ? pentry->int_name : "NULL",
2784            pentry->reg_num,
2785            pentry->metric ? pentry->metric : "NULL",
2786            pentry->lval, /* low-resolution/long run */
2787            pentry->val, /* normal */
2788            pentry->hval, /* high-resolution/short run */
2789            pentry->timecvt,
2790            pentry->memop, /* type of instruction that can trigger */
2791            pentry->sort_order);
2792   get_regnolist (buf, sizeof (buf), pentry->reg_list, 0);
2793   Tprintf (lvl, "%s\n", buf);
2794 }
2795 #endif
2796
2797 /* add <regno> to a Hwcentry's list */
2798 static void
2799 regno_add (Hwcentry * pctr, regno_t regno)
2800 {
2801   int jj;
2802   regno_t *reg_list;
2803   if (!pctr)
2804     {
2805       Tprintf (0, "hwctable: regno_add(): ERROR: pctr==NULL\n");
2806       return;
2807     }
2808   reg_list = pctr->reg_list;
2809   if (!reg_list)
2810     {
2811       /* create list */
2812       reg_list = (regno_t*) malloc (sizeof (regno_t*) * MAX_PICS);
2813       if (!reg_list)
2814         {
2815           hwcentry_print (DBG_LT0, "hwctable: regno_add: ERROR:"
2816                           " Out of memory: ", pctr);
2817           return;
2818         }
2819       /* initialize list */
2820       for (jj = 0; jj < MAX_PICS; jj++)
2821         reg_list[jj] = REGNO_ANY;
2822       pctr->reg_list = reg_list;
2823     }
2824   if (regno == REGNO_ANY)
2825     {
2826       /* add all counters up to cpcx_npics */
2827       for (jj = 0; jj < MAX_PICS && jj < cpcx_npics; jj++)
2828         reg_list[jj] = jj;
2829     }
2830   else
2831     {
2832       /* add <regno> to list of registers */
2833       for (jj = 0; jj < MAX_PICS; jj++)
2834         {
2835           if (reg_list[jj] == regno)
2836             {
2837               hwcentry_print (DBG_LT0, "hwctable: regno_add: WARNING: "
2838                               "Duplicate regno: ", pctr);
2839               break;
2840             }
2841           if (reg_list[jj] == REGNO_ANY)
2842             {
2843               reg_list[jj] = regno;
2844               break;
2845             }
2846         }
2847     }
2848   if (jj == MAX_PICS)
2849     hwcentry_print (DBG_LT0, "hwctable: regno_add: WARNING:"
2850                     " regno list is full:", pctr);
2851 }
2852
2853 /*---------------------------------------------------------------------------*/
2854 /* utilities for rawlist (list of raw counters with reglist[] filled in) */
2855
2856 /* search the 'raw' list of counters for <name> */
2857 static Hwcentry *
2858 ptrarray_find_by_name (Hwcentry** array, const char * name)
2859 {
2860   if (name == NULL)
2861     return NULL;
2862   Tprintf (DBG_LT3, "hwctable: array_find_by_name(%s):\n", name);
2863   for (int ii = 0; array && array[ii]; ii++)
2864     if (strcmp (array[ii]->name, name) == 0)
2865       return array[ii];
2866   return NULL; /* not found */
2867 }
2868
2869 /* add Hwcentry to the 'raw' list of counters */
2870 static Hwcentry *
2871 alloc_shallow_copy (const Hwcentry *pctr)
2872 {
2873   Hwcentry *node = (Hwcentry *) malloc (sizeof (Hwcentry));
2874   if (!node)
2875     return NULL; // fail
2876   *node = *pctr; /* shallow copy! */
2877   if (pctr->name)
2878     node->name = strdup (pctr->name);
2879   return node;
2880 }
2881
2882 /* add Hwcentry to the 'raw' list of counters */
2883 static Hwcentry *
2884 list_append_shallow_copy (ptr_list *list, const Hwcentry *pctr)
2885 {
2886   Hwcentry *node = alloc_shallow_copy (pctr);
2887   if (!node)
2888     return NULL; // fail
2889   ptr_list_add (list, (void*) node);
2890   return node;
2891 }
2892
2893 static Hwcentry *
2894 list_add (ptr_list *list, uint_t regno, const char *name)
2895 {
2896   Hwcentry *praw;
2897   praw = ptrarray_find_by_name ((Hwcentry**) list->array, name);
2898   if (!praw)
2899     {
2900       Hwcentry tmpctr = empty_ctr;
2901       tmpctr.name = (char *) name;
2902       praw = list_append_shallow_copy (list, &tmpctr);
2903     }
2904   if (praw)
2905     regno_add (praw, regno);
2906   return praw;
2907 }
2908
2909 /*---------------------------------------------------------------------------*/
2910 /* utilities for stdlist (table of aliased, hidden, & convenience, ctrs) */
2911
2912 /* find top level definition for <cpuid> */
2913 static cpu_list_t*
2914 cputabs_find_entry (int cpuid)
2915 {
2916   int i;
2917   /* now search for the appropriate table */
2918   for (i = 0;; i++)
2919     {
2920       if (cputabs[i].cputag == 0)
2921         break;
2922       if (cpuid == cputabs[i].cputag)
2923         return &cputabs[i];
2924     }
2925   Tprintf (0, "hwctable: cputabs_find_entry: WARNING: "
2926            "cpu_id = %d not defined.  No 'standard' counters are available\n",
2927            cpuid);
2928   return &cputabs[i];
2929 }
2930
2931 /* find Hwcentry table for <cpuid> */
2932 static Hwcentry*
2933 stdlist_get_table (int cpuid)
2934 {
2935   cpu_list_t* tmp = cputabs_find_entry (cpuid);
2936   if (tmp)
2937     return tmp->stdlist_table;
2938   return NULL;
2939 }
2940
2941 /* search the 'standard' list of counters for <name>,<regno> */
2942 /* note: <regno>=REGNO_ANY is a wildcard that matches any value. */
2943
2944 /* note: int_name==NULL is a wildcard */
2945 static const Hwcentry *
2946 ptrarray_find (const Hwcentry **array, const char *name, const char *int_name,
2947                int check_regno, regno_t regno)
2948 {
2949   const Hwcentry *pctr;
2950   if (!array)
2951     return NULL;
2952   for (int ii = 0; array[ii]; ii++)
2953     {
2954       pctr = array[ii];
2955       if (strcmp (pctr->name, name))
2956         continue;
2957       if (int_name && int_name[0] != 0 && pctr->int_name)
2958         {
2959           if (NULL == strstr (int_name, pctr->int_name))
2960             continue;
2961         }
2962       if (!check_regno)
2963         return pctr;
2964       else
2965         {
2966           /* duplicates aliases are allowed in table because of 6759307 */
2967           if (REG_LIST_IS_EMPTY (pctr->reg_list))
2968             {
2969               /* skip aliases that don't have a valid list of registers */
2970               hwcentry_print (1, "hwctable: stdlist_find_by_name:"
2971                               " WARNING: alias found, but event not supported by HW:",
2972                               pctr);
2973               continue;
2974             }
2975           if (!regno_is_valid (pctr, regno))
2976             {
2977               hwcentry_print (1, "hwctable: stdlist_find_by_name():"
2978                               " WARNING: alias found, but regno doesn't match:",
2979                               pctr);
2980               continue;
2981             }
2982           return pctr;
2983         }
2984     }
2985   return NULL;
2986 }
2987
2988 /* search the 'standard' list of counters for <name>,<regno> */
2989
2990 /* note: <regno>=REGNO_ANY is a wildcard that matches any value. */
2991 static const Hwcentry *
2992 static_table_find (const Hwcentry *table, const char *name, const char *int_name,
2993                    int check_regno, regno_t regno)
2994 {
2995   int sz;
2996   for (sz = 0; table && table[sz].name; sz++)
2997     ;
2998   if (!sz)
2999     return NULL;
3000   const Hwcentry ** list = calloc (sz + 1, sizeof (void*));
3001   if (!list)
3002     return NULL;
3003   for (int ii = 0; ii < sz; ii++)
3004     list[ii] = &table[ii];
3005   list[sz] = NULL;
3006   const Hwcentry *pctr = ptrarray_find (list, name, int_name, check_regno, regno);
3007   free (list);
3008   return pctr;
3009 }
3010
3011 #if !HWC_DEBUG
3012 #define stdlist_print(dbg_lvl,table)
3013 #else
3014
3015 /* print all Hwcentries in standard table.  Check for weird stuff */
3016 static void
3017 stdlist_print (int dbg_lvl, const Hwcentry* table)
3018 {
3019   const Hwcentry *pctr;
3020   if (!table)
3021     {
3022       Tprintf (0, "hwctable: stdlist_print: ERROR: "
3023                "table is invalid.\n");
3024       return;
3025     }
3026   for (pctr = table; pctr->name; pctr++)
3027     {
3028       int ii;
3029       hwcentry_print (dbg_lvl, "hwctable: stdlist: ", pctr);
3030       if (REG_LIST_IS_EMPTY (pctr->reg_list))
3031         {
3032           if (pctr->int_name || !pctr->metric)
3033             hwcentry_print (DBG_LT1, "hwctable: stdlist_print: WARNING: "
3034                             "no hardware event found for table entry", pctr);
3035           continue;
3036         }
3037       /* check if incorrect reg_num used in table */
3038       if (!regno_is_valid (pctr, pctr->reg_num))
3039         {
3040           hwcentry_print (DBG_LT0, "hwctable: stdlist_print: ERROR: "
3041                           "reg_num is not in table. ", pctr);
3042           continue;
3043         }
3044       for (ii = 0; ii < MAX_PICS; ii++)
3045         {
3046           regno_t regno = pctr->reg_list[ii];
3047           if (REG_LIST_EOL (regno))
3048             break;
3049         }
3050       if (ii > 1 && pctr->reg_num != REGNO_ANY)
3051         {
3052           /* several regnos were valid, but only one can be specified */
3053           if (pctr->metric || !pctr->int_name)
3054             {
3055               /* pctr is standard or a raw definition */
3056               /* (pctr is not an alias like cycles0) */
3057               hwcentry_print (DBG_LT0, "hwctable: stdlist_print: ERROR: "
3058                               "regno in table should have been REGNO_ANY. ",
3059                               pctr);
3060             }
3061         }
3062     }
3063 }
3064 #endif
3065
3066 /*---------------------------------------------------------------------------*/
3067 /* utilities for init */
3068
3069 /* try to bind counters to hw.  Return 0 on success, nonzero otherwise */
3070 static int
3071 test_hwcs (const Hwcentry* entries[], unsigned numctrs)
3072 {
3073   int rc = -1;
3074   hwc_event_t sample;
3075   int created = 0;
3076   hwcdrv_api_t *hwcdrv = get_hwcdrv ();
3077   Tprintf (DBG_LT2, "hwctable: test_hwcs()...\n");
3078   rc = hwcfuncs_bind_hwcentry (entries, numctrs);
3079   if (rc)
3080     {
3081       Tprintf (0, "hwctable: WARNING: test "
3082                "counters could not be created\n");
3083       goto end_test_hwcs;
3084     }
3085   created = 1;
3086   if (!signals_disabled)
3087     {
3088       (void) signal (HWCFUNCS_SIGNAL, SIG_IGN);
3089       signals_disabled = 1;
3090     }
3091   rc = hwcdrv->hwcdrv_start ();
3092   if (rc)
3093     {
3094       Tprintf (0, "hwctable: WARNING: test "
3095                "counters could not be started\n");
3096       goto end_test_hwcs;
3097     }
3098   rc = hwcdrv->hwcdrv_read_events (&sample, NULL);
3099   if (rc)
3100     Tprintf (0, "hwctable: WARNING: test sample failed\n");
3101   rc = 0;
3102 #if HWC_DEBUG
3103   {
3104     unsigned ii;
3105     Tprintf (DBG_LT1, "hwctable: test_hwcs(");
3106     for (ii = 0; ii < numctrs; ii++)
3107       Tprintf (DBG_LT1, "%s%s", ii ? "," : "", entries[ii]->name);
3108     Tprintf (DBG_LT1, ") PASS\n");
3109   }
3110 #endif
3111
3112 end_test_hwcs:
3113   if (created && hwcdrv->hwcdrv_free_counters ())
3114     Tprintf (0, "hwctable: WARNING: test counters could not be freed\n");
3115   return rc;
3116 }
3117
3118 #if !HWC_DEBUG
3119 #define check_tables()
3120 #else
3121
3122 /* check for typos in tables */
3123 static void
3124 check_tables ()
3125 {
3126   int i;
3127   /* now search the known table of counters */
3128   for (i = 0;; i++)
3129     {
3130       Hwcentry * pentry;
3131       int cputag = cputabs[i].cputag;
3132       if (cputag == 0)
3133         break;
3134       if (cputag == CPC_KPROF)
3135         continue;
3136       pentry = cputabs[i].stdlist_table;
3137       for (; pentry; pentry++)
3138         {
3139           if (!pentry->name)
3140             break;
3141           if (!pentry->int_name)
3142             {/* internal, only to supply ABST and timecvt */
3143               if (pentry->metric)
3144                 Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:"
3145                          " internal && metric @%d, %s\n", cputag, pentry->name);
3146               if (pentry->reg_num != REGNO_ANY)
3147                 Tprintf (DBG_LT1, "hwctable: check_tables: WARNING:"
3148                          " internal && reg_num!=REGNO_ANY @%d, %s\n",
3149                          cputag, pentry->name);
3150               if (pentry->val != PRELOAD_DEF
3151                   && pentry->memop != ABST_EXACT_PEBS_PLUS1)
3152                 Tprintf (DBG_LT2, "hwctable: check_tables: INFO:"
3153                          " internal && custom val=%d @%d, %s\n",
3154                          pentry->val, cputag, pentry->name);
3155 #if 0
3156               if (!pentry->timecvt && pentry->memop == ABST_NONE)
3157                 Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:"
3158                          " internal && not special! @%d, %s\n",
3159                          cputag, pentry->name);
3160 #endif
3161             }
3162           if (pentry->metric)
3163             { /* aliased */
3164               if (!pentry->int_name)
3165                 Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:"
3166                          " aliased && !int_name @%d, %s\n", cputag, pentry->name);
3167 #if 0
3168               else if (!strcmp (pentry->name, pentry->int_name))
3169                 Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:"
3170                          " name==int_name @%d, %s\n",
3171                          cputag, pentry->name);
3172 #endif
3173               if (pentry->reg_num != REGNO_ANY && pentry->reg_num != REGNO_INVALID)
3174                 Tprintf (DBG_LT1, "hwctable: check_tables: INFO:"
3175                          " aliased && custom reg_num==%d @%d, %s\n",
3176                          pentry->reg_num, cputag, pentry->name);
3177               if (pentry->reg_num == REGNO_INVALID)
3178                 Tprintf (DBG_LT2, "hwctable: check_tables: INFO:"
3179                          " aliased && reg_num==REGNO_INVALID @%d, %s\n",
3180                          cputag, pentry->name);
3181             }
3182           if (pentry->int_name && !pentry->metric)
3183             { /* convenience */
3184               if (!strcmp (pentry->name, pentry->int_name))
3185                   Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:"
3186                            " convenience && name==int_name @%d, %s\n",
3187                            cputag, pentry->name);
3188               if (pentry->reg_num == REGNO_ANY)
3189                   Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:"
3190                            " convenience && reg_num==REGNO_ANY @%d, %s\n",
3191                            cputag, pentry->name);
3192             }
3193         }
3194     }
3195 }
3196 #endif
3197
3198 static int try_a_counter ();
3199 static void hwc_process_raw_ctrs (int forKernel, Hwcentry ***pstd_out,
3200                                   Hwcentry ***praw_out, Hwcentry ***phidden_out,
3201                                   Hwcentry**static_tables,
3202                                   Hwcentry **raw_unfiltered_in);
3203
3204 /* internal call to initialize libs, ctr tables */
3205 static void
3206 setup_cpc_general (int skip_hwc_test)
3207 {
3208   const cpu_list_t* cputabs_entry;
3209   int rc = -1;
3210   Tprintf (DBG_LT2, "hwctable: setup_cpc()... \n");
3211   if (initialized)
3212     {
3213       Tprintf (0, "hwctable: WARNING: setup_cpc() has already been called\n");
3214       return;
3215     }
3216   initialized = 1;
3217   cpcx_cpuver = CPUVER_UNDEFINED;
3218   cpcx_cciname = NULL;
3219   cpcx_npics = 0;
3220   cpcx_docref = NULL;
3221   cpcx_support_bitmask = 0;
3222   for (int kk = 0; kk < 2; kk++)
3223     { // collect-0 and kernel-1
3224       cpcx_attrs[kk] = NULL;
3225       cpcx_std[kk] = NULL;
3226       cpcx_raw[kk] = NULL;
3227       cpcx_hidden[kk] = NULL;
3228       cpcx_max_concurrent[kk] = 0;
3229       cpcx_default_hwcs[kk] = NULL;
3230       cpcx_orig_default_hwcs[kk] = NULL;
3231       cpcx_has_precise[kk] = 0;
3232     }
3233   check_tables ();
3234   hwcdrv_api_t *hwcdrv = get_hwcdrv ();
3235   if (hwcdrv->hwcdrv_init_status)
3236     {
3237       Tprintf (0, "WARNING: setup_cpc_general() failed. init_status=%d \n",
3238                hwcdrv->hwcdrv_init_status);
3239       goto setup_cpc_wrapup;
3240     }
3241   hwcdrv->hwcdrv_get_info (&cpcx_cpuver, &cpcx_cciname, &cpcx_npics,
3242                            &cpcx_docref, &cpcx_support_bitmask);
3243
3244 #ifdef DISALLOW_USI_USII_6357446
3245   if (cpcx_cpuver == CPC_ULTRA1 || cpcx_cpuver == CPC_ULTRA2)
3246     {
3247       Tprintf (0, "hwctable: WARNING: setup_cpc(): cpu=%d"
3248                " US-I/US-II cannot provide profile interrupts\n", cpcx_cpuver);
3249       /* profiling interrupts don't work on US-I, US-II */
3250       hwcfuncs_int_logerr (GTXT ("UltraSPARC I and II cannot provide overflow interrupts\n"));
3251       goto setup_cpc_wrapup;
3252     }
3253 #endif
3254
3255 #ifdef DISALLOW_PENTIUM_PRO_MMX_7007575
3256   if (cpcx_cpuver == CPC_PENTIUM_PRO_MMX)
3257     {
3258       Tprintf (0, "hwctable: WARNING: setup_cpc(): cpu=%d"
3259                " `Pentium Pro with MMX, Pentium II' is not supported\n", cpcx_cpuver);
3260       hwcfuncs_int_logerr (GTXT ("libcpc cannot identify processor type\n"));
3261       goto setup_cpc_wrapup;
3262     }
3263 #endif
3264
3265   /* now search the known table of counters */
3266   cputabs_entry = cputabs_find_entry (cpcx_cpuver);
3267   if (cputabs_entry == NULL)
3268     {
3269       Tprintf (0, "hwctable: WARNING: setup_cpc(): cpu=%d"
3270                " could not be found in the tables\n", cpcx_cpuver);
3271       /* strange, should have at least selected "unknownlist" */
3272       hwcfuncs_int_logerr (GTXT ("Analyzer CPU table could not be found\n"));
3273       goto setup_cpc_wrapup;
3274     }
3275
3276   Hwcentry * valid_cpu_tables[2]; // [0]:static table of counters, [1]:static table of generic counters
3277   valid_cpu_tables[0] = cputabs_entry->stdlist_table;
3278   if (valid_cpu_tables[0] == NULL)
3279     {
3280       Tprintf (0, "hwctable: WARNING: setup_cpc(): "
3281                " valid_cpu_tables was NULL??\n");
3282       /* strange, someone put a NULL in the lookup table? */
3283       hwcfuncs_int_logerr (GTXT ("Analyzer CPU table is invalid\n"));
3284       goto setup_cpc_wrapup;
3285     }
3286   valid_cpu_tables[1] = papi_generic_list;
3287   Tprintf (DBG_LT2, "hwctable: setup_cpc(): getting descriptions \n");
3288   // populate cpcx_raw and cpcx_attr
3289   hwcdrv->hwcdrv_get_descriptions (hwc_cb, attrs_cb);
3290   for (int kk = 0; kk < 2; kk++)
3291     { // collect and er_kernel
3292       hwc_process_raw_ctrs (kk, &cpcx_std[kk], &cpcx_raw[kk], &cpcx_hidden[kk],
3293                             valid_cpu_tables, (Hwcentry**) unfiltered_raw.array);
3294       cpcx_has_precise[kk] = 0;
3295       for (int rr = 0; cpcx_raw[kk] && cpcx_raw[kk][rr]; rr++)
3296         {
3297           int memop = cpcx_raw[kk][rr]->memop;
3298           if (ABST_MEMSPACE_ENABLED (memop))
3299             {
3300               cpcx_has_precise[kk] = 1;
3301               break;
3302             }
3303         }
3304       cpcx_attrs[kk] = (char**) unfiltered_attrs.array;
3305       cpcx_max_concurrent[kk] = cpcx_npics;
3306     }
3307 #if 1 // 22897042 - DTrace cpc provider does not support profiling on multiple ctrs on some systems
3308   if ((cpcx_support_bitmask & HWCFUNCS_SUPPORT_OVERFLOW_CTR_ID) != HWCFUNCS_SUPPORT_OVERFLOW_CTR_ID)
3309     {
3310       // kernel profiling only supports one counter if overflowing counter can't be identified
3311       cpcx_max_concurrent[1] = cpcx_npics ? 1 : 0;
3312     }
3313 #endif
3314
3315   /* --- quick test of the cpc interface --- */
3316   if (skip_hwc_test)
3317     rc = 0;
3318   else
3319     rc = try_a_counter (0);
3320
3321   /* initialize the default counter string definition */
3322   for (int kk = 0; kk < 2; kk++)
3323     {
3324       char * default_exp = 0;
3325       int jj;
3326       for (jj = 0; (default_exp = cputabs_entry->default_exp_p[jj]); jj++)
3327         {
3328           int rc = hwc_lookup (kk, 0, default_exp, NULL, 0, NULL, NULL);
3329           if (rc > 0)
3330             break;
3331         }
3332       if (!default_exp)
3333         {
3334           char * fallback[3] = {NTXT ("insts,,cycles,,l3m"), NTXT ("insts,,cycles"), NTXT ("insts")};
3335           for (int ff = 0; ff < 3; ff++)
3336             {
3337               int rc = hwc_lookup (kk, 0, fallback[ff], NULL, 0, NULL, NULL);
3338               if (rc > 0)
3339                 {
3340                   default_exp = strdup (fallback[ff]);
3341                   break;
3342                 }
3343             }
3344         }
3345       cpcx_default_hwcs[kk] = default_exp;
3346       cpcx_orig_default_hwcs[kk] = default_exp;
3347     }
3348
3349 setup_cpc_wrapup:
3350   if (rc)
3351     {
3352       cpcx_npics = 0;
3353       /*
3354               ptr_list_free(&tmp_raw); // free stuff... YXXX
3355               ptr_list_free(&unfiltered_attrs);
3356        */
3357     }
3358   return;
3359 }
3360
3361 static void
3362 setup_cpcx ()
3363 {
3364   if (initialized)
3365     return;
3366   setup_cpc_general (0); // set up and include a hwc test run
3367 }
3368
3369 static void
3370 setup_cpc_skip_hwctest ()
3371 {
3372   if (initialized)
3373     return;
3374   setup_cpc_general (1); // set up but skip hwc test run
3375 }
3376
3377 static int
3378 try_a_counter (int forKernel)
3379 {
3380   if (!VALID_FOR_KERNEL (forKernel))
3381     return -1;
3382   int rc = -1;
3383   const Hwcentry * testevent;
3384   if (cpcx_std[forKernel] == NULL)
3385     {
3386       Tprintf (0, "hwctable: WARNING: cpcx_std not initialized");
3387       return 0; /* consider this an automatic PASS */
3388     }
3389   /* look for a valid table entry, only try valid_cpu_tables[0] */
3390   {
3391     testevent = cpcx_std[forKernel][0];
3392     if (!testevent || !testevent->name)
3393       {
3394         Tprintf (0, "hwctable: WARNING: no test metric"
3395                  " available to verify counters\n");
3396         return 0; /* consider this an automatic PASS */
3397       }
3398     if (REG_LIST_IS_EMPTY (testevent->reg_list))
3399       return 0; // weird
3400   }
3401   Hwcentry tmp_testevent;
3402   tmp_testevent = *testevent; /* shallow copy */
3403   if (tmp_testevent.int_name == NULL)
3404     {
3405       /* counter is defined in 'hidden' section of table, supply int_name */
3406       tmp_testevent.int_name = strdup (tmp_testevent.name);
3407     }
3408   Hwcentry * test_array[1] = {&tmp_testevent};
3409   rc = hwcfuncs_assign_regnos (test_array, 1); /* may modify test_array */
3410   if (rc)
3411     return rc;
3412   rc = test_hwcs ((const Hwcentry**) test_array, 1);
3413   if (rc == HWCFUNCS_ERROR_UNAVAIL)
3414     {
3415       // consider this a pass (allow HWC table to be printed)
3416       Tprintf (0, "hwctable: WARNING: "
3417                "cpc_bind_event() shows counters busy; allow to continue\n");
3418       return 0;
3419     }
3420   else if (rc)
3421     {
3422       // failed to start for some other reason
3423       Tprintf (0, "hwctable: WARNING: "
3424                "test of counter '%s' failed\n",
3425                testevent->name);
3426       return rc;
3427     }
3428   return 0;
3429 }
3430
3431 void
3432 hwc_update_val (Hwcentry *hwc)
3433 {
3434   if (hwc->ref_val == 0)
3435     hwc->ref_val = hwc->val; // save original reference
3436   int64_t newVal;
3437   hrtime_t min_time_nsec = hwc->min_time;
3438   if (min_time_nsec == HWCTIME_TBD)
3439     min_time_nsec = hwc->min_time_default;
3440   switch (min_time_nsec)
3441     {
3442     case 0: // disable time-based intervals
3443       // do not modify val
3444       return;
3445     case HWCTIME_ON:
3446     case HWCTIME_TBD:
3447       newVal = HWC_VAL_ON (hwc->ref_val);
3448       break;
3449     case HWCTIME_LO:
3450       newVal = HWC_VAL_LO (hwc->ref_val);
3451       break;
3452     case HWCTIME_HI:
3453       newVal = HWC_VAL_HI (hwc->ref_val);
3454       break;
3455     default:
3456       newVal = HWC_VAL_CUSTOM (hwc->ref_val, min_time_nsec);
3457       break;
3458     }
3459 #define MAX_INT_VAL (2*1000*1000*1000 + 1000100)// yuck, limited to signed int
3460   if (newVal >= MAX_INT_VAL)
3461     newVal = MAX_INT_VAL;
3462   hwc->val = newVal;
3463 }
3464
3465 /* convert value string to value and store result in hwc->val */
3466 /* This function moved here from collctrl.cc */
3467 /*
3468  * Keep the HWCTIME_* definitions in sync with those in
3469  * collctrl.cc Coll_Ctrl::add_hwcstring().
3470  */
3471 static int
3472 set_hwcval (Hwcentry *hwc, hrtime_t global_min_time_nsec, const char *valptr)
3473 {
3474   hwc->min_time_default = global_min_time_nsec;
3475   if (hwc->val == 1)
3476     {
3477       // An interval of 1 is used for certain types of count data.
3478       // (er_bit, er_generic, er_rock ...)
3479       // Hi and Lo do not apply.
3480       /* use the default */
3481     }
3482   else if (valptr == NULL || valptr[0] == 0 || strcmp (valptr, "auto") == 0)
3483     hwc->min_time = HWCTIME_TBD;
3484   else if (strcmp (valptr, "on") == 0)
3485     hwc->min_time = HWCTIME_ON;
3486   else if (strcmp (valptr, "lo") == 0 || strcmp (valptr, "low") == 0)
3487     hwc->min_time = HWCTIME_LO;
3488   else if (strcmp (valptr, "hi") == 0 || strcmp (valptr, "high") == 0
3489            || strcmp (valptr, "h") == 0)
3490     hwc->min_time = HWCTIME_HI;
3491   else
3492     {
3493       /* the remaining string should be a number > 0 */
3494       char *endchar = NULL;
3495       long long tmp = strtoll (valptr, &endchar, 0);
3496       int value = (int) tmp;
3497       if (*endchar != 0 || tmp <= 0 || value != tmp)
3498         {
3499           // also covers errno == ERANGE
3500           Tprintf (0, "hwctable: set_hwcval(): ERROR: "
3501                    "Invalid counter value %s for counter `%s'\n",
3502                    valptr, hwc->name);
3503           return -1;
3504         }
3505       if (tmp > UINT32_MAX / 2)
3506         {
3507           /* Roch B. says that we MUST do this check for er_kernel
3508              because some platforms deliver overflow interrupts without
3509              identifying which counter overflowed.  The only way to
3510              determine which counter overflowed is to have enough
3511              margin on 32 bit counters to make sure they don't
3512              wrap.
3513            */
3514           Tprintf (0, "hwctable: set_hwcval(): ERROR: "
3515                    "Counter value %s exceeds %lu\n",
3516                    valptr, (unsigned long) UINT32_MAX / 2);
3517           return -1;
3518         }
3519       /* set the value */
3520       if (value != 0)
3521         {
3522           if (hwc->ref_val == 0)
3523             hwc->ref_val = hwc->val; // save original reference
3524           hwc->val = value;
3525           hwc->min_time = 0; // turn off auto-adjust
3526         }
3527     }
3528   hwc_update_val (hwc);
3529   return 0;
3530 }
3531
3532 static char *
3533 canonical_name (const char *counter)
3534 {
3535   char *nameOnly = NULL;
3536   char *attrs = NULL;
3537   char tmpbuf[1024];
3538   tmpbuf[0] = 0;
3539   hwcfuncs_parse_ctr (counter, NULL, &nameOnly, &attrs, NULL, NULL);
3540   snprintf (tmpbuf + strlen (tmpbuf), sizeof (tmpbuf) - strlen (tmpbuf),
3541             "%s", nameOnly);
3542   if (attrs)
3543     {
3544       hwcfuncs_attr_t cpc2_attrs[HWCFUNCS_MAX_ATTRS];
3545       void * attr_mem;
3546       unsigned nattrs;
3547       int ii, jj;
3548
3549       /* extract attributes from counter */
3550       attr_mem = hwcfuncs_parse_attrs (counter, cpc2_attrs, HWCFUNCS_MAX_ATTRS,
3551                                        &nattrs, NULL);
3552       if (!attr_mem)
3553         {
3554           snprintf (tmpbuf + strlen (tmpbuf), sizeof (tmpbuf) - strlen (tmpbuf),
3555                     "~UNKNOWN");
3556           goto canonical_attrs_wrapup;
3557         }
3558
3559       /* sort the attributes */
3560       for (ii = 0; ii < (int) nattrs - 1; ii++)
3561         {
3562           for (jj = ii + 1; jj < nattrs; jj++)
3563             {
3564               int cmp = strcmp (cpc2_attrs[ii].ca_name,
3565                                 cpc2_attrs[jj].ca_name);
3566               if (cmp > 0)
3567                 {
3568                   hwcfuncs_attr_t tmp = cpc2_attrs[jj];
3569                   cpc2_attrs[jj] = cpc2_attrs[ii];
3570                   cpc2_attrs[ii] = tmp;
3571                 }
3572             }
3573         }
3574
3575       /* print attributes in canonical format */
3576       for (ii = 0; ii < nattrs; ii++)
3577         snprintf (tmpbuf + strlen (tmpbuf), sizeof (tmpbuf) - strlen (tmpbuf),
3578                   "~%s=0x%llx", cpc2_attrs[ii].ca_name, (long long) cpc2_attrs[ii].ca_val);
3579       free (attr_mem);
3580     }
3581 canonical_attrs_wrapup:
3582   free (nameOnly);
3583   free (attrs);
3584   return strdup (tmpbuf);
3585 }
3586
3587 /* process counter and value strings - put results in <*pret_ctr> */
3588
3589 /* Print errors to UEbuf for any failure that results in nonzero return */
3590 static int
3591 process_ctr_def (int forKernel, hrtime_t global_min_time_nsec,
3592                  const char *counter, const char *value, Hwcentry *pret_ctr,
3593                  char* UWbuf, size_t UWsz, char* UEbuf, size_t UEsz)
3594 {
3595   int rc = -1;
3596   char *nameOnly = NULL;
3597   char *attrs = NULL;
3598   char *regstr = NULL;
3599   int plus;
3600   regno_t regno;
3601   const Hwcentry *pfound = NULL;
3602   const char *uname = NULL;
3603   int disable_backtrack;
3604   UEbuf[0] = 0;
3605   UWbuf[0] = 0;
3606   Tprintf (DBG_LT3, "hwctable: process_ctr_def(): counter=%s value=%s \n",
3607            counter, value ? value : "NULL");
3608   hwcfuncs_parse_ctr (counter, &plus, &nameOnly, &attrs, &regstr, &regno);
3609
3610   /* search for the counter in the std and raw lists */
3611   {
3612     pfound = ptrarray_find ((const Hwcentry**) cpcx_std[forKernel], nameOnly, NULL, 1, regno);
3613     if (pfound)
3614       hwcentry_print (DBG_LT1, "hwctable: process_ctr_def: found in stdlist:",
3615                       pfound);
3616   }
3617   if (!pfound)
3618     {
3619       pfound = ptrarray_find ((const Hwcentry**) cpcx_hidden[forKernel], nameOnly, NULL, 1, regno);
3620       if (pfound)
3621         hwcentry_print (DBG_LT1, "hwctable: process_ctr_def: found in stdlist(hidden):", pfound);
3622     }
3623   if (!pfound)
3624     {
3625       pfound = ptrarray_find_by_name (cpcx_raw[forKernel], nameOnly); /* (regno match checked later) */
3626       if (pfound)
3627         hwcentry_print (DBG_LT1, "hwctable: process_ctr_def: found in rawlist:", pfound);
3628     }
3629   if (!pfound)
3630     {
3631       pfound = ptrarray_find ((const Hwcentry**) cpcx_std[forKernel], nameOnly, NULL, 1, REGNO_ANY);
3632       if (pfound)
3633         hwcentry_print (DBG_LT1, "hwctable: process_ctr_def: found in stdlist but regno didn't match:", pfound);
3634     }
3635   if (!pfound)
3636     {
3637       pfound = ptrarray_find ((const Hwcentry**) cpcx_hidden[forKernel], nameOnly, NULL, 1, REGNO_ANY);
3638       if (pfound)
3639         hwcentry_print (DBG_LT1, "hwctable: process_ctr_def: found in stdlist(hidden) but regno didn't match:", pfound);
3640     }
3641   if (!pfound)
3642     {
3643       uint64_t val = 0;
3644       if (is_numeric (nameOnly, &val))
3645         {
3646           Hwcentry *tmp = alloc_shallow_copy (&empty_ctr); // Leaks?
3647           if (tmp)
3648             {
3649               tmp->name = strdup (nameOnly);
3650               regno_add (tmp, REGNO_ANY);
3651               pfound = tmp;
3652             }
3653         }
3654       if (pfound)
3655         hwcentry_print (DBG_LT1, "hwctable: process_ctr_def: counter specified by numeric value:", pfound);
3656     }
3657   if (!pfound)
3658     {
3659       snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3660                 GTXT ("Invalid HW counter name: %s\n"), nameOnly);
3661       snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3662                 GTXT ("Run \"%s -h\" with no other arguments for more information on HW counters on this system.\n"),
3663                 (IS_KERNEL (forKernel) ? "er_kernel" : "collect"));
3664       goto process_ctr_def_wrapup;
3665     }
3666
3667   /* counter found */
3668   *pret_ctr = *pfound; /* shallow copy */
3669   pret_ctr->int_name = NULL; /* so free doesn't try to free these pfound's ptrs */
3670   pret_ctr->name = NULL; /* so free doesn't try to free these pfound's ptrs */
3671
3672   /* update uname,memop */
3673   uname = counter;
3674   disable_backtrack = 0;
3675   if (plus != 0 || ABST_PLUS_BY_DEFAULT (pret_ctr->memop))
3676     {
3677       // attempt to process memoryspace profiling
3678       int message_printed = 0;
3679       if (cpcx_cpuver == CPUVER_GENERIC)
3680         {
3681           // accept plus, since we don't know what this CPU is
3682           snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3683                     GTXT ("`+' may not be correctly supported on `%s' because processor is not recognized."),
3684                     cpcx_cciname);
3685           pret_ctr->memop = ABST_LDST; // supply a backtracking data type - required for collector
3686         }
3687       else if (cpcx_cpuver == CPC_ULTRA1 || cpcx_cpuver == CPC_ULTRA2
3688                || cpcx_cpuver == CPC_ULTRA3 || cpcx_cpuver == CPC_ULTRA3_PLUS
3689                || cpcx_cpuver == CPC_ULTRA3_I || cpcx_cpuver == CPC_ULTRA4_PLUS
3690                || cpcx_cpuver == CPC_ULTRA4 || cpcx_cpuver == CPC_ULTRA_T1
3691                || cpcx_cpuver == CPC_ULTRA_T2 || cpcx_cpuver == CPC_ULTRA_T2P
3692                || cpcx_cpuver == CPC_ULTRA_T3)
3693         {
3694           if (!ABST_BACKTRACK_ENABLED (pret_ctr->memop))
3695             disable_backtrack = 1;
3696         }
3697       else if (cpcx_cpuver == CPC_SPARC_T4 || cpcx_cpuver == CPC_SPARC_T5
3698                || cpcx_cpuver == CPC_SPARC_T6 || cpcx_cpuver == CPC_SPARC_M4
3699                || cpcx_cpuver == CPC_SPARC_M5 || cpcx_cpuver == CPC_SPARC_M6
3700                || cpcx_cpuver == CPC_SPARC_M7 || cpcx_cpuver == CPC_SPARC_M8)
3701         {
3702           if (pret_ctr->memop != ABST_EXACT)
3703             disable_backtrack = 1;
3704         }
3705       else if (cpcx_cpuver == CPC_INTEL_NEHALEM || cpcx_cpuver == CPC_INTEL_WESTMERE
3706                || cpcx_cpuver == CPC_INTEL_SANDYBRIDGE
3707                || cpcx_cpuver == CPC_INTEL_IVYBRIDGE
3708                || cpcx_cpuver == CPC_INTEL_HASWELL
3709                || cpcx_cpuver == CPC_INTEL_BROADWELL
3710                || cpcx_cpuver == CPC_INTEL_SKYLAKE)
3711         {
3712           if (pret_ctr->memop != ABST_EXACT_PEBS_PLUS1)
3713             disable_backtrack = 1;
3714           else if (plus < 0)
3715             {
3716               // disabling memoryspace not supported for
3717               // remove specified -
3718               uname++;
3719               plus = 0;
3720               snprintf (UWbuf + strlen (UWbuf), UWsz - strlen (UWbuf),
3721                         GTXT ("Warning: `-' is not supported on `%s' -- memory reference backtracking will remain enabled for this counter\n"),
3722                         nameOnly);
3723             }
3724         }
3725       else
3726         {
3727           message_printed = 1;
3728           snprintf (UWbuf + strlen (UWbuf), UWsz - strlen (UWbuf),
3729                     GTXT ("Warning: `+' is not supported on `%s' -- memory reference backtracking will not be enabled for `%s'\n"),
3730                     cpcx_cciname, nameOnly);
3731           disable_backtrack = 1;
3732         }
3733       if (disable_backtrack)
3734         {
3735           if (plus != 0)
3736             uname++;    // remove specified + or -
3737           if (!message_printed && plus > 0)
3738             snprintf (UWbuf + strlen (UWbuf), UWsz - strlen (UWbuf),
3739                       GTXT ("Warning: `+' is not supported on `%s' -- memory reference backtracking will not be enabled for this counter\n"),
3740                       nameOnly);
3741         }
3742     }
3743   else
3744     disable_backtrack = 1;
3745   if (disable_backtrack || plus < 0)
3746     if (pret_ctr->memop != ABST_NOPC)
3747       pret_ctr->memop = ABST_NONE;
3748   if (pret_ctr->memop == ABST_NOPC)
3749     snprintf (UWbuf + strlen (UWbuf), UWsz - strlen (UWbuf),
3750               GTXT ("Warning: HW counter `%s' is not program-related -- callstacks will be not be recorded for this counter\n"),
3751               uname);
3752
3753   /* update reg_num */
3754   if (!regno_is_valid (pfound, regno))
3755     {
3756       char buf[1024];
3757       snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3758                 GTXT ("For counter `%s', %s is not a valid register; valid registers: %s\n"),
3759                 nameOnly, regstr ? regstr + 1 : "?",
3760                 get_regnolist (buf, sizeof (buf), pfound->reg_list, 1));
3761       goto process_ctr_def_wrapup;
3762     }
3763   if (pret_ctr->reg_num == REGNO_ANY)
3764     { /* table's regno is a wildcard */
3765       if (REG_LIST_EOL (pfound->reg_list[1]))
3766         {
3767           /* valid list only contains one regno, so use it */
3768           pret_ctr->reg_num = pfound->reg_list[0];
3769         }
3770       else
3771         pret_ctr->reg_num = regno;  /* use user's selection */
3772     }
3773
3774   /* update name and int_name */
3775   {
3776     // validate attributes
3777     if (attrs)
3778       {
3779         hwcfuncs_attr_t cpc2_attrs[HWCFUNCS_MAX_ATTRS];
3780         void * attr_mem;
3781         unsigned nattrs;
3782         char *errbuf;
3783         /* extract attributes from uname */
3784         attr_mem = hwcfuncs_parse_attrs (uname, cpc2_attrs, HWCFUNCS_MAX_ATTRS,
3785                                          &nattrs, &errbuf);
3786         if (!attr_mem)
3787           {
3788             snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3789                       "%s\n", errbuf);
3790             free (errbuf);
3791             goto process_ctr_def_wrapup;
3792           }
3793         /* make sure all attributes are valid */
3794         for (unsigned ii = 0; ii < nattrs; ii++)
3795           {
3796             if (!attr_is_valid (forKernel, cpc2_attrs[ii].ca_name))
3797               {
3798                 snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3799                           GTXT ("Invalid attribute specified for counter `%s': %s\n"),
3800                           nameOnly, cpc2_attrs[ii].ca_name);
3801                 snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3802                           GTXT ("Run \"%s -h\" with no other arguments for more information on HW counters on this system.\n"),
3803                           (IS_KERNEL (forKernel) ? "er_kernel" : "collect"));
3804                 free (attr_mem);
3805                 goto process_ctr_def_wrapup;
3806               }
3807             for (unsigned jj = ii + 1; jj < nattrs; jj++)
3808               {
3809                 if (strcmp (cpc2_attrs[ii].ca_name,
3810                             cpc2_attrs[jj].ca_name) == 0)
3811                   {
3812                     snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3813                               GTXT ("Duplicate attribute specified for counter `%s': %s\n"),
3814                               nameOnly, cpc2_attrs[ii].ca_name);
3815                     free (attr_mem);
3816                     goto process_ctr_def_wrapup;
3817                   }
3818               }
3819           }
3820         free (attr_mem);
3821       }
3822     pret_ctr->name = strdup (uname);
3823
3824     // assign int_name
3825     if (pfound->int_name)
3826       {
3827         // Counter is one of the following:
3828         // - aliased (e.g. cycles~system=1),
3829         // - convenience (e.g. cycles0~system=1),
3830         if (!attrs) // convert alias to internal name
3831           pret_ctr->int_name = strdup (pfound->int_name);
3832         else
3833           {
3834             // convert alias to internal name and
3835             // append user-supplied attributes
3836             size_t sz = strlen (pfound->int_name) + strlen (attrs) + 1;
3837             char *tbuf = calloc (sz, 1);
3838             if (tbuf)
3839               snprintf (tbuf, sz, "%s%s", pfound->int_name, attrs);
3840             pret_ctr->int_name = tbuf;
3841           }
3842       }
3843     else
3844       pret_ctr->int_name = strdup (uname);  // user-supplied name
3845   }
3846
3847   /* update val */
3848   if (set_hwcval (pret_ctr, global_min_time_nsec, value))
3849     {
3850       snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3851                 GTXT ("Invalid interval for HW counter `%s': %s\n"),
3852                 nameOnly, value);
3853       goto process_ctr_def_wrapup;
3854     }
3855   hwcentry_print (DBG_LT2, "hwctable: process_ctr_def:", pret_ctr);
3856   rc = 0;
3857
3858 process_ctr_def_wrapup:
3859   free (regstr);
3860   free (attrs);
3861   free (nameOnly);
3862   return rc;
3863 }
3864
3865 /*---------------------------------------------------------------------------*/
3866
3867 /* external interfaces, see hwcentry.h for descriptions. */
3868
3869 extern int
3870 hwc_lookup (int forKernel, hrtime_t global_min_time_nsec, const char *instring,
3871             Hwcentry *caller_entries[], unsigned maxctrs, char **emsg, char **wmsg)
3872 {
3873   unsigned ii;
3874   char *instr_copy = NULL, *ss = NULL;
3875   unsigned numctrs = 0;
3876   int rc = 0;
3877   char *tokenptr[MAX_PICS * 2];
3878   unsigned numtokens = 0;
3879   char UEbuf[1024 * 5]; /* error message buffer; strdup of it is passed back to user  */
3880   char UWbuf[1024 * 5]; /* warning message buffer; strdup of it is passed back to user  */
3881   if (emsg)
3882     *emsg = NULL;
3883   if (wmsg)
3884     *wmsg = NULL;
3885   UEbuf[0] = 0;
3886   UWbuf[0] = 0;
3887
3888   // supply temporary result buffers as needed
3889   Hwcentry tmp_entry_table[MAX_PICS];
3890   Hwcentry * tmp_entries[MAX_PICS];
3891   Hwcentry **entries;
3892   if (caller_entries)
3893     entries = caller_entries;
3894   else
3895     {
3896       // user doesn't care about results; provide temporary storage for results
3897       for (ii = 0; ii < MAX_PICS; ii++)
3898         tmp_entries[ii] = &tmp_entry_table[ii];
3899       entries = tmp_entries;
3900       maxctrs = MAX_PICS;
3901     }
3902   Tprintf (DBG_LT1, "hwctable: hwc_lookup(%s)\n",
3903            instring ? instring : "NULL");
3904
3905   /* clear <entries> first - prevent seg faults in hwc_lookup_wrapup */
3906   for (ii = 0; ii < maxctrs; ii++)
3907     *entries[ii] = empty_ctr;
3908   if (!instring)
3909     {
3910       snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
3911                 GTXT ("No HW counters were specified."));
3912       rc = -1;
3913       goto hwc_lookup_wrapup;
3914     }
3915
3916   /* make sure tables are initialized */
3917   setup_cpc_skip_hwctest ();
3918   if (cpcx_npics == 0)
3919     {
3920       if (cpcx_cpuver < 0)
3921         {
3922           char buf[1024];
3923           *buf = 0;
3924           char *pch = hwcfuncs_errmsg_get (buf, sizeof (buf), 0); /* get first err msg, disable capture */
3925           if (*pch)
3926             snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
3927                       GTXT ("HW counter profiling is not supported on this system: %s%s"),
3928                       pch, pch[strlen (pch) - 1] == '\n' ? "" : "\n");
3929           else
3930             snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
3931                       GTXT ("HW counter profiling is not supported on this system\n"));
3932         }
3933       else
3934         snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
3935                   GTXT ("HW counter profiling is not supported on '%s'\n"),
3936                   cpcx_cciname);
3937       rc = -1;
3938       goto hwc_lookup_wrapup;
3939     }
3940   ss = instr_copy = strdup (instring);
3941   while (*ss != 0 && (*ss == ' ' || *ss == '\t'))
3942     ss++;
3943   tokenptr[numtokens++] = ss;
3944   do
3945     {
3946       /* find end of previous token, replace w/ NULL, skip whitespace, set <tokenptr>, repeat */
3947       for (; *ss; ss++)
3948         {
3949           if (*ss == ',' || *ss == ' ' || *ss == '\t')
3950             {
3951               /* end of previous token found */
3952               *ss = 0; /* terminate the previous token */
3953               ss++;
3954               while (*ss != 0 && (*ss == ' ' || *ss == '\t'))
3955                 ss++;
3956               if (*ss)
3957                 tokenptr[numtokens++] = ss;
3958               break; // from for loop
3959             }
3960         }
3961     }
3962   while (*ss && numtokens < (MAX_PICS * 2));
3963
3964   if (*ss)
3965     {
3966       snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
3967                 GTXT ("The number of HW counters specified exceeds internal resources\n"));
3968       snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
3969                 GTXT ("Run \"%s -h\" with no other arguments for more information on HW counters on this system.\n"),
3970                 (IS_KERNEL (forKernel) ? "er_kernel" : "collect"));
3971       rc = -1;
3972       goto hwc_lookup_wrapup;
3973     }
3974   Tprintf (DBG_LT3, "hwctable: hwc_lookup(): numtokens=%d\n", numtokens);
3975
3976   /* look up individual counters */
3977   {
3978     int fail = 0;
3979     for (ii = 0; ii < numtokens && numctrs < maxctrs; ii += 2)
3980       {
3981         const char *counter;
3982         const char *value;
3983         Hwcentry *pret_ctr = entries[numctrs];
3984
3985         /* assign the tokens to ctrnames, timeoutValues. */
3986         counter = tokenptr[ii];
3987         if (ii + 1 < numtokens)
3988           value = tokenptr[ii + 1];
3989         else
3990           value = 0;
3991         if (process_ctr_def (forKernel, global_min_time_nsec, counter, value, pret_ctr,
3992                              UWbuf + strlen (UWbuf),
3993                              sizeof (UWbuf) - strlen (UWbuf),
3994                              UEbuf + strlen (UEbuf),
3995                              sizeof (UEbuf) - strlen (UEbuf)))
3996           {
3997             /* could choose to set fail=1 and continue here,
3998                but errmsgs would be aggregated (messy) */
3999             rc = -1;
4000             goto hwc_lookup_wrapup;
4001           }
4002         numctrs++;
4003       }
4004     if (fail)
4005       {
4006         rc = -1;
4007         goto hwc_lookup_wrapup;
4008       }
4009   }
4010
4011   if (!numctrs)
4012     {
4013       snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4014                 GTXT ("No HW counters were specified.\n"));
4015       rc = -1;
4016       goto hwc_lookup_wrapup;
4017     }
4018   if (numctrs > cpcx_max_concurrent[forKernel])
4019     {
4020       snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4021                 GTXT ("The HW counter configuration could not be loaded: More than %d counters were specified\n"), cpcx_max_concurrent[forKernel]);
4022       snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4023                 GTXT ("Run \"%s -h\" with no other arguments for more information on HW counters on this system.\n"),
4024                 (IS_KERNEL (forKernel) ? "er_kernel" : "collect"));
4025       rc = -1;
4026       goto hwc_lookup_wrapup;
4027     }
4028
4029 hwc_lookup_wrapup:
4030   free (instr_copy);
4031   if (wmsg && strlen (UWbuf))
4032     *wmsg = strdup (UWbuf);
4033   if (emsg && strlen (UEbuf))
4034     *emsg = strdup (UEbuf);
4035   if (rc == 0)
4036     rc = numctrs;
4037   return rc;
4038 }
4039
4040 extern char *
4041 hwc_validate_ctrs (int forKernel, Hwcentry *entries[], unsigned numctrs)
4042 {
4043   char UEbuf[1024 * 5];
4044   UEbuf[0] = 0;
4045
4046   /* search for obvious duplicates*/
4047   unsigned ii;
4048   for (ii = 0; ii < numctrs; ii++)
4049     {
4050       regno_t reg_a = entries[ii]->reg_num;
4051       if (reg_a != REGNO_ANY)
4052         {
4053           unsigned jj;
4054           for (jj = ii + 1; jj < numctrs; jj++)
4055             {
4056               int reg_b = entries[jj]->reg_num;
4057               if (reg_a == reg_b)
4058                 {
4059                   snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4060                             GTXT ("Only one HW counter is allowed per register.  The following counters use register %d: \n"),
4061                             reg_a);
4062                   for (jj = 0; jj < numctrs; jj++)
4063                     {
4064                       char buf[256];
4065                       int reg_b = entries[jj]->reg_num;
4066                       if (reg_a == reg_b)
4067                         snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4068                                   GTXT ("  %d. %s\n"), jj + 1,
4069                                   hwc_hwcentry_specd_string (buf, sizeof (buf),
4070                                                              entries[jj]));
4071                     }
4072                   return strdup (UEbuf);
4073                 }
4074             }
4075         }
4076     }
4077
4078   /* test counters */
4079   hwcfuncs_errmsg_get (NULL, 0, 1); /* enable errmsg capture */
4080   int hwc_rc = hwcfuncs_assign_regnos (entries, numctrs);
4081   if (!hwc_rc)
4082     hwc_rc = test_hwcs ((const Hwcentry**) entries, numctrs);
4083   if (hwc_rc)
4084     {
4085       if (cpcx_cpuver == CPC_PENTIUM_4_HT || cpcx_cpuver == CPC_PENTIUM_4)
4086         {
4087           snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4088                     GTXT ("HW counter profiling is disabled unless only one logical CPU per HyperThreaded processor is online (see psradm)\n"));
4089           return strdup (UEbuf);
4090         }
4091       char buf[1024];
4092       *buf = 0;
4093       char * pch = hwcfuncs_errmsg_get (buf, sizeof (buf), 0); /* get first err msg, disable capture */
4094       if (*pch)
4095         snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4096                   GTXT ("The HW counter configuration could not be loaded: %s%s"),
4097                   pch, pch[strlen (pch) - 1] == '\n' ? "" : "\n");
4098       else
4099         snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4100                   GTXT ("The HW counter configuration could not be loaded\n"));
4101       snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4102                 GTXT ("Run \"%s -h\" with no other arguments for more information on HW counters on this system.\n"),
4103                 (IS_KERNEL (forKernel) ? "er_kernel" : "collect"));
4104       return strdup (UEbuf);
4105     }
4106   return NULL;
4107 }
4108
4109 extern Hwcentry *
4110 hwc_post_lookup (Hwcentry * pret_ctr, char *counter, char * int_name, int cpuver)
4111 {
4112   const Hwcentry *pfound;
4113   regno_t regno;
4114   char *nameOnly = NULL;
4115   char *attrs = NULL;
4116
4117   /* fields in pret_ctr (name and int_name) should already be free */
4118   hwcfuncs_parse_ctr (counter, NULL, &nameOnly, &attrs, NULL, &regno);
4119
4120   /* look for it in the canonical list */
4121   pfound = static_table_find (stdlist_get_table (cpuver),
4122                               nameOnly, int_name, 0, REGNO_ANY);
4123   if (!pfound)  /* try the generic list */
4124     pfound = static_table_find (papi_generic_list,
4125                                 nameOnly, int_name, 0, REGNO_ANY);
4126   if (pfound)
4127     {
4128       /* in standard list */
4129       *pret_ctr = *pfound; /* shallow copy */
4130       if (pret_ctr->int_name)
4131         {
4132           // aliased counter
4133           pret_ctr->int_name = strdup (pret_ctr->int_name);
4134           if (pret_ctr->short_desc == NULL)
4135             {
4136               // look for short_desc of corresponding raw counter
4137               const Hwcentry *praw = static_table_find (stdlist_get_table (cpuver),
4138                                                         pret_ctr->int_name, NULL, 0, REGNO_ANY);
4139               if (praw && praw->short_desc)
4140                 pret_ctr->short_desc = strdup (praw->short_desc);
4141             }
4142         }
4143       else
4144         pret_ctr->int_name = strdup (counter);
4145       if (pret_ctr->reg_num == REGNO_ANY)
4146         pret_ctr->reg_num = regno;  /* table's regno is a wildcard */
4147     }
4148   else
4149     {
4150       /* not a standard counter */
4151       *pret_ctr = empty_ctr;
4152       pret_ctr->int_name = strdup (counter);
4153       pret_ctr->reg_num = regno;
4154     }
4155
4156   /* update the name */
4157   if (attrs)
4158     {
4159       pret_ctr->name = canonical_name (counter);
4160       if (pret_ctr->metric)
4161         {
4162           // metric text is supplied from a table. (User supplied HWC alias)
4163           // Append user-supplied attributes to metric name:
4164           size_t len = strlen (pret_ctr->metric) + strlen (attrs) + 4;
4165           char *pch = calloc (len, 1);
4166           if (pch)
4167             snprintf (pch, len, "%s (%s)", pret_ctr->metric, attrs);
4168           pret_ctr->metric = pch; // leaks
4169         }
4170     }
4171   else
4172     pret_ctr->name = strdup (nameOnly);
4173
4174   if (pfound)
4175     hwcentry_print (DBG_LT2, "hwctable: hwc_post_lookup: found: ", pret_ctr);
4176   else
4177     hwcentry_print (DBG_LT2, "hwctable: hwc_post_lookup: default: ", pret_ctr);
4178   free (attrs);
4179   free (nameOnly);
4180   return pret_ctr;
4181 }
4182
4183 static const char *
4184 hwc_on_lo_hi (const Hwcentry *pctr)
4185 {
4186   char* rate;
4187   {
4188     switch (pctr->min_time)
4189       {
4190       case (HWCTIME_LO):
4191         rate = NTXT ("lo");
4192         break;
4193       case (HWCTIME_ON):
4194         rate = NTXT ("on");
4195         break;
4196       case (HWCTIME_HI):
4197         rate = NTXT ("hi");
4198         break;
4199       case (0):
4200         rate = NULL; // null => use interval count
4201         break;
4202       default:
4203       case (HWCTIME_TBD):
4204         rate = NTXT ("on");
4205         break;
4206       }
4207   }
4208   return rate; //strdup( rate );
4209 }
4210
4211 extern char *
4212 hwc_rate_string (const Hwcentry *pctr, int force_numeric)
4213 {
4214   const char * rateString = hwc_on_lo_hi (pctr);
4215   char buf[128];
4216   if (!rateString || force_numeric)
4217     {
4218       snprintf (buf, sizeof (buf), NTXT ("%d"), pctr->val);
4219       rateString = buf;
4220     }
4221   return strdup (rateString);
4222 }
4223
4224 static char metricbuf[2048];
4225
4226 extern char *
4227 hwc_i18n_metric (const Hwcentry *pctr)
4228 {
4229   if (pctr->metric != NULL)
4230     snprintf (metricbuf, sizeof (metricbuf), NTXT ("%s"), PTXT (pctr->metric));
4231   else if (pctr->name != NULL)
4232     snprintf (metricbuf, sizeof (metricbuf), GTXT ("%s Events"), pctr->name);
4233   else if (pctr->int_name != NULL)
4234     snprintf (metricbuf, sizeof (metricbuf), GTXT ("%s Events"), pctr->int_name);
4235   else
4236     snprintf (metricbuf, sizeof (metricbuf), GTXT ("Undefined Events"));
4237   return metricbuf;
4238 }
4239
4240 /* return cpu version, should only be called when about to generate an experiment,
4241    not when reading back an experiment */
4242 #if 0 /* called by ... */
4243 . / perfan / collect / src / collect.cc : start : 245 : cpuver = hwc_get_cpc_cpuver ();
4244 . / ccr_components / Collector_Interface / collctrl.cc : constructor : 202 : cpcx_cpuver = hwc_get_cpc_cpuver ();
4245 . / perfan / dbe / src / Dbe.cc : 3041 : JApplication::cpuver = hwc_get_cpc_cpuver ();
4246 . / perfan / dbe / src / Dbe.cc : 3164 : JApplication::cpuver = hwc_get_cpc_cpuver ();
4247
4248 note:
4249 cpc_getcpuver () : only papi, ostest, this and hwprofile.c call it
4250 #endif
4251 int
4252 hwc_get_cpc_cpuver ()
4253 {
4254   setup_cpcx ();
4255   return cpcx_cpuver;
4256 }
4257
4258 extern char*
4259 hwc_get_cpuname (char *buf, size_t buflen)
4260 {
4261   setup_cpcx ();
4262   if (!buf || !buflen)
4263     return buf;
4264   buf[0] = 0;
4265   if (cpcx_cciname)
4266     {
4267       strncpy (buf, cpcx_cciname, buflen - 1);
4268       buf[buflen - 1] = 0;
4269     }
4270   return buf;
4271 }
4272
4273 extern char*
4274 hwc_get_docref (char *buf, size_t buflen)
4275 {
4276   setup_cpcx ();
4277   if (!buf || !buflen)
4278     return buf;
4279   buf[0] = 0;
4280   if (cpcx_docref)
4281     {
4282       strncpy (buf, cpcx_docref, buflen - 1);
4283       buf[buflen - 1] = 0;
4284     }
4285   return buf;
4286 }
4287
4288 //TBR:
4289
4290 extern char*
4291 hwc_get_default_cntrs ()
4292 {
4293   setup_cpcx ();
4294   if (cpcx_default_hwcs[0] != NULL)
4295     return strdup (cpcx_default_hwcs[0]); // TBR deprecate this
4296   return NULL;
4297 }
4298
4299 extern char*
4300 hwc_get_default_cntrs2 (int forKernel, int style)
4301 {
4302   setup_cpcx ();
4303   if (!VALID_FOR_KERNEL (forKernel))
4304     return NULL;
4305   char *cpcx_default = cpcx_default_hwcs[forKernel];
4306   if (cpcx_default == NULL || cpcx_npics == 0)
4307     return NULL;
4308   if (style == 1)
4309     return strdup (cpcx_default);
4310
4311   // style == 2
4312   // we will replace "," delimiters with " -h " (an extra 3 chars per HWC)
4313   char *s = (char *) malloc (strlen (cpcx_default) + 3 * cpcx_npics);
4314   if (s == NULL) return s;
4315   char *p = s;
4316   char *q = cpcx_default;
4317   int i;
4318   for (i = 0; i < cpcx_npics; i++)
4319     {
4320       int qlen = strlen (q);
4321       if (qlen == 0)
4322         {
4323           p[0] = '\0';
4324           break;
4325         }
4326       // add " -h " if not the first HWC
4327       if (i != 0)
4328         {
4329           p[0] = ' ';
4330           p[1] = '-';
4331           p[2] = 'h';
4332           p[3] = ' ';
4333           p += 4;
4334         }
4335
4336       // find second comma
4337       char *r = strchr (q, ',');
4338       if (r)
4339         r = strchr (r + 1, ',');
4340
4341       // we didn't find one, so the rest of the string is the last HWC
4342       if (r == NULL)
4343         {
4344           // EUGENE could check i==cpcx_npicx-1, but what if it isn't???
4345           strcpy (p, q);
4346           if (p[qlen - 1] == ',')
4347             qlen--;
4348           p[qlen] = '\0';
4349           break;
4350         }
4351
4352       // copy the HWC, trim trailing comma, add null char
4353       qlen = r - q - 1;
4354       strcpy (p, q);
4355       if (p[qlen - 1] == ',')
4356         qlen--;
4357       p += qlen;
4358       p[0] = '\0';
4359       q = r + 1;
4360     }
4361   return s;
4362 }
4363
4364 extern char*
4365 hwc_get_orig_default_cntrs (int forKernel)
4366 {
4367   setup_cpcx ();
4368   if (!VALID_FOR_KERNEL (forKernel))
4369     return NULL;
4370   if (cpcx_orig_default_hwcs[forKernel] != NULL)
4371     return strdup (cpcx_orig_default_hwcs[forKernel]);
4372   return NULL;
4373 }
4374
4375 extern const char *
4376 hwc_memop_string (ABST_type memop)
4377 {
4378   const char * s;
4379   switch (memop)
4380     {
4381     case ABST_NONE:
4382       s = "";
4383       break;
4384     case ABST_LOAD:
4385       s = GTXT ("load ");
4386       break;
4387     case ABST_STORE:
4388       s = GTXT ("store ");
4389       break;
4390     case ABST_LDST:
4391     case ABST_US_DTLBM:
4392     case ABST_LDST_SPARC64:
4393       s = GTXT ("load-store ");
4394       break;
4395     case ABST_EXACT_PEBS_PLUS1:
4396     case ABST_EXACT:
4397       s = GTXT ("memoryspace ");
4398       break;
4399     case ABST_COUNT:
4400       s = GTXT ("count ");
4401       break;
4402     case ABST_NOPC:
4403       s = GTXT ("not-program-related ");
4404       break;
4405     default:
4406       s = ""; // was "ABST_UNK", but that's meaningless to users
4407       break;
4408     }
4409   return s;
4410 }
4411
4412 static const char *
4413 timecvt_string (int timecvt)
4414 {
4415   if (timecvt > 0)
4416     return GTXT ("CPU-cycles");
4417   if (timecvt < 0)
4418     return GTXT ("ref-cycles");
4419   return GTXT ("events");
4420 }
4421
4422 int show_regs = 0;  // The register setting is available on Solaris only
4423
4424 /*
4425  * print the specified strings in aligned columns
4426  */
4427 static void
4428 format_columns (char *buf, int bufsiz, char *s1, char *s2, const char *s3,
4429                 const char *s4, char *s5, const char *s6)
4430 {
4431   // NULL strings are blanks
4432   char *blank = NTXT ("");
4433   if (s2 == NULL)
4434     s2 = blank;
4435   if (s3 == NULL)
4436     s3 = blank;
4437   if (s6 == NULL)
4438     s6 = blank;
4439
4440   // get the lengths and target widths
4441   // (s6 can be as wide as it likes)
4442   int l1 = strlen (s1), n1 = 10, l2 = strlen (s2), n2 = 13;
4443   int l3 = strlen (s3), n3 = 20, l4 = strlen (s4), n4 = 10, n5;
4444   char divide = ' ';
4445
4446   // adjust widths, stealing from one column to help a neighbor
4447   // There's a ragged boundary between s2 and s3.
4448   // So push this boundary to the right.
4449   n2 += n3 - l3;
4450   n3 -= n3 - l3;
4451
4452   // If s3 is empty, push the boundary over to s4.
4453   if (l3 == 0)
4454     {
4455       n2 += n4 - l4;
4456       n4 -= n4 - l4;
4457     }
4458
4459   // If there's enough room to fit s1 and s2, do so.
4460   if (n1 + n2 >= l1 + l2)
4461     {
4462       if (n1 < l1)
4463         {
4464           n2 -= l1 - n1;
4465           n1 += l1 - n1;
4466         }
4467       if (n2 < l2)
4468         {
4469           n1 -= l2 - n2;
4470           n2 += l2 - n2;
4471         }
4472     }
4473   else
4474     {
4475       // not enough room, so we need to divide the line
4476       n3 += 4 // 4-blank margin
4477               + n1 // 1st column
4478               + 1 // space between 1st and 2nd columns
4479               + n2 // 2nd column
4480               + 1; // space between 2nd and 3th columns
4481       divide = '\n';
4482
4483       // make 1st column large enough
4484       if (n1 < l1)
4485         n1 = l1;
4486
4487       // width of 2nd column no longer matters since we divided the line
4488       n2 = 0;
4489     }
4490
4491   if (show_regs)
4492     {
4493       // fifth column should be wide enough for regnolist
4494       //     see function get_regnolist()
4495       if (cpcx_npics < 10)
4496         n5 = cpcx_npics; // one char per regno
4497       else
4498         n5 = 16 + 3 * (cpcx_npics - 9); // spaces between regnos and some regnos are 2-char wide
4499       // ... and be wide enough for header "regs"
4500       if (n5 < 4)
4501         n5 = 4;
4502
4503       // print to buffer
4504       // (don't need a space before s4 since historical precedent to have a trailing space in s3)
4505       snprintf (buf, bufsiz, "%-*s %-*s%c%*s%*s %-*s %s",
4506                 n1, s1, n2, s2, divide, n3, s3, n4, s4, n5, s5, s6);
4507     }
4508   else
4509     snprintf (buf, bufsiz, "%-*s %-*s%c%*s%*s %s",
4510               n1, s1, n2, s2, divide, n3, s3, n4, s4, s6);
4511   for (int i = strlen (buf); i > 0; i--)
4512     if (buf[i] == ' ' || buf[i] == '\t')
4513       buf[i] = 0;
4514     else
4515       break;
4516 }
4517
4518 /* routine to return HW counter string formatted and i18n'd */
4519 static char *
4520 hwc_hwcentry_string_internal (char *buf, size_t buflen, const Hwcentry *ctr,
4521                               int show_short_desc)
4522 {
4523   char stderrbuf[1024];
4524   char regnolist[256];
4525   if (!buf || !buflen)
4526     return buf;
4527   buf[0] = 0;
4528   if (ctr == NULL)
4529     {
4530       snprintf (stderrbuf, sizeof (stderrbuf), GTXT ("HW counter not available"));
4531       goto hwc_hwcentry_string_done;
4532     }
4533   char *desc = NULL;
4534   if (show_short_desc)
4535     desc = ctr->short_desc;
4536   if (desc == NULL)
4537     desc = ctr->metric ? hwc_i18n_metric (ctr) : NULL;
4538   format_columns (stderrbuf, sizeof (stderrbuf), ctr->name, ctr->int_name,
4539                   hwc_memop_string (ctr->memop), timecvt_string (ctr->timecvt),
4540                   get_regnolist (regnolist, sizeof (regnolist), ctr->reg_list, 2),
4541                   desc);
4542
4543 hwc_hwcentry_string_done:
4544   strncpy (buf, stderrbuf, buflen - 1);
4545   buf[buflen - 1] = 0;
4546   return buf;
4547 }
4548
4549 /* routine to return HW counter string formatted and i18n'd */
4550 extern char *
4551 hwc_hwcentry_string (char *buf, size_t buflen, const Hwcentry *ctr)
4552 {
4553   return hwc_hwcentry_string_internal (buf, buflen, ctr, 0);
4554 }
4555
4556 /* routine to return HW counter string formatted and i18n'd */
4557 extern char *
4558 hwc_hwcentry_specd_string (char *buf, size_t buflen, const Hwcentry *ctr)
4559 {
4560   char stderrbuf[1024];
4561   const char *memop, *timecvt;
4562   char descstr[1024];
4563   if (!buf || !buflen)
4564     return buf;
4565   buf[0] = 0;
4566   if (ctr == NULL)
4567     {
4568       snprintf (stderrbuf, sizeof (stderrbuf), GTXT ("HW counter not available"));
4569       goto hwc_hwcentry_specd_string_done;
4570     }
4571   timecvt = timecvt_string (ctr->timecvt);
4572   if (ctr->memop)
4573     memop = hwc_memop_string (ctr->memop);
4574   else
4575     memop = "";
4576   if (ctr->metric != NULL)  /* a standard counter for a specific register */
4577     snprintf (descstr, sizeof (descstr), GTXT (" (`%s'; %s%s)"),
4578               hwc_i18n_metric (ctr), memop, timecvt);
4579   else  /* raw counter */
4580     snprintf (descstr, sizeof (descstr), GTXT (" (%s%s)"), memop, timecvt);
4581
4582   char *rateString = hwc_rate_string (ctr, 1);
4583   snprintf (stderrbuf, sizeof (stderrbuf), NTXT ("%s,%s%s"), ctr->name,
4584             rateString ? rateString : "", descstr);
4585   free (rateString);
4586
4587 hwc_hwcentry_specd_string_done:
4588   strncpy (buf, stderrbuf, buflen - 1);
4589   buf[buflen - 1] = 0;
4590   return buf;
4591 }
4592
4593 unsigned
4594 hwc_get_max_regs ()
4595 {
4596   setup_cpcx ();
4597   return cpcx_npics;
4598 }
4599
4600 unsigned
4601 hwc_get_max_concurrent (int forKernel)
4602 {
4603   setup_cpcx ();
4604   if (!VALID_FOR_KERNEL (forKernel))
4605     return 0;
4606   return cpcx_max_concurrent[forKernel];
4607 }
4608
4609 char**
4610 hwc_get_attrs (int forKernel)
4611 {
4612   setup_cpcx ();
4613   if (!VALID_FOR_KERNEL (forKernel))
4614     return NULL;
4615   return cpcx_attrs[forKernel];
4616 }
4617
4618 Hwcentry **
4619 hwc_get_std_ctrs (int forKernel)
4620 {
4621   setup_cpcx ();
4622   if (!VALID_FOR_KERNEL (forKernel))
4623     return NULL;
4624   return cpcx_std[forKernel];
4625 }
4626
4627 Hwcentry **
4628 hwc_get_raw_ctrs (int forKernel)
4629 {
4630   setup_cpcx ();
4631   if (!VALID_FOR_KERNEL (forKernel))
4632     return NULL;
4633   return cpcx_raw[forKernel];
4634 }
4635
4636 /* Call an action function for each attribute supported */
4637 unsigned
4638 hwc_scan_attrs (void (*action)(const char *attr, const char *desc))
4639 {
4640   setup_cpcx ();
4641   int cnt = 0;
4642   for (int ii = 0; cpcx_attrs[0] && cpcx_attrs[0][ii]; ii++, cnt++)
4643     {
4644       if (action)
4645         action (cpcx_attrs[0][ii], NULL);
4646     }
4647   if (!cnt && action)
4648     action (NULL, NULL);
4649   return cnt;
4650 }
4651
4652 unsigned
4653 hwc_scan_std_ctrs (void (*action)(const Hwcentry *))
4654 {
4655   setup_cpcx ();
4656   Tprintf (DBG_LT1, "hwctable: hwc_scan_standard_ctrs()...\n");
4657   int cnt = 0;
4658   for (int ii = 0; cpcx_std[0] && cpcx_std[0][ii]; ii++, cnt++)
4659     if (action)
4660       action (cpcx_std[0][ii]);
4661   if (!cnt && action)
4662     action (NULL);
4663   return cnt;
4664 }
4665
4666 /* Call an action function for each counter supported */
4667 /* action is called with NULL when all counters have been seen */
4668 unsigned
4669 hwc_scan_raw_ctrs (void (*action)(const Hwcentry *))
4670 {
4671   setup_cpcx ();
4672   Tprintf (DBG_LT1, "hwctable: hwc_scan_raw_ctrs()...\n");
4673   int cnt = 0;
4674   for (int ii = 0; cpcx_raw[0] && cpcx_raw[0][ii]; ii++, cnt++)
4675     if (action)
4676       action (cpcx_raw[0][ii]);
4677   if (!cnt && action)
4678     action (NULL);
4679   return cnt;
4680 }
4681
4682 static void
4683 hwc_usage_raw_overview_sparc (FILE *f_usage, int cpuver)
4684 {
4685   /* All these cpuver's use cputabs[]==sparc_t5_m6 anyhow. */
4686   if ((cpuver == CPC_SPARC_M5) || (cpuver == CPC_SPARC_M6)
4687       || (cpuver == CPC_SPARC_T5) || (cpuver == CPC_SPARC_T6))
4688     cpuver = CPC_SPARC_M4; // M4 was renamed to M5
4689
4690   /* While there are small differences between
4691    *     cputabs[]== sparc_t4
4692    *     cputabs[]== sparc_t5_m6
4693    * they are in HWCs we don't discuss in the overview anyhow.
4694    * So just lump them in with T4.
4695    */
4696   if (cpuver == CPC_SPARC_M4)
4697     cpuver = CPC_SPARC_T4;
4698
4699   /* Check for the cases we support. */
4700   if (cpuver != CPC_SPARC_T4 && cpuver != CPC_SPARC_M7 && cpuver != CPC_SPARC_M8)
4701     return;
4702   fprintf (f_usage, GTXT ("    While the above aliases represent the most useful hardware counters\n"
4703                           "    for this processor, a full list of raw (unaliased) counter names appears\n"
4704                           "    below.  First is an overview of some of these names.\n\n"));
4705   fprintf (f_usage, GTXT ("        == Cycles.\n"
4706                           "        Count active cycles with\n"
4707                           "            Cycles_user\n"
4708                           "        Set attributes to choose user, system, and/or hyperprivileged cycles.\n\n"));
4709   fprintf (f_usage, GTXT ("        == Instructions.\n"
4710                           "        Count instructions when they are committed with:\n"));
4711   fprintf (f_usage, NTXT ("            Instr_all\n"));
4712   if (cpuver != CPC_SPARC_M8)
4713     fprintf (f_usage, GTXT ("        It is the total of these counters:\n"));
4714   else
4715     fprintf (f_usage, GTXT ("        Some subsets of instructions can be counted separately:\n"));
4716   fprintf (f_usage, NTXT ("            Branches               %s\n"), GTXT ("branches"));
4717   fprintf (f_usage, NTXT ("            Instr_FGU_crypto       %s\n"), GTXT ("Floating Point and Graphics Unit"));
4718   fprintf (f_usage, NTXT ("            Instr_ld               %s\n"), GTXT ("loads"));
4719   fprintf (f_usage, NTXT ("            Instr_st               %s\n"), GTXT ("stores"));
4720   fprintf (f_usage, NTXT ("            %-19s    %s\n"),
4721            cpuver == CPC_SPARC_M7 ? NTXT ("Instr_SPR_ring_ops")
4722            : NTXT ("SPR_ring_ops"),
4723            GTXT ("internal use of SPR ring"));
4724   fprintf (f_usage, NTXT ("            Instr_other            %s\n"), GTXT ("basic arithmetic and logical instructions"));
4725   if (cpuver != CPC_SPARC_M8)
4726     fprintf (f_usage, GTXT ("        Some subsets of these instructions can be counted separately:\n"));
4727   fprintf (f_usage, NTXT ("            Br_taken               %s\n"), GTXT ("Branches that are taken"));
4728   fprintf (f_usage, NTXT ("            %-19s    %s\n"),
4729            cpuver == CPC_SPARC_M7 ? NTXT ("Instr_block_ld_st")
4730            : NTXT ("Block_ld_st"),
4731            GTXT ("block load/store"));
4732   fprintf (f_usage, NTXT ("            %-19s    %s\n"),
4733            cpuver == CPC_SPARC_M7 ? NTXT ("Instr_atomic")
4734            : NTXT ("Atomics"),
4735            GTXT ("atomic instructions"));
4736   fprintf (f_usage, NTXT ("            %-19s    %s\n"),
4737            cpuver == CPC_SPARC_M7 ? NTXT ("Instr_SW_prefetch")
4738            : NTXT ("SW_prefetch"),
4739            GTXT ("prefetches"));
4740   fprintf (f_usage, NTXT ("            %-19s    %s\n"),
4741            cpuver == CPC_SPARC_M7 ? NTXT ("Instr_SW_count")
4742            : NTXT ("Sw_count_intr"),
4743            GTXT ("SW Count instructions (counts special no-op assembler instructions)"));
4744   fprintf (f_usage, NTXT ("\n"));
4745
4746 #ifdef TMPLEN
4747   compilation error : we're trying to use a macro that's already defined
4748 #endif
4749 #define TMPLEN 32
4750           char s0[TMPLEN], s1[TMPLEN], s2[TMPLEN], s3[TMPLEN];
4751   if (cpuver == CPC_SPARC_M7)
4752     {
4753       snprintf (s0, TMPLEN, "Commit_0_cyc");
4754       snprintf (s1, TMPLEN, "Commit_1_cyc");
4755       snprintf (s2, TMPLEN, "Commit_2_cyc");
4756       snprintf (s3, TMPLEN, "Commit_1_or_2_cyc");
4757     }
4758   else
4759     {
4760       snprintf (s0, TMPLEN, "Commit_0");
4761       snprintf (s1, TMPLEN, "Commit_1");
4762       snprintf (s2, TMPLEN, "Commit_2");
4763       snprintf (s3, TMPLEN, "Commit_1_or_2");
4764     }
4765 #undef TMPLEN
4766   fprintf (f_usage, GTXT ("        == Commit.\n"
4767                           "        Instructions may be launched speculatively, executed out of order, etc.\n"));
4768   if (cpuver != CPC_SPARC_M8)
4769     {
4770       fprintf (f_usage, GTXT ("        We can count the number of cycles during which 0, 1, or 2 instructions are\n"
4771                               "        actually completed and their results committed:\n"));
4772       fprintf (f_usage, GTXT ("            %s\n"
4773                               "            %s\n"
4774                               "            %s\n"
4775                               "            %s\n"
4776                               "        %s is a useful way of identifying parts of your application with\n"
4777                               "        high-latency instructions.\n\n"),
4778                s0, s1, s2, s3, s0);
4779     }
4780   else
4781     {
4782       fprintf (f_usage, GTXT ("        We can count the number of cycles during which no instructions were\n"
4783                               "        able to commit results using:\n"));
4784       fprintf (f_usage, GTXT ("            %s\n"
4785                               "        %s is a useful way of identifying parts of your application with\n"
4786                               "        high-latency instructions.\n\n"),
4787                s0, s0);
4788     }
4789
4790   fprintf (f_usage, GTXT ("        == Cache/memory hierarchy.\n"));
4791   if (cpuver == CPC_SPARC_M7)
4792     {
4793       fprintf (f_usage, GTXT ("        In the cache hierarchy:\n"
4794                               "         * Each socket has memory and multiple SPARC core clusters (scc).\n"
4795                               "         * Each scc has an L3 cache and multiple L2 and L1 caches.\n"));
4796       fprintf (f_usage, GTXT ("        Loads can be counted by where they hit on socket:\n"));
4797       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4798                NTXT ("DC_hit"), GTXT ("hit own L1 data cache"));
4799       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4800                NTXT ("DC_miss_L2_hit"), GTXT ("hit own L2"));
4801       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4802                NTXT ("DC_miss_L3_hit"), GTXT ("hit own L3"));
4803       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4804                NTXT ("DC_miss_nbr_L2_hit"), GTXT ("hit neighbor L2  (same scc)"));
4805       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4806                NTXT ("DC_miss_nbr_scc_hit"), GTXT ("hit neighbor scc (same socket)"));
4807       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4808                NTXT ("DC_miss_nbr_scc_miss"), GTXT ("miss all caches  (same socket)"));
4809       fprintf (f_usage, GTXT ("        These loads can also be grouped:\n"));
4810       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4811                NTXT ("DC_miss"), GTXT ("all - DC_hit"));
4812       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4813                NTXT ("DC_miss_L2_miss"), GTXT ("all - DC_hit - DC_miss_L2_hit"));
4814       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4815                NTXT ("DC_miss_L3_miss"), GTXT ("DC_miss_nbr_scc_hit + DC_miss_nbr_scc_miss"));
4816       fprintf (f_usage, GTXT ("        Loads that miss all caches on this socket can be counted:\n"));
4817       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4818                NTXT ("DC_miss_remote_scc_hit"), GTXT ("hit cache on different socket"));
4819       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4820                NTXT ("DC_miss_local_mem_hit"), GTXT ("hit local memory (same socket)"));
4821       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4822                NTXT ("DC_miss_remote_mem_hit"), GTXT ("hit remote memory (off socket)"));
4823       fprintf (f_usage, GTXT ("        These events are for speculative loads, launched in anticipation\n"
4824                               "        of helping performance but whose results might not be committed.\n"));
4825 #if 0 // was: #if defined(linux).  See 22236226 - sparc-Linux: Support basic Memoryspace and Dataspace profiling (capture VADDR)
4826       /* 21869427 should not look like memoryspace profiling is supported on Linux */
4827       /* 21869424 desire memoryspace profiling on Linux */
4828       fprintf (f_usage, GTXT ("        To count only data-cache misses that commit, use:\n"));
4829       fprintf (f_usage, NTXT ("            DC_miss_commit\n"));
4830 #else
4831       fprintf (f_usage, GTXT ("        To count only data-cache misses that commit, or for memoryspace profiling,\n"
4832                               "        use the 'memoryspace' counter:\n"));
4833       fprintf (f_usage, NTXT ("            DC_miss_commit\n"));
4834 #endif
4835       fprintf (f_usage, NTXT ("\n"));
4836     }
4837   else if (cpuver == CPC_SPARC_M8)
4838     {
4839       fprintf (f_usage, GTXT ("        In the cache hierarchy:\n"
4840                               "         * Each processor has 4 memory controllers and 2 quad core clusters (QCC).\n"
4841                               "         * Each QCC contains 4 cache processor clusters (CPC).\n"
4842                               "         * Each CPC contains 4 cores.\n"
4843                               "         * Each core supports 8 hardware threads.\n"
4844                               "         * The L3 consists of 2 partitions with 1 QCC per partition.\n"
4845                               ));
4846       fprintf (f_usage, GTXT ("        Loads can be counted by where they hit on socket:\n"));
4847       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4848                NTXT ("DC_miss_L2_hit"), GTXT ("hit own L2"));
4849       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4850                NTXT ("DC_miss_L3_hit"), GTXT ("hit own L3"));
4851       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4852                NTXT ("DC_miss_L3_dirty_copyback"), GTXT ("hit own L3 but require copyback from L2D"));
4853       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4854                NTXT ("DC_miss_nbr_L3_hit"), GTXT ("hit neighbor L3 (same socket)"));
4855       fprintf (f_usage, GTXT ("        Loads that miss all caches on this socket can be counted:\n"));
4856       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4857                NTXT ("DC_miss_remote_L3_hit"), GTXT ("hit cache on different socket"));
4858       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4859                NTXT ("DC_miss_local_mem_hit"), GTXT ("hit local memory (same socket)"));
4860       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4861                NTXT ("DC_miss_remote_mem_hit"), GTXT ("hit remote memory (off socket)"));
4862       fprintf (f_usage, GTXT ("        These events are for speculative loads, launched in anticipation\n"
4863                               "        of helping performance but whose results might not be committed.\n"));
4864 #if 0 // was: #if defined(linux).  See 22236226 - sparc-Linux: Support basic Memoryspace and Dataspace profiling (capture VADDR)
4865       /* 21869427 should not look like memoryspace profiling is supported on Linux */
4866       /* 21869424 desire memoryspace profiling on Linux */
4867       fprintf (f_usage, GTXT ("        To count only data-cache misses that commit, use:\n"));
4868       fprintf (f_usage, NTXT ("            DC_miss_commit\n"));
4869 #else
4870       fprintf (f_usage, GTXT ("        To count only data-cache misses that commit, or for memoryspace profiling,\n"
4871                               "        use the 'memoryspace' counter:\n"));
4872       fprintf (f_usage, NTXT ("            DC_miss_commit\n"));
4873 #endif
4874       fprintf (f_usage, NTXT ("\n"));
4875     }
4876   else
4877     {
4878       fprintf (f_usage, GTXT ("        Total data-cache misses can be counted with:\n"));
4879       fprintf (f_usage, NTXT ("            DC_miss                DC_miss_nospec\n"));
4880       fprintf (f_usage, GTXT ("        They are the totals of misses that hit in L2/L3 cache, local memory, or\n"
4881                               "        remote memory:\n"));
4882       fprintf (f_usage, NTXT ("            DC_miss_L2_L3_hit      DC_miss_L2_L3_hit_nospec\n"));
4883       fprintf (f_usage, NTXT ("            DC_miss_local_hit      DC_miss_local_hit_nospec\n"));
4884       fprintf (f_usage, NTXT ("            DC_miss_remote_L3_hit  DC_miss_remote_L3_hit_nospec\n"));
4885       fprintf (f_usage, GTXT ("        The events in the left column include speculative operations.  Use the\n"
4886                               "        right-hand _nospec events to count only data accesses that commit\n"
4887                               "        or for memoryspace profiling.\n\n"));
4888     }
4889
4890   fprintf (f_usage, GTXT ("        == TLB misses.\n"
4891                           "        The Translation Lookaside Buffer (TLB) is a cache of virtual-to-physical\n"
4892                           "        page translations."));
4893   fprintf (f_usage, GTXT ("  If a virtual address (VA) is not represented in the\n"
4894                           "        TLB, an expensive hardware table walk (HWTW) must be conducted."));
4895   fprintf (f_usage, GTXT ("  If the\n"
4896                           "        page is still not found, a trap results.  There is a data TLB (DTLB) and\n"
4897                           "        an instruction TLB (ITLB).\n\n"));
4898   fprintf (f_usage, GTXT ("        TLB misses can be counted by:\n"));
4899   fprintf (f_usage, NTXT ("            %s\n"),
4900            cpuver == CPC_SPARC_M7 ?
4901            NTXT ("DTLB_HWTW_search            ITLB_HWTW_search") :
4902            cpuver == CPC_SPARC_M8 ?
4903            NTXT ("DTLB_HWTW                   ITLB_HWTW") :
4904            NTXT ("DTLB_miss_asynch            ITLB_miss_asynch"));
4905   fprintf (f_usage, GTXT ("        or broken down by page size:\n"));
4906   fprintf (f_usage, NTXT ("            %s"),
4907            cpuver == CPC_SPARC_M7 ?
4908            NTXT ("DTLB_HWTW_hit_8K            ITLB_HWTW_hit_8K\n"
4909                  "            DTLB_HWTW_hit_64K           ITLB_HWTW_hit_64K\n"
4910                  "            DTLB_HWTW_hit_4M            ITLB_HWTW_hit_4M\n") :
4911            NTXT ("DTLB_fill_8KB               ITLB_fill_8KB\n"
4912                  "            DTLB_fill_64KB              ITLB_fill_64KB\n"
4913                  "            DTLB_fill_4MB               ITLB_fill_4MB\n"));
4914   fprintf (f_usage, NTXT ("            %s\n\n"),
4915            cpuver == CPC_SPARC_M7 ?
4916            NTXT ("DTLB_HWTW_hit_256M          ITLB_HWTW_hit_256M\n"
4917                  "            DTLB_HWTW_hit_2G_16G        ITLB_HWTW_hit_2G_16G\n"
4918                  "            DTLB_HWTW_miss_trap         ITLB_HWTW_miss_trap") :
4919            cpuver == CPC_SPARC_M8 ?
4920            NTXT ("DTLB_HWTW_hit_256M          ITLB_HWTW_hit_256M\n"
4921                  "            DTLB_HWTW_hit_16G           ITLB_HWTW_hit_16G\n"
4922                  "            DTLB_HWTW_hit_1T            ITLB_HWTW_hit_1T") :
4923            NTXT ("DTLB_fill_256MB             ITLB_fill_256MB\n"
4924                  "            DTLB_fill_2GB               ITLB_fill_2GB\n"
4925                  "            DTLB_fill_trap              ITLB_fill_trap"));
4926   if (cpuver == CPC_SPARC_M8)
4927     {
4928       fprintf (f_usage, GTXT ("        TLB traps, which can require hundreds of cycles, can be counted with:\n"));
4929       fprintf (f_usage, NTXT ("            %s\n\n"),
4930                NTXT ("DTLB_fill_trap              ITLB_fill_trap"));
4931     }
4932
4933   fprintf (f_usage, GTXT ("        == Branch misprediction.\n"
4934                           "        Count branch mispredictions with:\n"
4935                           "            Br_mispred\n"
4936                           "        It is the total of:\n"
4937                           "            Br_dir_mispred         direction was mispredicted\n"
4938                           "            %s         target    was mispredicted\n"
4939                           "\n"), cpuver == CPC_SPARC_M7 ? NTXT ("Br_tgt_mispred") : NTXT ("Br_trg_mispred"));
4940
4941   fprintf (f_usage, GTXT ("        == RAW hazards.\n"
4942                           "        A read-after-write (RAW) delay occurs when we attempt to read a datum\n"
4943                           "        before an earlier write has had time to complete:\n"));
4944   if (cpuver == CPC_SPARC_M8)
4945     {
4946       fprintf (f_usage, NTXT ("            RAW_hit\n"));
4947       fprintf (f_usage, GTXT ("        RAW_hit events can be broken down into:\n"));
4948     }
4949   else
4950     {
4951       fprintf (f_usage, NTXT ("            RAW_hit_st_q~emask=0xf\n"));
4952       fprintf (f_usage, GTXT ("        The mask 0xf counts the total of all types such as:\n"));
4953     }
4954   fprintf (f_usage, NTXT ("            RAW_hit_st_buf         write is still in store buffer\n"
4955                           "            RAW_hit_st_q           write is still in store queue\n"
4956                           "\n"));
4957   if (cpuver == CPC_SPARC_M7)
4958     {
4959       fprintf (f_usage, GTXT ("        == Flush.\n"
4960                               "        One can count the number of times the pipeline must be flushed:\n"));
4961       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4962                NTXT ("Flush_L3_miss"), GTXT ("load missed L3 and >1 strand is active on the core"));
4963       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4964                NTXT ("Flush_br_mispred"), GTXT ("branch misprediction"));
4965       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4966                NTXT ("Flush_arch_exception"), GTXT ("SPARC exceptions and trap entry/return"));
4967       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4968                NTXT ("Flush_other"), GTXT ("state change to/from halted/paused"));
4969       fprintf (f_usage, NTXT ("\n"));
4970     }
4971 }
4972
4973 static void
4974 hwc_usage_internal (int forKernel, FILE *f_usage, const char *cmd, const char *dataspace_msg, int show_syntax, int show_short_desc)
4975 {
4976   if (!VALID_FOR_KERNEL (forKernel))
4977     return;
4978   char cpuname[128];
4979   hwc_get_cpuname (cpuname, 128);
4980   Hwcentry** raw_ctrs = hwc_get_raw_ctrs (forKernel);
4981   int has_raw_ctrs = (raw_ctrs && raw_ctrs[0]);
4982   Hwcentry** std_ctrs = hwc_get_std_ctrs (forKernel);
4983   int has_std_ctrs = (std_ctrs && std_ctrs[0]);
4984   unsigned hwc_maxregs = hwc_get_max_concurrent (forKernel);
4985   int cpuver = hwc_get_cpc_cpuver ();
4986   if (hwc_maxregs != 0)
4987     {
4988       if (show_syntax)
4989         {
4990           fprintf (f_usage, GTXT ("\nSpecifying HW counters on `%s' (cpuver=%d):\n\n"), cpuname, cpuver);
4991           fprintf (f_usage, GTXT ("    -h {auto|lo|on|hi}\n"));
4992           fprintf (f_usage, GTXT ("\tturn on default set of HW counters at the specified rate\n"));
4993           if (hwc_maxregs == 1)
4994             {
4995               fprintf (f_usage, GTXT ("    -h <ctr_def>\n"));
4996               fprintf (f_usage, GTXT ("\tspecify HW counter profiling for one HW counter only\n"));
4997             }
4998           else
4999             {
5000               fprintf (f_usage, GTXT ("    -h <ctr_def> [-h <ctr_def>]...\n"));
5001               fprintf (f_usage, GTXT ("    -h <ctr_def>[,<ctr_def>]...\n"));
5002               fprintf (f_usage, GTXT ("\tspecify HW counter profiling for up to %u HW counters\n"), hwc_maxregs);
5003             }
5004           fprintf (f_usage, NTXT ("\n"));
5005         }
5006       else
5007         {
5008           fprintf (f_usage, GTXT ("\nSpecifying HW counters on `%s' (cpuver=%d)\n\n"), cpuname, cpuver);
5009           if (hwc_maxregs == 1)
5010             fprintf (f_usage, GTXT ("           Hardware counter profiling is supported for only one counter.\n"));
5011           else
5012             fprintf (f_usage, GTXT ("           Hardware counter profiling is supported for up to %u HW counters.\n"), hwc_maxregs);
5013         }
5014     }
5015   else
5016     {
5017       if (!IS_KERNEL (forKernel))
5018         { // EUGENE I don't see why we don't also use this for er_kernel
5019           char buf[1024];
5020           *buf = 0;
5021           char *pch = hwcfuncs_errmsg_get (buf, sizeof (buf), 0);
5022           if (*pch)
5023             fprintf (f_usage, GTXT ("HW counter profiling is not supported on this system: %s%s"),
5024                      pch, pch[strlen (pch) - 1] == '\n' ? "" : "\n");
5025           else
5026             fprintf (f_usage, GTXT ("HW counter profiling is not supported on this system\n"));
5027         }
5028       return;
5029     }
5030
5031   /* At this point, we know we have counters */
5032   char**hwc_attrs = hwc_get_attrs (forKernel);
5033   int has_attrs = (hwc_attrs && hwc_attrs[0]);
5034   if (show_syntax)
5035     {
5036       const char *reg_s = show_regs ? "[/<reg#>]" : "";
5037       const char *attr_s = has_attrs ? "[[~<attr>=<val>]...]" : "";
5038       fprintf (f_usage, GTXT ("    <ctr_def> == <ctr>%s%s,[<rate>]\n"), attr_s, reg_s);
5039       if (dataspace_msg)
5040         fprintf (f_usage, NTXT ("%s"), dataspace_msg);
5041       fprintf (f_usage, GTXT ("        <ctr>\n"));
5042       fprintf (f_usage, GTXT ("           counter name, "));
5043     }
5044   else
5045     fprintf (f_usage, GTXT ("           Counter name "));
5046   fprintf (f_usage, GTXT ("must be selected from the available counters\n"
5047                           "           listed below.  On most systems, if a counter is not listed\n"
5048                           "           below, it may still be specified by its numeric value.\n"));
5049   if (cpcx_has_precise[forKernel])
5050     {
5051       if (!forKernel)
5052         fprintf (f_usage, GTXT ("           Counters labeled as 'memoryspace' in the list below will\n"
5053                                 "           collect memoryspace data by default.\n"));
5054     }
5055   fprintf (f_usage, GTXT ("\n"));
5056   if (has_attrs)
5057     {
5058       if (show_syntax)
5059         {
5060           fprintf (f_usage, GTXT ("        ~<attr>=<val>\n"));
5061           fprintf (f_usage, GTXT ("           optional attribute where <val> can be in decimal or hex\n"
5062                                   "           format, and <attr> can be one of: \n"));
5063         }
5064       else
5065         fprintf (f_usage, GTXT ("           Optional attribute where <val> can be in decimal or hex\n"
5066                                 "           format, and <attr> can be one of: \n"));
5067       for (char **pattr = hwc_attrs; *pattr; pattr++)
5068         fprintf (f_usage, NTXT ("             `%s'\n"), *pattr);
5069       if (show_syntax)
5070         fprintf (f_usage, GTXT ("           Multiple attributes may be specified, and each must be preceded by a ~.\n\n"));
5071       else
5072         fprintf (f_usage, GTXT ("           Multiple attributes may be specified.\n\n"));
5073       if (IS_KERNEL (forKernel))
5074         fprintf (f_usage, GTXT ("           Other attributes may be supported by the chip, but are not supported by DTrace and will be ignored by er_kernel.\n\n"));
5075     }
5076
5077   if (show_syntax)
5078     {
5079       if (show_regs)
5080         fprintf (f_usage, GTXT ("        /<reg#>\n"
5081                                 "           forces use of a specific hardware register.  (Solaris only)\n"
5082                                 "           If not specified, %s will attempt to place the counter into the first\n"
5083                                 "           available register and as a result may be unable to place\n"
5084                                 "           subsequent counters due to register conflicts.\n"
5085                                 "           The / in front of the register number is required if a register is specified.\n\n"),
5086                  cmd);
5087
5088       fprintf (f_usage, GTXT ("        <rate> == {auto|lo|on|hi}\n"));
5089       fprintf (f_usage, GTXT ("           `auto'   (default) match the rate used by clock profiling.\n"));
5090       fprintf (f_usage, GTXT ("                    If clock profiling is disabled, use `on'.\n"));
5091       fprintf (f_usage, GTXT ("           `lo'     per-thread maximum rate of ~10 samples/second\n"));
5092       fprintf (f_usage, GTXT ("           `on'     per-thread maximum rate of ~100 samples/second\n"));
5093       fprintf (f_usage, GTXT ("           `hi'     per-thread maximum rate of ~1000 samples/second\n\n"));
5094       fprintf (f_usage, GTXT ("        <rate> == <interval>\n"));
5095       fprintf (f_usage, GTXT ("           event interval; see collect (1) for details\n\n"));
5096
5097       fprintf (f_usage, GTXT ("        A comma ',' followed immediately by white space may be omitted.\n\n"));
5098     }
5099
5100   /* default counters */
5101   fprintf (f_usage, GTXT ("Default set of HW counters:\n\n"));
5102   char * defctrs = hwc_get_default_cntrs2 (forKernel, 1);
5103   if (defctrs == NULL)
5104     fprintf (f_usage, GTXT ("    No default HW counter set defined for this system.\n"));
5105   else if (strlen (defctrs) == 0)
5106     {
5107       char *s = hwc_get_orig_default_cntrs (forKernel);
5108       fprintf (f_usage, GTXT ("    The default HW counter set (%s) defined for %s cannot be loaded on this system.\n"),
5109                s, cpuname);
5110       free (s);
5111       free (defctrs);
5112     }
5113   else
5114     {
5115       char *defctrs2 = hwc_get_default_cntrs2 (forKernel, 2);
5116       fprintf (f_usage, GTXT ("    -h %s\n"), defctrs);
5117       free (defctrs2);
5118       free (defctrs);
5119     }
5120
5121   /* long listings */
5122   char tmp[1024];
5123   if (has_std_ctrs)
5124     {
5125       fprintf (f_usage, GTXT ("\nAliases for most useful HW counters:\n\n"));
5126       format_columns (tmp, 1024, "alias", "raw name", "type ", "units", "regs", "description");
5127       fprintf (f_usage, NTXT ("    %s\n\n"), tmp);
5128       for (Hwcentry **pctr = std_ctrs; *pctr; pctr++)
5129         {
5130           Hwcentry *ctr = *pctr;
5131           hwc_hwcentry_string_internal (tmp, sizeof (tmp), ctr, 0);
5132           fprintf (f_usage, NTXT ("    %s\n"), tmp);
5133         }
5134     }
5135   if (has_raw_ctrs)
5136     {
5137       fprintf (f_usage, GTXT ("\nRaw HW counters:\n\n"));
5138       hwc_usage_raw_overview_sparc (f_usage, cpuver);
5139       format_columns (tmp, 1024, "name", NULL, "type ", "units", "regs", "description");
5140       fprintf (f_usage, NTXT ("    %s\n\n"), tmp);
5141       for (Hwcentry **pctr = raw_ctrs; *pctr; pctr++)
5142         {
5143           Hwcentry *ctr = *pctr;
5144           hwc_hwcentry_string_internal (tmp, sizeof (tmp), ctr, show_short_desc);
5145           fprintf (f_usage, NTXT ("    %s\n"), tmp);
5146         }
5147     }
5148
5149   /* documentation notice */
5150   hwc_get_docref (tmp, 1024);
5151   if (strlen (tmp))
5152     fprintf (f_usage, NTXT ("\n%s\n"), tmp);
5153 }
5154
5155 /* Print a description of "-h" usage, largely common to collect and er_kernel. */
5156 void
5157 hwc_usage (int forKernel, const char *cmd, const char *dataspace_msg)
5158 {
5159   hwc_usage_internal (forKernel, stdout, cmd, dataspace_msg, 1, 0);
5160 }
5161
5162 void
5163 hwc_usage_f (int forKernel, FILE *f, const char *cmd, const char *dataspace_msg, int show_syntax, int show_short_desc)
5164 {
5165   hwc_usage_internal (forKernel, f, cmd, dataspace_msg, show_syntax, show_short_desc);
5166 }
5167
5168 /*---------------------------------------------------------------------------*/
5169 /* init functions */
5170
5171 static char* supported_pebs_counters[] = {
5172   "mem_inst_retired.latency_above_threshold",
5173   "mem_trans_retired.load_latency",
5174   "mem_trans_retired.precise_store",
5175   NULL
5176 };
5177
5178 /* callback, (see setup_cpc()) called for each valid regno/name combo */
5179
5180 /* builds rawlist,, creates and updates reg_list[] arrays in stdlist table */
5181 static void
5182 hwc_cb (uint_t cpc_regno, const char *name)
5183 {
5184   regno_t regno = cpc_regno; /* convert type */
5185   list_add (&unfiltered_raw, regno, name);
5186 }
5187
5188 /* input:
5189  *   forKernel: 1 - generate lists for er_kernel, 0 - generate lists for collect
5190  *
5191  *   raw_orig: HWCs as generated by hwc_cb()
5192  * output:
5193  *   pstd_out[], praw_out[]: malloc'd array of pointers to malloc'd hwcentry, or NULL
5194  */
5195 static void
5196 hwc_process_raw_ctrs (int forKernel, Hwcentry ***pstd_out,
5197                       Hwcentry ***praw_out, Hwcentry ***phidden_out,
5198                       Hwcentry**static_tables, Hwcentry **raw_unfiltered_in)
5199 {
5200   // set up output buffers
5201   ptr_list s_outbufs[3];
5202   ptr_list *std_out = &s_outbufs[0];
5203   ptr_list_init (std_out);
5204   ptr_list *raw_out = &s_outbufs[1];
5205   ptr_list_init (raw_out);
5206   ptr_list *hidden_out = &s_outbufs[2];
5207   ptr_list_init (hidden_out);
5208
5209 #define NUM_TABLES 3
5210   ptr_list table_copy[NUM_TABLES]; // copy of data from static tables. [0]std, [1]generic, and [2]hidden
5211   for (int tt = 0; tt < NUM_TABLES; tt++)
5212     ptr_list_init (&table_copy[tt]);
5213
5214   // copy records from std [0] and generic [1] static input tables into table_copy[0],[1],or[2]
5215   for (int tt = 0; tt < 2; tt++)
5216     for (Hwcentry *pctr = static_tables[tt]; pctr && pctr->name; pctr++)
5217       if (is_hidden_alias (pctr))
5218         list_append_shallow_copy (&table_copy[2], pctr); // hidden list
5219       else
5220         list_append_shallow_copy (&table_copy[tt], pctr);
5221
5222   // copy raw_unfiltered_in to raw_out
5223   for (int ii = 0; raw_unfiltered_in && raw_unfiltered_in[ii]; ii++)
5224     {
5225       Hwcentry *pctr = raw_unfiltered_in[ii];
5226       // filter out raw counters that don't work correctly
5227
5228 #ifdef WORKAROUND_6231196_NIAGARA1_NO_CTR_0
5229       if (cpcx_cpuver == CPC_ULTRA_T1)
5230         if (!regno_is_valid (pctr, 1))
5231           continue;   /* Niagara can not profile on register zero; skip this */
5232 #endif
5233       // remove specific PEBs counters when back end doesn't support sampling
5234       const char *name = pctr->name;
5235       if ((cpcx_support_bitmask & HWCFUNCS_SUPPORT_PEBS_SAMPLING) == 0 || forKernel)
5236         {
5237           int skip = 0;
5238           for (int ii = 0; supported_pebs_counters[ii]; ii++)
5239             if (strcmp (supported_pebs_counters[ii], name) == 0)
5240               {
5241                 skip = 1;
5242                 break;
5243               }
5244           if (skip)
5245             continue;
5246         }
5247
5248       Hwcentry *pnew = list_append_shallow_copy (raw_out, pctr);
5249 #ifdef WORKAROUND_6231196_NIAGARA1_NO_CTR_0
5250       if (cpcx_cpuver == CPC_ULTRA_T1)
5251         {
5252           free (pnew->reg_list);
5253           pnew->reg_list = NULL;
5254           regno_add (pnew, 1); // only allow register 1
5255         }
5256 #endif
5257     } // raw_unfiltered_in
5258
5259   // Scan raw counters to populate Hwcentry fields from matching static_tables entries
5260   // Also populate reg_list for aliases found in table_copy[]
5261   for (int uu = 0; uu < raw_out->sz; uu++)
5262     {
5263       Hwcentry *praw = (Hwcentry*) raw_out->array[uu];
5264       Hwcentry *pstd = NULL; // set if non-alias entry from std table matches
5265       char *name = praw->name;
5266       /* in the standard counter and generic lists,
5267          update reg_list for all matching items  */
5268       for (int tt = 0; tt < NUM_TABLES; tt++)
5269         { // std, generic, and hidden
5270           if (table_copy[tt].sz == 0)
5271             continue;
5272           Hwcentry **array = (Hwcentry**) table_copy[tt].array;
5273           for (int jj = 0; array[jj]; jj++)
5274             { // all table counters
5275               Hwcentry *pctr = array[jj];
5276               char *pname;
5277               if (pctr->int_name)
5278                 pname = pctr->int_name;
5279               else
5280                 pname = pctr->name;
5281               if (!is_same (name, pname, '~'))
5282                 continue;
5283
5284               /* truncated pname matches <name>... */
5285               // check to see if table entry applies only to specific register
5286               int specific_reg_num_only = 0;
5287               if (pctr->reg_num != REGNO_ANY)
5288                 {
5289                   // table entry applies only to specific register
5290                   if (!regno_is_valid (praw, pctr->reg_num))
5291                     continue;
5292                   specific_reg_num_only = 1;
5293                 }
5294
5295               // Match!
5296               // Update cpu_table_copy's supported registers
5297               if (specific_reg_num_only)
5298                 regno_add (pctr, pctr->reg_num);
5299               else
5300                 pctr->reg_list = praw->reg_list;
5301
5302               if (!is_visible_alias (pctr) && !is_hidden_alias (pctr))
5303                 {
5304                   // Note: we could expand criteria to also allow aliases to set default rates for raw HWCs
5305                   /* This is an 'internal' raw counter */
5306                   if (!pstd)
5307                     pstd = pctr; /* use info as a template when adding to raw list */
5308                   else
5309                     hwcentry_print (DBG_LT0, "hwctable: hwc_cb: Warning: "
5310                                     "counter %s appears in table more than once: ",
5311                                     pstd);
5312                 }
5313             }/* for table rows */
5314         }/* for std and generic tables */
5315
5316       if (pstd)
5317         {
5318           /* the main table had an entry that matched <name> exactly */
5319           /* Apply the main table entry as a template */
5320           *praw = *pstd;
5321         }
5322     }/* for (raw_out) */
5323
5324   // update std_out and hidden_out
5325   for (int tt = 0; tt < NUM_TABLES; tt++)
5326     {
5327       if (tt == 1 /*skip std_raw*/ || table_copy[tt].sz == 0)
5328         continue;
5329       Hwcentry *pctr;
5330       for (int ii = 0; (pctr = table_copy[tt].array[ii]); ii++)
5331         {
5332           // prune unsupported rows from std table
5333           if (!is_visible_alias (pctr) && !is_hidden_alias (pctr))
5334             continue; // only aliases
5335           if (REG_LIST_IS_EMPTY (pctr->reg_list))
5336             {
5337               if (is_numeric_alias (pctr))
5338                 {
5339 #if 1 //22844570 DTrace cpc provider does not accept numeric counter names
5340                   if (forKernel)
5341                     continue;
5342 #endif
5343                   regno_add (pctr, REGNO_ANY); // hwcs specified by number allowed on any register
5344                 }
5345               else
5346                 continue;
5347             }
5348
5349           ptr_list *dest = (tt == 0) ? std_out : hidden_out;
5350           Hwcentry *isInList;
5351           if (pctr->short_desc == NULL)
5352             {
5353               isInList = ptrarray_find_by_name ((Hwcentry**) raw_out->array, pctr->int_name);
5354               if (isInList)
5355                 pctr->short_desc = isInList->short_desc; // copy the raw counter's detailed description
5356             }
5357           isInList = ptrarray_find_by_name ((Hwcentry**) dest->array, pctr->name);
5358           if (isInList)
5359             hwcentry_print (DBG_LT0, "hwctable: hwc_cb: Warning: "
5360                             "counter %s appears in alias list more than once: ",
5361                             pctr);
5362           else
5363             list_append_shallow_copy (dest, pctr);
5364         }
5365     }
5366   for (int tt = 0; tt < NUM_TABLES; tt++)
5367     ptr_list_free (&table_copy[tt]);
5368
5369   if (forKernel)
5370     {
5371       // for er_kernel, use baseline value of PRELOAD_DEF_ERKERNEL instead of PRELOAD_DEF
5372       for (int tt = 0; tt < 3; tt++)
5373         { // std_out-0, raw_out-1, hidden_out-2
5374           Hwcentry** hwcs = (Hwcentry**) (s_outbufs[tt].array);
5375           for (int ii = 0; hwcs && hwcs[ii]; ii++)
5376             {
5377               Hwcentry *hwc = hwcs[ii];
5378               if (hwc->val == PRELOAD_DEF)
5379                 hwc->val = PRELOAD_DEF_ERKERNEL;
5380             }
5381         }
5382     }
5383   *pstd_out = (Hwcentry**) std_out->array;
5384   *praw_out = (Hwcentry**) raw_out->array;
5385   *phidden_out = (Hwcentry**) hidden_out->array;
5386 }
5387
5388 /* callback, (see setup_cpc()) called for each valid attribute */
5389 /* builds attrlist */
5390 static void
5391 attrs_cb (const char *attr)
5392 {
5393   Tprintf (DBG_LT3, "hwctable: attrs_cb(): %s\n", attr);
5394   if (strcmp (attr, "picnum") == 0)
5395     return;     /* don't make this attribute available to users */
5396   ptr_list_add (&unfiltered_attrs, (void*) strdup (attr));
5397 }
5398
5399 /* returns true if attribute is valid for this platform */
5400 static int
5401 attr_is_valid (int forKernel, const char *attr)
5402 {
5403   setup_cpcx ();
5404   if (!VALID_FOR_KERNEL (forKernel) || !cpcx_attrs[forKernel])
5405     return 0;
5406   for (int ii = 0; cpcx_attrs[forKernel][ii]; ii++)
5407     if (strcmp (attr, cpcx_attrs[forKernel][ii]) == 0)
5408       return 1;
5409   return 0;
5410 }