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[binutils.git] / include / opcode / score-inst.h
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1 /* score-inst.h -- Score Instructions Table
2 Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by:
4 Brain.lin (brain.lin@sunplusct.com)
5 Mei Ligang (ligang@sunnorth.com.cn)
6 Pei-Lin Tsai (pltsai@sunplus.com)
8 This file is part of GAS, the GNU Assembler.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING3. If not, write to the Free
22 Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
23 02110-1301, USA. */
25 #ifndef SCORE_INST_H
26 #define SCORE_INST_H
28 #define LDST_UNALIGN_MASK 0x0000007f
29 #define UA_LCB 0x00000060
30 #define UA_LCW 0x00000062
31 #define UA_LCE 0x00000066
32 #define UA_SCB 0x00000068
33 #define UA_SCW 0x0000006a
34 #define UA_SCE 0x0000006e
35 #define UA_LL 0x0000000c
36 #define UA_SC 0x0000000e
37 #define LDST16_RR_MASK 0x0000000f
38 #define N16_LW 8
39 #define N16_LH 9
40 #define N16_POP 10
41 #define N16_LBU 11
42 #define N16_SW 12
43 #define N16_SH 13
44 #define N16_PUSH 14
45 #define N16_SB 15
46 #define LDST16_RI_MASK 0x7007
47 #define N16_LWP 0x7000
48 #define N16_LHP 0x7001
49 #define N16_LBUP 0x7003
50 #define N16_SWP 0x7004
51 #define N16_SHP 0x7005
52 #define N16_SBP 0x7007
53 #define N16_LIU 0x5000
55 #define OPC_PSEUDOLDST_MASK 0x00000007
57 enum
59 INSN_LW = 0,
60 INSN_LH = 1,
61 INSN_LHU = 2,
62 INSN_LB = 3,
63 INSN_SW = 4,
64 INSN_SH = 5,
65 INSN_LBU = 6,
66 INSN_SB = 7,
69 /* Sub opcdoe opcode. */
70 enum
72 INSN16_LBU = 11,
73 INSN16_LH = 9,
74 INSN16_LW = 8,
75 INSN16_SB = 15,
76 INSN16_SH = 13,
77 INSN16_SW = 12,
80 enum
82 LDST_NOUPDATE = 0,
83 LDST_PRE = 1,
84 LDST_POST = 2,
87 enum score_insn_type
89 Rd_I4,
90 Rd_I5,
91 Rd_rvalueBP_I5,
92 Rd_lvalueBP_I5,
93 Rd_Rs_I5,
94 x_Rs_I5,
95 x_I5_x,
96 Rd_I8,
97 Rd_Rs_I14,
98 I15,
99 Rd_I16,
100 Rd_I30,
101 Rd_I32,
102 Rd_rvalueRs_SI10,
103 Rd_lvalueRs_SI10,
104 Rd_rvalueRs_preSI12,
105 Rd_rvalueRs_postSI12,
106 Rd_lvalueRs_preSI12,
107 Rd_lvalueRs_postSI12,
108 Rd_Rs_SI14,
109 Rd_rvalueRs_SI15,
110 Rd_lvalueRs_SI15,
111 Rd_SI5,
112 Rd_SI6,
113 Rd_SI16,
114 PC_DISP8div2,
115 PC_DISP11div2,
116 PC_DISP19div2,
117 PC_DISP24div2,
118 Rd_Rs_Rs,
119 x_Rs_x,
120 x_Rs_Rs,
121 Rd_Rs_x,
122 Rd_x_Rs,
123 Rd_x_x,
124 Rd_Rs,
125 Rd_HighRs,
126 Rd_lvalueRs,
127 Rd_rvalueRs,
128 Rd_lvalue32Rs,
129 Rd_rvalue32Rs,
130 x_Rs,
131 NO_OPD,
132 NO16_OPD,
133 OP5_rvalueRs_SI15,
134 I5_Rs_Rs_I5_OP5,
135 x_rvalueRs_post4,
136 Rd_rvalueRs_post4,
137 Rd_x_I5,
138 Rd_lvalueRs_post4,
139 x_lvalueRs_post4,
140 Rd_LowRs,
141 Rd_Rs_Rs_imm,
142 Insn_Type_PCE,
143 Insn_Type_SYN,
144 Insn_GP,
145 Insn_PIC,
146 Insn_internal,
147 Insn_BCMP,
148 Ra_I9_I5,
151 enum score_data_type
153 _IMM4 = 0,
154 _IMM5,
155 _IMM8,
156 _IMM14,
157 _IMM15,
158 _IMM16,
159 _SIMM10 = 6,
160 _SIMM12,
161 _SIMM14,
162 _SIMM15,
163 _SIMM16,
164 _SIMM14_NEG = 11,
165 _IMM16_NEG,
166 _SIMM16_NEG,
167 _IMM20,
168 _IMM25,
169 _DISP8div2 = 16,
170 _DISP11div2,
171 _DISP19div2,
172 _DISP24div2,
173 _VALUE,
174 _VALUE_HI16,
175 _VALUE_LO16,
176 _VALUE_LDST_LO16 = 23,
177 _SIMM16_LA,
178 _IMM5_RSHIFT_1,
179 _IMM5_RSHIFT_2,
180 _SIMM16_LA_POS,
181 _IMM5_RANGE_8_31,
182 _IMM10_RSHIFT_2,
183 _GP_IMM15 = 30,
184 _GP_IMM14 = 31,
185 _SIMM16_pic = 42, /* Index in score_df_range. */
186 _IMM16_LO16_pic = 43,
187 _IMM16_pic = 44,
189 _SIMM5 = 45,
190 _SIMM6 = 46,
191 _IMM32 = 47,
192 _SIMM32 = 48,
193 _IMM11 = 49,
194 _IMM5_MULTI_LOAD = 50,
197 #define REG_TMP 1
199 #define OP_REG_TYPE (1 << 6)
200 #define OP_IMM_TYPE (1 << 7)
201 #define OP_SH_REGD (OP_REG_TYPE |20)
202 #define OP_SH_REGS1 (OP_REG_TYPE |15)
203 #define OP_SH_REGS2 (OP_REG_TYPE |10)
204 #define OP_SH_I (OP_IMM_TYPE | 1)
205 #define OP_SH_RI15 (OP_IMM_TYPE | 0)
206 #define OP_SH_I12 (OP_IMM_TYPE | 3)
207 #define OP_SH_DISP24 (OP_IMM_TYPE | 1)
208 #define OP_SH_DISP19_p1 (OP_IMM_TYPE |15)
209 #define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1)
210 #define OP_SH_I5 (OP_IMM_TYPE |10)
211 #define OP_SH_I10 (OP_IMM_TYPE | 5)
212 #define OP_SH_COPID (OP_IMM_TYPE | 5)
213 #define OP_SH_TRAPI5 (OP_IMM_TYPE |15)
214 #define OP_SH_I15 (OP_IMM_TYPE |10)
216 #define OP16_SH_REGD (OP_REG_TYPE | 8)
217 #define OP16_SH_REGS1 (OP_REG_TYPE | 4)
218 #define OP16_SH_I45 (OP_IMM_TYPE | 3)
219 #define OP16_SH_I8 (OP_IMM_TYPE | 0)
220 #define OP16_SH_DISP8 (OP_IMM_TYPE | 0)
221 #define OP16_SH_DISP11 (OP_IMM_TYPE | 1)
223 enum insn_class
225 INSN_CLASS_16,
226 INSN_CLASS_32,
227 INSN_CLASS_48,
228 INSN_CLASS_PCE,
229 INSN_CLASS_SYN
232 /* s3_s7: Globals for both tc-score.c and elf32-score.c. */
233 extern int score3;
234 extern int score7;
236 #endif