opcodes/m32r-ibld.c

   1 /* Instruction building/extraction support for m32r. -*- C -*-
   2
   3    THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
   4    - the resultant file is machine generated, cgen-ibld.in isn't
   5
   6    Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007,
   7    2008, 2010  Free Software Foundation, Inc.
   8
   9    This file is part of libopcodes.
  10
  11    This library is free software; you can redistribute it and/or modify
  12    it under the terms of the GNU General Public License as published by
  13    the Free Software Foundation; either version 3, or (at your option)
  14    any later version.
  15
  16    It is distributed in the hope that it will be useful, but WITHOUT
  17    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  18    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  19    License for more details.
  20
  21    You should have received a copy of the GNU General Public License
  22    along with this program; if not, write to the Free Software Foundation, Inc.,
  23    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  24
  25 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  26    Keep that in mind.  */
  27
  28 #include "sysdep.h"
  29 #include <stdio.h>
  30 #include "ansidecl.h"
  31 #include "dis-asm.h"
  32 #include "bfd.h"
  33 #include "symcat.h"
  34 #include "m32r-desc.h"
  35 #include "m32r-opc.h"
  36 #include "cgen/basic-modes.h"
  37 #include "opintl.h"
  38 #include "safe-ctype.h"
  39
  40 #undef  min
  41 #define min(a,b) ((a) < (b) ? (a) : (b))
  42 #undef  max
  43 #define max(a,b) ((a) > (b) ? (a) : (b))
  44
  45 /* Used by the ifield rtx function.  */
  46 #define FLD(f) (fields->f)
  47
  48 static const char * insert_normal
  49   (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
  50    unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
  51 static const char * insert_insn_normal
  52   (CGEN_CPU_DESC, const CGEN_INSN *,
  53    CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
  54 static int extract_normal
  55   (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
  56    unsigned int, unsigned int, unsigned int, unsigned int,
  57    unsigned int, unsigned int, bfd_vma, long *);
  58 static int extract_insn_normal
  59   (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
  60    CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
  61 #if CGEN_INT_INSN_P
  62 static void put_insn_int_value
  63   (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
  64 #endif
  65 #if ! CGEN_INT_INSN_P
  66 static CGEN_INLINE void insert_1
  67   (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
  68 static CGEN_INLINE int fill_cache
  69   (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma);
  70 static CGEN_INLINE long extract_1
  71   (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
  72 #endif
  73 \f
  74 /* Operand insertion.  */
  75
  76 #if ! CGEN_INT_INSN_P
  77
  78 /* Subroutine of insert_normal.  */
  79
  80 static CGEN_INLINE void
  81 insert_1 (CGEN_CPU_DESC cd,
  82           unsigned long value,
  83           int start,
  84           int length,
  85           int word_length,
  86           unsigned char *bufp)
  87 {
  88   unsigned long x,mask;
  89   int shift;
  90
  91   x = cgen_get_insn_value (cd, bufp, word_length);
  92
  93   /* Written this way to avoid undefined behaviour.  */
  94   mask = (((1L << (length - 1)) - 1) << 1) | 1;
  95   if (CGEN_INSN_LSB0_P)
  96     shift = (start + 1) - length;
  97   else
  98     shift = (word_length - (start + length));
  99   x = (x & ~(mask << shift)) | ((value & mask) << shift);
 100
 101   cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
 102 }
 103
 104 #endif /* ! CGEN_INT_INSN_P */
 105
 106 /* Default insertion routine.
 107
 108    ATTRS is a mask of the boolean attributes.
 109    WORD_OFFSET is the offset in bits from the start of the insn of the value.
 110    WORD_LENGTH is the length of the word in bits in which the value resides.
 111    START is the starting bit number in the word, architecture origin.
 112    LENGTH is the length of VALUE in bits.
 113    TOTAL_LENGTH is the total length of the insn in bits.
 114
 115    The result is an error message or NULL if success.  */
 116
 117 /* ??? This duplicates functionality with bfd's howto table and
 118    bfd_install_relocation.  */
 119 /* ??? This doesn't handle bfd_vma's.  Create another function when
 120    necessary.  */
 121
 122 static const char *
 123 insert_normal (CGEN_CPU_DESC cd,
 124                long value,
 125                unsigned int attrs,
 126                unsigned int word_offset,
 127                unsigned int start,
 128                unsigned int length,
 129                unsigned int word_length,
 130                unsigned int total_length,
 131                CGEN_INSN_BYTES_PTR buffer)
 132 {
 133   static char errbuf[100];
 134   /* Written this way to avoid undefined behaviour.  */
 135   unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
 136
 137   /* If LENGTH is zero, this operand doesn't contribute to the value.  */
 138   if (length == 0)
 139     return NULL;
 140
 141   if (word_length > 8 * sizeof (CGEN_INSN_INT))
 142     abort ();
 143
 144   /* For architectures with insns smaller than the base-insn-bitsize,
 145      word_length may be too big.  */
 146   if (cd->min_insn_bitsize < cd->base_insn_bitsize)
 147     {
 148       if (word_offset == 0
 149           && word_length > total_length)
 150         word_length = total_length;
 151     }
 152
 153   /* Ensure VALUE will fit.  */
 154   if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
 155     {
 156       long minval = - (1L << (length - 1));
 157       unsigned long maxval = mask;
 158
 159       if ((value > 0 && (unsigned long) value > maxval)
 160           || value < minval)
 161         {
 162           /* xgettext:c-format */
 163           sprintf (errbuf,
 164                    _("operand out of range (%ld not between %ld and %lu)"),
 165                    value, minval, maxval);
 166           return errbuf;
 167         }
 168     }
 169   else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
 170     {
 171       unsigned long maxval = mask;
 172       unsigned long val = (unsigned long) value;
 173
 174       /* For hosts with a word size > 32 check to see if value has been sign
 175          extended beyond 32 bits.  If so then ignore these higher sign bits
 176          as the user is attempting to store a 32-bit signed value into an
 177          unsigned 32-bit field which is allowed.  */
 178       if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
 179         val &= 0xFFFFFFFF;
 180
 181       if (val > maxval)
 182         {
 183           /* xgettext:c-format */
 184           sprintf (errbuf,
 185                    _("operand out of range (0x%lx not between 0 and 0x%lx)"),
 186                    val, maxval);
 187           return errbuf;
 188         }
 189     }
 190   else
 191     {
 192       if (! cgen_signed_overflow_ok_p (cd))
 193         {
 194           long minval = - (1L << (length - 1));
 195           long maxval =   (1L << (length - 1)) - 1;
 196
 197           if (value < minval || value > maxval)
 198             {
 199               sprintf
 200                 /* xgettext:c-format */
 201                 (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
 202                  value, minval, maxval);
 203               return errbuf;
 204             }
 205         }
 206     }
 207
 208 #if CGEN_INT_INSN_P
 209
 210   {
 211     int shift;
 212
 213     if (CGEN_INSN_LSB0_P)
 214       shift = (word_offset + start + 1) - length;
 215     else
 216       shift = total_length - (word_offset + start + length);
 217     *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
 218   }
 219
 220 #else /* ! CGEN_INT_INSN_P */
 221
 222   {
 223     unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
 224
 225     insert_1 (cd, value, start, length, word_length, bufp);
 226   }
 227
 228 #endif /* ! CGEN_INT_INSN_P */
 229
 230   return NULL;
 231 }
 232
 233 /* Default insn builder (insert handler).
 234    The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
 235    that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
 236    recorded in host byte order, otherwise BUFFER is an array of bytes
 237    and the value is recorded in target byte order).
 238    The result is an error message or NULL if success.  */
 239
 240 static const char *
 241 insert_insn_normal (CGEN_CPU_DESC cd,
 242                     const CGEN_INSN * insn,
 243                     CGEN_FIELDS * fields,
 244                     CGEN_INSN_BYTES_PTR buffer,
 245                     bfd_vma pc)
 246 {
 247   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 248   unsigned long value;
 249   const CGEN_SYNTAX_CHAR_TYPE * syn;
 250
 251   CGEN_INIT_INSERT (cd);
 252   value = CGEN_INSN_BASE_VALUE (insn);
 253
 254   /* If we're recording insns as numbers (rather than a string of bytes),
 255      target byte order handling is deferred until later.  */
 256
 257 #if CGEN_INT_INSN_P
 258
 259   put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
 260                       CGEN_FIELDS_BITSIZE (fields), value);
 261
 262 #else
 263
 264   cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
 265                                         (unsigned) CGEN_FIELDS_BITSIZE (fields)),
 266                        value);
 267
 268 #endif /* ! CGEN_INT_INSN_P */
 269
 270   /* ??? It would be better to scan the format's fields.
 271      Still need to be able to insert a value based on the operand though;
 272      e.g. storing a branch displacement that got resolved later.
 273      Needs more thought first.  */
 274
 275   for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
 276     {
 277       const char *errmsg;
 278
 279       if (CGEN_SYNTAX_CHAR_P (* syn))
 280         continue;
 281
 282       errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
 283                                        fields, buffer, pc);
 284       if (errmsg)
 285         return errmsg;
 286     }
 287
 288   return NULL;
 289 }
 290
 291 #if CGEN_INT_INSN_P
 292 /* Cover function to store an insn value into an integral insn.  Must go here
 293    because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
 294
 295 static void
 296 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 297                     CGEN_INSN_BYTES_PTR buf,
 298                     int length,
 299                     int insn_length,
 300                     CGEN_INSN_INT value)
 301 {
 302   /* For architectures with insns smaller than the base-insn-bitsize,
 303      length may be too big.  */
 304   if (length > insn_length)
 305     *buf = value;
 306   else
 307     {
 308       int shift = insn_length - length;
 309       /* Written this way to avoid undefined behaviour.  */
 310       CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
 311
 312       *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
 313     }
 314 }
 315 #endif
 316 \f
 317 /* Operand extraction.  */
 318
 319 #if ! CGEN_INT_INSN_P
 320
 321 /* Subroutine of extract_normal.
 322    Ensure sufficient bytes are cached in EX_INFO.
 323    OFFSET is the offset in bytes from the start of the insn of the value.
 324    BYTES is the length of the needed value.
 325    Returns 1 for success, 0 for failure.  */
 326
 327 static CGEN_INLINE int
 328 fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 329             CGEN_EXTRACT_INFO *ex_info,
 330             int offset,
 331             int bytes,
 332             bfd_vma pc)
 333 {
 334   /* It's doubtful that the middle part has already been fetched so
 335      we don't optimize that case.  kiss.  */
 336   unsigned int mask;
 337   disassemble_info *info = (disassemble_info *) ex_info->dis_info;
 338
 339   /* First do a quick check.  */
 340   mask = (1 << bytes) - 1;
 341   if (((ex_info->valid >> offset) & mask) == mask)
 342     return 1;
 343
 344   /* Search for the first byte we need to read.  */
 345   for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
 346     if (! (mask & ex_info->valid))
 347       break;
 348
 349   if (bytes)
 350     {
 351       int status;
 352
 353       pc += offset;
 354       status = (*info->read_memory_func)
 355         (pc, ex_info->insn_bytes + offset, bytes, info);
 356
 357       if (status != 0)
 358         {
 359           (*info->memory_error_func) (status, pc, info);
 360           return 0;
 361         }
 362
 363       ex_info->valid |= ((1 << bytes) - 1) << offset;
 364     }
 365
 366   return 1;
 367 }
 368
 369 /* Subroutine of extract_normal.  */
 370
 371 static CGEN_INLINE long
 372 extract_1 (CGEN_CPU_DESC cd,
 373            CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
 374            int start,
 375            int length,
 376            int word_length,
 377            unsigned char *bufp,
 378            bfd_vma pc ATTRIBUTE_UNUSED)
 379 {
 380   unsigned long x;
 381   int shift;
 382
 383   x = cgen_get_insn_value (cd, bufp, word_length);
 384
 385   if (CGEN_INSN_LSB0_P)
 386     shift = (start + 1) - length;
 387   else
 388     shift = (word_length - (start + length));
 389   return x >> shift;
 390 }
 391
 392 #endif /* ! CGEN_INT_INSN_P */
 393
 394 /* Default extraction routine.
 395
 396    INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
 397    or sometimes less for cases like the m32r where the base insn size is 32
 398    but some insns are 16 bits.
 399    ATTRS is a mask of the boolean attributes.  We only need `SIGNED',
 400    but for generality we take a bitmask of all of them.
 401    WORD_OFFSET is the offset in bits from the start of the insn of the value.
 402    WORD_LENGTH is the length of the word in bits in which the value resides.
 403    START is the starting bit number in the word, architecture origin.
 404    LENGTH is the length of VALUE in bits.
 405    TOTAL_LENGTH is the total length of the insn in bits.
 406
 407    Returns 1 for success, 0 for failure.  */
 408
 409 /* ??? The return code isn't properly used.  wip.  */
 410
 411 /* ??? This doesn't handle bfd_vma's.  Create another function when
 412    necessary.  */
 413
 414 static int
 415 extract_normal (CGEN_CPU_DESC cd,
 416 #if ! CGEN_INT_INSN_P
 417                 CGEN_EXTRACT_INFO *ex_info,
 418 #else
 419                 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
 420 #endif
 421                 CGEN_INSN_INT insn_value,
 422                 unsigned int attrs,
 423                 unsigned int word_offset,
 424                 unsigned int start,
 425                 unsigned int length,
 426                 unsigned int word_length,
 427                 unsigned int total_length,
 428 #if ! CGEN_INT_INSN_P
 429                 bfd_vma pc,
 430 #else
 431                 bfd_vma pc ATTRIBUTE_UNUSED,
 432 #endif
 433                 long *valuep)
 434 {
 435   long value, mask;
 436
 437   /* If LENGTH is zero, this operand doesn't contribute to the value
 438      so give it a standard value of zero.  */
 439   if (length == 0)
 440     {
 441       *valuep = 0;
 442       return 1;
 443     }
 444
 445   if (word_length > 8 * sizeof (CGEN_INSN_INT))
 446     abort ();
 447
 448   /* For architectures with insns smaller than the insn-base-bitsize,
 449      word_length may be too big.  */
 450   if (cd->min_insn_bitsize < cd->base_insn_bitsize)
 451     {
 452       if (word_offset + word_length > total_length)
 453         word_length = total_length - word_offset;
 454     }
 455
 456   /* Does the value reside in INSN_VALUE, and at the right alignment?  */
 457
 458   if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
 459     {
 460       if (CGEN_INSN_LSB0_P)
 461         value = insn_value >> ((word_offset + start + 1) - length);
 462       else
 463         value = insn_value >> (total_length - ( word_offset + start + length));
 464     }
 465
 466 #if ! CGEN_INT_INSN_P
 467
 468   else
 469     {
 470       unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
 471
 472       if (word_length > 8 * sizeof (CGEN_INSN_INT))
 473         abort ();
 474
 475       if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
 476         return 0;
 477
 478       value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
 479     }
 480
 481 #endif /* ! CGEN_INT_INSN_P */
 482
 483   /* Written this way to avoid undefined behaviour.  */
 484   mask = (((1L << (length - 1)) - 1) << 1) | 1;
 485
 486   value &= mask;
 487   /* sign extend? */
 488   if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
 489       && (value & (1L << (length - 1))))
 490     value |= ~mask;
 491
 492   *valuep = value;
 493
 494   return 1;
 495 }
 496
 497 /* Default insn extractor.
 498
 499    INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
 500    The extracted fields are stored in FIELDS.
 501    EX_INFO is used to handle reading variable length insns.
 502    Return the length of the insn in bits, or 0 if no match,
 503    or -1 if an error occurs fetching data (memory_error_func will have
 504    been called).  */
 505
 506 static int
 507 extract_insn_normal (CGEN_CPU_DESC cd,
 508                      const CGEN_INSN *insn,
 509                      CGEN_EXTRACT_INFO *ex_info,
 510                      CGEN_INSN_INT insn_value,
 511                      CGEN_FIELDS *fields,
 512                      bfd_vma pc)
 513 {
 514   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 515   const CGEN_SYNTAX_CHAR_TYPE *syn;
 516
 517   CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
 518
 519   CGEN_INIT_EXTRACT (cd);
 520
 521   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 522     {
 523       int length;
 524
 525       if (CGEN_SYNTAX_CHAR_P (*syn))
 526         continue;
 527
 528       length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
 529                                         ex_info, insn_value, fields, pc);
 530       if (length <= 0)
 531         return length;
 532     }
 533
 534   /* We recognized and successfully extracted this insn.  */
 535   return CGEN_INSN_BITSIZE (insn);
 536 }
 537 \f
 538 /* Machine generated code added here.  */
 539
 540 const char * m32r_cgen_insert_operand
 541   (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
 542
 543 /* Main entry point for operand insertion.
 544
 545    This function is basically just a big switch statement.  Earlier versions
 546    used tables to look up the function to use, but
 547    - if the table contains both assembler and disassembler functions then
 548      the disassembler contains much of the assembler and vice-versa,
 549    - there's a lot of inlining possibilities as things grow,
 550    - using a switch statement avoids the function call overhead.
 551
 552    This function could be moved into `parse_insn_normal', but keeping it
 553    separate makes clear the interface between `parse_insn_normal' and each of
 554    the handlers.  It's also needed by GAS to insert operands that couldn't be
 555    resolved during parsing.  */
 556
 557 const char *
 558 m32r_cgen_insert_operand (CGEN_CPU_DESC cd,
 559                              int opindex,
 560                              CGEN_FIELDS * fields,
 561                              CGEN_INSN_BYTES_PTR buffer,
 562                              bfd_vma pc ATTRIBUTE_UNUSED)
 563 {
 564   const char * errmsg = NULL;
 565   unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
 566
 567   switch (opindex)
 568     {
 569     case M32R_OPERAND_ACC :
 570       errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer);
 571       break;
 572     case M32R_OPERAND_ACCD :
 573       errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer);
 574       break;
 575     case M32R_OPERAND_ACCS :
 576       errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer);
 577       break;
 578     case M32R_OPERAND_DCR :
 579       errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
 580       break;
 581     case M32R_OPERAND_DISP16 :
 582       {
 583         long value = fields->f_disp16;
 584         value = ((SI) (((value) - (pc))) >> (2));
 585         errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer);
 586       }
 587       break;
 588     case M32R_OPERAND_DISP24 :
 589       {
 590         long value = fields->f_disp24;
 591         value = ((SI) (((value) - (pc))) >> (2));
 592         errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, buffer);
 593       }
 594       break;
 595     case M32R_OPERAND_DISP8 :
 596       {
 597         long value = fields->f_disp8;
 598         value = ((SI) (((value) - (((pc) & (-4))))) >> (2));
 599         errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer);
 600       }
 601       break;
 602     case M32R_OPERAND_DR :
 603       errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
 604       break;
 605     case M32R_OPERAND_HASH :
 606       break;
 607     case M32R_OPERAND_HI16 :
 608       errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer);
 609       break;
 610     case M32R_OPERAND_IMM1 :
 611       {
 612         long value = fields->f_imm1;
 613         value = ((value) - (1));
 614         errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer);
 615       }
 616       break;
 617     case M32R_OPERAND_SCR :
 618       errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
 619       break;
 620     case M32R_OPERAND_SIMM16 :
 621       errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
 622       break;
 623     case M32R_OPERAND_SIMM8 :
 624       errmsg = insert_normal (cd, fields->f_simm8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer);
 625       break;
 626     case M32R_OPERAND_SLO16 :
 627       errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
 628       break;
 629     case M32R_OPERAND_SR :
 630       errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
 631       break;
 632     case M32R_OPERAND_SRC1 :
 633       errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
 634       break;
 635     case M32R_OPERAND_SRC2 :
 636       errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
 637       break;
 638     case M32R_OPERAND_UIMM16 :
 639       errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
 640       break;
 641     case M32R_OPERAND_UIMM24 :
 642       errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer);
 643       break;
 644     case M32R_OPERAND_UIMM3 :
 645       errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 5, 3, 32, total_length, buffer);
 646       break;
 647     case M32R_OPERAND_UIMM4 :
 648       errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer);
 649       break;
 650     case M32R_OPERAND_UIMM5 :
 651       errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer);
 652       break;
 653     case M32R_OPERAND_UIMM8 :
 654       errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 8, 8, 32, total_length, buffer);
 655       break;
 656     case M32R_OPERAND_ULO16 :
 657       errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
 658       break;
 659
 660     default :
 661       /* xgettext:c-format */
 662       fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
 663                opindex);
 664       abort ();
 665   }
 666
 667   return errmsg;
 668 }
 669
 670 int m32r_cgen_extract_operand
 671   (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
 672
 673 /* Main entry point for operand extraction.
 674    The result is <= 0 for error, >0 for success.
 675    ??? Actual values aren't well defined right now.
 676
 677    This function is basically just a big switch statement.  Earlier versions
 678    used tables to look up the function to use, but
 679    - if the table contains both assembler and disassembler functions then
 680      the disassembler contains much of the assembler and vice-versa,
 681    - there's a lot of inlining possibilities as things grow,
 682    - using a switch statement avoids the function call overhead.
 683
 684    This function could be moved into `print_insn_normal', but keeping it
 685    separate makes clear the interface between `print_insn_normal' and each of
 686    the handlers.  */
 687
 688 int
 689 m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
 690                              int opindex,
 691                              CGEN_EXTRACT_INFO *ex_info,
 692                              CGEN_INSN_INT insn_value,
 693                              CGEN_FIELDS * fields,
 694                              bfd_vma pc)
 695 {
 696   /* Assume success (for those operands that are nops).  */
 697   int length = 1;
 698   unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
 699
 700   switch (opindex)
 701     {
 702     case M32R_OPERAND_ACC :
 703       length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc);
 704       break;
 705     case M32R_OPERAND_ACCD :
 706       length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd);
 707       break;
 708     case M32R_OPERAND_ACCS :
 709       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs);
 710       break;
 711     case M32R_OPERAND_DCR :
 712       length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
 713       break;
 714     case M32R_OPERAND_DISP16 :
 715       {
 716         long value;
 717         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value);
 718         value = ((((value) << (2))) + (pc));
 719         fields->f_disp16 = value;
 720       }
 721       break;
 722     case M32R_OPERAND_DISP24 :
 723       {
 724         long value;
 725         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value);
 726         value = ((((value) << (2))) + (pc));
 727         fields->f_disp24 = value;
 728       }
 729       break;
 730     case M32R_OPERAND_DISP8 :
 731       {
 732         long value;
 733         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
 734         value = ((((value) << (2))) + (((pc) & (-4))));
 735         fields->f_disp8 = value;
 736       }
 737       break;
 738     case M32R_OPERAND_DR :
 739       length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
 740       break;
 741     case M32R_OPERAND_HASH :
 742       break;
 743     case M32R_OPERAND_HI16 :
 744       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16);
 745       break;
 746     case M32R_OPERAND_IMM1 :
 747       {
 748         long value;
 749         length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value);
 750         value = ((value) + (1));
 751         fields->f_imm1 = value;
 752       }
 753       break;
 754     case M32R_OPERAND_SCR :
 755       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
 756       break;
 757     case M32R_OPERAND_SIMM16 :
 758       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
 759       break;
 760     case M32R_OPERAND_SIMM8 :
 761       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_simm8);
 762       break;
 763     case M32R_OPERAND_SLO16 :
 764       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
 765       break;
 766     case M32R_OPERAND_SR :
 767       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
 768       break;
 769     case M32R_OPERAND_SRC1 :
 770       length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
 771       break;
 772     case M32R_OPERAND_SRC2 :
 773       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
 774       break;
 775     case M32R_OPERAND_UIMM16 :
 776       length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
 777       break;
 778     case M32R_OPERAND_UIMM24 :
 779       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
 780       break;
 781     case M32R_OPERAND_UIMM3 :
 782       length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_uimm3);
 783       break;
 784     case M32R_OPERAND_UIMM4 :
 785       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
 786       break;
 787     case M32R_OPERAND_UIMM5 :
 788       length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
 789       break;
 790     case M32R_OPERAND_UIMM8 :
 791       length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_uimm8);
 792       break;
 793     case M32R_OPERAND_ULO16 :
 794       length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
 795       break;
 796
 797     default :
 798       /* xgettext:c-format */
 799       fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
 800                opindex);
 801       abort ();
 802     }
 803
 804   return length;
 805 }
 806
 807 cgen_insert_fn * const m32r_cgen_insert_handlers[] =
 808 {
 809   insert_insn_normal,
 810 };
 811
 812 cgen_extract_fn * const m32r_cgen_extract_handlers[] =
 813 {
 814   extract_insn_normal,
 815 };
 816
 817 int m32r_cgen_get_int_operand     (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
 818 bfd_vma m32r_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
 819
 820 /* Getting values from cgen_fields is handled by a collection of functions.
 821    They are distinguished by the type of the VALUE argument they return.
 822    TODO: floating point, inlining support, remove cases where result type
 823    not appropriate.  */
 824
 825 int
 826 m32r_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 827                              int opindex,
 828                              const CGEN_FIELDS * fields)
 829 {
 830   int value;
 831
 832   switch (opindex)
 833     {
 834     case M32R_OPERAND_ACC :
 835       value = fields->f_acc;
 836       break;
 837     case M32R_OPERAND_ACCD :
 838       value = fields->f_accd;
 839       break;
 840     case M32R_OPERAND_ACCS :
 841       value = fields->f_accs;
 842       break;
 843     case M32R_OPERAND_DCR :
 844       value = fields->f_r1;
 845       break;
 846     case M32R_OPERAND_DISP16 :
 847       value = fields->f_disp16;
 848       break;
 849     case M32R_OPERAND_DISP24 :
 850       value = fields->f_disp24;
 851       break;
 852     case M32R_OPERAND_DISP8 :
 853       value = fields->f_disp8;
 854       break;
 855     case M32R_OPERAND_DR :
 856       value = fields->f_r1;
 857       break;
 858     case M32R_OPERAND_HASH :
 859       value = 0;
 860       break;
 861     case M32R_OPERAND_HI16 :
 862       value = fields->f_hi16;
 863       break;
 864     case M32R_OPERAND_IMM1 :
 865       value = fields->f_imm1;
 866       break;
 867     case M32R_OPERAND_SCR :
 868       value = fields->f_r2;
 869       break;
 870     case M32R_OPERAND_SIMM16 :
 871       value = fields->f_simm16;
 872       break;
 873     case M32R_OPERAND_SIMM8 :
 874       value = fields->f_simm8;
 875       break;
 876     case M32R_OPERAND_SLO16 :
 877       value = fields->f_simm16;
 878       break;
 879     case M32R_OPERAND_SR :
 880       value = fields->f_r2;
 881       break;
 882     case M32R_OPERAND_SRC1 :
 883       value = fields->f_r1;
 884       break;
 885     case M32R_OPERAND_SRC2 :
 886       value = fields->f_r2;
 887       break;
 888     case M32R_OPERAND_UIMM16 :
 889       value = fields->f_uimm16;
 890       break;
 891     case M32R_OPERAND_UIMM24 :
 892       value = fields->f_uimm24;
 893       break;
 894     case M32R_OPERAND_UIMM3 :
 895       value = fields->f_uimm3;
 896       break;
 897     case M32R_OPERAND_UIMM4 :
 898       value = fields->f_uimm4;
 899       break;
 900     case M32R_OPERAND_UIMM5 :
 901       value = fields->f_uimm5;
 902       break;
 903     case M32R_OPERAND_UIMM8 :
 904       value = fields->f_uimm8;
 905       break;
 906     case M32R_OPERAND_ULO16 :
 907       value = fields->f_uimm16;
 908       break;
 909
 910     default :
 911       /* xgettext:c-format */
 912       fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
 913                        opindex);
 914       abort ();
 915   }
 916
 917   return value;
 918 }
 919
 920 bfd_vma
 921 m32r_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 922                              int opindex,
 923                              const CGEN_FIELDS * fields)
 924 {
 925   bfd_vma value;
 926
 927   switch (opindex)
 928     {
 929     case M32R_OPERAND_ACC :
 930       value = fields->f_acc;
 931       break;
 932     case M32R_OPERAND_ACCD :
 933       value = fields->f_accd;
 934       break;
 935     case M32R_OPERAND_ACCS :
 936       value = fields->f_accs;
 937       break;
 938     case M32R_OPERAND_DCR :
 939       value = fields->f_r1;
 940       break;
 941     case M32R_OPERAND_DISP16 :
 942       value = fields->f_disp16;
 943       break;
 944     case M32R_OPERAND_DISP24 :
 945       value = fields->f_disp24;
 946       break;
 947     case M32R_OPERAND_DISP8 :
 948       value = fields->f_disp8;
 949       break;
 950     case M32R_OPERAND_DR :
 951       value = fields->f_r1;
 952       break;
 953     case M32R_OPERAND_HASH :
 954       value = 0;
 955       break;
 956     case M32R_OPERAND_HI16 :
 957       value = fields->f_hi16;
 958       break;
 959     case M32R_OPERAND_IMM1 :
 960       value = fields->f_imm1;
 961       break;
 962     case M32R_OPERAND_SCR :
 963       value = fields->f_r2;
 964       break;
 965     case M32R_OPERAND_SIMM16 :
 966       value = fields->f_simm16;
 967       break;
 968     case M32R_OPERAND_SIMM8 :
 969       value = fields->f_simm8;
 970       break;
 971     case M32R_OPERAND_SLO16 :
 972       value = fields->f_simm16;
 973       break;
 974     case M32R_OPERAND_SR :
 975       value = fields->f_r2;
 976       break;
 977     case M32R_OPERAND_SRC1 :
 978       value = fields->f_r1;
 979       break;
 980     case M32R_OPERAND_SRC2 :
 981       value = fields->f_r2;
 982       break;
 983     case M32R_OPERAND_UIMM16 :
 984       value = fields->f_uimm16;
 985       break;
 986     case M32R_OPERAND_UIMM24 :
 987       value = fields->f_uimm24;
 988       break;
 989     case M32R_OPERAND_UIMM3 :
 990       value = fields->f_uimm3;
 991       break;
 992     case M32R_OPERAND_UIMM4 :
 993       value = fields->f_uimm4;
 994       break;
 995     case M32R_OPERAND_UIMM5 :
 996       value = fields->f_uimm5;
 997       break;
 998     case M32R_OPERAND_UIMM8 :
 999       value = fields->f_uimm8;
1000       break;
1001     case M32R_OPERAND_ULO16 :
1002       value = fields->f_uimm16;
1003       break;
1004
1005     default :
1006       /* xgettext:c-format */
1007       fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
1008                        opindex);
1009       abort ();
1010   }
1011
1012   return value;
1013 }
1014
1015 void m32r_cgen_set_int_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
1016 void m32r_cgen_set_vma_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
1017
1018 /* Stuffing values in cgen_fields is handled by a collection of functions.
1019    They are distinguished by the type of the VALUE argument they accept.
1020    TODO: floating point, inlining support, remove cases where argument type
1021    not appropriate.  */
1022
1023 void
1024 m32r_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1025                              int opindex,
1026                              CGEN_FIELDS * fields,
1027                              int value)
1028 {
1029   switch (opindex)
1030     {
1031     case M32R_OPERAND_ACC :
1032       fields->f_acc = value;
1033       break;
1034     case M32R_OPERAND_ACCD :
1035       fields->f_accd = value;
1036       break;
1037     case M32R_OPERAND_ACCS :
1038       fields->f_accs = value;
1039       break;
1040     case M32R_OPERAND_DCR :
1041       fields->f_r1 = value;
1042       break;
1043     case M32R_OPERAND_DISP16 :
1044       fields->f_disp16 = value;
1045       break;
1046     case M32R_OPERAND_DISP24 :
1047       fields->f_disp24 = value;
1048       break;
1049     case M32R_OPERAND_DISP8 :
1050       fields->f_disp8 = value;
1051       break;
1052     case M32R_OPERAND_DR :
1053       fields->f_r1 = value;
1054       break;
1055     case M32R_OPERAND_HASH :
1056       break;
1057     case M32R_OPERAND_HI16 :
1058       fields->f_hi16 = value;
1059       break;
1060     case M32R_OPERAND_IMM1 :
1061       fields->f_imm1 = value;
1062       break;
1063     case M32R_OPERAND_SCR :
1064       fields->f_r2 = value;
1065       break;
1066     case M32R_OPERAND_SIMM16 :
1067       fields->f_simm16 = value;
1068       break;
1069     case M32R_OPERAND_SIMM8 :
1070       fields->f_simm8 = value;
1071       break;
1072     case M32R_OPERAND_SLO16 :
1073       fields->f_simm16 = value;
1074       break;
1075     case M32R_OPERAND_SR :
1076       fields->f_r2 = value;
1077       break;
1078     case M32R_OPERAND_SRC1 :
1079       fields->f_r1 = value;
1080       break;
1081     case M32R_OPERAND_SRC2 :
1082       fields->f_r2 = value;
1083       break;
1084     case M32R_OPERAND_UIMM16 :
1085       fields->f_uimm16 = value;
1086       break;
1087     case M32R_OPERAND_UIMM24 :
1088       fields->f_uimm24 = value;
1089       break;
1090     case M32R_OPERAND_UIMM3 :
1091       fields->f_uimm3 = value;
1092       break;
1093     case M32R_OPERAND_UIMM4 :
1094       fields->f_uimm4 = value;
1095       break;
1096     case M32R_OPERAND_UIMM5 :
1097       fields->f_uimm5 = value;
1098       break;
1099     case M32R_OPERAND_UIMM8 :
1100       fields->f_uimm8 = value;
1101       break;
1102     case M32R_OPERAND_ULO16 :
1103       fields->f_uimm16 = value;
1104       break;
1105
1106     default :
1107       /* xgettext:c-format */
1108       fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
1109                        opindex);
1110       abort ();
1111   }
1112 }
1113
1114 void
1115 m32r_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
1116                              int opindex,
1117                              CGEN_FIELDS * fields,
1118                              bfd_vma value)
1119 {
1120   switch (opindex)
1121     {
1122     case M32R_OPERAND_ACC :
1123       fields->f_acc = value;
1124       break;
1125     case M32R_OPERAND_ACCD :
1126       fields->f_accd = value;
1127       break;
1128     case M32R_OPERAND_ACCS :
1129       fields->f_accs = value;
1130       break;
1131     case M32R_OPERAND_DCR :
1132       fields->f_r1 = value;
1133       break;
1134     case M32R_OPERAND_DISP16 :
1135       fields->f_disp16 = value;
1136       break;
1137     case M32R_OPERAND_DISP24 :
1138       fields->f_disp24 = value;
1139       break;
1140     case M32R_OPERAND_DISP8 :
1141       fields->f_disp8 = value;
1142       break;
1143     case M32R_OPERAND_DR :
1144       fields->f_r1 = value;
1145       break;
1146     case M32R_OPERAND_HASH :
1147       break;
1148     case M32R_OPERAND_HI16 :
1149       fields->f_hi16 = value;
1150       break;
1151     case M32R_OPERAND_IMM1 :
1152       fields->f_imm1 = value;
1153       break;
1154     case M32R_OPERAND_SCR :
1155       fields->f_r2 = value;
1156       break;
1157     case M32R_OPERAND_SIMM16 :
1158       fields->f_simm16 = value;
1159       break;
1160     case M32R_OPERAND_SIMM8 :
1161       fields->f_simm8 = value;
1162       break;
1163     case M32R_OPERAND_SLO16 :
1164       fields->f_simm16 = value;
1165       break;
1166     case M32R_OPERAND_SR :
1167       fields->f_r2 = value;
1168       break;
1169     case M32R_OPERAND_SRC1 :
1170       fields->f_r1 = value;
1171       break;
1172     case M32R_OPERAND_SRC2 :
1173       fields->f_r2 = value;
1174       break;
1175     case M32R_OPERAND_UIMM16 :
1176       fields->f_uimm16 = value;
1177       break;
1178     case M32R_OPERAND_UIMM24 :
1179       fields->f_uimm24 = value;
1180       break;
1181     case M32R_OPERAND_UIMM3 :
1182       fields->f_uimm3 = value;
1183       break;
1184     case M32R_OPERAND_UIMM4 :
1185       fields->f_uimm4 = value;
1186       break;
1187     case M32R_OPERAND_UIMM5 :
1188       fields->f_uimm5 = value;
1189       break;
1190     case M32R_OPERAND_UIMM8 :
1191       fields->f_uimm8 = value;
1192       break;
1193     case M32R_OPERAND_ULO16 :
1194       fields->f_uimm16 = value;
1195       break;
1196
1197     default :
1198       /* xgettext:c-format */
1199       fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
1200                        opindex);
1201       abort ();
1202   }
1203 }
1204
1205 /* Function to call before using the instruction builder tables.  */
1206
1207 void
1208 m32r_cgen_init_ibld_table (CGEN_CPU_DESC cd)
1209 {
1210   cd->insert_handlers = & m32r_cgen_insert_handlers[0];
1211   cd->extract_handlers = & m32r_cgen_extract_handlers[0];
1212
1213   cd->insert_operand = m32r_cgen_insert_operand;
1214   cd->extract_operand = m32r_cgen_extract_operand;
1215
1216   cd->get_int_operand = m32r_cgen_get_int_operand;
1217   cd->set_int_operand = m32r_cgen_set_int_operand;
1218   cd->get_vma_operand = m32r_cgen_get_vma_operand;
1219   cd->set_vma_operand = m32r_cgen_set_vma_operand;
1220 }