| blob | 6b69fd633e1467da727f8c3b3c5d5f9c058cbd8e |
1 /* 32-bit ELF support for ARM
2 Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
3 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
23 #include <limits.h>
32 /* Return the relocation section associated with NAME. HTAB is the
33 bfd's elf32_arm_link_hash_entry. */
34 #define RELOC_SECTION(HTAB, NAME) \
37 /* Return size of a relocation entry. HTAB is the bfd's
38 elf32_arm_link_hash_entry. */
39 #define RELOC_SIZE(HTAB) \
40 ((HTAB)->use_rel \
41 ? sizeof (Elf32_External_Rel) \
42 : sizeof (Elf32_External_Rela))
44 /* Return function to swap relocations in. HTAB is the bfd's
45 elf32_arm_link_hash_entry. */
46 #define SWAP_RELOC_IN(HTAB) \
47 ((HTAB)->use_rel \
48 ? bfd_elf32_swap_reloc_in \
49 : bfd_elf32_swap_reloca_in)
51 /* Return function to swap relocations out. HTAB is the bfd's
52 elf32_arm_link_hash_entry. */
53 #define SWAP_RELOC_OUT(HTAB) \
54 ((HTAB)->use_rel \
55 ? bfd_elf32_swap_reloc_out \
56 : bfd_elf32_swap_reloca_out)
58 #define elf_info_to_howto 0
59 #define elf_info_to_howto_rel elf32_arm_info_to_howto
61 #define ARM_ELF_ABI_VERSION 0
62 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
69 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
70 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
71 in that slot. */
74 {
75 /* No relocation. */
104 /* 32 bit absolute */
119 /* standard 32bit pc-relative reloc */
134 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
149 /* 16 bit absolute */
164 /* 12 bit absolute */
193 /* 8 bit absolute */
292 /* BLX instruction for the ARM. */
307 /* BLX instruction for the Thumb. */
322 /* Dynamic TLS relocations. */
366 /* Relocs used in ARM Linux */
830 /* These are declared as 13-bit signed relocations because we can
831 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
832 versa. */
889 /* Group relocations. */
1269 /* End of group relocations. */
1483 /* GNU extension to record C++ vtable member usage */
1498 /* GNU extension to record C++ vtable hierarchy */
1541 /* TLS relocations */
1654 /* 112-127 private relocations. */
1672 /* R_ARM_ME_TOO, obsolete. */
1688 };
1690 /* 160 onwards: */
1692 {
1706 };
1708 /* 249-255 extended, currently unused, relocations: */
1710 {
1766 };
1770 {
1782 }
1784 static void
1787 {
1792 }
1794 struct elf32_arm_reloc_map
1795 {
1796 bfd_reloc_code_real_type bfd_reloc_val;
1798 };
1800 /* All entries in this list must also be present in elf32_arm_howto_table. */
1802 {
1889 };
1893 bfd_reloc_code_real_type code)
1894 {
1902 }
1907 {
1926 }
1928 /* Support for core dump NOTE sections. */
1930 static bfd_boolean
1932 {
1937 {
1942 /* pr_cursig */
1945 /* pr_pid */
1948 /* pr_reg */
1953 }
1955 /* Make a ".reg/999" section. */
1958 }
1960 static bfd_boolean
1962 {
1964 {
1973 }
1975 /* Note that for some reason, a spurious space is tacked
1976 onto the end of the args in some (at least one anyway)
1977 implementations, so strip it off if it exists. */
1978 {
1984 }
1987 }
1989 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_vec
1991 #define TARGET_BIG_SYM bfd_elf32_bigarm_vec
1994 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
1995 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2000 /* In lieu of proper flags, assume all EABIv4 or later objects are
2001 interworkable. */
2002 #define INTERWORK_FLAG(abfd) \
2003 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2004 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2005 || ((abfd)->flags & BFD_LINKER_CREATED))
2007 /* The linker script knows the section names for placement.
2008 The entry_names are used to do simple name mangling on the stubs.
2009 Given a function name, and its type, the stub can be found. The
2010 name can be changed. The only requirement is the %s be present. */
2025 /* The name of the dynamic interpreter. This is put in the .interp
2026 section. */
2030 {
2034 };
2037 {
2045 + dl_tlsdesc_lazy_resolver(GOT) */
2047 };
2049 #ifdef FOUR_WORD_PLT
2051 /* The first entry in a procedure linkage table looks like
2052 this. It is set up so that any shared library function that is
2053 called before the relocation has been set up calls the dynamic
2054 linker first. */
2056 {
2061 };
2063 /* Subsequent entries in a procedure linkage table look like
2064 this. */
2066 {
2071 };
2073 #else
2075 /* The first entry in a procedure linkage table looks like
2076 this. It is set up so that any shared library function that is
2077 called before the relocation has been set up calls the dynamic
2078 linker first. */
2080 {
2086 };
2088 /* Subsequent entries in a procedure linkage table look like
2089 this. */
2091 {
2095 };
2097 #endif
2099 /* The format of the first entry in the procedure linkage table
2100 for a VxWorks executable. */
2102 {
2107 };
2109 /* The format of subsequent entries in a VxWorks executable. */
2111 {
2118 };
2120 /* The format of entries in a VxWorks shared library. */
2122 {
2129 };
2131 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2132 #define PLT_THUMB_STUB_SIZE 4
2134 {
2137 };
2139 /* The entries in a PLT when using a DLL-based target with multiple
2140 address spaces. */
2142 {
2145 };
2147 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2148 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2149 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2150 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2151 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2152 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2154 enum stub_insn_type
2155 {
2157 THUMB32_TYPE,
2158 ARM_TYPE,
2159 DATA_TYPE
2160 };
2162 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2163 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2164 is inserted in arm_build_one_stub(). */
2165 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2166 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2167 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2168 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2169 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2170 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2173 {
2174 bfd_vma data;
2180 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2181 to reach the stub if necessary. */
2183 {
2186 };
2188 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2189 available. */
2191 {
2195 };
2197 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2199 {
2207 };
2209 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2210 allowed. */
2212 {
2218 };
2220 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2221 available. */
2223 {
2228 };
2230 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2231 one, when the destination is close enough. */
2233 {
2237 };
2239 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2240 blx to reach the stub if necessary. */
2242 {
2246 };
2248 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2249 blx to reach the stub if necessary. We can not add into pc;
2250 it is not guaranteed to mode switch (different in ARMv6 and
2251 ARMv7). */
2253 {
2258 };
2260 /* V4T ARM -> ARM long branch stub, PIC. */
2262 {
2267 };
2269 /* V4T Thumb -> ARM long branch stub, PIC. */
2271 {
2277 };
2279 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2280 architectures. */
2282 {
2290 };
2292 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2293 allowed. */
2295 {
2302 };
2304 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2305 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2307 {
2311 };
2313 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2314 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2316 {
2322 };
2324 /* Cortex-A8 erratum-workaround stubs. */
2326 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2327 can't use a conditional branch to reach this stub). */
2330 {
2334 };
2336 /* Stub used for b.w and bl.w instructions. */
2339 {
2341 };
2344 {
2346 };
2348 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2349 instruction (which switches to ARM mode) to point to this stub. Jump to the
2350 real destination using an ARM-mode branch. */
2353 {
2355 };
2357 /* Section name for stubs is the associated section name plus this
2358 string. */
2361 /* One entry per long/short branch stub defined above. */
2362 #define DEF_STUBS \
2363 DEF_STUB(long_branch_any_any) \
2364 DEF_STUB(long_branch_v4t_arm_thumb) \
2365 DEF_STUB(long_branch_thumb_only) \
2366 DEF_STUB(long_branch_v4t_thumb_thumb) \
2367 DEF_STUB(long_branch_v4t_thumb_arm) \
2368 DEF_STUB(short_branch_v4t_thumb_arm) \
2369 DEF_STUB(long_branch_any_arm_pic) \
2370 DEF_STUB(long_branch_any_thumb_pic) \
2371 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2372 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2373 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
2374 DEF_STUB(long_branch_thumb_only_pic) \
2375 DEF_STUB(long_branch_any_tls_pic) \
2376 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
2377 DEF_STUB(a8_veneer_b_cond) \
2378 DEF_STUB(a8_veneer_b) \
2379 DEF_STUB(a8_veneer_bl) \
2380 DEF_STUB(a8_veneer_blx)
2382 #define DEF_STUB(x) arm_stub_##x,
2384 arm_stub_none,
2385 DEF_STUBS
2386 /* Note the first a8_veneer type */
2387 arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond
2388 };
2389 #undef DEF_STUB
2392 {
2397 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2400 DEF_STUBS
2401 };
2403 struct elf32_arm_stub_hash_entry
2404 {
2405 /* Base hash table entry structure. */
2408 /* The stub section. */
2411 /* Offset within stub_sec of the beginning of this stub. */
2412 bfd_vma stub_offset;
2414 /* Given the symbol's value and its section we can determine its final
2415 value when building the stubs (so the stub knows where to jump). */
2416 bfd_vma target_value;
2419 /* Offset to apply to relocation referencing target_value. */
2420 bfd_vma target_addend;
2422 /* The instruction which caused this stub to be generated (only valid for
2423 Cortex-A8 erratum workaround stubs at present). */
2426 /* The stub type. */
2428 /* Its encoding size in bytes. */
2430 /* Its template. */
2432 /* The size of the template (number of entries). */
2435 /* The symbol table entry, if any, that this was derived from. */
2438 /* Type of branch. */
2441 /* Where this stub is being called from, or, in the case of combined
2442 stub sections, the first input section in the group. */
2445 /* The name for the local symbol at the start of this stub. The
2446 stub name in the hash table has to be unique; this does not, so
2447 it can be friendlier. */
2449 };
2451 /* Used to build a map of a section. This is required for mixed-endian
2452 code/data. */
2455 {
2456 bfd_vma vma;
2458 }
2459 elf32_arm_section_map;
2461 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2464 {
2465 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2466 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2467 VFP11_ERRATUM_ARM_VENEER,
2468 VFP11_ERRATUM_THUMB_VENEER
2469 }
2470 elf32_vfp11_erratum_type;
2473 {
2475 bfd_vma vma;
2476 union
2477 {
2478 struct
2479 {
2483 struct
2484 {
2489 elf32_vfp11_erratum_type type;
2490 }
2491 elf32_vfp11_erratum_list;
2494 {
2495 DELETE_EXIDX_ENTRY,
2496 INSERT_EXIDX_CANTUNWIND_AT_END
2497 }
2498 arm_unwind_edit_type;
2500 /* A (sorted) list of edits to apply to an unwind table. */
2502 {
2503 arm_unwind_edit_type type;
2504 /* Note: we sometimes want to insert an unwind entry corresponding to a
2505 section different from the one we're currently writing out, so record the
2506 (text) section this edit relates to here. */
2510 }
2511 arm_unwind_table_edit;
2514 {
2515 /* Information about mapping symbols. */
2520 /* Information about CPU errata. */
2523 /* Information about unwind tables. */
2524 union
2525 {
2526 /* Unwind info attached to a text section. */
2527 struct
2528 {
2532 /* Unwind info attached to an .ARM.exidx section. */
2533 struct
2534 {
2539 }
2540 _arm_elf_section_data;
2542 #define elf32_arm_section_data(sec) \
2543 ((_arm_elf_section_data *) elf_section_data (sec))
2545 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2546 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2547 so may be created multiple times: we use an array of these entries whilst
2548 relaxing which we can refresh easily, then create stubs for each potentially
2549 erratum-triggering instruction once we've settled on a solution. */
2554 bfd_vma offset;
2555 bfd_vma addend;
2560 };
2562 /* A table of relocs applied to branches which might trigger Cortex-A8
2563 erratum. */
2566 bfd_vma from;
2567 bfd_vma destination;
2572 bfd_boolean non_a8_stub;
2573 };
2575 /* The size of the thread control block. */
2576 #define TCB_SIZE 8
2578 /* ARM-specific information about a PLT entry, over and above the usual
2579 gotplt_union. */
2581 /* We reference count Thumb references to a PLT entry separately,
2582 so that we can emit the Thumb trampoline only if needed. */
2583 bfd_signed_vma thumb_refcount;
2585 /* Some references from Thumb code may be eliminated by BL->BLX
2586 conversion, so record them separately. */
2587 bfd_signed_vma maybe_thumb_refcount;
2589 /* How many of the recorded PLT accesses were from non-call relocations.
2590 This information is useful when deciding whether anything takes the
2591 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2592 non-call references to the function should resolve directly to the
2593 real runtime target. */
2596 /* Since PLT entries have variable size if the Thumb prologue is
2597 used, we need to record the index into .got.plt instead of
2598 recomputing it from the PLT offset. */
2599 bfd_signed_vma got_offset;
2600 };
2602 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
2604 /* The information that is usually found in the generic ELF part of
2605 the hash table entry. */
2608 /* The information that is usually found in the ARM-specific part of
2609 the hash table entry. */
2612 /* A list of all potential dynamic relocations against this symbol. */
2614 };
2616 struct elf_arm_obj_tdata
2617 {
2620 /* tls_type for each local got entry. */
2623 /* GOTPLT entries for TLS descriptors. */
2626 /* Information for local symbols that need entries in .iplt. */
2629 /* Zero to warn when linking objects with incompatible enum sizes. */
2632 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2634 };
2636 #define elf_arm_tdata(bfd) \
2637 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
2639 #define elf32_arm_local_got_tls_type(bfd) \
2640 (elf_arm_tdata (bfd)->local_got_tls_type)
2642 #define elf32_arm_local_tlsdesc_gotent(bfd) \
2643 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2645 #define elf32_arm_local_iplt(bfd) \
2646 (elf_arm_tdata (bfd)->local_iplt)
2648 #define is_arm_elf(bfd) \
2649 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2650 && elf_tdata (bfd) != NULL \
2651 && elf_object_id (bfd) == ARM_ELF_DATA)
2653 static bfd_boolean
2655 {
2657 ARM_ELF_DATA);
2658 }
2660 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2662 /* Arm ELF linker hash entry. */
2663 struct elf32_arm_link_hash_entry
2664 {
2667 /* Track dynamic relocs copied for this symbol. */
2670 /* ARM-specific PLT information. */
2673 #define GOT_UNKNOWN 0
2674 #define GOT_NORMAL 1
2675 #define GOT_TLS_GD 2
2676 #define GOT_TLS_IE 4
2677 #define GOT_TLS_GDESC 8
2678 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
2681 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2686 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2687 starting at the end of the jump table. */
2688 bfd_vma tlsdesc_got;
2690 /* The symbol marking the real symbol location for exported thumb
2691 symbols with Arm stubs. */
2694 /* A pointer to the most recently used stub hash entry against this
2695 symbol. */
2697 };
2699 /* Traverse an arm ELF linker hash table. */
2700 #define elf32_arm_link_hash_traverse(table, func, info) \
2701 (elf_link_hash_traverse \
2702 (&(table)->root, \
2703 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
2704 (info)))
2706 /* Get the ARM elf linker hash table from a link_info structure. */
2707 #define elf32_arm_hash_table(info) \
2708 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
2709 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
2711 #define arm_stub_hash_lookup(table, string, create, copy) \
2712 ((struct elf32_arm_stub_hash_entry *) \
2713 bfd_hash_lookup ((table), (string), (create), (copy)))
2715 /* Array to keep track of which stub sections have been created, and
2716 information on stub grouping. */
2717 struct map_stub
2718 {
2719 /* This is the section to which stubs in the group will be
2720 attached. */
2722 /* The stub section. */
2724 };
2726 #define elf32_arm_compute_jump_table_size(htab) \
2727 ((htab)->next_tls_desc_index * 4)
2729 /* ARM ELF linker hash table. */
2730 struct elf32_arm_link_hash_table
2731 {
2732 /* The main hash table. */
2735 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
2736 bfd_size_type thumb_glue_size;
2738 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
2739 bfd_size_type arm_glue_size;
2741 /* The size in bytes of section containing the ARMv4 BX veneers. */
2742 bfd_size_type bx_glue_size;
2744 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
2745 veneer has been populated. */
2748 /* The size in bytes of the section containing glue for VFP11 erratum
2749 veneers. */
2750 bfd_size_type vfp11_erratum_glue_size;
2752 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
2753 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
2754 elf32_arm_write_section(). */
2758 /* An arbitrary input BFD chosen to hold the glue sections. */
2761 /* Nonzero to output a BE8 image. */
2764 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
2765 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
2768 /* The relocation to use for R_ARM_TARGET2 relocations. */
2771 /* 0 = Ignore R_ARM_V4BX.
2772 1 = Convert BX to MOV PC.
2773 2 = Generate v4 interworing stubs. */
2776 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
2779 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
2782 /* What sort of code sequences we should look for which may trigger the
2783 VFP11 denorm erratum. */
2784 bfd_arm_vfp11_fix vfp11_fix;
2786 /* Global counter for the number of fixes we have emitted. */
2789 /* Nonzero to force PIC branch veneers. */
2792 /* The number of bytes in the initial entry in the PLT. */
2793 bfd_size_type plt_header_size;
2795 /* The number of bytes in the subsequent PLT etries. */
2796 bfd_size_type plt_entry_size;
2798 /* True if the target system is VxWorks. */
2801 /* True if the target system is Symbian OS. */
2804 /* True if the target uses REL relocations. */
2807 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
2808 bfd_vma next_tls_desc_index;
2810 /* How many R_ARM_TLS_DESC relocations were generated so far. */
2811 bfd_vma num_tls_desc;
2813 /* Short-cuts to get to dynamic linker sections. */
2817 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
2820 /* The offset into splt of the PLT entry for the TLS descriptor
2821 resolver. Special values are 0, if not necessary (or not found
2822 to be necessary yet), and -1 if needed but not determined
2823 yet. */
2824 bfd_vma dt_tlsdesc_plt;
2826 /* The offset into sgot of the GOT entry used by the PLT entry
2827 above. */
2828 bfd_vma dt_tlsdesc_got;
2830 /* Offset in .plt section of tls_arm_trampoline. */
2831 bfd_vma tls_trampoline;
2833 /* Data for R_ARM_TLS_LDM32 relocations. */
2834 union
2835 {
2836 bfd_signed_vma refcount;
2837 bfd_vma offset;
2840 /* Small local sym cache. */
2843 /* For convenience in allocate_dynrelocs. */
2846 /* The amount of space used by the reserved portion of the sgotplt
2847 section, plus whatever space is used by the jump slots. */
2848 bfd_vma sgotplt_jump_table_size;
2850 /* The stub hash table. */
2853 /* Linker stub bfd. */
2856 /* Linker call-backs. */
2860 /* Array to keep track of which stub sections have been created, and
2861 information on stub grouping. */
2864 /* Number of elements in stub_group. */
2867 /* Assorted information used by elf32_arm_size_stubs. */
2871 };
2873 /* Create an entry in an ARM ELF linker hash table. */
2879 {
2883 /* Allocate the structure if it has not already been allocated by a
2884 subclass. */
2891 /* Call the allocation method of the superclass. */
2896 {
2908 }
2911 }
2913 /* Ensure that we have allocated bookkeeping structures for ABFD's local
2914 symbols. */
2916 static bfd_boolean
2918 {
2920 {
2921 bfd_size_type num_syms;
2922 bfd_size_type size;
2944 }
2946 }
2948 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
2949 to input bfd ABFD. Create the information if it doesn't already exist.
2950 Return null if an allocation fails. */
2954 {
2965 }
2967 /* Try to obtain PLT information for the symbol with index R_SYMNDX
2968 in ABFD's symbol table. If the symbol is global, H points to its
2969 hash table entry, otherwise H is null.
2971 Return true if the symbol does have PLT information. When returning
2972 true, point *ROOT_PLT at the target-independent reference count/offset
2973 union and *ARM_PLT at the ARM-specific information. */
2975 static bfd_boolean
2979 {
2983 {
2987 }
2999 }
3001 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3002 before it. */
3004 static bfd_boolean
3007 {
3013 }
3015 /* Return a pointer to the head of the dynamic reloc list that should
3016 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3017 ABFD's symbol table. Return null if an error occurs. */
3022 {
3024 {
3031 }
3032 else
3033 {
3034 /* Track dynamic relocs needed for local syms too.
3035 We really need local syms available to do this
3036 easily. Oh well. */
3046 }
3047 }
3049 /* Initialize an entry in the stub hash table. */
3055 {
3056 /* Allocate the structure if it has not already been allocated by a
3057 subclass. */
3059 {
3064 }
3066 /* Call the allocation method of the superclass. */
3069 {
3072 /* Initialize the local fields. */
3087 }
3090 }
3092 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3093 shortcuts to them in our hash table. */
3095 static bfd_boolean
3097 {
3104 /* BPABI objects never have a GOT, or associated sections. */
3112 }
3114 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3116 static bfd_boolean
3118 {
3123 flagword flags;
3131 {
3138 }
3141 {
3148 }
3151 {
3157 }
3159 }
3161 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3162 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3163 hash table. */
3165 static bfd_boolean
3167 {
3186 {
3191 {
3193 htab->plt_entry_size
3195 }
3196 else
3197 {
3198 htab->plt_header_size
3200 htab->plt_entry_size
3202 }
3203 }
3212 }
3214 /* Copy the extra info we tack onto an elf_link_hash_entry. */
3216 static void
3220 {
3227 {
3229 {
3233 /* Add reloc counts against the indirect sym to the direct sym
3234 list. Merge any entries against the same section. */
3236 {
3241 {
3246 }
3249 }
3251 }
3255 }
3258 {
3259 /* Copy over PLT info. */
3267 /* We should only allocate a function to .iplt once the final
3268 symbol information is known. */
3272 {
3275 }
3276 }
3279 }
3281 /* Create an ARM elf linker hash table. */
3285 {
3294 elf32_arm_link_hash_newfunc,
3296 ARM_ELF_DATA))
3297 {
3300 }
3322 #ifdef FOUR_WORD_PLT
3325 #else
3328 #endif
3348 {
3351 }
3354 }
3356 /* Free the derived linker hash table. */
3358 static void
3360 {
3366 }
3368 /* Determine if we're dealing with a Thumb only architecture. */
3370 static bfd_boolean
3372 {
3374 Tag_CPU_arch);
3384 Tag_CPU_arch_profile);
3387 }
3389 /* Determine if we're dealing with a Thumb-2 object. */
3391 static bfd_boolean
3393 {
3395 Tag_CPU_arch);
3397 }
3399 /* Determine what kind of NOPs are available. */
3401 static bfd_boolean
3403 {
3405 Tag_CPU_arch);
3410 }
3412 static bfd_boolean
3414 {
3416 Tag_CPU_arch);
3419 }
3421 static bfd_boolean
3423 {
3425 {
3438 }
3439 }
3441 /* Determine the type of stub needed, if any, for a call. */
3443 static enum elf32_arm_stub_type
3450 bfd_vma destination,
3454 {
3455 bfd_vma location;
3456 bfd_signed_vma branch_offset;
3478 /* Determine where the call point is. */
3485 /* For TLS call relocs, it is the caller's responsibility to provide
3486 the address of the appropriate trampoline. */
3492 {
3497 else
3500 {
3503 /* Note when dealing with PLT entries: the main PLT stub is in
3504 ARM mode, so if the branch is in Thumb mode, another
3505 Thumb->ARM stub will be inserted later just before the ARM
3506 PLT stub. We don't take this extra distance into account
3507 here, because if a long branch stub is needed, we'll add a
3508 Thumb->Arm one and branch directly to the ARM PLT entry
3509 because it avoids spreading offset corrections in several
3510 places. */
3517 }
3518 }
3519 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3526 {
3527 /* Handle cases where:
3528 - this call goes too far (different Thumb/Thumb2 max
3529 distance)
3530 - it's a Thumb->Arm call and blx is not available, or it's a
3531 Thumb->Arm branch (not bl). A stub is needed in this case,
3532 but only if this call is not through a PLT entry. Indeed,
3533 PLT stubs handle mode switching already.
3534 */
3538 || (thumb2
3546 {
3548 {
3549 /* Thumb to thumb. */
3551 {
3553 /* PIC stubs. */
3556 /* V5T and above. Stub starts with ARM code, so
3557 we must be able to switch mode before
3558 reaching it, which is only possible for 'bl'
3559 (ie R_ARM_THM_CALL relocation). */
3560 ? arm_stub_long_branch_any_thumb_pic
3561 /* On V4T, use Thumb code only. */
3564 /* non-PIC stubs. */
3567 /* V5T and above. */
3568 ? arm_stub_long_branch_any_any
3569 /* V4T. */
3571 }
3572 else
3573 {
3575 /* PIC stub. */
3576 ? arm_stub_long_branch_thumb_only_pic
3577 /* non-PIC stub. */
3579 }
3580 }
3581 else
3582 {
3583 /* Thumb to arm. */
3587 {
3592 }
3594 stub_type =
3596 /* PIC stubs. */
3598 /* TLS PIC stubs */
3602 /* V5T PIC and above. */
3603 ? arm_stub_long_branch_any_arm_pic
3604 /* V4T PIC stub. */
3607 /* non-PIC stubs. */
3609 /* V5T and above. */
3610 ? arm_stub_long_branch_any_any
3611 /* V4T. */
3614 /* Handle v4t short branches. */
3619 }
3620 }
3621 }
3626 {
3628 {
3629 /* Arm to thumb. */
3634 {
3639 }
3641 /* We have an extra 2-bytes reach because of
3642 the mode change (bit 24 (H) of BLX encoding). */
3648 {
3650 /* PIC stubs. */
3652 /* V5T and above. */
3653 ? arm_stub_long_branch_any_thumb_pic
3654 /* V4T stub. */
3657 /* non-PIC stubs. */
3659 /* V5T and above. */
3660 ? arm_stub_long_branch_any_any
3661 /* V4T. */
3663 }
3664 }
3665 else
3666 {
3667 /* Arm to arm. */
3670 {
3671 stub_type =
3673 /* PIC stubs. */
3675 /* TLS PIC Stub */
3676 ? arm_stub_long_branch_any_tls_pic
3678 /* non-PIC stubs. */
3680 }
3681 }
3682 }
3684 /* If a stub is needed, record the actual destination type. */
3689 }
3691 /* Build a name for an entry in the stub hash table. */
3699 {
3701 bfd_size_type len;
3704 {
3713 }
3714 else
3715 {
3727 }
3730 }
3732 /* Look up an entry in the stub hash. Stub entries are cached because
3733 creating the stub name takes a bit of time. */
3742 {
3750 /* If this input section is part of a group of sections sharing one
3751 stub section, then use the id of the first section in the group.
3752 Stub names need to include a section id, as there may well be
3753 more than one stub used to reach say, printf, and we need to
3754 distinguish between them. */
3761 {
3763 }
3764 else
3765 {
3778 }
3781 }
3783 /* Find or create a stub section. Returns a pointer to the stub section, and
3784 the section to which the stub section will be attached (in *LINK_SEC_P).
3785 LINK_SEC_P may be NULL. */
3790 {
3797 {
3800 {
3802 bfd_size_type len;
3817 }
3819 }
3825 }
3827 /* Add a new stub entry to the stub hash. Not all fields of the new
3828 stub entry are initialised. */
3834 {
3843 /* Enter this entry into the linker stub hash table. */
3847 {
3850 stub_name);
3852 }
3859 }
3861 /* Store an Arm insn into an output section not processed by
3862 elf32_arm_write_section. */
3864 static void
3867 {
3870 else
3872 }
3874 /* Store a 16-bit Thumb insn into an output section not processed by
3875 elf32_arm_write_section. */
3877 static void
3880 {
3883 else
3885 }
3887 /* If it's possible to change R_TYPE to a more efficient access
3888 model, return the new reloc type. */
3890 static unsigned
3893 {
3899 /* We do not support relaxations for Old TLS models. */
3901 {
3908 }
3911 }
3913 static bfd_reloc_status_type elf32_arm_final_link_relocate
3919 static unsigned int
3921 {
3923 {
3948 }
3949 }
3951 static bfd_boolean
3954 {
3955 #define MAXRELOCS 2
3962 bfd_vma sym_value;
3971 /* Massage our args to the form they really have. */
3983 /* We have to do less-strictly-aligned fixes last. */
3986 /* Make a note of the offset within the stubs for this entry. */
3992 /* This is the address of the stub destination. */
4002 {
4004 {
4006 {
4009 {
4010 /* We've borrowed the reloc_addend field to mean we should
4011 insert a condition code into this (Thumb-1 branch)
4012 instruction. See THUMB16_BCOND_INSN. */
4015 }
4018 }
4028 {
4031 }
4038 /* Handle cases where the target is encoded within the
4039 instruction. */
4041 {
4044 }
4058 }
4059 }
4063 /* Stub size has already been computed in arm_size_one_stub. Check
4064 consistency. */
4067 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
4071 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4072 in each stub. */
4080 {
4081 Elf_Internal_Rela rel;
4082 bfd_boolean unresolved_reloc;
4084 enum arm_st_branch_type branch_type
4095 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4096 template should refer back to the instruction after the original
4097 branch. */
4100 /* There may be unintended consequences if this is not true. */
4103 /* Note: _bfd_final_link_relocate doesn't handle these relocations
4104 properly. We should probably use this function unconditionally,
4105 rather than only for certain relocations listed in the enclosing
4106 conditional, for the sake of consistency. */
4113 }
4114 else
4115 {
4116 Elf_Internal_Rela rel;
4117 bfd_boolean unresolved_reloc;
4134 }
4137 #undef MAXRELOCS
4138 }
4140 /* Calculate the template, template size and instruction size for a stub.
4141 Return value is the instruction size. */
4143 static unsigned int
4147 {
4162 {
4164 {
4178 }
4179 }
4182 }
4184 /* As above, but don't actually build the stub. Just bump offset so
4185 we know stub section sizes. */
4187 static bfd_boolean
4190 {
4195 /* Massage our args to the form they really have. */
4212 }
4214 /* External entry points for sizing and building linker stubs. */
4216 /* Set up various things so that we can make a list of input sections
4217 for each output section included in the link. Returns -1 on error,
4218 0 when no stubs will be needed, and 1 on success. */
4220 int
4223 {
4229 bfd_size_type amt;
4237 /* Count the number of input BFDs and find the top input section id. */
4241 {
4246 {
4249 }
4250 }
4259 /* We can't use output_bfd->section_count here to find the top output
4260 section index as some sections may have been removed, and
4261 _bfd_strip_section_from_output doesn't renumber the indices. */
4265 {
4268 }
4277 /* For sections we aren't interested in, mark their entries with a
4278 value we can check later. */
4280 do
4287 {
4290 }
4293 }
4295 /* The linker repeatedly calls this function for each input section,
4296 in the order that input sections are linked into output sections.
4297 Build lists of input sections to determine groupings between which
4298 we may insert linker stubs. */
4300 void
4303 {
4310 {
4314 {
4315 /* Steal the link_sec pointer for our list. */
4316 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4317 /* This happens to make the list in reverse order,
4318 which we reverse later. */
4321 }
4322 }
4323 }
4325 /* See whether we can group stub sections together. Grouping stub
4326 sections may result in fewer stubs. More importantly, we need to
4327 put all .init* and .fini* stubs at the end of the .init or
4328 .fini output sections respectively, because glibc splits the
4329 _init and _fini functions into multiple parts. Putting a stub in
4330 the middle of a function is not a good idea. */
4332 static void
4334 bfd_size_type stub_group_size,
4335 bfd_boolean stubs_always_after_branch)
4336 {
4339 do
4340 {
4347 /* Reverse the list: we must avoid placing stubs at the
4348 beginning of the section because the beginning of the text
4349 section may be required for an interrupt vector in bare metal
4350 code. */
4351 #define NEXT_SEC PREV_SEC
4354 {
4355 /* Pop from tail. */
4359 /* Push on head. */
4362 }
4365 {
4369 bfd_vma end_of_next;
4373 {
4377 /* End of NEXT is too far from start, so stop. */
4379 /* Add NEXT to the group. */
4381 }
4383 /* OK, the size from the start to the start of CURR is less
4384 than stub_group_size and thus can be handled by one stub
4385 section. (Or the head section is itself larger than
4386 stub_group_size, in which case we may be toast.)
4387 We should really be keeping track of the total size of
4388 stubs added here, as stubs contribute to the final output
4389 section size. */
4390 do
4391 {
4393 /* Set up this stub group. */
4395 }
4398 /* But wait, there's more! Input sections up to stub_group_size
4399 bytes after the stub section can be handled by it too. */
4401 {
4405 {
4408 /* End of NEXT is too far from stubs, so stop. */
4410 /* Add NEXT to the stub group. */
4414 }
4415 }
4417 }
4418 }
4422 #undef PREV_SEC
4423 #undef NEXT_SEC
4424 }
4426 /* Comparison function for sorting/searching relocations relating to Cortex-A8
4427 erratum fix. */
4429 static int
4431 {
4439 else
4441 }
4446 /* Helper function to scan code for sequences which might trigger the Cortex-A8
4447 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
4448 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
4449 otherwise. */
4451 static bfd_boolean
4461 {
4474 {
4478 bfd_vma base_vma;
4497 {
4508 /* Span is entirely within a single 4KB region: skip scanning. */
4513 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4515 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4516 * The branch target is in the same 4KB region as the
4517 first half of the branch.
4518 * The instruction before the branch is a 32-bit
4519 length non-branch instruction. */
4521 {
4530 {
4531 /* Load the rest of the insn (in manual-friendly order). */
4534 /* Encoding T4: B<c>.W. */
4536 /* Encoding T1: BL<c>.W. */
4538 /* Encoding T2: BLX<c>.W. */
4540 /* Encoding T3: B<c>.W (not permitted in IT block). */
4543 }
4548 && insn_32bit
4549 && is_32bit_branch
4550 && last_was_32bit
4552 {
4556 bfd_vma target;
4567 {
4572 /* We don't care about the error returned from this
4573 function, only if there is glue or not. */
4580 /* Keep a simpler condition, for the sake of clarity. */
4586 {
4590 else
4592 }
4593 }
4595 /* Check if we have an offending branch instruction. */
4598 /* We've already made a stub for this instruction, e.g.
4599 it's a long branch or a Thumb->ARM stub. Assume that
4600 stub will suffice to work around the A8 erratum (see
4601 setting of always_after_branch above). */
4602 ;
4604 {
4613 }
4615 {
4635 }
4638 {
4641 /* The original instruction is a BL, but the target is
4642 an ARM instruction. If we were not making a stub,
4643 the BL would have been converted to a BLX. Use the
4644 BLX stub instead in that case. */
4647 {
4651 }
4652 /* Conversely, if the original instruction was
4653 BLX but the target is Thumb mode, use the BL
4654 stub. */
4657 {
4661 }
4666 /* If we found a relocation, use the proper destination,
4667 not the offset in the (unrelocated) instruction.
4668 Note this is always done if we switched the stub type
4669 above. */
4671 offset =
4676 /* The BLX stub is ARM-mode code. Adjust the offset to
4677 take the different PC value (+8 instead of +4) into
4678 account. */
4683 {
4687 {
4693 }
4696 {
4697 /* If we're doing a subsequent scan,
4698 check if we've found the same fix as
4699 before, and try and reuse the stub
4700 name. */
4704 {
4708 }
4709 }
4712 {
4716 }
4728 num_a8_fixes++;
4729 }
4730 }
4731 }
4736 }
4737 }
4741 }
4748 }
4750 /* Determine and set the size of the stub section for a final link.
4752 The basic idea here is to examine all the relocations looking for
4753 PC-relative calls to a target that is unreachable with a "bl"
4754 instruction. */
4756 bfd_boolean
4760 bfd_signed_vma group_size,
4763 {
4764 bfd_size_type stub_group_size;
4765 bfd_boolean stubs_always_after_branch;
4776 {
4781 }
4783 /* Propagate mach to stub bfd, because it may not have been
4784 finalized when we created stub_bfd. */
4788 /* Stash our params away. */
4794 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
4795 as the first half of a 32-bit branch straddling two 4K pages. This is a
4796 crude way of enforcing that. */
4802 else
4806 {
4807 /* Default values. */
4808 /* Thumb branch range is +-4MB has to be used as the default
4809 maximum size (a given section can contain both ARM and Thumb
4810 code, so the worst case has to be taken into account).
4812 This value is 24K less than that, which allows for 2025
4813 12-byte stubs. If we exceed that, then we will fail to link.
4814 The user will have to relink with an explicit group size
4815 option. */
4817 }
4821 /* If we're applying the cortex A8 fix, we need to determine the
4822 program header size now, because we cannot change it later --
4823 that could alter section placements. Notice the A8 erratum fix
4824 ends up requiring the section addresses to remain unchanged
4825 modulo the page size. That's something we cannot represent
4826 inside BFD, and we don't want to force the section alignment to
4827 be the page size. */
4832 {
4843 {
4850 /* We'll need the symbol table in a second. */
4855 /* Walk over each section attached to the input bfd. */
4859 {
4862 /* If there aren't any relocs, then there's nothing more
4863 to do. */
4869 /* If this section is a link-once section that will be
4870 discarded, then don't create any stubs. */
4875 /* Get the relocs. */
4876 internal_relocs
4882 /* Now examine each relocation. */
4886 {
4891 bfd_vma sym_value;
4892 bfd_vma destination;
4905 {
4907 error_ret_free_internal:
4911 }
4915 hash = elf32_arm_hash_entry
4919 /* Only look for stubs on branch instructions, or
4920 non-relaxed TLSCALL */
4933 : (elf32_arm_local_got_tls_type
4938 /* Now determine the call target, its name, value,
4939 section. */
4947 {
4948 /* A non-relaxed TLS call. The target is the
4949 plt-resident trampoline and nothing to do
4950 with the symbol. */
4957 }
4959 {
4960 /* It's a local symbol. */
4964 {
4965 local_syms
4968 local_syms
4974 }
4983 else
4984 sym_sec =
4988 /* This is an undefined symbol. It can never
4989 be resolved. */
4999 sym_name
5003 }
5004 else
5005 {
5006 /* It's an external symbol. */
5014 {
5021 /* For a destination in a shared library,
5022 use the PLT stub as target address to
5023 decide whether a branch stub is
5024 needed. */
5029 {
5033 destination = (sym_value
5036 }
5041 }
5044 {
5045 /* For a shared library, use the PLT stub as
5046 target address to decide whether a long
5047 branch stub is needed.
5048 For absolute code, they cannot be handled. */
5056 {
5060 destination = (sym_value
5063 }
5064 else
5066 }
5067 else
5068 {
5071 }
5075 }
5077 do
5078 {
5079 /* Determine what (if any) linker stub is needed. */
5087 /* Support for grouping stub sections. */
5090 /* Get the name of this stub. */
5096 /* We've either created a stub for this reloc already,
5097 or we are about to. */
5100 stub_entry = arm_stub_hash_lookup
5104 {
5105 /* The proper stub has already been created. */
5109 }
5112 htab);
5114 {
5117 }
5132 {
5135 }
5137 /* For historical reasons, use the existing names for
5138 ARM-to-Thumb and Thumb-to-ARM stubs. */
5149 else
5151 sym_name);
5154 }
5157 /* Look for relocations which might trigger Cortex-A8
5158 erratum. */
5164 {
5170 {
5171 /* Found a candidate. Note we haven't checked the
5172 destination is within 4K here: if we do so (and
5173 don't create an entry in a8_relocs) we can't tell
5174 that a branch should have been relocated when
5175 scanning later. */
5177 {
5183 }
5193 num_a8_relocs++;
5194 }
5195 }
5196 }
5198 /* We're done with the internal relocs, free them. */
5201 }
5204 {
5205 /* Sort relocs which might apply to Cortex-A8 erratum. */
5210 /* Scan for branches which might trigger Cortex-A8 erratum. */
5217 }
5218 }
5226 /* OK, we've added some stubs. Find out the new size of the
5227 stub sections. */
5231 {
5232 /* Ignore non-stub sections. */
5237 }
5241 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5244 {
5251 stub_sec->size
5253 NULL);
5254 }
5257 /* Ask the linker to do its stuff. */
5259 }
5261 /* Add stubs for Cortex-A8 erratum fixes now. */
5263 {
5265 {
5278 {
5281 stub_name);
5283 }
5302 }
5304 /* Stash the Cortex-A8 erratum fix array for use later in
5305 elf32_arm_write_section(). */
5308 }
5309 else
5310 {
5313 }
5316 error_ret_free_local:
5318 }
5320 /* Build all the stubs associated with the current output file. The
5321 stubs are kept in a hash table attached to the main linker hash
5322 table. We also set up the .plt entries for statically linked PIC
5323 functions here. This function is called via arm_elf_finish in the
5324 linker. */
5326 bfd_boolean
5328 {
5340 {
5341 bfd_size_type size;
5343 /* Ignore non-stub sections. */
5347 /* Allocate memory to hold the linker stubs. */
5353 }
5355 /* Build the stubs as directed by the stub hash table. */
5359 {
5360 /* Place the cortex a8 stubs last. */
5363 }
5366 }
5368 /* Locate the Thumb encoded calling stub for NAME. */
5374 {
5379 /* We need a pointer to the armelf specific hash table. */
5391 hash = elf_link_hash_lookup
5402 }
5404 /* Locate the ARM encoded calling stub for NAME. */
5410 {
5415 /* We need a pointer to the elfarm specific hash table. */
5427 myh = elf_link_hash_lookup
5438 }
5440 /* ARM->Thumb glue (static images):
5442 .arm
5443 __func_from_arm:
5444 ldr r12, __func_addr
5445 bx r12
5446 __func_addr:
5447 .word func @ behave as if you saw a ARM_32 reloc.
5449 (v5t static images)
5450 .arm
5451 __func_from_arm:
5452 ldr pc, __func_addr
5453 __func_addr:
5454 .word func @ behave as if you saw a ARM_32 reloc.
5456 (relocatable images)
5457 .arm
5458 __func_from_arm:
5459 ldr r12, __func_offset
5460 add r12, r12, pc
5461 bx r12
5462 __func_offset:
5463 .word func - . */
5465 #define ARM2THUMB_STATIC_GLUE_SIZE 12
5470 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5474 #define ARM2THUMB_PIC_GLUE_SIZE 16
5479 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
5481 .thumb .thumb
5482 .align 2 .align 2
5483 __func_from_thumb: __func_from_thumb:
5484 bx pc push {r6, lr}
5485 nop ldr r6, __func_addr
5486 .arm mov lr, pc
5487 b func bx r6
5488 .arm
5489 ;; back_to_thumb
5490 ldmia r13! {r6, lr}
5491 bx lr
5492 __func_addr:
5493 .word func */
5495 #define THUMB2ARM_GLUE_SIZE 8
5500 #define VFP11_ERRATUM_VENEER_SIZE 8
5502 #define ARM_BX_VENEER_SIZE 12
5507 #ifndef ELFARM_NABI_C_INCLUDED
5508 static void
5510 {
5515 {
5516 /* Do not include empty glue sections in the output. */
5518 {
5522 }
5524 }
5535 }
5537 bfd_boolean
5539 {
5547 ARM2THUMB_GLUE_SECTION_NAME);
5551 THUMB2ARM_GLUE_SECTION_NAME);
5555 VFP11_ERRATUM_VENEER_SECTION_NAME);
5559 ARM_BX_GLUE_SECTION_NAME);
5562 }
5564 /* Allocate space and symbols for calling a Thumb function from Arm mode.
5565 returns the symbol identifying the stub. */
5570 {
5577 bfd_vma val;
5578 bfd_size_type size;
5584 s = bfd_get_section_by_name
5596 myh = elf_link_hash_lookup
5600 {
5601 /* We've already seen this guy. */
5604 }
5606 /* The only trick here is using hash_table->arm_glue_size as the value.
5607 Even though the section isn't allocated yet, this is where we will be
5608 putting it. The +1 on the value marks that the stub has not been
5609 output yet - not that it is a Thumb function. */
5627 else
5634 }
5636 /* Allocate space for ARMv4 BX veneers. */
5638 static void
5640 {
5646 bfd_vma val;
5648 /* BX PC does not need a veneer. */
5656 /* Check if this veneer has already been allocated. */
5660 s = bfd_get_section_by_name
5665 /* Add symbol for veneer. */
5673 myh = elf_link_hash_lookup
5691 }
5694 /* Add an entry to the code/data map for section SEC. */
5696 static void
5698 {
5703 {
5708 }
5713 {
5718 }
5721 {
5724 }
5725 }
5728 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
5729 veneers are handled for now. */
5731 static bfd_vma
5737 {
5743 bfd_vma val;
5751 s = bfd_get_section_by_name
5766 myh = elf_link_hash_lookup
5781 /* Link veneer back to calling location. */
5795 /* A symbol for the return from the veneer. */
5799 myh = elf_link_hash_lookup
5816 /* Generate a mapping symbol for the veneer section, and explicitly add an
5817 entry for that symbol to the code/data map for the section. */
5819 {
5821 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
5822 ever requires this erratum fix. */
5832 /* The elf32_arm_init_maps function only cares about symbols from input
5833 BFDs. We must make a note of this generated mapping symbol
5834 ourselves so that code byteswapping works properly in
5835 elf32_arm_write_section. */
5837 }
5843 /* The offset of the veneer. */
5845 }
5847 #define ARM_GLUE_SECTION_FLAGS \
5848 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
5849 | SEC_READONLY | SEC_LINKER_CREATED)
5851 /* Create a fake section for use by the ARM backend of the linker. */
5853 static bfd_boolean
5855 {
5860 /* Already made. */
5869 /* Set the gc mark to prevent the section from being removed by garbage
5870 collection, despite the fact that no relocs refer to this section. */
5874 }
5876 /* Add the glue sections to ABFD. This function is called from the
5877 linker scripts in ld/emultempl/{armelf}.em. */
5879 bfd_boolean
5882 {
5883 /* If we are only performing a partial
5884 link do not bother adding the glue. */
5892 }
5894 /* Select a BFD to be used to hold the sections used by the glue code.
5895 This function is called from the linker scripts in ld/emultempl/
5896 {armelf/pe}.em. */
5898 bfd_boolean
5900 {
5903 /* If we are only performing a partial link
5904 do not bother getting a bfd to hold the glue. */
5908 /* Make sure we don't attach the glue sections to a dynamic object. */
5917 /* Save the bfd for later use. */
5921 }
5923 static void
5925 {
5929 }
5931 bfd_boolean
5934 {
5943 /* If we are only performing a partial link do not bother
5944 to construct any glue. */
5948 /* Here we have a bfd that is to be included on the link. We have a
5949 hook to do reloc rummaging, before section sizes are nailed down. */
5956 {
5958 abfd);
5960 }
5962 /* PR 5398: If we have not decided to include any loadable sections in
5963 the output then we will not have a glue owner bfd. This is OK, it
5964 just means that there is nothing else for us to do here. */
5968 /* Rummage around all the relocs and map the glue vectors. */
5975 {
5984 /* Load the relocs. */
5985 internal_relocs
5993 {
6002 /* These are the only relocation types we care about. */
6007 /* Get the section contents if we haven't done so already. */
6009 {
6010 /* Get cached copy if it exists. */
6013 else
6014 {
6015 /* Go get them off disk. */
6018 }
6019 }
6022 {
6028 }
6030 /* If the relocation is not against a symbol it cannot concern us. */
6033 /* We don't care about local symbols. */
6037 /* This is an external symbol. */
6042 /* If the relocation is against a static symbol it must be within
6043 the current section and so cannot be a cross ARM/Thumb relocation. */
6047 /* If the call will go through a PLT entry then we do not need
6048 glue. */
6053 {
6055 /* This one is a call from arm code. We need to look up
6056 the target of the call. If it is a thumb target, we
6057 insert glue. */
6064 }
6065 }
6076 }
6080 error_return:
6089 }
6090 #endif
6093 /* Initialise maps of ARM/Thumb/data for input BFDs. */
6095 void
6097 {
6102 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6112 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6113 should contain the number of local symbols, which should come before any
6114 global symbols. Mapping symbols are always local. */
6116 NULL);
6118 /* No internal symbols read? Skip this BFD. */
6123 {
6130 {
6135 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
6137 }
6138 }
6139 }
6142 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6143 say what they wanted. */
6145 void
6147 {
6155 {
6156 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6161 else
6163 }
6164 }
6167 void
6169 {
6175 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6177 {
6179 {
6186 /* Give a warning, but do as the user requests anyway. */
6189 }
6190 }
6192 /* For earlier architectures, we might need the workaround, but do not
6193 enable it by default. If users is running with broken hardware, they
6194 must enable the erratum fix explicitly. */
6196 }
6199 enum bfd_arm_vfp11_pipe
6200 {
6201 VFP11_FMAC,
6202 VFP11_LS,
6203 VFP11_DS,
6204 VFP11_BAD
6205 };
6207 /* Return a VFP register number. This is encoded as RX:X for single-precision
6208 registers, or X:RX for double-precision registers, where RX is the group of
6209 four bits in the instruction encoding and X is the single extension bit.
6210 RX and X fields are specified using their lowest (starting) bit. The return
6211 value is:
6213 0...31: single-precision registers s0...s31
6214 32...63: double-precision registers d0...d31.
6216 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6217 encounter VFP3 instructions, so we allow the full range for DP registers. */
6219 static unsigned int
6222 {
6225 else
6227 }
6229 /* Set bits in *WMASK according to a register number REG as encoded by
6230 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6232 static void
6234 {
6239 }
6241 /* Return TRUE if WMASK overwrites anything in REGS. */
6243 static bfd_boolean
6245 {
6249 {
6262 }
6265 }
6267 /* In this function, we're interested in two things: finding input registers
6268 for VFP data-processing instructions, and finding the set of registers which
6269 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6270 hold the written set, so FLDM etc. are easy to deal with (we're only
6271 interested in 32 SP registers or 16 dp registers, due to the VFP version
6272 implemented by the chip in question). DP registers are marked by setting
6273 both SP registers in the write mask). */
6275 static enum bfd_arm_vfp11_pipe
6278 {
6283 {
6293 {
6315 vfp_binop:
6323 {
6328 {
6342 /* These instructions will not bounce due to underflow. */
6348 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6349 registers to cause the erratum in previous instructions. */
6355 {
6360 /* Only FCVTSD can underflow. */
6367 }
6372 }
6373 }
6378 }
6379 }
6380 /* Two-register transfer. */
6382 {
6386 {
6389 else
6390 {
6393 }
6394 }
6397 }
6399 {
6404 {
6411 {
6419 }
6429 }
6432 }
6433 /* Single-register transfer. Note L==0. */
6435 {
6440 {
6443 /* Mark fmdhr and fmdlr as writing to the whole of the DP
6444 destination register. I don't know if this is exactly right,
6445 but it is the conservative choice. */
6451 }
6454 }
6457 }
6463 /* Look for potentially-troublesome code sequences which might trigger the
6464 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
6465 (available from ARM) for details of the erratum. A short version is
6466 described in ld.texinfo. */
6468 bfd_boolean
6470 {
6481 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
6482 The states transition as follows:
6484 0 -> 1 (vector) or 0 -> 2 (scalar)
6485 A VFP FMAC-pipeline instruction has been seen. Fill
6486 regs[0]..regs[numregs-1] with its input operands. Remember this
6487 instruction in 'first_fmac'.
6489 1 -> 2
6490 Any instruction, except for a VFP instruction which overwrites
6491 regs[*].
6493 1 -> 3 [ -> 0 ] or
6494 2 -> 3 [ -> 0 ]
6495 A VFP instruction has been seen which overwrites any of regs[*].
6496 We must make a veneer! Reset state to 0 before examining next
6497 instruction.
6499 2 -> 0
6500 If we fail to match anything in state 2, reset to state 0 and reset
6501 the instruction pointer to the instruction after 'first_fmac'.
6503 If the VFP11 vector mode is in use, there must be at least two unrelated
6504 instructions between anti-dependent VFP11 instructions to properly avoid
6505 triggering the erratum, hence the use of the extra state 1. */
6507 /* If we are only performing a partial link do not bother
6508 to construct any glue. */
6512 /* Skip if this bfd does not correspond to an ELF image. */
6516 /* We should have chosen a fix type by the time we get here. */
6522 /* Skip this BFD if it corresponds to an executable or dynamic object. */
6527 {
6531 /* If we don't have executable progbits, we're not interested in this
6532 section. Also skip if section is to be excluded. */
6552 elf32_arm_compare_mapping);
6555 {
6561 /* FIXME: Only ARM mode is supported at present. We may need to
6562 support Thumb-2 mode also at some point. */
6567 {
6582 {
6586 /* I'm assuming the VFP11 erratum can trigger with denorm
6587 operands on either the FMAC or the DS pipeline. This might
6588 lead to slightly overenthusiastic veneer insertion. */
6590 {
6594 }
6598 {
6601 other_regs,
6605 numregs))
6607 else
6609 }
6613 {
6616 other_regs,
6620 numregs))
6622 else
6623 {
6626 }
6627 }
6632 }
6635 {
6644 {
6651 }
6654 first_fmac);
6662 }
6665 }
6666 }
6672 }
6676 error_return:
6682 }
6684 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
6685 after sections have been laid out, using specially-named symbols. */
6687 void
6690 {
6698 /* Skip if this bfd does not correspond to an ELF image. */
6710 {
6715 {
6717 bfd_vma vma;
6720 {
6723 /* Find veneer symbol. */
6727 myh = elf_link_hash_lookup
6743 /* Find return location. */
6747 myh = elf_link_hash_lookup
6763 }
6764 }
6765 }
6768 }
6771 /* Set target relocation values needed during linking. */
6773 void
6780 bfd_arm_vfp11_fix vfp11_fix,
6783 {
6797 else
6798 {
6800 target2_type);
6801 }
6811 }
6813 /* Replace the target offset of a Thumb bl or b.w instruction. */
6815 static void
6817 {
6818 bfd_vma upper;
6819 bfd_vma lower;
6836 }
6838 /* Thumb code calling an ARM function. */
6840 static int
6848 bfd_vma offset,
6849 bfd_signed_vma addend,
6850 bfd_vma val,
6852 {
6854 bfd_vma my_offset;
6870 THUMB2ARM_GLUE_SECTION_NAME);
6877 {
6881 {
6888 }
6899 ret_offset =
6900 /* Address of destination of the stub. */
6903 /* Offset from the start of the current section
6904 to the start of the stubs. */
6906 /* Offset of the start of this stub from the start of the stubs. */
6907 + my_offset
6908 /* Address of the start of the current section. */
6910 /* The branch instruction is 4 bytes into the stub. */
6912 /* ARM branches work from the pc of the instruction + 8. */
6918 }
6922 /* Now go back and fix up the original BL insn to point to here. */
6923 ret_offset =
6924 /* Address of where the stub is located. */
6926 /* Address of where the BL is located. */
6929 /* Addend in the relocation. */
6930 - addend
6931 /* Biassing for PC-relative addressing. */
6937 }
6939 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
6947 bfd_vma val,
6950 {
6951 bfd_vma my_offset;
6967 {
6971 {
6976 }
6983 {
6984 /* For relocatable objects we can't use absolute addresses,
6985 so construct the address from a relative offset. */
6986 /* TODO: If the offset is small it's probably worth
6987 constructing the address with adds. */
6994 /* Adjust the offset by 4 for the position of the add,
6995 and 8 for the pipeline offset. */
7002 }
7004 {
7008 /* It's a thumb address. Add the low order bit. */
7011 }
7012 else
7013 {
7020 /* It's a thumb address. Add the low order bit. */
7025 }
7026 }
7031 }
7033 /* Arm code calling a Thumb function. */
7035 static int
7043 bfd_vma offset,
7044 bfd_signed_vma addend,
7045 bfd_vma val,
7047 {
7049 bfd_vma my_offset;
7060 ARM2THUMB_GLUE_SECTION_NAME);
7074 /* Somehow these are both 4 too far, so subtract 8. */
7076 + my_offset
7088 }
7090 /* Populate Arm stub for an exported Thumb function. */
7092 static bfd_boolean
7094 {
7101 bfd_vma val;
7105 /* Allocate stubs for exported Thumb functions on v4t. */
7114 ARM2THUMB_GLUE_SECTION_NAME);
7132 }
7134 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
7136 static bfd_vma
7138 {
7140 bfd_vma glue_addr;
7149 ARM_BX_GLUE_SECTION_NAME);
7159 {
7165 }
7168 }
7170 /* Generate Arm stubs for exported Thumb symbols. */
7171 static void
7174 {
7178 /* Ignore this if we are not called by the ELF backend linker. */
7185 /* If blx is available then exported Thumb symbols are OK and there is
7186 nothing to do. */
7191 link_info);
7192 }
7194 /* Reserve space for COUNT dynamic relocations in relocation selection
7195 SRELOC. */
7197 static void
7199 bfd_size_type count)
7200 {
7208 }
7210 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
7211 dynamic, the relocations should go in SRELOC, otherwise they should
7212 go in the special .rel.iplt section. */
7214 static void
7216 bfd_size_type count)
7217 {
7223 else
7224 {
7227 }
7228 }
7230 /* Add relocation REL to the end of relocation section SRELOC. */
7232 static void
7235 {
7250 }
7252 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
7253 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
7254 to .plt. */
7256 static void
7258 bfd_boolean is_iplt_entry,
7261 {
7269 {
7273 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
7275 }
7276 else
7277 {
7281 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
7284 /* If this is the first .plt entry, make room for the special
7285 first entry. */
7288 }
7290 /* Allocate the PLT entry itself, including any leading Thumb stub. */
7297 {
7298 /* We also need to make an entry in the .got.plt section, which
7299 will be placed in the .got section by the linker script. */
7302 }
7303 }
7305 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
7306 the entry lives in .iplt and resolves to (*SYM_VALUE)().
7307 Otherwise, DYNINDX is the index of the symbol in the dynamic
7308 symbol table and SYM_VALUE is undefined.
7310 ROOT_PLT points to the offset of the PLT entry from the start of its
7311 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
7312 bookkeeping information. */
7314 static void
7319 {
7325 bfd_vma plt_index;
7326 Elf_Internal_Rela rel;
7327 bfd_vma plt_header_size;
7328 bfd_vma got_header_size;
7332 /* Pick the appropriate sections and sizes. */
7334 {
7339 /* There are no reserved entries in .igot.plt, and no special
7340 first entry in .iplt. */
7343 }
7344 else
7345 {
7352 }
7355 /* Fill in the entry in the procedure linkage table. */
7357 {
7366 /* Fill in the entry in the .rel.plt section. */
7372 /* Get the index in the procedure linkage table which
7373 corresponds to this symbol. This is the index of this symbol
7374 in all the symbols for which we are making plt entries. The
7375 first entry in the procedure linkage table is reserved. */
7378 }
7379 else
7380 {
7387 /* Get the offset into the .(i)got.plt table of the entry that
7388 corresponds to this function. */
7391 /* Get the index in the procedure linkage table which
7392 corresponds to this symbol. This is the index of this symbol
7393 in all the symbols for which we are making plt entries.
7394 After the reserved .got.plt entries, all symbols appear in
7395 the same order as in .plt. */
7398 /* Calculate the address of the GOT entry. */
7403 /* ...and the address of the PLT entry. */
7410 {
7412 bfd_vma val;
7415 {
7423 else
7425 }
7426 }
7428 {
7430 bfd_vma val;
7433 {
7443 else
7445 }
7450 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
7451 referencing the GOT for this PLT entry. */
7458 /* Create the R_ARM_ABS32 relocation referencing the
7459 beginning of the PLT for this GOT entry. */
7464 }
7465 else
7466 {
7467 /* Calculate the displacement between the PLT slot and the
7468 entry in the GOT. The eight-byte offset accounts for the
7469 value produced by adding to pc in the first instruction
7470 of the PLT stub. */
7476 {
7481 }
7495 #ifdef FOUR_WORD_PLT
7497 #endif
7498 }
7500 /* Fill in the entry in the .rel(a).(i)plt section. */
7504 {
7505 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
7506 The dynamic linker or static executable then calls SYM_VALUE
7507 to determine the correct run-time value of the .igot.plt entry. */
7510 }
7511 else
7512 {
7516 }
7518 /* Fill in the entry in the global offset table. */
7521 }
7525 }
7527 /* Some relocations map to different relocations depending on the
7528 target. Return the real relocation. */
7530 static int
7533 {
7535 {
7539 else
7547 }
7548 }
7550 /* Return the base VMA address which should be subtracted from real addresses
7551 when resolving @dtpoff relocation.
7552 This is PT_TLS segment p_vaddr. */
7554 static bfd_vma
7556 {
7557 /* If tls_sec is NULL, we should have signalled an error already. */
7561 }
7563 /* Return the relocation value for @tpoff relocation
7564 if STT_TLS virtual address is ADDRESS. */
7566 static bfd_vma
7568 {
7570 bfd_vma base;
7572 /* If tls_sec is NULL, we should have signalled an error already. */
7577 }
7579 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
7580 VALUE is the relocation value. */
7582 static bfd_reloc_status_type
7584 {
7591 }
7593 /* Handle TLS relaxations. Relaxing is possible for symbols that use
7594 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
7595 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
7597 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
7598 is to then call final_link_relocate. Return other values in the
7599 case of error.
7601 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
7602 the pre-relaxed code. It would be nice if the relocs were updated
7603 to match the optimization. */
7605 static bfd_reloc_status_type
7609 {
7613 {
7620 else
7621 {
7625 else
7627 }
7632 /* Thumb insn. */
7635 {
7637 /* nop */
7639 }
7641 {
7643 /* nop */
7645 else
7646 /* ldr rx,[ry] */
7648 }
7650 {
7652 /* nop */
7654 else
7655 /* mov r0, rx */
7658 }
7659 else
7660 {
7662 /* It's a 32 bit instruction, fetch the rest of it for
7663 error generation. */
7670 }
7674 /* arm insn. */
7677 {
7679 /* mov rx, ry */
7682 }
7684 {
7686 /* nop */
7688 else
7689 /* ldr rx,[ry] */
7692 }
7694 {
7696 /* nop */
7698 else
7699 /* mov r0, rx */
7702 }
7703 else
7704 {
7709 }
7713 /* GD->IE relaxation, turn the instruction into 'nop' or
7714 'ldr r0, [pc,r0]' */
7720 /* GD->IE relaxation */
7722 /* add r0,pc; ldr r0, [r0] */
7725 /* nop.w */
7727 else
7728 /* nop; nop */
7734 }
7736 }
7738 /* For a given value of n, calculate the value of G_n as required to
7739 deal with group relocations. We return it in the form of an
7740 encoded constant-and-rotation, together with the final residual. If n is
7741 specified as less than zero, then final_residual is filled with the
7742 input value and no further action is performed. */
7744 static bfd_vma
7746 {
7748 bfd_vma g_n;
7753 {
7756 /* Calculate which part of the value to mask. */
7759 else
7760 {
7763 /* Determine the most significant bit in the residual and
7764 align the resulting value to a 2-bit boundary. */
7769 /* The desired shift is now (msb - 6), or zero, whichever
7770 is the greater. */
7774 }
7776 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
7781 /* Calculate the residual for the next time around. */
7783 }
7788 }
7790 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
7791 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
7793 static int
7795 {
7805 }
7807 /* Perform a relocation as part of a final link. */
7809 static bfd_reloc_status_type
7816 bfd_vma value,
7825 {
7835 bfd_vma addend;
7836 bfd_signed_vma signed_addend;
7838 bfd_vma dynreloc_value;
7843 bfd_vma plt_offset;
7844 bfd_vma gotplt_offset;
7845 bfd_boolean has_iplt_entry;
7853 /* Some relocation types map to different relocations depending on the
7854 target. We pick the right one here. */
7857 /* It is possible to have linker relaxations on some TLS access
7858 models. Update our information here. */
7864 /* If the start address has been set, then set the EF_ARM_HASENTRY
7865 flag. Setting this more than once is redundant, but the cost is
7866 not too high, and it keeps the code simple.
7868 The test is done here, rather than somewhere else, because the
7869 start address is only set just before the final link commences.
7871 Note - if the user deliberately sets a start address of 0, the
7872 flag will not be set. */
7883 else
7889 {
7893 {
7897 }
7898 else
7900 }
7901 else
7904 /* Record the symbol information that should be used in dynamic
7905 relocations. */
7911 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
7912 VALUE appropriately for relocations that we resolve at link time. */
7916 {
7921 {
7925 /* Populate .iplt entries here, because not all of them will
7926 be seen by finish_dynamic_symbol. The lower bit is set if
7927 we have already populated the entry. */
7929 plt_offset--;
7930 else
7931 {
7935 }
7937 /* Static relocations always resolve to the .iplt entry. */
7944 /* If there are non-call relocations that resolve to the .iplt
7945 entry, then all dynamic ones must too. */
7947 {
7950 }
7951 }
7952 else
7953 /* We populate the .plt entry in finish_dynamic_symbol. */
7955 }
7956 else
7957 {
7961 }
7964 {
7966 /* We don't need to find a value for this symbol. It's just a
7967 marker. */
7985 /* Handle relocations which should use the PLT entry. ABS32/REL32
7986 will use the symbol's value, which may point to a PLT entry, but we
7987 don't need to handle that here. If we created a PLT entry, all
7988 branches in this object should go to it, except if the PLT is too
7989 far away, in which case a long branch stub should be inserted. */
7996 {
7997 /* If we've created a .plt section, and assigned a PLT entry
7998 to this function, it must either be a STT_GNU_IFUNC reference
7999 or not be known to bind locally. In other cases, we should
8000 have cleared the PLT entry by now. */
8010 }
8012 /* When generating a shared object or relocatable executable, these
8013 relocations are copied into the output file to be resolved at
8014 run time. */
8031 {
8032 Elf_Internal_Rela outrel;
8038 {
8044 }
8068 else
8069 {
8072 /* This symbol is local, or marked to become local. */
8075 {
8078 /* On Symbian OS, the data segment and text segement
8079 can be relocated independently. Therefore, we
8080 must indicate the segment to which this
8081 relocation is relative. The BPABI allows us to
8082 use any symbol in the right segment; we just use
8083 the section symbol as it is convenient. (We
8084 cannot use the symbol given by "h" directly as it
8085 will not appear in the dynamic symbol table.)
8087 Note that the dynamic linker ignores the section
8088 symbol value, so we don't subtract osec->vma
8089 from the emitted reloc addend. */
8092 else
8096 {
8102 else
8105 }
8107 }
8108 else
8109 /* On SVR4-ish systems, the dynamic loader cannot
8110 relocate the text and data segments independently,
8111 so the symbol does not matter. */
8114 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
8115 to the .iplt entry. Instead, every non-call reference
8116 must use an R_ARM_IRELATIVE relocation to obtain the
8117 correct run-time address. */
8119 else
8123 else
8125 }
8129 /* If this reloc is against an external symbol, we do not want to
8130 fiddle with the addend. Otherwise, we need to include the symbol
8131 value so that it becomes an addend for the dynamic reloc. */
8138 }
8140 {
8149 {
8153 {
8154 /* Check for Arm calling Arm function. */
8155 /* FIXME: Should we translate the instruction into a BL
8156 instruction instead ? */
8160 input_bfd,
8162 }
8164 {
8165 /* Check for Arm calling Thumb function. */
8167 {
8172 error_message))
8174 else
8176 }
8177 }
8179 /* Check if a stub has to be inserted because the
8180 destination is too far or we are changing mode. */
8184 {
8195 {
8196 /* The target is out of reach, so redirect the
8197 branch to the local stub for this function. */
8202 stub_type);
8207 }
8208 else
8209 {
8210 /* If the call goes through a PLT entry, make sure to
8211 check distance to the right destination address. */
8213 {
8218 /* The PLT entry is in ARM mode, regardless of the
8219 target function. */
8221 }
8222 }
8223 }
8225 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
8226 where:
8227 S is the address of the symbol in the relocation.
8228 P is address of the instruction being relocated.
8229 A is the addend (extracted from the instruction) in bytes.
8231 S is held in 'value'.
8232 P is the base address of the section containing the
8233 instruction plus the offset of the reloc into that
8234 section, ie:
8235 (input_section->output_section->vma +
8236 input_section->output_offset +
8237 rel->r_offset).
8238 A is the addend, converted into bytes, ie:
8239 (signed_addend * 4)
8241 Note: None of these operations have knowledge of the pipeline
8242 size of the processor, thus it is up to the assembler to
8243 encode this information into the addend. */
8249 else
8250 /* RELA addends do not have to be adjusted by howto->size. */
8256 /* A branch to an undefined weak symbol is turned into a jump to
8257 the next instruction unless a PLT entry will be created.
8258 Do the same for local undefined symbols (but not for STN_UNDEF).
8259 The jump to the next instruction is optimized as a NOP depending
8260 on the architecture. */
8264 {
8269 else
8271 }
8272 else
8273 {
8274 /* Perform a signed range check. */
8285 {
8286 /* Set the H bit in the BLX instruction. */
8288 {
8291 else
8293 }
8295 /* Select the correct instruction (BL or BLX). */
8296 /* Only if we are not handling a BL to a stub. In this
8297 case, mode switching is performed by the stub. */
8300 else
8301 {
8304 }
8305 }
8306 }
8307 }
8339 {
8340 /* Check for overflow. */
8343 }
8349 }
8357 /* There is no way to tell whether the user intended to use a signed or
8358 unsigned addend. When checking for overflow we accept either,
8359 as specified by the AAELF. */
8369 /* See comment for R_ARM_ABS8. */
8377 /* Support ldr and str instructions for the thumb. */
8379 {
8380 /* Need to refetch addend. */
8382 /* ??? Need to determine shift amount from operand size. */
8384 }
8387 /* ??? Isn't value unsigned? */
8391 /* ??? Value needs to be properly shifted into place first. */
8397 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
8398 {
8399 bfd_vma insn;
8400 bfd_signed_vma relocation;
8406 {
8411 }
8433 }
8436 /* PR 10073: This reloc is not generated by the GNU toolchain,
8437 but it is supported for compatibility with third party libraries
8438 generated by other compilers, specifically the ARM/IAR. */
8439 {
8440 bfd_vma insn;
8441 bfd_signed_vma relocation;
8455 /* We do not check for overflow of this reloc. Although strictly
8456 speaking this is incorrect, it appears to be necessary in order
8457 to work with IAR generated relocs. Since GCC and GAS do not
8458 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
8459 a problem for them. */
8467 }
8470 /* Corresponds to: ldr.w reg, [pc, #offset]. */
8471 {
8472 bfd_vma insn;
8473 bfd_signed_vma relocation;
8479 {
8483 }
8503 }
8508 /* Thumb BL (branch long instruction). */
8509 {
8510 bfd_vma relocation;
8511 bfd_vma reloc_sign;
8515 bfd_signed_vma reloc_signed_max;
8516 bfd_signed_vma reloc_signed_min;
8517 bfd_vma check;
8518 bfd_signed_vma signed_check;
8522 /* A branch to an undefined weak symbol is turned into a jump to
8523 the next instruction unless a PLT entry will be created.
8524 The jump to the next instruction is optimized as a NOP.W for
8525 Thumb-2 enabled architectures. */
8528 {
8530 {
8533 }
8534 else
8535 {
8538 }
8540 }
8542 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
8543 with Thumb-1) involving the J1 and J2 bits. */
8545 {
8555 /* Sign extend. */
8559 }
8562 {
8563 /* Check for Thumb to Thumb call. */
8564 /* FIXME: Should we translate the instruction into a BL
8565 instruction instead ? */
8569 input_bfd,
8571 }
8572 else
8573 {
8574 /* If it is not a call to Thumb, assume call to Arm.
8575 If it is a call relative to a section name, then it is not a
8576 function call at all, but rather a long jump. Calls through
8577 the PLT do not require stubs. */
8579 {
8581 {
8582 /* Convert BL to BLX. */
8584 }
8587 {
8591 error_message))
8593 else
8595 }
8596 }
8600 {
8601 /* Make sure this is a BL. */
8603 }
8604 }
8608 {
8609 /* Check if a stub has to be inserted because the destination
8610 is too far. */
8622 {
8623 /* The target is out of reach or we are changing modes, so
8624 redirect the branch to the local stub for this
8625 function. */
8629 stub_type);
8635 /* If this call becomes a call to Arm, force BLX. */
8637 {
8642 }
8643 }
8644 }
8646 /* Handle calls via the PLT. */
8648 {
8654 {
8655 /* If the Thumb BLX instruction is available, convert
8656 the BL to a BLX instruction to call the ARM-mode
8657 PLT entry. */
8660 }
8661 else
8662 {
8663 /* Target the Thumb stub before the ARM PLT entry. */
8666 }
8668 }
8678 /* If this is a signed value, the rightshift just dropped
8679 leading 1 bits (assuming twos complement). */
8682 else
8685 /* Calculate the permissable maximum and minimum values for
8686 this relocation according to whether we're relocating for
8687 Thumb-2 or not. */
8694 /* Assumes two's complement. */
8699 /* For a BLX instruction, make sure that the relocation is rounded up
8700 to a word boundary. This follows the semantics of the instruction
8701 which specifies that bit 1 of the target address will come from bit
8702 1 of the base address. */
8705 /* Put RELOCATION back into the insn. Assumes two's complement.
8706 We use the Thumb-2 encoding, which is safe even if dealing with
8707 a Thumb-1 instruction by virtue of our overflow check above. */
8717 /* Put the relocated value back in the object file: */
8722 }
8726 /* Thumb32 conditional branch instruction. */
8727 {
8728 bfd_vma relocation;
8734 bfd_signed_vma signed_check;
8736 /* Need to refetch the addend, reconstruct the top three bits,
8737 and squish the two 11 bit pieces together. */
8739 {
8753 }
8755 /* Handle calls via the PLT. */
8757 {
8761 /* Target the Thumb stub before the ARM PLT entry. */
8764 }
8766 /* ??? Should handle interworking? GCC might someday try to
8767 use this for tail calls. */
8778 /* Put RELOCATION back into the insn. */
8779 {
8788 }
8790 /* Put the relocated value back in the object file: */
8795 }
8800 /* Thumb B (branch) instruction). */
8801 {
8802 bfd_signed_vma relocation;
8805 bfd_signed_vma signed_check;
8807 /* CZB cannot jump backward. */
8812 {
8813 /* Need to refetch addend. */
8816 {
8820 }
8821 else
8823 /* The value in the insn has been right shifted. We need to
8824 undo this, so that we can perform the address calculation
8825 in terms of bytes. */
8827 }
8839 else
8845 /* Assumes two's complement. */
8850 }
8855 {
8856 bfd_vma insn;
8857 bfd_vma relocation;
8861 {
8862 /* Extract the addend. */
8865 }
8875 }
8883 /* Relocation is relative to the start of the
8884 global offset table. */
8890 /* If we are addressing a Thumb function, we need to adjust the
8891 address by one, so that attempts to call the function pointer will
8892 correctly interpret it as Thumb code. */
8896 /* Note that sgot->output_offset is not involved in this
8897 calculation. We always want the start of .got. If we
8898 define _GLOBAL_OFFSET_TABLE in a different way, as is
8899 permitted by the ABI, we might have to change this
8900 calculation. */
8907 /* Use global offset table as symbol value. */
8921 /* Relocation is to the entry for this symbol in the
8922 global offset table. */
8929 {
8930 /* We have a relocation against a locally-binding STT_GNU_IFUNC
8931 symbol, and the relocation resolves directly to the runtime
8932 target rather than to the .iplt entry. This means that any
8933 .got entry would be the same value as the .igot.plt entry,
8934 so there's no point creating both. */
8937 }
8939 {
8940 bfd_vma off;
8945 {
8946 /* We have already processsed one GOT relocation against
8947 this symbol. */
8952 }
8953 else
8954 {
8955 Elf_Internal_Rela outrel;
8958 {
8959 /* If the symbol doesn't resolve locally in a static
8960 object, we have an undefined reference. If the
8961 symbol doesn't resolve locally in a dynamic object,
8962 it should be resolved by the dynamic linker. */
8964 {
8967 }
8968 else
8971 }
8972 else
8973 {
8978 else
8981 }
8983 /* The GOT entry is initialized to zero by default.
8984 See if we should install a different value. */
8987 {
8991 }
8994 {
8999 }
9001 }
9003 }
9004 else
9005 {
9006 bfd_vma off;
9013 /* The offset must always be a multiple of 4. We use the
9014 least significant bit to record whether we have already
9015 generated the necessary reloc. */
9018 else
9019 {
9024 {
9025 Elf_Internal_Rela outrel;
9033 else
9036 }
9039 }
9042 }
9058 {
9059 bfd_vma off;
9068 else
9069 {
9070 /* If we don't know the module number, create a relocation
9071 for it. */
9073 {
9074 Elf_Internal_Rela outrel;
9089 }
9090 else
9094 }
9102 }
9111 {
9119 {
9120 bfd_boolean dyn;
9125 {
9128 }
9132 }
9133 else
9134 {
9139 }
9141 /* Linker relaxations happens from one of the
9142 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
9150 else
9151 {
9153 Elf_Internal_Rela outrel;
9156 /* The GOT entries have not been initialized yet. Do it
9157 now, and emit any relocations. If both an IE GOT and a
9158 GD GOT are necessary, we emit the GD first. */
9164 {
9167 }
9170 {
9173 /* We should have relaxed, unless this is an undefined
9174 weak symbol. */
9183 + offplt
9195 /* For globals, the first word in the relocation gets
9196 the relocation index and the top bit set, or zero,
9197 if we're binding now. For locals, it gets the
9198 symbol's offset in the tls section. */
9206 /* Second word in the relocation is always zero. */
9210 }
9212 {
9214 {
9230 else
9231 {
9234 R_ARM_TLS_DTPOFF32);
9243 }
9244 }
9245 else
9246 {
9247 /* If we are not emitting relocations for a
9248 general dynamic reference, then we must be in a
9249 static link or an executable link with the
9250 symbol binding locally. Mark it as belonging
9251 to module 1, the executable. */
9256 }
9259 }
9262 {
9264 {
9267 else
9279 }
9280 else
9284 }
9288 else
9290 }
9299 {
9300 bfd_signed_vma offset;
9301 enum elf32_arm_stub_type stub_type
9309 {
9311 = elf32_arm_get_stub_entry
9317 }
9318 else
9324 {
9333 }
9334 else
9335 {
9336 /* Thumb blx encodes the offset in a complicated
9337 fashion. */
9342 input_section->output_offset
9345 /* Round up the offset to a word boundary */
9358 }
9359 }
9360 /* These relocations needs special care, as besides the fact
9361 they point somewhere in .gotplt, the addend must be
9362 adjusted accordingly depending on the type of instruction
9363 we refer to */
9365 {
9374 {
9381 /* bl/blx */
9384 /* add */
9386 else
9387 {
9393 }
9394 }
9395 else
9396 {
9400 {
9416 }
9417 }
9425 }
9426 else
9435 }
9439 {
9445 }
9446 else
9455 {
9458 /* Ensure that we have a BX instruction. */
9462 {
9463 /* Branch to veneer. */
9464 bfd_vma glue_addr;
9471 }
9472 else
9473 {
9474 /* Preserve Rm (lowest four bits) and the condition code
9475 (highest four bits). Other bits encode MOV PC,Rm. */
9477 }
9480 }
9487 /* Until we properly support segment-base-relative addressing then
9488 we assume the segment base to be zero, as for the group relocations.
9489 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
9490 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
9494 {
9498 {
9501 }
9523 }
9530 /* Until we properly support segment-base-relative addressing then
9531 we assume the segment base to be zero, as for the above relocations.
9532 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
9533 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
9534 as R_ARM_THM_MOVT_ABS. */
9538 {
9539 bfd_vma insn;
9545 {
9551 }
9577 }
9590 {
9594 /* sb should be the origin of the *segment* containing the symbol.
9595 It is not clear how to obtain this OS-dependent value, so we
9596 make an arbitrary choice of zero. */
9598 bfd_vma residual;
9599 bfd_vma g_n;
9600 bfd_signed_vma signed_value;
9603 /* Determine which group of bits to select. */
9605 {
9627 }
9629 /* If REL, extract the addend from the insn. If RELA, it will
9630 have already been fetched for us. */
9632 {
9639 else
9640 {
9641 /* Compensate for the fact that in the instruction, the
9642 rotation is stored in multiples of 2 bits. */
9645 /* Rotate "constant" right by "rotation" bits. */
9648 }
9650 /* Determine if the instruction is an ADD or a SUB.
9651 (For REL, this determines the sign of the addend.) */
9654 {
9660 }
9663 }
9665 /* Compute the value (X) to go in the place. */
9671 /* PC relative. */
9673 else
9674 /* Section base relative. */
9677 /* If the target symbol is a Thumb function, then set the
9678 Thumb bit in the address. */
9682 /* Calculate the value of the relevant G_n, in encoded
9683 constant-with-rotation format. */
9687 /* Check for overflow if required. */
9694 {
9700 }
9702 /* Mask out the value and the ADD/SUB part of the opcode; take care
9703 not to destroy the S bit. */
9706 /* Set the opcode according to whether the value to go in the
9707 place is negative. */
9710 else
9713 /* Encode the offset. */
9717 }
9726 {
9731 bfd_vma residual;
9732 bfd_signed_vma signed_value;
9735 /* Determine which groups of bits to calculate. */
9737 {
9755 }
9757 /* If REL, extract the addend from the insn. If RELA, it will
9758 have already been fetched for us. */
9760 {
9763 }
9765 /* Compute the value (X) to go in the place. */
9769 /* PC relative. */
9771 else
9772 /* Section base relative. */
9775 /* Calculate the value of the relevant G_{n-1} to obtain
9776 the residual at that stage. */
9779 /* Check for overflow. */
9781 {
9787 }
9789 /* Mask out the value and U bit. */
9792 /* Set the U bit if the value to go in the place is non-negative. */
9796 /* Encode the offset. */
9800 }
9809 {
9814 bfd_vma residual;
9815 bfd_signed_vma signed_value;
9818 /* Determine which groups of bits to calculate. */
9820 {
9838 }
9840 /* If REL, extract the addend from the insn. If RELA, it will
9841 have already been fetched for us. */
9843 {
9846 }
9848 /* Compute the value (X) to go in the place. */
9852 /* PC relative. */
9854 else
9855 /* Section base relative. */
9858 /* Calculate the value of the relevant G_{n-1} to obtain
9859 the residual at that stage. */
9862 /* Check for overflow. */
9864 {
9870 }
9872 /* Mask out the value and U bit. */
9875 /* Set the U bit if the value to go in the place is non-negative. */
9879 /* Encode the offset. */
9883 }
9892 {
9897 bfd_vma residual;
9898 bfd_signed_vma signed_value;
9901 /* Determine which groups of bits to calculate. */
9903 {
9921 }
9923 /* If REL, extract the addend from the insn. If RELA, it will
9924 have already been fetched for us. */
9926 {
9929 }
9931 /* Compute the value (X) to go in the place. */
9935 /* PC relative. */
9937 else
9938 /* Section base relative. */
9941 /* Calculate the value of the relevant G_{n-1} to obtain
9942 the residual at that stage. */
9945 /* Check for overflow. (The absolute value to go in the place must be
9946 divisible by four and, after having been divided by four, must
9947 fit in eight bits.) */
9949 {
9955 }
9957 /* Mask out the value and U bit. */
9960 /* Set the U bit if the value to go in the place is non-negative. */
9964 /* Encode the offset. */
9968 }
9973 }
9974 }
9976 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
9977 static void
9981 bfd_signed_vma increment)
9982 {
9983 bfd_signed_vma addend;
9987 {
10005 }
10006 else
10007 {
10008 bfd_vma contents;
10012 /* Get the (signed) value from the instruction. */
10015 {
10016 bfd_signed_vma mask;
10021 }
10023 /* Add in the increment, (which is a byte value). */
10025 {
10037 /* Should we check for overflow here ? */
10039 /* Drop any undesired bits. */
10042 }
10047 }
10048 }
10050 #define IS_ARM_TLS_RELOC(R_TYPE) \
10051 ((R_TYPE) == R_ARM_TLS_GD32 \
10052 || (R_TYPE) == R_ARM_TLS_LDO32 \
10053 || (R_TYPE) == R_ARM_TLS_LDM32 \
10054 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
10055 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
10056 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
10057 || (R_TYPE) == R_ARM_TLS_LE32 \
10058 || (R_TYPE) == R_ARM_TLS_IE32 \
10059 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
10061 /* Specific set of relocations for the gnu tls dialect. */
10062 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
10063 ((R_TYPE) == R_ARM_TLS_GOTDESC \
10064 || (R_TYPE) == R_ARM_TLS_CALL \
10065 || (R_TYPE) == R_ARM_THM_TLS_CALL \
10066 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
10067 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
10069 /* Relocate an ARM ELF section. */
10071 static bfd_boolean
10080 {
10098 {
10105 bfd_vma relocation;
10106 bfd_reloc_status_type r;
10107 arelent bfd_reloc;
10128 {
10133 /* An object file might have a reference to a local
10134 undefined symbol. This is a daft object file, but we
10135 should at least do something about it. V4BX & NONE
10136 relocations do not use the symbol and are explicitly
10137 allowed to use the undefined symbol, so allow those.
10138 Likewise for relocations against STN_UNDEF. */
10144 {
10151 }
10154 {
10161 {
10166 {
10188 {
10194 }
10198 /* Get the (signed) value from the instruction. */
10201 {
10202 bfd_signed_vma mask;
10207 }
10209 }
10212 addend =
10217 /* Cases here must match those in the preceeding
10218 switch statement. */
10220 {
10243 }
10244 }
10245 }
10246 else
10248 }
10249 else
10250 {
10251 bfd_boolean warned;
10259 }
10266 {
10267 /* This is a relocatable link. We don't have to change
10268 anything, unless the reloc is against a section symbol,
10269 in which case we have to adjust according to where the
10270 section symbol winds up in the output section. */
10272 {
10276 else
10278 }
10280 }
10284 else
10285 {
10286 name = (bfd_elf_string_from_elf_section
10290 }
10298 {
10303 input_bfd,
10304 input_section,
10307 name);
10308 }
10310 /* We call elf32_arm_final_link_relocate unless we're completely
10311 done, i.e., the relaxation produced the final output we want,
10312 and we won't let anybody mess with it. Also, we have to do
10313 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
10314 both in relaxed and non-relaxed cases */
10320 {
10323 /* This may have been marked unresolved because it came from
10324 a shared library. But we've just dealt with that. */
10326 }
10327 else
10338 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
10339 because such sections are not SEC_ALLOC and thus ld.so will
10340 not process them. */
10344 {
10347 input_bfd,
10348 input_section,
10353 }
10356 {
10358 {
10360 /* If the overflowing reloc was to an undefined symbol,
10361 we have already printed one error message and there
10362 is no point complaining again. */
10388 /* error_message should already be set. */
10393 /* Fall through. */
10395 common_error:
10402 }
10403 }
10404 }
10407 }
10409 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
10410 adds the edit to the start of the list. (The list must be built in order of
10411 ascending TINDEX: the function's callers are primarily responsible for
10412 maintaining that condition). */
10414 static void
10417 arm_unwind_edit_type type,
10420 {
10429 {
10439 }
10440 else
10441 {
10448 }
10449 }
10453 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
10454 static void
10456 {
10464 /* Adjust size of output section. */
10466 }
10468 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
10469 static void
10471 {
10481 }
10483 /* Scan .ARM.exidx tables, and create a list describing edits which should be
10484 made to those tables, such that:
10486 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
10487 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
10488 codes which have been inlined into the index).
10490 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
10492 The edits are applied when the tables are written
10493 (in elf32_arm_write_section).
10494 */
10496 bfd_boolean
10500 bfd_boolean merge_exidx_entries)
10501 {
10508 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
10509 text sections. */
10511 {
10515 {
10523 {
10524 Elf_Internal_Shdr *linked_hdr
10532 /* Link this .ARM.exidx section back from the text section it
10533 describes. */
10535 }
10536 }
10537 }
10539 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
10540 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
10541 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
10544 {
10551 bfd_vma j;
10562 {
10563 /* Section has no unwind data. */
10567 /* Ignore zero sized sections. */
10574 }
10576 /* Skip /DISCARD/ sections. */
10593 /* An error? */
10597 {
10602 /* An EXIDX_CANTUNWIND entry. */
10604 {
10608 }
10609 /* Inlined unwinding data. Merge if equal to previous. */
10611 {
10617 }
10618 /* Normal table entry. In theory we could merge these too,
10619 but duplicate entries are likely to be much less common. */
10620 else
10624 {
10629 }
10632 }
10634 /* Free contents if we allocated it ourselves. */
10638 /* Record edits to be applied later (in elf32_arm_write_section). */
10647 }
10649 /* Add terminating CANTUNWIND entry. */
10654 }
10656 static bfd_boolean
10659 {
10675 }
10677 static bfd_boolean
10679 {
10686 /* Invoke the regular ELF backend linker to do all the work. */
10690 /* Process stub sections (eg BE8 encoding, ...). */
10694 {
10696 /* Only process it once, in its link_sec slot. */
10698 {
10704 }
10705 }
10707 /* Write out any glue sections now that we have created all the
10708 stubs. */
10710 {
10713 ARM2THUMB_GLUE_SECTION_NAME))
10718 THUMB2ARM_GLUE_SECTION_NAME))
10723 VFP11_ERRATUM_VENEER_SECTION_NAME))
10728 ARM_BX_GLUE_SECTION_NAME))
10730 }
10733 }
10735 /* Set the right machine number. */
10737 static bfd_boolean
10739 {
10750 else
10754 }
10756 /* Function to keep ARM specific flags in the ELF header. */
10758 static bfd_boolean
10760 {
10763 {
10765 {
10768 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
10769 abfd);
10770 else
10771 _bfd_error_handler
10773 abfd);
10774 }
10775 }
10776 else
10777 {
10780 }
10783 }
10785 /* Copy backend specific data from one object module to another. */
10787 static bfd_boolean
10789 {
10790 flagword in_flags;
10791 flagword out_flags;
10802 {
10803 /* Cannot mix APCS26 and APCS32 code. */
10807 /* Cannot mix float APCS and non-float APCS code. */
10811 /* If the src and dest have different interworking flags
10812 then turn off the interworking bit. */
10814 {
10816 _bfd_error_handler
10817 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
10821 }
10823 /* Likewise for PIC, though don't warn for this case. */
10826 }
10831 /* Also copy the EI_OSABI field. */
10835 /* Copy object attributes. */
10839 }
10841 /* Values for Tag_ABI_PCS_R9_use. */
10842 enum
10843 {
10844 AEABI_R9_V6,
10845 AEABI_R9_SB,
10846 AEABI_R9_TLS,
10847 AEABI_R9_unused
10848 };
10850 /* Values for Tag_ABI_PCS_RW_data. */
10851 enum
10852 {
10853 AEABI_PCS_RW_data_absolute,
10854 AEABI_PCS_RW_data_PCrel,
10855 AEABI_PCS_RW_data_SBrel,
10856 AEABI_PCS_RW_data_unused
10857 };
10859 /* Values for Tag_ABI_enum_size. */
10860 enum
10861 {
10862 AEABI_enum_unused,
10863 AEABI_enum_short,
10864 AEABI_enum_wide,
10865 AEABI_enum_forced_wide
10866 };
10868 /* Determine whether an object attribute tag takes an integer, a
10869 string or both. */
10871 static int
10873 {
10882 else
10884 }
10886 /* The ABI defines that Tag_conformance should be emitted first, and that
10887 Tag_nodefaults should be second (if either is defined). This sets those
10888 two positions, and bumps up the position of all the remaining tags to
10889 compensate. */
10890 static int
10892 {
10902 }
10904 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
10905 static bfd_boolean
10907 {
10909 {
10910 _bfd_error_handler
10915 }
10916 else
10917 {
10918 _bfd_error_handler
10922 }
10923 }
10925 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
10926 Returns -1 if no architecture could be read. */
10928 static int
10930 {
10934 /* Note: the tag and its argument below are uleb128 values, though
10935 currently-defined values fit in one byte for each. */
10942 /* This tag is "safely ignorable", so don't complain if it looks funny. */
10944 }
10946 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
10947 The tag is removed if ARCH is -1. */
10949 static void
10951 {
10956 {
10959 }
10961 /* Note: the tag and its argument below are uleb128 values, though
10962 currently-defined values fit in one byte for each. */
10968 }
10970 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
10971 into account. */
10973 static int
10976 {
10977 #define T(X) TAG_CPU_ARCH_##X
10980 {
10990 };
10992 {
11003 };
11005 {
11017 };
11019 {
11032 };
11034 {
11048 };
11050 {
11065 };
11067 {
11083 };
11085 {
11086 v6t2,
11087 v6k,
11088 v7,
11089 v6_m,
11090 v6s_m,
11091 v7e_m,
11092 /* Pseudo-architecture. */
11093 v4t_plus_v6_m
11094 };
11096 /* Check we've not got a higher architecture than we know about. */
11099 {
11102 }
11104 /* Override old tag if we have a Tag_also_compatible_with on the output. */
11110 /* And override the new tag if we have a Tag_also_compatible_with on the
11111 input. */
11120 /* Architectures before V6KZ add features monotonically. */
11126 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
11127 as the canonical version. */
11129 {
11132 }
11133 else
11137 {
11141 }
11144 #undef T
11145 }
11147 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
11148 are conflicting attributes. */
11150 static bfd_boolean
11152 {
11155 /* Some tags have 0 = don't care, 1 = strong requirement,
11156 2 = weak requirement. */
11161 /* Skip the linker stubs file. This preserves previous behavior
11162 of accepting unknown attributes in the first input file - but
11163 is that a bug? */
11168 {
11169 /* This is the first object. Copy the attributes. */
11174 /* Use the Tag_null value to indicate the attributes have been
11175 initialized. */
11178 /* We do not output objects with Tag_MPextension_use_legacy - we move
11179 the attribute's value to Tag_MPextension_use. */
11181 {
11185 {
11186 _bfd_error_handler
11190 }
11196 }
11199 }
11203 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
11205 {
11206 /* Ignore mismatches if the object doesn't use floating point. */
11210 {
11211 _bfd_error_handler
11216 }
11217 }
11220 {
11221 /* Merge this attribute with existing attributes. */
11223 {
11226 /* These are merged after Tag_CPU_arch. */
11231 /* Use the first value seen. */
11235 {
11239 /* These aren't real CPU names, but we can't guess
11240 that from the architecture version alone. */
11253 "ARM v6S-M"
11254 };
11256 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
11262 secondary_compat);
11265 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
11269 {
11270 /* The output architecture has been changed to match the
11271 input architecture. Use the input names. */
11278 }
11279 else
11280 {
11283 }
11285 /* If we still don't have a value for Tag_CPU_name,
11286 make one up now. Tag_CPU_raw_name remains blank. */
11291 }
11298 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
11307 /* Use the largest value specified. */
11314 /* Use the smallest value specified. */
11323 {
11324 /* This error message should be enabled once all non-conformant
11325 binaries in the toolchain have had the attributes set
11326 properly.
11327 _bfd_error_handler
11328 (_("error: %B: 8-byte data alignment conflicts with %B"),
11329 obfd, ibfd);
11330 result = FALSE; */
11331 }
11332 /* Fall through. */
11335 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
11336 value if greater than 2 (for future-proofing). */
11344 /* The virtualization tag effectively stores two bits of
11345 information: the intended use of TrustZone (in bit 0), and the
11346 intended use of Virtualization (in bit 1). */
11351 {
11354 else
11355 {
11356 _bfd_error_handler
11361 }
11362 }
11367 {
11368 /* 0 will merge with anything.
11369 'A' and 'S' merge to 'A'.
11370 'R' and 'S' merge to 'R'.
11371 'M' and 'A|R|S' is an error. */
11380 else
11381 {
11382 _bfd_error_handler
11384 ibfd,
11388 }
11389 }
11392 {
11393 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
11394 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
11395 when it's 0. It might mean absence of FP hardware if
11396 Tag_FP_arch is zero, otherwise it is effectively SP + DP. */
11398 static const struct
11399 {
11403 {
11411 };
11416 /* If the output has no requirement about FP hardware,
11417 follow the requirement of the input. */
11419 {
11425 }
11426 /* If the input has no requirement about FP hardware, do
11427 nothing. */
11429 {
11432 }
11434 /* Both the input and the output have nonzero Tag_FP_arch.
11435 So Tag_ABI_HardFP_use is (SP & DP) when it's zero. */
11437 /* If both the input and the output have zero Tag_ABI_HardFP_use,
11438 do nothing. */
11441 ;
11442 /* If the input and the output have different Tag_ABI_HardFP_use,
11443 the combination of them is 3 (SP & DP). */
11448 /* Now we can handle Tag_FP_arch. */
11450 /* Values greater than 6 aren't defined, so just pick the
11451 biggest */
11453 {
11456 }
11457 /* The output uses the superset of input features
11458 (ISA version) and registers. */
11465 /* This assumes all possible supersets are also a valid
11466 options. */
11468 {
11472 }
11474 }
11480 {
11481 /* It's sometimes ok to mix different configs, so this is only
11482 a warning. */
11483 _bfd_error_handler
11485 }
11491 {
11492 _bfd_error_handler
11495 }
11503 {
11504 _bfd_error_handler
11506 ibfd);
11508 }
11509 /* Use the smallest value specified. */
11516 {
11517 _bfd_error_handler
11518 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
11520 }
11526 {
11529 {
11530 /* The existing object is compatible with anything.
11531 Use whatever requirements the new object has. */
11533 }
11537 {
11548 _bfd_error_handler
11549 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
11551 }
11552 }
11555 /* Aready done. */
11559 {
11560 _bfd_error_handler
11564 }
11567 /* Merged in target-independent code. */
11570 /* This is handled along with Tag_FP_arch. */
11574 {
11576 {
11577 _bfd_error_handler
11581 }
11582 }
11588 /* This tag is set to zero if we can use UDIV and SDIV in Thumb
11589 mode on a v7-M or v7-R CPU; to one if we can not use UDIV or
11590 SDIV at all; and to two if we can use UDIV or SDIV on a v7-A
11591 CPU. We will merge as follows: If the input attribute's value
11592 is one then the output attribute's value remains unchanged. If
11593 the input attribute's value is zero or two then if the output
11594 attribute's value is one the output value is set to the input
11595 value, otherwise the output value must be the same as the
11596 inputs. */
11598 {
11600 {
11601 _bfd_error_handler
11605 }
11606 }
11614 /* We don't output objects with Tag_MPextension_use_legacy - we
11615 move the value to Tag_MPextension_use. */
11617 {
11619 {
11620 _bfd_error_handler
11623 ibfd);
11625 }
11626 }
11634 /* This tag is set if it exists, but the value is unused (and is
11635 typically zero). We don't actually need to do anything here -
11636 the merge happens automatically when the type flags are merged
11637 below. */
11640 /* Already done in Tag_CPU_arch. */
11643 /* Keep the attribute if it matches. Throw it away otherwise.
11644 No attribute means no claim to conform. */
11651 result
11653 }
11655 /* If out_attr was copied from in_attr then it won't have a type yet. */
11658 }
11660 /* Merge Tag_compatibility attributes and any common GNU ones. */
11664 /* Check for any attributes not known on ARM. */
11668 }
11671 /* Return TRUE if the two EABI versions are incompatible. */
11673 static bfd_boolean
11675 {
11676 /* v4 and v5 are the same spec before and after it was released,
11677 so allow mixing them. */
11683 }
11685 /* Merge backend specific data from an object file to the output
11686 object file when linking. */
11688 static bfd_boolean
11691 /* Display the flags field. */
11693 static bfd_boolean
11695 {
11701 /* Print normal ELF private data. */
11705 /* Ignore init flag - it may not be set, despite the flags field
11706 containing valid data. */
11708 /* xgettext:c-format */
11712 {
11714 /* The following flag bits are GNU extensions and not part of the
11715 official ARM ELF extended ABI. Hence they are only decoded if
11716 the EABI version is not set. */
11722 else
11729 else
11758 else
11769 else
11792 eabi:
11805 }
11823 }
11825 static int
11827 {
11829 {
11834 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
11835 This allows us to distinguish between data used by Thumb instructions
11836 and non-data (which is probably code) inside Thumb regions of an
11837 executable. */
11844 }
11847 }
11855 {
11858 {
11862 }
11865 }
11867 /* Update the got entry reference counts for the section being removed. */
11869 static bfd_boolean
11874 {
11898 {
11903 bfd_boolean call_reloc_p;
11904 bfd_boolean may_become_dynamic_p;
11905 bfd_boolean may_need_local_target_p;
11911 {
11916 }
11926 {
11932 {
11935 }
11937 {
11940 }
11961 {
11964 }
11965 /* Fall through. */
11978 /* Should the interworking branches be here also? */
11981 {
11984 {
11987 }
11988 else
11990 }
11991 else
11997 }
12001 {
12014 }
12017 {
12023 else
12024 {
12034 }
12037 {
12038 /* Everything must go for SEC. */
12041 }
12042 }
12043 }
12046 }
12048 /* Look through the relocs for a section during the first phase. */
12050 static bfd_boolean
12053 {
12061 bfd_boolean call_reloc_p;
12062 bfd_boolean may_become_dynamic_p;
12063 bfd_boolean may_need_local_target_p;
12077 /* Create dynamic sections for relocatable executables so that we can
12078 copy relocations. */
12081 {
12084 }
12099 {
12111 /* PR 9934: It is possible to have relocations that do not
12112 refer to symbols, thus it is also possible to have an
12113 object file containing relocations but no symbol table. */
12115 {
12117 r_symndx);
12119 }
12124 {
12126 {
12127 /* A local symbol. */
12132 }
12133 else
12134 {
12139 }
12140 }
12148 /* Could be done earlier, if h were already available. */
12151 {
12161 /* This symbol requires a global offset table entry. */
12162 {
12166 {
12177 }
12180 {
12183 }
12184 else
12185 {
12186 /* This is a global offset table entry for a local symbol. */
12191 }
12193 /* If a variable is accessed with both tls methods, two
12194 slots may be created. */
12199 /* We will already have issued an error message if there
12200 is a TLS/non-TLS mismatch, based on the symbol
12201 type. So just combine any TLS types needed. */
12206 /* If the symbol is accessed in both IE and GDESC
12207 method, we're able to relax. Turn off the GDESC flag,
12208 without messing up with any other kind of tls types
12209 that may be involved */
12214 {
12217 else
12219 }
12220 }
12221 /* Fall through. */
12226 /* Fall through. */
12248 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
12249 ldr __GOTT_INDEX__ offsets. */
12251 {
12254 }
12255 /* Fall through. */
12262 {
12264 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
12269 }
12271 /* Fall through. */
12281 /* Should the interworking branches be listed here? */
12284 {
12287 {
12288 /* In shared libraries and relocatable executables,
12289 we treat local relative references as calls;
12290 see the related SYMBOL_CALLS_LOCAL code in
12291 allocate_dynrelocs. */
12294 }
12295 else
12296 /* We are creating a shared library or relocatable
12297 executable, and this is a reloc against a global symbol,
12298 or a non-PC-relative reloc against a local symbol.
12299 We may need to copy the reloc into the output. */
12301 }
12302 else
12306 /* This relocation describes the C++ object vtable hierarchy.
12307 Reconstruct it for later use during GC. */
12313 /* This relocation describes which C++ vtable entries are actually
12314 used. Record for later use during GC. */
12321 }
12324 {
12326 /* We may need a .plt entry if the function this reloc
12327 refers to is in a different object, regardless of the
12328 symbol's type. We can't tell for sure yet, because
12329 something later might force the symbol local. */
12332 /* If this reloc is in a read-only section, we might
12333 need a copy reloc. We can't check reliably at this
12334 stage whether the section is read-only, as input
12335 sections have not yet been mapped to output sections.
12336 Tentatively set the flag for now, and correct in
12337 adjust_dynamic_symbol. */
12339 }
12343 {
12349 {
12352 }
12353 else
12354 {
12360 }
12362 /* If the symbol is a function that doesn't bind locally,
12363 this relocation will need a PLT entry. */
12369 /* It's too early to use htab->use_blx here, so we have to
12370 record possible blx references separately from
12371 relocs that definitely need a thumb stub. */
12379 }
12382 {
12385 /* Create a reloc section in dynobj. */
12387 {
12388 sreloc = _bfd_elf_make_dynamic_reloc_section
12394 /* BPABI objects never have dynamic relocations mapped. */
12396 {
12397 flagword flags;
12402 }
12403 }
12405 /* If this is a global symbol, count the number of
12406 relocations we need for this symbol. */
12409 else
12410 {
12414 }
12418 {
12429 }
12434 }
12435 }
12438 }
12440 /* Unwinding tables are not referenced directly. This pass marks them as
12441 required if the corresponding code section is marked. */
12443 static bfd_boolean
12445 elf_gc_mark_hook_fn gc_mark_hook)
12446 {
12449 bfd_boolean again;
12451 /* Marking EH data may cause additional code sections to be marked,
12452 requiring multiple passes. */
12455 {
12458 {
12466 {
12475 {
12479 }
12480 }
12481 }
12482 }
12485 }
12487 /* Treat mapping symbols as special target symbols. */
12489 static bfd_boolean
12491 {
12493 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
12494 }
12496 /* This is a copy of elf_find_function() from elf.c except that
12497 ARM mapping symbols are ignored when looking for function names
12498 and STT_ARM_TFUNC is considered to a function type. */
12500 static bfd_boolean
12504 bfd_vma offset,
12507 {
12514 {
12520 {
12529 /* Skip mapping symbols. */
12532 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
12534 /* Fall through. */
12538 {
12541 }
12543 }
12544 }
12555 }
12558 /* Find the nearest line to a particular section and offset, for error
12559 reporting. This code is a duplicate of the code in elf.c, except
12560 that it uses arm_elf_find_function. */
12562 static bfd_boolean
12566 bfd_vma offset,
12570 {
12573 /* We skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain uses it. */
12579 {
12583 functionname_ptr);
12586 }
12606 }
12608 static bfd_boolean
12613 {
12614 bfd_boolean found;
12619 }
12621 /* Adjust a symbol defined by a dynamic object and referenced by a
12622 regular object. The current definition is in some section of the
12623 dynamic object, but we're not including those sections. We have to
12624 change the definition to something the rest of the link can
12625 understand. */
12627 static bfd_boolean
12630 {
12642 /* Make sure we know what is going on here. */
12653 /* If this is a function, put it in the procedure linkage table. We
12654 will fill in the contents of the procedure linkage table later,
12655 when we know the address of the .got section. */
12657 {
12658 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
12659 symbol binds locally. */
12665 {
12666 /* This case can occur if we saw a PLT32 reloc in an input
12667 file, but the symbol was never referred to by a dynamic
12668 object, or if all references were garbage collected. In
12669 such a case, we don't actually need to build a procedure
12670 linkage table, and we can just do a PC24 reloc instead. */
12676 }
12679 }
12680 else
12681 {
12682 /* It's possible that we incorrectly decided a .plt reloc was
12683 needed for an R_ARM_PC24 or similar reloc to a non-function sym
12684 in check_relocs. We can't decide accurately between function
12685 and non-function syms in check-relocs; Objects loaded later in
12686 the link may change h->type. So fix it now. */
12691 }
12693 /* If this is a weak symbol, and there is a real definition, the
12694 processor independent code will have arranged for us to see the
12695 real definition first, and we can just use the same value. */
12697 {
12703 }
12705 /* If there are no non-GOT references, we do not need a copy
12706 relocation. */
12710 /* This is a reference to a symbol defined by a dynamic object which
12711 is not a function. */
12713 /* If we are creating a shared library, we must presume that the
12714 only references to the symbol are via the global offset table.
12715 For such cases we need not do anything here; the relocations will
12716 be handled correctly by relocate_section. Relocatable executables
12717 can reference data in shared objects directly, so we don't need to
12718 do anything here. */
12723 {
12727 }
12729 /* We must allocate the symbol in our .dynbss section, which will
12730 become part of the .bss section of the executable. There will be
12731 an entry for this symbol in the .dynsym section. The dynamic
12732 object will contain position independent code, so all references
12733 from the dynamic object to this symbol will go through the global
12734 offset table. The dynamic linker will use the .dynsym entry to
12735 determine the address it must put in the global offset table, so
12736 both the dynamic object and the regular object will refer to the
12737 same memory location for the variable. */
12741 /* We must generate a R_ARM_COPY reloc to tell the dynamic linker to
12742 copy the initial value out of the dynamic object and into the
12743 runtime process image. We need to remember the offset into the
12744 .rel(a).bss section we are going to use. */
12746 {
12752 }
12755 }
12757 /* Allocate space in .plt, .got and associated reloc sections for
12758 dynamic relocs. */
12760 static bfd_boolean
12762 {
12772 /* When warning symbols are created, they **replace** the "real"
12773 entry in the hash table, thus we never get to see the real
12774 symbol in a hash traversal. So look at it now. */
12786 {
12787 /* Make sure this symbol is output as a dynamic symbol.
12788 Undefined weak syms won't yet be marked as dynamic. */
12791 {
12794 }
12796 /* If the call in the PLT entry binds locally, the associated
12797 GOT entry should use an R_ARM_IRELATIVE relocation instead of
12798 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
12799 than the .plt section. */
12801 {
12805 /* All non-call references can be resolved directly.
12806 This means that they can (and in some cases, must)
12807 resolve directly to the run-time target, rather than
12808 to the PLT. That in turns means that any .got entry
12809 would be equal to the .igot.plt entry, so there's
12810 no point having both. */
12812 }
12817 {
12820 /* If this symbol is not defined in a regular file, and we are
12821 not generating a shared library, then set the symbol to this
12822 location in the .plt. This is required to make function
12823 pointers compare as equal between the normal executable and
12824 the shared library. */
12827 {
12831 /* Make sure the function is not marked as Thumb, in case
12832 it is the target of an ABS32 relocation, which will
12833 point to the PLT entry. */
12835 }
12839 /* VxWorks executables have a second set of relocations for
12840 each PLT entry. They go in a separate relocation section,
12841 which is processed by the kernel loader. */
12843 {
12844 /* There is a relocation for the initial PLT entry:
12845 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
12849 /* There are two extra relocations for each subsequent
12850 PLT entry: an R_ARM_32 relocation for the GOT entry,
12851 and an R_ARM_32 relocation for the PLT entry. */
12853 }
12854 }
12855 else
12856 {
12859 }
12860 }
12861 else
12862 {
12865 }
12871 {
12873 bfd_boolean dyn;
12877 /* Make sure this symbol is output as a dynamic symbol.
12878 Undefined weak syms won't yet be marked as dynamic. */
12881 {
12884 }
12887 {
12895 /* Non-TLS symbols need one GOT slot. */
12897 else
12898 {
12900 {
12901 /* R_ARM_TLS_DESC needs 2 GOT slots. */
12902 eh->tlsdesc_got
12907 /* plt.got_offset needs to know there's a TLS_DESC
12908 reloc in the middle of .got.plt. */
12910 }
12913 {
12914 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
12915 the symbol is both GD and GDESC, got.offset may
12916 have been overwritten. */
12919 }
12922 /* R_ARM_TLS_IE32 needs one GOT slot. */
12924 }
12938 {
12946 {
12948 /* GDESC needs a trampoline to jump to. */
12950 }
12952 /* Only GD needs it. GDESC just emits one relocation per
12953 2 entries. */
12956 }
12958 {
12960 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
12962 }
12965 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
12966 they all resolve dynamically instead. Reserve room for the
12967 GOT entry's R_ARM_IRELATIVE relocation. */
12970 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
12972 }
12973 }
12974 else
12977 /* Allocate stubs for exported Thumb functions on v4t. */
12982 {
12989 /* Create a new symbol to regist the real location of the function. */
13003 /* Point the symbol at the stub. */
13008 }
13013 /* In the shared -Bsymbolic case, discard space allocated for
13014 dynamic pc-relative relocs against symbols which turn out to be
13015 defined in regular objects. For the normal shared case, discard
13016 space for pc-relative relocs that have become local due to symbol
13017 visibility changes. */
13020 {
13021 /* The only relocs that use pc_count are R_ARM_REL32 and
13022 R_ARM_REL32_NOI, which will appear on something like
13023 ".long foo - .". We want calls to protected symbols to resolve
13024 directly to the function rather than going via the plt. If people
13025 want function pointer comparisons to work as expected then they
13026 should avoid writing assembly like ".long foo - .". */
13028 {
13032 {
13037 else
13039 }
13040 }
13043 {
13047 {
13050 else
13052 }
13053 }
13055 /* Also discard relocs on undefined weak syms with non-default
13056 visibility. */
13059 {
13063 /* Make sure undefined weak symbols are output as a dynamic
13064 symbol in PIEs. */
13067 {
13070 }
13071 }
13075 {
13076 /* Output absolute symbols so that we can create relocations
13077 against them. For normal symbols we output a relocation
13078 against the section that contains them. */
13081 }
13083 }
13084 else
13085 {
13086 /* For the non-shared case, discard space for relocs against
13087 symbols which turn out to need copy relocs or are not
13088 dynamic. */
13096 {
13097 /* Make sure this symbol is output as a dynamic symbol.
13098 Undefined weak syms won't yet be marked as dynamic. */
13101 {
13104 }
13106 /* If that succeeded, we know we'll be keeping all the
13107 relocs. */
13110 }
13114 keep: ;
13115 }
13117 /* Finally, allocate space. */
13119 {
13125 else
13127 }
13130 }
13132 /* Find any dynamic relocs that apply to read-only sections. */
13134 static bfd_boolean
13136 {
13145 {
13149 {
13154 /* Not an error, just cut short the traversal. */
13156 }
13157 }
13159 }
13161 void
13164 {
13172 }
13174 /* Set the sizes of the dynamic sections. */
13176 static bfd_boolean
13179 {
13182 bfd_boolean plt;
13183 bfd_boolean relocs;
13196 {
13197 /* Set the contents of the .interp section to the interpreter. */
13199 {
13204 }
13205 }
13207 /* Set up .got offsets for local syms, and space for local dynamic
13208 relocs. */
13210 {
13216 bfd_size_type locsymcount;
13226 {
13231 {
13234 {
13235 /* Input section has been discarded, either because
13236 it is a copy of a linkonce section or due to
13237 linker script /DISCARD/, so we'll be discarding
13238 the relocs too. */
13239 }
13243 {
13244 /* Relocations in vxworks .tls_vars sections are
13245 handled specially by the loader. */
13246 }
13248 {
13253 }
13254 }
13255 }
13273 {
13277 {
13281 {
13286 /* All references to the PLT are calls, so all
13287 non-call references can resolve directly to the
13288 run-time target. This means that the .got entry
13289 would be the same as the .igot.plt entry, so there's
13290 no point creating both. */
13292 }
13293 else
13294 {
13297 }
13300 {
13306 else
13308 }
13309 }
13311 {
13316 /* TLS_GD relocs need an 8-byte structure in the GOT. */
13319 {
13324 /* plt.got_offset needs to know there's a TLS_DESC
13325 reloc in the middle of .got.plt. */
13327 }
13332 {
13333 /* If the symbol is both GD and GDESC, *local_got
13334 may have been overwritten. */
13337 }
13343 /* If all references to an STT_GNU_IFUNC PLT are calls,
13344 then all non-call references, including this GOT entry,
13345 resolve directly to the run-time target. */
13355 {
13358 }
13359 }
13360 else
13362 }
13363 }
13366 {
13367 /* Allocate two GOT entries and one dynamic relocation (if necessary)
13368 for R_ARM_TLS_LDM32 relocations. */
13373 }
13374 else
13377 /* Allocate global sym .plt and .got entries, and space for global
13378 sym dynamic relocs. */
13381 /* Here we rummage through the found bfds to collect glue information. */
13383 {
13387 /* Initialise mapping tables for code/data. */
13392 /* xgettext:c-format */
13395 }
13397 /* Allocate space for the glue sections now that we've sized them. */
13400 /* For every jump slot reserved in the sgotplt, reloc_count is
13401 incremented. However, when we reserve space for TLS descriptors,
13402 it's not incremented, so in order to compute the space reserved
13403 for them, it suffices to multiply the reloc count by the jump
13404 slot size. */
13409 {
13416 /* If we're not using lazy TLS relocations, don't generate the
13417 PLT and GOT entries they require. */
13419 {
13425 }
13426 }
13428 /* The check_relocs and adjust_dynamic_symbol entry points have
13429 determined the sizes of the various dynamic sections. Allocate
13430 memory for them. */
13434 {
13440 /* It's OK to base decisions on the section name, because none
13441 of the dynobj section names depend upon the input files. */
13445 {
13446 /* Remember whether there is a PLT. */
13448 }
13450 {
13452 {
13453 /* Remember whether there are any reloc sections other
13454 than .rel(a).plt and .rela.plt.unloaded. */
13458 /* We use the reloc_count field as a counter if we need
13459 to copy relocs into the output file. */
13461 }
13462 }
13468 {
13469 /* It's not one of our sections, so don't allocate space. */
13471 }
13474 {
13475 /* If we don't need this section, strip it from the
13476 output file. This is mostly to handle .rel(a).bss and
13477 .rel(a).plt. We must create both sections in
13478 create_dynamic_sections, because they must be created
13479 before the linker maps input sections to output
13480 sections. The linker does that before
13481 adjust_dynamic_symbol is called, and it is that
13482 function which decides whether anything needs to go
13483 into these sections. */
13486 }
13491 /* Allocate memory for the section contents. */
13495 }
13498 {
13499 /* Add some entries to the .dynamic section. We fill in the
13500 values later, in elf32_arm_finish_dynamic_sections, but we
13501 must add the entries now so that we get the correct size for
13502 the .dynamic section. The DT_DEBUG entry is filled in by the
13503 dynamic linker and used by the debugger. */
13504 #define add_dynamic_entry(TAG, VAL) \
13505 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
13508 {
13511 }
13514 {
13526 }
13529 {
13531 {
13536 }
13537 else
13538 {
13543 }
13544 }
13546 /* If any dynamic relocs apply to a read-only section,
13547 then we need a DT_TEXTREL entry. */
13550 info);
13553 {
13556 }
13560 }
13561 #undef add_dynamic_entry
13564 }
13566 /* Size sections even though they're not dynamic. We use it to setup
13567 _TLS_MODULE_BASE_, if needed. */
13569 static bfd_boolean
13572 {
13581 {
13584 tlsbase = elf_link_hash_lookup
13588 {
13604 }
13605 }
13607 }
13609 /* Finish up dynamic symbol handling. We set the contents of various
13610 dynamic sections here. */
13612 static bfd_boolean
13617 {
13628 {
13630 {
13634 }
13637 {
13638 /* Mark the symbol as undefined, rather than as defined in
13639 the .plt section. Leave the value alone. */
13641 /* If the symbol is weak, we do need to clear the value.
13642 Otherwise, the PLT entry would provide a definition for
13643 the symbol even if the symbol wasn't defined anywhere,
13644 and so the symbol would never be NULL. */
13647 }
13649 {
13650 /* At least one non-call relocation references this .iplt entry,
13651 so the .iplt entry is the function's canonical address. */
13659 }
13660 }
13663 {
13665 Elf_Internal_Rela rel;
13667 /* This symbol needs a copy reloc. Set it up. */
13681 }
13683 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
13684 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
13685 to the ".got" section. */
13691 }
13693 static void
13697 {
13701 {
13704 /* Emit mov pc,rx if bx is not permitted. */
13708 }
13709 }
13711 /* Finish up the dynamic sections. */
13713 static bfd_boolean
13715 {
13731 {
13743 {
13744 Elf_Internal_Dyn dyn;
13751 {
13784 get_vma:
13789 else
13790 /* In the BPABI, tags in the PT_DYNAMIC section point
13791 at the file offset, not the memory address, for the
13792 convenience of the post linker. */
13797 get_vma_if_bpabi:
13812 {
13813 /* My reading of the SVR4 ABI indicates that the
13814 procedure linkage table relocs (DT_JMPREL) should be
13815 included in the overall relocs (DT_REL). This is
13816 what Solaris does. However, UnixWare can not handle
13817 that case. Therefore, we override the DT_RELSZ entry
13818 here to make it not include the JMPREL relocs. Since
13819 the linker script arranges for .rel(a).plt to follow all
13820 other relocation sections, we don't have to worry
13821 about changing the DT_REL entry. */
13827 }
13828 /* Fall through. */
13832 /* In the BPABI, the DT_REL tag must point at the file
13833 offset, not the VMA, of the first relocation
13834 section. So, we use code similar to that in
13835 elflink.c, but do not check for SHF_ALLOC on the
13836 relcoation section, since relocations sections are
13837 never allocated under the BPABI. The comments above
13838 about Unixware notwithstanding, we include all of the
13839 relocations here. */
13841 {
13847 {
13848 Elf_Internal_Shdr *hdr
13851 {
13858 }
13859 }
13861 }
13878 /* Set the bottom bit of DT_INIT/FINI if the
13879 corresponding function is Thumb. */
13885 get_sym:
13886 /* If it wasn't set by elf_bfd_final_link
13887 then there is nothing to adjust. */
13889 {
13895 {
13898 }
13899 }
13901 }
13902 }
13904 /* Fill in the first entry in the procedure linkage table. */
13906 {
13910 /* Calculate the addresses of the GOT and PLT. */
13915 {
13916 /* The VxWorks GOT is relocated by the dynamic linker.
13917 Therefore, we must emit relocations rather than simply
13918 computing the values now. */
13919 Elf_Internal_Rela rel;
13930 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
13936 }
13937 else
13938 {
13951 #ifdef FOUR_WORD_PLT
13952 /* The displacement value goes in the otherwise-unused
13953 last word of the second entry. */
13955 #else
13957 #endif
13958 }
13959 }
13961 /* UnixWare sets the entsize of .plt to 4, although that doesn't
13962 really seem like the right value. */
13967 {
13968 bfd_vma got_address
13972 bfd_vma plt_address
13988 }
13991 {
13995 #ifdef FOUR_WORD_PLT
13998 #endif
13999 }
14002 {
14003 /* Correct the .rel(a).plt.unloaded relocations. They will have
14004 incorrect symbol indexes. */
14013 {
14014 Elf_Internal_Rela rel;
14025 }
14026 }
14027 }
14029 /* Fill in the first three entries in the global offset table. */
14031 {
14033 {
14036 else
14042 }
14045 }
14048 }
14050 static void
14051 elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
14052 {
14060 else
14065 {
14069 }
14070 }
14072 static enum elf_reloc_type_class
14074 {
14076 {
14085 }
14086 }
14088 /* Set the right machine number for an Arm ELF file. */
14090 static bfd_boolean
14092 {
14097 }
14099 static void
14101 {
14103 }
14105 /* Return TRUE if this is an unwinding table entry. */
14107 static bfd_boolean
14109 {
14112 }
14115 /* Set the type and flags for an ARM section. We do this by
14116 the section name, which is a hack, but ought to work. */
14118 static bfd_boolean
14120 {
14126 {
14129 }
14131 }
14133 /* Handle an ARM specific section when reading an object file. This is
14134 called when bfd_section_from_shdr finds a section with an unknown
14135 type. */
14137 static bfd_boolean
14142 {
14143 /* There ought to be a place to keep ELF backend specific flags, but
14144 at the moment there isn't one. We just keep track of the
14145 sections by their name, instead. Fortunately, the ABI gives
14146 names for all the ARM specific sections, so we will probably get
14147 away with this. */
14149 {
14157 }
14163 }
14167 {
14170 else
14172 }
14175 {
14184 enum map_symbol_type
14185 {
14186 ARM_MAP_ARM,
14187 ARM_MAP_THUMB,
14188 ARM_MAP_DATA
14189 };
14192 /* Output a single mapping symbol. */
14194 static bfd_boolean
14197 bfd_vma offset)
14198 {
14200 Elf_Internal_Sym sym;
14212 }
14214 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
14215 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
14217 static bfd_boolean
14219 bfd_boolean is_iplt_entry_p,
14222 {
14234 {
14237 }
14238 else
14239 {
14242 }
14248 {
14253 }
14255 {
14264 }
14265 else
14266 {
14267 bfd_boolean thumb_stub_p;
14271 {
14274 }
14275 #ifdef FOUR_WORD_PLT
14280 #else
14281 /* A three-word PLT with no Thumb thunk contains only Arm code,
14282 so only need to output a mapping symbol for the first PLT entry and
14283 entries with thumb thunks. */
14285 {
14288 }
14289 #endif
14290 }
14293 }
14295 /* Output mapping symbols for PLT entries associated with H. */
14297 static bfd_boolean
14299 {
14307 /* When warning symbols are created, they **replace** the "real"
14308 entry in the hash table, thus we never get to see the real
14309 symbol in a hash traversal. So look at it now. */
14315 }
14317 /* Output a single local symbol for a generated stub. */
14319 static bfd_boolean
14322 {
14323 Elf_Internal_Sym sym;
14334 }
14336 static bfd_boolean
14339 {
14342 bfd_vma addr;
14351 /* Massage our args to the form they really have. */
14357 /* Ensure this stub is attached to the current section being
14358 processed. */
14367 {
14381 }
14386 {
14388 {
14405 }
14408 {
14412 }
14415 {
14432 }
14433 }
14436 }
14438 /* Output mapping symbols for linker generated sections,
14439 and for those data-only sections that do not have a
14440 $d. */
14442 static bfd_boolean
14447 Elf_Internal_Sym *,
14448 asection *,
14450 {
14451 output_arch_syminfo osi;
14453 bfd_vma offset;
14454 bfd_size_type size;
14467 /* Add a $d mapping symbol to data-only sections that
14468 don't have any mapping symbol. This may result in (harmless) redundant
14469 mapping symbols. */
14473 {
14478 {
14483 == SEC_HAS_CONTENTS
14487 {
14492 }
14493 }
14494 }
14496 /* ARM->Thumb glue. */
14498 {
14500 ARM2THUMB_GLUE_SECTION_NAME);
14509 else
14513 {
14516 }
14517 }
14519 /* Thumb->ARM glue. */
14521 {
14523 THUMB2ARM_GLUE_SECTION_NAME);
14530 {
14533 }
14534 }
14536 /* ARMv4 BX veneers. */
14538 {
14540 ARM_BX_GLUE_SECTION_NAME);
14546 }
14548 /* Long calls stubs. */
14550 {
14556 {
14557 /* Ignore non-stub sections. */
14567 }
14568 }
14570 /* Finally, output mapping symbols for the PLT. */
14572 {
14577 /* Output mapping symbols for the plt header. SymbianOS does not have a
14578 plt header. */
14580 {
14581 /* VxWorks shared libraries have no PLT header. */
14583 {
14588 }
14589 }
14591 {
14594 #ifndef FOUR_WORD_PLT
14597 #endif
14598 }
14599 }
14602 {
14607 {
14613 {
14621 }
14622 }
14623 }
14625 {
14626 /* Mapping symbols for the lazy tls trampoline. */
14633 }
14635 {
14636 /* Mapping symbols for the tls trampoline. */
14639 #ifdef FOUR_WORD_PLT
14643 #endif
14644 }
14647 }
14649 /* Allocate target specific section data. */
14651 static bfd_boolean
14653 {
14655 {
14663 }
14666 }
14669 /* Used to order a list of mapping symbols by address. */
14671 static int
14673 {
14682 /* Ensure results do not depend on the host qsort for objects with
14683 multiple mapping symbols at the same address by sorting on type
14684 after vma. */
14688 else
14690 }
14692 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
14694 static unsigned long
14696 {
14698 }
14700 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
14701 relocations. */
14703 static void
14705 {
14709 /* High bit of first word is supposed to be zero. */
14713 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
14714 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
14720 }
14722 /* Data for make_branch_to_a8_stub(). */
14727 };
14730 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
14731 places for a particular section. */
14733 static bfd_boolean
14736 {
14742 bfd_signed_vma branch_offset;
14771 /* We attempt to avoid this condition by setting stubs_always_after_branch
14772 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
14773 This check is just to be on the safe side... */
14775 {
14779 }
14782 {
14793 {
14798 jump24:
14800 {
14801 /* There's not much we can do apart from complain if this
14802 happens. */
14806 }
14808 /* i1 = not(j1 eor s), so:
14809 not i1 = j1 eor s
14810 j1 = (not i1) eor s. */
14822 }
14828 }
14834 }
14836 /* Do code byteswapping. Return FALSE afterwards so that the section is
14837 written out as normal. */
14839 static bfd_boolean
14844 {
14850 bfd_vma ptr;
14851 bfd_vma end;
14853 bfd_byte tmp;
14859 /* If this section has not been allocated an _arm_elf_section_data
14860 structure then we cannot record anything. */
14870 {
14875 {
14879 {
14881 {
14882 bfd_vma branch_to_veneer;
14883 /* Original condition code of instruction, plus bit mask for
14884 ARM B instruction. */
14888 /* The instruction is before the label. */
14891 /* Above offset included in -4 below. */
14905 }
14909 {
14910 bfd_vma branch_from_veneer;
14913 /* Take size of veneer into account. */
14922 /* Original instruction. */
14929 /* Branch back to insn after original insn. */
14935 }
14940 }
14941 }
14942 }
14945 {
14946 arm_unwind_table_edit *edit_node
14948 /* Now, sec->size is the size of the section we will write. The original
14949 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
14950 markers) was sec->rawsize. (This isn't the case if we perform no
14951 edits, then rawsize will be zero and we should use size). */
14958 {
14960 {
14964 {
14967 out_index++;
14968 in_index++;
14969 }
14973 {
14975 {
14977 in_index++;
14982 {
14990 /* Note: this is meant to be equivalent to an
14991 R_ARM_PREL31 relocation. These synthetic
14992 EXIDX_CANTUNWIND markers are not relocated by the
14993 usual BFD method. */
14997 /* First address we can't unwind. */
15001 /* Code for EXIDX_CANTUNWIND. */
15005 out_index++;
15007 }
15009 }
15012 }
15013 }
15014 else
15015 {
15016 /* No more edits, copy remaining entries verbatim. */
15019 out_index++;
15020 in_index++;
15021 }
15022 }
15026 edited_contents,
15030 }
15032 /* Fix code to point to Cortex-A8 erratum stubs. */
15034 {
15042 }
15048 {
15053 {
15056 else
15060 {
15062 /* Byte swap code words. */
15064 {
15072 }
15076 /* Byte swap code halfwords. */
15078 {
15083 }
15087 /* Leave data alone. */
15089 }
15091 }
15092 }
15100 }
15102 /* Mangle thumb function symbols as we read them in. */
15104 static bfd_boolean
15109 {
15113 /* New EABI objects mark thumb function symbols by setting the low bit of
15114 the address. */
15118 {
15121 }
15123 {
15126 }
15129 else
15133 }
15136 /* Mangle thumb function symbols as we write them out. */
15138 static void
15143 {
15144 Elf_Internal_Sym newsym;
15146 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
15147 of the address set, as per the new EABI. We do this unconditionally
15148 because objcopy does not set the elf header flags until after
15149 it writes out the symbol table. */
15151 {
15156 {
15157 /* Do this only for defined symbols. At link type, the static
15158 linker will simulate the work of dynamic linker of resolving
15159 symbols and will carry over the thumbness of found symbols to
15160 the output symbol table. It's not clear how it happens, but
15161 the thumbness of undefined symbols can well be different at
15162 runtime, and writing '1' for them will be confusing for users
15163 and possibly for dynamic linker itself.
15164 */
15166 }
15169 }
15171 }
15173 /* Add the PT_ARM_EXIDX program header. */
15175 static bfd_boolean
15178 {
15184 {
15185 /* If there is already a PT_ARM_EXIDX header, then we do not
15186 want to add another one. This situation arises when running
15187 "strip"; the input binary already has the header. */
15192 {
15203 }
15204 }
15207 }
15209 /* We may add a PT_ARM_EXIDX program header. */
15211 static int
15214 {
15220 else
15222 }
15224 /* Hook called by the linker routine which adds symbols from an object
15225 file. */
15227 static bfd_boolean
15231 {
15242 }
15244 /* We use this to override swap_symbol_in and swap_symbol_out. */
15246 {
15259 bfd_elf32_write_out_phdrs,
15260 bfd_elf32_write_shdrs_and_ehdr,
15261 bfd_elf32_checksum_contents,
15262 bfd_elf32_write_relocs,
15263 elf32_arm_swap_symbol_in,
15264 elf32_arm_swap_symbol_out,
15265 bfd_elf32_slurp_reloc_table,
15266 bfd_elf32_slurp_symbol_table,
15267 bfd_elf32_swap_dyn_in,
15268 bfd_elf32_swap_dyn_out,
15269 bfd_elf32_swap_reloc_in,
15270 bfd_elf32_swap_reloc_out,
15271 bfd_elf32_swap_reloca_in,
15272 bfd_elf32_swap_reloca_out
15273 };
15275 #define ELF_ARCH bfd_arch_arm
15276 #define ELF_TARGET_ID ARM_ELF_DATA
15277 #define ELF_MACHINE_CODE EM_ARM
15278 #ifdef __QNXTARGET__
15279 #define ELF_MAXPAGESIZE 0x1000
15280 #else
15281 #define ELF_MAXPAGESIZE 0x8000
15282 #endif
15283 #define ELF_MINPAGESIZE 0x1000
15284 #define ELF_COMMONPAGESIZE 0x1000
15286 #define bfd_elf32_mkobject elf32_arm_mkobject
15288 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
15289 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
15290 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
15291 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
15292 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
15293 #define bfd_elf32_bfd_link_hash_table_free elf32_arm_hash_table_free
15294 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
15295 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
15296 #define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
15297 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
15298 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
15299 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
15300 #define bfd_elf32_bfd_final_link elf32_arm_final_link
15302 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
15303 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
15304 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
15305 #define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
15306 #define elf_backend_check_relocs elf32_arm_check_relocs
15307 #define elf_backend_relocate_section elf32_arm_relocate_section
15308 #define elf_backend_write_section elf32_arm_write_section
15309 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
15310 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
15311 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
15312 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
15313 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
15314 #define elf_backend_always_size_sections elf32_arm_always_size_sections
15315 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
15316 #define elf_backend_post_process_headers elf32_arm_post_process_headers
15317 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
15318 #define elf_backend_object_p elf32_arm_object_p
15319 #define elf_backend_section_flags elf32_arm_section_flags
15320 #define elf_backend_fake_sections elf32_arm_fake_sections
15321 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
15322 #define elf_backend_final_write_processing elf32_arm_final_write_processing
15323 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
15324 #define elf_backend_size_info elf32_arm_size_info
15325 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
15326 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
15327 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
15328 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
15329 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
15331 #define elf_backend_can_refcount 1
15332 #define elf_backend_can_gc_sections 1
15333 #define elf_backend_plt_readonly 1
15334 #define elf_backend_want_got_plt 1
15335 #define elf_backend_want_plt_sym 0
15336 #define elf_backend_may_use_rel_p 1
15337 #define elf_backend_may_use_rela_p 0
15338 #define elf_backend_default_use_rela_p 0
15340 #define elf_backend_got_header_size 12
15342 #undef elf_backend_obj_attrs_vendor
15344 #undef elf_backend_obj_attrs_section
15346 #undef elf_backend_obj_attrs_arg_type
15347 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
15348 #undef elf_backend_obj_attrs_section_type
15349 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
15350 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
15351 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
15355 /* VxWorks Targets. */
15357 #undef TARGET_LITTLE_SYM
15358 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_vxworks_vec
15359 #undef TARGET_LITTLE_NAME
15361 #undef TARGET_BIG_SYM
15362 #define TARGET_BIG_SYM bfd_elf32_bigarm_vxworks_vec
15363 #undef TARGET_BIG_NAME
15366 /* Like elf32_arm_link_hash_table_create -- but overrides
15367 appropriately for VxWorks. */
15371 {
15376 {
15381 }
15383 }
15385 static void
15387 {
15390 }
15392 #undef elf32_bed
15393 #define elf32_bed elf32_arm_vxworks_bed
15395 #undef bfd_elf32_bfd_link_hash_table_create
15396 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
15397 #undef elf_backend_final_write_processing
15398 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
15399 #undef elf_backend_emit_relocs
15400 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
15402 #undef elf_backend_may_use_rel_p
15403 #define elf_backend_may_use_rel_p 0
15404 #undef elf_backend_may_use_rela_p
15405 #define elf_backend_may_use_rela_p 1
15406 #undef elf_backend_default_use_rela_p
15407 #define elf_backend_default_use_rela_p 1
15408 #undef elf_backend_want_plt_sym
15409 #define elf_backend_want_plt_sym 1
15410 #undef ELF_MAXPAGESIZE
15411 #define ELF_MAXPAGESIZE 0x1000
15416 /* Merge backend specific data from an object file to the output
15417 object file when linking. */
15419 static bfd_boolean
15421 {
15422 flagword out_flags;
15423 flagword in_flags;
15427 /* Check if we have the same endianess. */
15437 /* The input BFD must have had its flags initialised. */
15438 /* The following seems bogus to me -- The flags are initialized in
15439 the assembler but I don't think an elf_flags_init field is
15440 written into the object. */
15441 /* BFD_ASSERT (elf_flags_init (ibfd)); */
15446 /* In theory there is no reason why we couldn't handle this. However
15447 in practice it isn't even close to working and there is no real
15448 reason to want it. */
15452 {
15454 ibfd);
15456 }
15459 {
15460 /* If the input is the default architecture and had the default
15461 flags then do not bother setting the flags for the output
15462 architecture, instead allow future merges to do this. If no
15463 future merges ever set these flags then they will retain their
15464 uninitialised values, which surprise surprise, correspond
15465 to the default values. */
15478 }
15480 /* Determine what should happen if the input ARM architecture
15481 does not match the output ARM architecture. */
15485 /* Identical flags must be compatible. */
15489 /* Check to see if the input BFD actually contains any sections. If
15490 not, its flags may not have been initialised either, but it
15491 cannot actually cause any incompatiblity. Do not short-circuit
15492 dynamic objects; their section list may be emptied by
15493 elf_link_add_object_symbols.
15495 Also check to see if there are no code sections in the input.
15496 In this case there is no need to check for code specific flags.
15497 XXX - do we need to worry about floating-point format compatability
15498 in data sections ? */
15500 {
15505 {
15506 /* Ignore synthetic glue sections. */
15509 {
15517 }
15518 }
15522 }
15524 /* Complain about various flag mismatches. */
15527 {
15528 _bfd_error_handler
15534 }
15536 /* Not sure what needs to be checked for EABI versions >= 1. */
15537 /* VxWorks libraries do not use these flags. */
15541 {
15543 {
15544 _bfd_error_handler
15550 }
15553 {
15555 _bfd_error_handler
15556 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
15558 else
15559 _bfd_error_handler
15560 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
15564 }
15567 {
15569 _bfd_error_handler
15572 else
15573 _bfd_error_handler
15578 }
15581 {
15583 _bfd_error_handler
15586 else
15587 _bfd_error_handler
15592 }
15594 #ifdef EF_ARM_SOFT_FLOAT
15596 {
15597 /* We can allow interworking between code that is VFP format
15598 layout, and uses either soft float or integer regs for
15599 passing floating point arguments and results. We already
15600 know that the APCS_FLOAT flags match; similarly for VFP
15601 flags. */
15604 {
15606 _bfd_error_handler
15609 else
15610 _bfd_error_handler
15615 }
15616 }
15617 #endif
15619 /* Interworking mismatch is only a warning. */
15621 {
15623 {
15624 _bfd_error_handler
15627 }
15628 else
15629 {
15630 _bfd_error_handler
15633 }
15634 }
15635 }
15638 }
15641 /* Symbian OS Targets. */
15643 #undef TARGET_LITTLE_SYM
15644 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_symbian_vec
15645 #undef TARGET_LITTLE_NAME
15647 #undef TARGET_BIG_SYM
15648 #define TARGET_BIG_SYM bfd_elf32_bigarm_symbian_vec
15649 #undef TARGET_BIG_NAME
15652 /* Like elf32_arm_link_hash_table_create -- but overrides
15653 appropriately for Symbian OS. */
15657 {
15662 {
15665 /* There is no PLT header for Symbian OS. */
15667 /* The PLT entries are each one instruction and one word. */
15670 /* Symbian uses armv5t or above, so use_blx is always true. */
15673 }
15675 }
15677 static const struct bfd_elf_special_section
15678 elf32_arm_symbian_special_sections[] =
15679 {
15680 /* In a BPABI executable, the dynamic linking sections do not go in
15681 the loadable read-only segment. The post-linker may wish to
15682 refer to these sections, but they are not part of the final
15683 program image. */
15689 /* These sections do not need to be writable as the SymbianOS
15690 postlinker will arrange things so that no dynamic relocation is
15691 required. */
15696 };
15698 static void
15701 {
15702 /* BPABI objects are never loaded directly by an OS kernel; they are
15703 processed by a postlinker first, into an OS-specific format. If
15704 the D_PAGED bit is set on the file, BFD will align segments on
15705 page boundaries, so that an OS can directly map the file. With
15706 BPABI objects, that just results in wasted space. In addition,
15707 because we clear the D_PAGED bit, map_sections_to_segments will
15708 recognize that the program headers should not be mapped into any
15709 loadable segment. */
15712 }
15714 static bfd_boolean
15717 {
15721 /* BPABI shared libraries and executables should have a PT_DYNAMIC
15722 segment. However, because the .dynamic section is not marked
15723 with SEC_LOAD, the generic ELF code will not create such a
15724 segment. */
15727 {
15733 {
15737 }
15738 }
15740 /* Also call the generic arm routine. */
15742 }
15744 /* Return address for Ith PLT stub in section PLT, for relocation REL
15745 or (bfd_vma) -1 if it should not be included. */
15747 static bfd_vma
15750 {
15752 }
15755 #undef elf32_bed
15756 #define elf32_bed elf32_arm_symbian_bed
15758 /* The dynamic sections are not allocated on SymbianOS; the postlinker
15759 will process them and then discard them. */
15760 #undef ELF_DYNAMIC_SEC_FLAGS
15761 #define ELF_DYNAMIC_SEC_FLAGS \
15762 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
15764 #undef elf_backend_emit_relocs
15766 #undef bfd_elf32_bfd_link_hash_table_create
15767 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
15768 #undef elf_backend_special_sections
15769 #define elf_backend_special_sections elf32_arm_symbian_special_sections
15770 #undef elf_backend_begin_write_processing
15771 #define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
15772 #undef elf_backend_final_write_processing
15773 #define elf_backend_final_write_processing elf32_arm_final_write_processing
15775 #undef elf_backend_modify_segment_map
15776 #define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
15778 /* There is no .got section for BPABI objects, and hence no header. */
15779 #undef elf_backend_got_header_size
15780 #define elf_backend_got_header_size 0
15782 /* Similarly, there is no .got.plt section. */
15783 #undef elf_backend_want_got_plt
15784 #define elf_backend_want_got_plt 0
15786 #undef elf_backend_plt_sym_val
15787 #define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
15789 #undef elf_backend_may_use_rel_p
15790 #define elf_backend_may_use_rel_p 1
15791 #undef elf_backend_may_use_rela_p
15792 #define elf_backend_may_use_rela_p 0
15793 #undef elf_backend_default_use_rela_p
15794 #define elf_backend_default_use_rela_p 0
15795 #undef elf_backend_want_plt_sym
15796 #define elf_backend_want_plt_sym 0
15797 #undef ELF_MAXPAGESIZE
15798 #define ELF_MAXPAGESIZE 0x8000