ld/testsuite/ld-spu/icache1.d

   1 #source: icache1.s
   2 #ld: --soft-icache --num-lines=4 --non-ia-text --auto-overlay=tmpdir/icache1.lnk --auto-relink
   3 #objdump: -D
   4
   5 .* elf32-spu
   6
   7
   8 Disassembly of section .ovl.init:
   9 00000800 <__icache_fileoff>:
  10 .*      00 00 00 00.*
  11 .*      00 00 07 80.*
  12         \.\.\.
  13
  14 Disassembly of section \.ovly1:
  15
  16 00000800 <\.ovly1>:
  17 .*      ai      \$1,\$1,64      # 40
  18 .*      lqd     \$0,16\(\$1\)
  19 .*      bi      \$0
  20         \.\.\.
  21
  22 Disassembly of section \.ovly2:
  23
  24 00000c00 <f1>:
  25 .*      40 20 00 00     nop     \$0
  26 .*      24 00 40 80     stqd    \$0,16\(\$1\)
  27 .*      1c f0 00 81     ai      \$1,\$1,-64
  28 .*      24 00 00 81     stqd    \$1,0\(\$1\)
  29 .*      33 00 73 80     brsl    \$0,fac .*
  30 .*      33 00 77 00     brsl    \$0,fcc .*
  31         \.\.\.
  32 .*      32 00 16 80     br      fec .*
  33         \.\.\.
  34      fa0:       00 00 00 02.*
  35      fa4:       00 00 11 04.*
  36      fa8:       a0 00 0c 10.*
  37      fac:       31 03 0a 4b     brasl   \$75,1850 <__icache_br_handler>
  38      fb0:       00 00 ed 00.*
  39         \.\.\.
  40      fc0:       00 00 00 02.*
  41      fc4:       00 00 10 00.*
  42      fc8:       a0 00 0c 14.*
  43      fcc:       31 03 0a 4b     brasl   \$75,1850 <__icache_br_handler>
  44      fd0:       00 00 00 00.*
  45      fd4:       00 00 0a 80.*
  46         \.\.\.
  47      fe4:       00 00 08 00.*
  48      fe8:       20 00 0f 38.*
  49      fec:       31 03 0a 4b     brasl   \$75,1850 <__icache_br_handler>
  50         \.\.\.
  51      ff8:       00 7f 0f 80.*
  52      ffc:       00 00 00 00.*
  53
  54 Disassembly of section \.ovly3:
  55
  56 00001000 <f3>:
  57         \.\.\.
  58 .*      35 00 00 00     bi      \$0
  59
  60 00001104 <f2>:
  61 .*      1c e0 00 81     ai      \$1,\$1,-128
  62 .*      24 00 00 81     stqd    \$1,0\(\$1\)
  63         \.\.\.
  64 .*      1c 20 00 81     ai      \$1,\$1,128     # 80
  65 .*      35 00 00 00     bi      \$0
  66         \.\.\.
  67
  68 Disassembly of section \.ovly4:
  69
  70 00001400 <f5>:
  71 .*      24 00 40 80     stqd    \$0,16\(\$1\)
  72 .*      24 f8 00 81     stqd    \$1,-512\(\$1\)
  73 .*      1c 80 00 81     ai      \$1,\$1,-512
  74 .*      33 7f fe 80     brsl    \$0,1400 <f5>   # 1400
  75         \.\.\.
  76 .*      42 01 00 03     ila     \$3,200 <__icache_linked_list\+0x1c0>
  77 .*      18 00 c0 81     a       \$1,\$1,\$3
  78 .*      34 00 40 80     lqd     \$0,16\(\$1\)
  79 .*      35 00 00 00     bi      \$0
  80         \.\.\.
  81
  82 Disassembly of section \.ovly5:
  83
  84 00000800 <\.ovly5>:
  85         \.\.\.
  86 .*      42 01 00 03     ila     \$3,200 .*
  87 .*      18 00 c0 81     a       \$1,\$1,\$3
  88 .*      34 00 40 80     lqd     \$0,16\(\$1\)
  89 .*      30 01 7d 80     bra     bec .*
  90         \.\.\.
  91  be0:   00 00 00 03.*
  92  be4:   00 00 14 00.*
  93  be8:   a0 00 0b 2c.*
  94  bec:   31 03 0a 4b     brasl   \$75,1850 <__icache_br_handler>
  95         \.\.\.
  96  bfc:   00 03 fd 80.*
  97
  98 Disassembly of section \.ovly6:
  99
 100 00000c00 <\.ovly6>:
 101 .*      31 01 f5 80     brasl   \$0,fac .*
 102 .*      33 00 79 00     brsl    \$0,fcc .*
 103         \.\.\.
 104 .*      32 00 18 80     br      fec .*
 105         \.\.\.
 106      fa0:       00 00 00 07.*
 107      fa4:       00 04 14 00.*
 108      fa8:       a0 00 0c 00.*
 109      fac:       31 03 0a 4b     brasl   \$75,1850 <__icache_br_handler>
 110      fb0:       00 03 75 80.*
 111         \.\.\.
 112      fc0:       00 00 00 07.*
 113      fc4:       00 04 14 00.*
 114      fc8:       a0 00 0c 04.*
 115      fcc:       31 03 0a 4b     brasl   \$75,1850 <__icache_br_handler>
 116      fd0:       00 00 00 00.*
 117      fd4:       00 00 86 80.*
 118         \.\.\.
 119      fe0:       00 00 00 04.*
 120      fe4:       00 04 08 00.*
 121      fe8:       20 00 0f 28.*
 122      fec:       31 03 0a 4b     brasl   \$75,1850 <__icache_br_handler>
 123         \.\.\.
 124      ff8:       00 7f 03 80.*
 125      ffc:       00 00 00 00.*
 126
 127 Disassembly of section \.ovly7:
 128
 129 00001000 <\.ovly7>:
 130 .*      41 7f ff 83     ilhu    \$3,65535       # ffff
 131 .*      60 f8 30 03     iohl    \$3,61536       # f060
 132 .*      18 00 c0 84     a       \$4,\$1,\$3
 133 .*      00 20 00 00     lnop
 134 .*      04 00 02 01     ori     \$1,\$4,0
 135 .*      24 00 02 04     stqd    \$4,0\(\$4\)
 136 .*      33 00 72 80     brsl    \$0,13ac .*
 137 .*      33 00 76 00     brsl    \$0,13cc .*
 138 .*      34 00 00 81     lqd     \$1,0\(\$1\)
 139         \.\.\.
 140 .*      32 00 15 00     br      13ec .*
 141         \.\.\.
 142     13a0:       00 00 00 03.*
 143     13a4:       00 00 14 00.*
 144     13a8:       a0 00 10 18.*
 145     13ac:       31 03 0a 4b     brasl   \$75,1850 <__icache_br_handler>
 146         \.\.\.
 147     13b8:       00 00 0f 80.*
 148     13bc:       00 00 00 00.*
 149     13c0:       00 00 00 07.*
 150     13c4:       00 04 14 00.*
 151     13c8:       a0 00 10 1c.*
 152     13cc:       31 03 0a 4b     brasl   \$75,1850 <__icache_br_handler>
 153         \.\.\.
 154     13dc:       00 00 0a 80.*
 155     13e0:       00 00 00 05.*
 156     13e4:       00 04 0c 00.*
 157     13e8:       20 00 13 44.*
 158     13ec:       31 03 0a 4b     brasl   \$75,1850 <__icache_br_handler>
 159     13f0:       00 00 00 00.*
 160     13f4:       00 7f 02 80.*
 161         \.\.\.
 162
 163 Disassembly of section \.ovly8:
 164
 165 00001400 <f4>:
 166 .*      24 00 40 80     stqd    \$0,16\(\$1\)
 167 .*      24 f8 00 81     stqd    \$1,-512\(\$1\)
 168 .*      1c 80 00 81     ai      \$1,\$1,-512
 169 .*      31 02 f9 80     brasl   \$0,17cc .*
 170         \.\.\.
 171 .*      32 00 17 80     br      17ec .*
 172         \.\.\.
 173     17c0:       00 00 00 02.*
 174     17c4:       00 00 11 04.*
 175     17c8:       a0 00 14 0c.*
 176     17cc:       31 03 0a 4b     brasl   \$75,1850 <__icache_br_handler>
 177         \.\.\.
 178     17dc:       00 00 d9 00.*
 179     17e0:       00 00 00 06.*
 180     17e4:       00 04 10 00.*
 181     17e8:       20 00 17 30.*
 182     17ec:       31 03 0a 4b     brasl   \$75,1850 <__icache_br_handler>
 183     17f0:       00 7f 0d 80.*
 184         \.\.\.
 185
 186 Disassembly of section \.text:
 187
 188 00001800 <_start>:
 189 .*      41 00 00 03     ilhu    \$3,0
 190 .*      60 8a 00 03     iohl    \$3,5120        # 1400
 191 .*      32 00 04 80     br      182c.*
 192         \.\.\.
 193     1820:       00 00 00 01.*
 194     1824:       00 00 0c 00.*
 195     1828:       a0 00 18 08.*
 196     182c:       31 03 0a 4b     brasl   \$75,1850 <__icache_br_handler>
 197         \.\.\.
 198     1838:       00 7e 7b 80.*
 199         \.\.\.
 200
 201 00001850 <__icache_br_handler>:
 202 #pass