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1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000
2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
5 @ifset GENERIC
6 @page
7 @node M68HC11-Dependent
8 @chapter M68HC11 and M68HC12 Dependent Features
9 @end ifset
10 @ifclear GENERIC
11 @node Machine Dependencies
12 @chapter M68HC11 and M68HC12 Dependent Features
13 @end ifclear
15 @cindex M68HC11 and M68HC12 support
16 @menu
17 * M68HC11-Opts:: M68HC11 and M68HC12 Options
18 * M68HC11-Syntax:: Syntax
19 * M68HC11-Modifiers:: Symbolic Operand Modifiers
20 * M68HC11-Directives:: Assembler Directives
21 * M68HC11-Float:: Floating Point
22 * M68HC11-opcodes:: Opcodes
23 @end menu
25 @node M68HC11-Opts
26 @section M68HC11 and M68HC12 Options
28 @cindex options, M68HC11
29 @cindex M68HC11 options
30 The Motorola 68HC11 and 68HC12 version of @code{@value{AS}} have a few machine
31 dependent options.
33 @table @code
35 @cindex @samp{-m68hc11}
36 @item -m68hc11
37 This option switches the assembler in the M68HC11 mode. In this mode,
38 the assembler only accepts 68HC11 operands and mnemonics. It produces
39 code for the 68HC11.
41 @cindex @samp{-m68hc12}
42 @item -m68hc12
43 This option switches the assembler in the M68HC12 mode. In this mode,
44 the assembler also accepts 68HC12 operands and mnemonics. It produces
45 code for the 68HC12. A few 68HC11 instructions are replaced by
46 some 68HC12 instructions as recommended by Motorola specifications.
48 @cindex @samp{-m68hcs12}
49 @item -m68hcs12
50 This option switches the assembler in the M68HCS12 mode. This mode is
51 similar to @samp{-m68hc12} but specifies to assemble for the 68HCS12
52 series. The only difference is on the assembling of the @samp{movb}
53 and @samp{movw} instruction when a PC-relative operand is used.
55 @cindex @samp{-mshort}
56 @item -mshort
57 This option controls the ABI and indicates to use a 16-bit integer ABI.
58 It has no effect on the assembled instructions.
59 This is the default.
61 @cindex @samp{-mlong}
62 @item -mlong
63 This option controls the ABI and indicates to use a 32-bit integer ABI.
65 @cindex @samp{-mshort-double}
66 @item -mshort-double
67 This option controls the ABI and indicates to use a 32-bit float ABI.
68 This is the default.
70 @cindex @samp{-mlong-double}
71 @item -mlong-double
72 This option controls the ABI and indicates to use a 64-bit float ABI.
74 @cindex @samp{--strict-direct-mode}
75 @item --strict-direct-mode
76 You can use the @samp{--strict-direct-mode} option to disable
77 the automatic translation of direct page mode addressing into
78 extended mode when the instruction does not support direct mode.
79 For example, the @samp{clr} instruction does not support direct page
80 mode addressing. When it is used with the direct page mode,
81 @code{@value{AS}} will ignore it and generate an absolute addressing.
82 This option prevents @code{@value{AS}} from doing this, and the wrong
83 usage of the direct page mode will raise an error.
85 @cindex @samp{--short-branchs}
86 @item --short-branchs
87 The @samp{--short-branchs} option turns off the translation of
88 relative branches into absolute branches when the branch offset is
89 out of range. By default @code{@value{AS}} transforms the relative
90 branch (@samp{bsr}, @samp{bgt}, @samp{bge}, @samp{beq}, @samp{bne},
91 @samp{ble}, @samp{blt}, @samp{bhi}, @samp{bcc}, @samp{bls},
92 @samp{bcs}, @samp{bmi}, @samp{bvs}, @samp{bvs}, @samp{bra}) into
93 an absolute branch when the offset is out of the -128 .. 127 range.
94 In that case, the @samp{bsr} instruction is translated into a
95 @samp{jsr}, the @samp{bra} instruction is translated into a
96 @samp{jmp} and the conditional branchs instructions are inverted and
97 followed by a @samp{jmp}. This option disables these translations
98 and @code{@value{AS}} will generate an error if a relative branch
99 is out of range. This option does not affect the optimization
100 associated to the @samp{jbra}, @samp{jbsr} and @samp{jbXX} pseudo opcodes.
102 @cindex @samp{--force-long-branchs}
103 @item --force-long-branchs
104 The @samp{--force-long-branchs} option forces the translation of
105 relative branches into absolute branches. This option does not affect
106 the optimization associated to the @samp{jbra}, @samp{jbsr} and
107 @samp{jbXX} pseudo opcodes.
109 @cindex @samp{--print-insn-syntax}
110 @item --print-insn-syntax
111 You can use the @samp{--print-insn-syntax} option to obtain the
112 syntax description of the instruction when an error is detected.
114 @cindex @samp{--print-opcodes}
115 @item --print-opcodes
116 The @samp{--print-opcodes} option prints the list of all the
117 instructions with their syntax. The first item of each line
118 represents the instruction name and the rest of the line indicates
119 the possible operands for that instruction. The list is printed
120 in alphabetical order. Once the list is printed @code{@value{AS}}
121 exits.
123 @cindex @samp{--generate-example}
124 @item --generate-example
125 The @samp{--generate-example} option is similar to @samp{--print-opcodes}
126 but it generates an example for each instruction instead.
127 @end table
129 @node M68HC11-Syntax
130 @section Syntax
132 @cindex M68HC11 syntax
133 @cindex syntax, M68HC11
135 In the M68HC11 syntax, the instruction name comes first and it may
136 be followed by one or several operands (up to three). Operands are
137 separated by comma (@samp{,}). In the normal mode,
138 @code{@value{AS}} will complain if too many operands are specified for
139 a given instruction. In the MRI mode (turned on with @samp{-M} option),
140 it will treat them as comments. Example:
142 @smallexample
143 inx
144 lda #23
145 bset 2,x #4
146 brclr *bot #8 foo
147 @end smallexample
149 @cindex M68HC11 addressing modes
150 @cindex addressing modes, M68HC11
151 The following addressing modes are understood for 68HC11 and 68HC12:
152 @table @dfn
153 @item Immediate
154 @samp{#@var{number}}
156 @item Address Register
157 @samp{@var{number},X}, @samp{@var{number},Y}
159 The @var{number} may be omitted in which case 0 is assumed.
161 @item Direct Addressing mode
162 @samp{*@var{symbol}}, or @samp{*@var{digits}}
164 @item Absolute
165 @samp{@var{symbol}}, or @samp{@var{digits}}
166 @end table
168 The M68HC12 has other more complex addressing modes. All of them
169 are supported and they are represented below:
171 @table @dfn
172 @item Constant Offset Indexed Addressing Mode
173 @samp{@var{number},@var{reg}}
175 The @var{number} may be omitted in which case 0 is assumed.
176 The register can be either @samp{X}, @samp{Y}, @samp{SP} or
177 @samp{PC}. The assembler will use the smaller post-byte definition
178 according to the constant value (5-bit constant offset, 9-bit constant
179 offset or 16-bit constant offset). If the constant is not known by
180 the assembler it will use the 16-bit constant offset post-byte and the value
181 will be resolved at link time.
183 @item Offset Indexed Indirect
184 @samp{[@var{number},@var{reg}]}
186 The register can be either @samp{X}, @samp{Y}, @samp{SP} or @samp{PC}.
188 @item Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement
189 @samp{@var{number},-@var{reg}}
190 @samp{@var{number},+@var{reg}}
191 @samp{@var{number},@var{reg}-}
192 @samp{@var{number},@var{reg}+}
194 The number must be in the range @samp{-8}..@samp{+8} and must not be 0.
195 The register can be either @samp{X}, @samp{Y}, @samp{SP} or @samp{PC}.
197 @item Accumulator Offset
198 @samp{@var{acc},@var{reg}}
200 The accumulator register can be either @samp{A}, @samp{B} or @samp{D}.
201 The register can be either @samp{X}, @samp{Y}, @samp{SP} or @samp{PC}.
203 @item Accumulator D offset indexed-indirect
204 @samp{[D,@var{reg}]}
206 The register can be either @samp{X}, @samp{Y}, @samp{SP} or @samp{PC}.
208 @end table
210 For example:
212 @smallexample
213 ldab 1024,sp
214 ldd [10,x]
215 orab 3,+x
216 stab -2,y-
217 ldx a,pc
218 sty [d,sp]
219 @end smallexample
222 @node M68HC11-Modifiers
223 @section Symbolic Operand Modifiers
225 @cindex M68HC11 modifiers
226 @cindex syntax, M68HC11
228 The assembler supports several modifiers when using symbol addresses
229 in 68HC11 and 68HC12 instruction operands. The general syntax is
230 the following:
232 @smallexample
233 %modifier(symbol)
234 @end smallexample
236 @table @code
237 @cindex symbol modifiers
238 @item %addr
239 This modifier indicates to the assembler and linker to use
240 the 16-bit physical address corresponding to the symbol. This is intended
241 to be used on memory window systems to map a symbol in the memory bank window.
242 If the symbol is in a memory expansion part, the physical address
243 corresponds to the symbol address within the memory bank window.
244 If the symbol is not in a memory expansion part, this is the symbol address
245 (using or not using the %addr modifier has no effect in that case).
247 @item %page
248 This modifier indicates to use the memory page number corresponding
249 to the symbol. If the symbol is in a memory expansion part, its page
250 number is computed by the linker as a number used to map the page containing
251 the symbol in the memory bank window. If the symbol is not in a memory
252 expansion part, the page number is 0.
254 @item %hi
255 This modifier indicates to use the 8-bit high part of the physical
256 address of the symbol.
258 @item %lo
259 This modifier indicates to use the 8-bit low part of the physical
260 address of the symbol.
262 @end table
264 For example a 68HC12 call to a function @samp{foo_example} stored in memory
265 expansion part could be written as follows:
267 @smallexample
268 call %addr(foo_example),%page(foo_example)
269 @end smallexample
271 and this is equivalent to
273 @smallexample
274 call foo_example
275 @end smallexample
277 And for 68HC11 it could be written as follows:
279 @smallexample
280 ldab #%page(foo_example)
281 stab _page_switch
282 jsr %addr(foo_example)
283 @end smallexample
285 @node M68HC11-Directives
286 @section Assembler Directives
288 @cindex assembler directives, M68HC11
289 @cindex assembler directives, M68HC12
290 @cindex M68HC11 assembler directives
291 @cindex M68HC12 assembler directives
293 The 68HC11 and 68HC12 version of @code{@value{AS}} have the following
294 specific assembler directives:
296 @table @code
297 @item .relax
298 @cindex assembler directive .relax, M68HC11
299 @cindex M68HC11 assembler directive .relax
300 The relax directive is used by the @samp{GNU Compiler} to emit a specific
301 relocation to mark a group of instructions for linker relaxation.
302 The sequence of instructions within the group must be known to the linker
303 so that relaxation can be performed.
305 @item .mode [mshort|mlong|mshort-double|mlong-double]
306 @cindex assembler directive .mode, M68HC11
307 @cindex M68HC11 assembler directive .mode
308 This directive specifies the ABI. It overrides the @samp{-mshort},
309 @samp{-mlong}, @samp{-mshort-double} and @samp{-mlong-double} options.
311 @item .far @var{symbol}
312 @cindex assembler directive .far, M68HC11
313 @cindex M68HC11 assembler directive .far
314 This directive marks the symbol as a @samp{far} symbol meaning that it
315 uses a @samp{call/rtc} calling convention as opposed to @samp{jsr/rts}.
316 During a final link, the linker will identify references to the @samp{far}
317 symbol and will verify the proper calling convention.
319 @item .interrupt @var{symbol}
320 @cindex assembler directive .interrupt, M68HC11
321 @cindex M68HC11 assembler directive .interrupt
322 This directive marks the symbol as an interrupt entry point.
323 This information is then used by the debugger to correctly unwind the
324 frame across interrupts.
326 @item .xrefb @var{symbol}
327 @cindex assembler directive .xrefb, M68HC11
328 @cindex M68HC11 assembler directive .xrefb
329 This directive is defined for compatibility with the
330 @samp{Specification for Motorola 8 and 16-Bit Assembly Language Input
331 Standard} and is ignored.
333 @end table
335 @node M68HC11-Float
336 @section Floating Point
338 @cindex floating point, M68HC11
339 @cindex M68HC11 floating point
340 Packed decimal (P) format floating literals are not supported.
341 Feel free to add the code!
343 The floating point formats generated by directives are these.
345 @table @code
346 @cindex @code{float} directive, M68HC11
347 @item .float
348 @code{Single} precision floating point constants.
350 @cindex @code{double} directive, M68HC11
351 @item .double
352 @code{Double} precision floating point constants.
354 @cindex @code{extend} directive M68HC11
355 @cindex @code{ldouble} directive M68HC11
356 @item .extend
357 @itemx .ldouble
358 @code{Extended} precision (@code{long double}) floating point constants.
359 @end table
361 @need 2000
362 @node M68HC11-opcodes
363 @section Opcodes
365 @cindex M68HC11 opcodes
366 @cindex opcodes, M68HC11
367 @cindex instruction set, M68HC11
369 @menu
370 * M68HC11-Branch:: Branch Improvement
371 @end menu
373 @node M68HC11-Branch
374 @subsection Branch Improvement
376 @cindex pseudo-opcodes, M68HC11
377 @cindex M68HC11 pseudo-opcodes
378 @cindex branch improvement, M68HC11
379 @cindex M68HC11 branch improvement
381 Certain pseudo opcodes are permitted for branch instructions.
382 They expand to the shortest branch instruction that reach the
383 target. Generally these mnemonics are made by prepending @samp{j} to
384 the start of Motorola mnemonic. These pseudo opcodes are not affected
385 by the @samp{--short-branchs} or @samp{--force-long-branchs} options.
387 The following table summarizes the pseudo-operations.
389 @smallexample
390 Displacement Width
391 +-------------------------------------------------------------+
392 | Options |
393 | --short-branchs --force-long-branchs |
394 +--------------------------+----------------------------------+
395 Op |BYTE WORD | BYTE WORD |
396 +--------------------------+----------------------------------+
397 bsr | bsr <pc-rel> <error> | jsr <abs> |
398 bra | bra <pc-rel> <error> | jmp <abs> |
399 jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> |
400 jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> |
401 bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> |
402 jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> |
403 | jmp <abs> | |
404 +--------------------------+----------------------------------+
405 XX: condition
406 NX: negative of condition XX
408 @end smallexample
410 @table @code
411 @item jbsr
412 @itemx jbra
413 These are the simplest jump pseudo-operations; they always map to one
414 particular machine instruction, depending on the displacement to the
415 branch target.
417 @item jb@var{XX}
418 Here, @samp{jb@var{XX}} stands for an entire family of pseudo-operations,
419 where @var{XX} is a conditional branch or condition-code test. The full
420 list of pseudo-ops in this family is:
421 @smallexample
422 jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo
423 jbcs jbne jblt jble jbls jbvc jbmi
424 @end smallexample
426 For the cases of non-PC relative displacements and long displacements,
427 @code{@value{AS}} issues a longer code fragment in terms of
428 @var{NX}, the opposite condition to @var{XX}. For example, for the
429 non-PC relative case:
430 @smallexample
431 jb@var{XX} foo
432 @end smallexample
433 gives
434 @smallexample
435 b@var{NX}s oof
436 jmp foo
437 oof:
438 @end smallexample
440 @end table