opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009, 2010
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i287 support required */
  56   Cpu287,
  57   /* i387 support required */
  58   Cpu387,
  59   /* i686 and floating point support required */
  60   Cpu687,
  61   /* SSE3 and floating point support required */
  62   CpuFISTTP,
  63   /* MMX support required */
  64   CpuMMX,
  65   /* SSE support required */
  66   CpuSSE,
  67   /* SSE2 support required */
  68   CpuSSE2,
  69   /* 3dnow! support required */
  70   Cpu3dnow,
  71   /* 3dnow! Extensions support required */
  72   Cpu3dnowA,
  73   /* SSE3 support required */
  74   CpuSSE3,
  75   /* VIA PadLock required */
  76   CpuPadLock,
  77   /* AMD Secure Virtual Machine Ext-s required */
  78   CpuSVME,
  79   /* VMX Instructions required */
  80   CpuVMX,
  81   /* SMX Instructions required */
  82   CpuSMX,
  83   /* SSSE3 support required */
  84   CpuSSSE3,
  85   /* SSE4a support required */
  86   CpuSSE4a,
  87   /* ABM New Instructions required */
  88   CpuABM,
  89   /* SSE4.1 support required */
  90   CpuSSE4_1,
  91   /* SSE4.2 support required */
  92   CpuSSE4_2,
  93   /* AVX support required */
  94   CpuAVX,
  95   /* AVX2 support required */
  96   CpuAVX2,
  97   /* Intel L1OM support required */
  98   CpuL1OM,
  99   /* Intel K1OM support required */
 100   CpuK1OM,
 101   /* Xsave/xrstor New Instructions support required */
 102   CpuXsave,
 103   /* Xsaveopt New Instructions support required */
 104   CpuXsaveopt,
 105   /* AES support required */
 106   CpuAES,
 107   /* PCLMUL support required */
 108   CpuPCLMUL,
 109   /* FMA support required */
 110   CpuFMA,
 111   /* FMA4 support required */
 112   CpuFMA4,
 113   /* XOP support required */
 114   CpuXOP,
 115   /* LWP support required */
 116   CpuLWP,
 117   /* BMI support required */
 118   CpuBMI,
 119   /* TBM support required */
 120   CpuTBM,
 121   /* MOVBE Instruction support required */
 122   CpuMovbe,
 123   /* EPT Instructions required */
 124   CpuEPT,
 125   /* RDTSCP Instruction support required */
 126   CpuRdtscp,
 127   /* FSGSBASE Instructions required */
 128   CpuFSGSBase,
 129   /* RDRND Instructions required */
 130   CpuRdRnd,
 131   /* F16C Instructions required */
 132   CpuF16C,
 133   /* Intel BMI2 support required */
 134   CpuBMI2,
 135   /* LZCNT support required */
 136   CpuLZCNT,
 137   /* HLE support required */
 138   CpuHLE,
 139   /* RTM support required */
 140   CpuRTM,
 141   /* INVPCID Instructions required */
 142   CpuINVPCID,
 143   /* VMFUNC Instruction required */
 144   CpuVMFUNC,
 145   /* 64bit support available, used by -march= in assembler.  */
 146   CpuLM,
 147   /* 64bit support required  */
 148   Cpu64,
 149   /* Not supported in the 64bit mode  */
 150   CpuNo64,
 151   /* The last bitfield in i386_cpu_flags.  */
 152   CpuMax = CpuNo64
 153 };
 154
 155 #define CpuNumOfUints \
 156   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 157 #define CpuNumOfBits \
 158   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 159
 160 /* If you get a compiler error for zero width of the unused field,
 161    comment it out.  */
 162 #define CpuUnused       (CpuMax + 1)
 163
 164 /* We can check if an instruction is available with array instead
 165    of bitfield. */
 166 typedef union i386_cpu_flags
 167 {
 168   struct
 169     {
 170       unsigned int cpui186:1;
 171       unsigned int cpui286:1;
 172       unsigned int cpui386:1;
 173       unsigned int cpui486:1;
 174       unsigned int cpui586:1;
 175       unsigned int cpui686:1;
 176       unsigned int cpuclflush:1;
 177       unsigned int cpunop:1;
 178       unsigned int cpusyscall:1;
 179       unsigned int cpu8087:1;
 180       unsigned int cpu287:1;
 181       unsigned int cpu387:1;
 182       unsigned int cpu687:1;
 183       unsigned int cpufisttp:1;
 184       unsigned int cpummx:1;
 185       unsigned int cpusse:1;
 186       unsigned int cpusse2:1;
 187       unsigned int cpua3dnow:1;
 188       unsigned int cpua3dnowa:1;
 189       unsigned int cpusse3:1;
 190       unsigned int cpupadlock:1;
 191       unsigned int cpusvme:1;
 192       unsigned int cpuvmx:1;
 193       unsigned int cpusmx:1;
 194       unsigned int cpussse3:1;
 195       unsigned int cpusse4a:1;
 196       unsigned int cpuabm:1;
 197       unsigned int cpusse4_1:1;
 198       unsigned int cpusse4_2:1;
 199       unsigned int cpuavx:1;
 200       unsigned int cpuavx2:1;
 201       unsigned int cpul1om:1;
 202       unsigned int cpuk1om:1;
 203       unsigned int cpuxsave:1;
 204       unsigned int cpuxsaveopt:1;
 205       unsigned int cpuaes:1;
 206       unsigned int cpupclmul:1;
 207       unsigned int cpufma:1;
 208       unsigned int cpufma4:1;
 209       unsigned int cpuxop:1;
 210       unsigned int cpulwp:1;
 211       unsigned int cpubmi:1;
 212       unsigned int cputbm:1;
 213       unsigned int cpumovbe:1;
 214       unsigned int cpuept:1;
 215       unsigned int cpurdtscp:1;
 216       unsigned int cpufsgsbase:1;
 217       unsigned int cpurdrnd:1;
 218       unsigned int cpuf16c:1;
 219       unsigned int cpubmi2:1;
 220       unsigned int cpulzcnt:1;
 221       unsigned int cpuhle:1;
 222       unsigned int cpurtm:1;
 223       unsigned int cpuinvpcid:1;
 224       unsigned int cpuvmfunc:1;
 225       unsigned int cpulm:1;
 226       unsigned int cpu64:1;
 227       unsigned int cpuno64:1;
 228 #ifdef CpuUnused
 229       unsigned int unused:(CpuNumOfBits - CpuUnused);
 230 #endif
 231     } bitfield;
 232   unsigned int array[CpuNumOfUints];
 233 } i386_cpu_flags;
 234
 235 /* Position of opcode_modifier bits.  */
 236
 237 enum
 238 {
 239   /* has direction bit. */
 240   D = 0,
 241   /* set if operands can be words or dwords encoded the canonical way */
 242   W,
 243   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 244      operand in encoding.  */
 245   S,
 246   /* insn has a modrm byte. */
 247   Modrm,
 248   /* register is in low 3 bits of opcode */
 249   ShortForm,
 250   /* special case for jump insns.  */
 251   Jump,
 252   /* call and jump */
 253   JumpDword,
 254   /* loop and jecxz */
 255   JumpByte,
 256   /* special case for intersegment leaps/calls */
 257   JumpInterSegment,
 258   /* FP insn memory format bit, sized by 0x4 */
 259   FloatMF,
 260   /* src/dest swap for floats. */
 261   FloatR,
 262   /* has float insn direction bit. */
 263   FloatD,
 264   /* needs size prefix if in 32-bit mode */
 265   Size16,
 266   /* needs size prefix if in 16-bit mode */
 267   Size32,
 268   /* needs size prefix if in 64-bit mode */
 269   Size64,
 270   /* check register size.  */
 271   CheckRegSize,
 272   /* instruction ignores operand size prefix and in Intel mode ignores
 273      mnemonic size suffix check.  */
 274   IgnoreSize,
 275   /* default insn size depends on mode */
 276   DefaultSize,
 277   /* b suffix on instruction illegal */
 278   No_bSuf,
 279   /* w suffix on instruction illegal */
 280   No_wSuf,
 281   /* l suffix on instruction illegal */
 282   No_lSuf,
 283   /* s suffix on instruction illegal */
 284   No_sSuf,
 285   /* q suffix on instruction illegal */
 286   No_qSuf,
 287   /* long double suffix on instruction illegal */
 288   No_ldSuf,
 289   /* instruction needs FWAIT */
 290   FWait,
 291   /* quick test for string instructions */
 292   IsString,
 293   /* quick test for lockable instructions */
 294   IsLockable,
 295   /* fake an extra reg operand for clr, imul and special register
 296      processing for some instructions.  */
 297   RegKludge,
 298   /* The first operand must be xmm0 */
 299   FirstXmm0,
 300   /* An implicit xmm0 as the first operand */
 301   Implicit1stXmm0,
 302   /* The HLE prefix is OK:
 303      1. With a LOCK prefix.
 304      2. With or without a LOCK prefix.
 305      3. With a RELEASE (0xf3) prefix.
 306    */
 307 #define HLEPrefixNone           0
 308 #define HLEPrefixLock           1
 309 #define HLEPrefixAny            2
 310 #define HLEPrefixRelease        3
 311   HLEPrefixOk,
 312   /* Convert to DWORD */
 313   ToDword,
 314   /* Convert to QWORD */
 315   ToQword,
 316   /* Address prefix changes operand 0 */
 317   AddrPrefixOp0,
 318   /* opcode is a prefix */
 319   IsPrefix,
 320   /* instruction has extension in 8 bit imm */
 321   ImmExt,
 322   /* instruction don't need Rex64 prefix.  */
 323   NoRex64,
 324   /* instruction require Rex64 prefix.  */
 325   Rex64,
 326   /* deprecated fp insn, gets a warning */
 327   Ugh,
 328   /* insn has VEX prefix:
 329         1: 128bit VEX prefix.
 330         2: 256bit VEX prefix.
 331         3: Scalar VEX prefix.
 332    */
 333 #define VEX128          1
 334 #define VEX256          2
 335 #define VEXScalar       3
 336   Vex,
 337   /* How to encode VEX.vvvv:
 338      0: VEX.vvvv must be 1111b.
 339      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 340         the content of source registers will be preserved.
 341         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 342         where the content of first source register will be overwritten
 343         by the result.
 344         VEX.NDD2.  The second destination register operand is encoded in
 345         VEX.vvvv for instructions with 2 destination register operands.
 346         For assembler, there are no difference between VEX.NDS, VEX.DDS
 347         and VEX.NDD2.
 348      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 349      instructions with 1 destination register operand.
 350      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 351         of the operands can access a memory location.
 352    */
 353 #define VEXXDS  1
 354 #define VEXNDD  2
 355 #define VEXLWP  3
 356   VexVVVV,
 357   /* How the VEX.W bit is used:
 358      0: Set by the REX.W bit.
 359      1: VEX.W0.  Should always be 0.
 360      2: VEX.W1.  Should always be 1.
 361    */
 362 #define VEXW0   1
 363 #define VEXW1   2
 364   VexW,
 365   /* VEX opcode prefix:
 366      0: VEX 0x0F opcode prefix.
 367      1: VEX 0x0F38 opcode prefix.
 368      2: VEX 0x0F3A opcode prefix
 369      3: XOP 0x08 opcode prefix.
 370      4: XOP 0x09 opcode prefix
 371      5: XOP 0x0A opcode prefix.
 372    */
 373 #define VEX0F           0
 374 #define VEX0F38         1
 375 #define VEX0F3A         2
 376 #define XOP08           3
 377 #define XOP09           4
 378 #define XOP0A           5
 379   VexOpcode,
 380   /* number of VEX source operands:
 381      0: <= 2 source operands.
 382      1: 2 XOP source operands.
 383      2: 3 source operands.
 384    */
 385 #define XOP2SOURCES     1
 386 #define VEX3SOURCES     2
 387   VexSources,
 388   /* instruction has VEX 8 bit imm */
 389   VexImmExt,
 390   /* Instruction with vector SIB byte:
 391         1: 128bit vector register.
 392         2: 256bit vector register.
 393    */
 394 #define VecSIB128       1
 395 #define VecSIB256       2
 396   VecSIB,
 397   /* SSE to AVX support required */
 398   SSE2AVX,
 399   /* No AVX equivalent */
 400   NoAVX,
 401   /* Compatible with old (<= 2.8.1) versions of gcc  */
 402   OldGcc,
 403   /* AT&T mnemonic.  */
 404   ATTMnemonic,
 405   /* AT&T syntax.  */
 406   ATTSyntax,
 407   /* Intel syntax.  */
 408   IntelSyntax,
 409   /* The last bitfield in i386_opcode_modifier.  */
 410   Opcode_Modifier_Max
 411 };
 412
 413 typedef struct i386_opcode_modifier
 414 {
 415   unsigned int d:1;
 416   unsigned int w:1;
 417   unsigned int s:1;
 418   unsigned int modrm:1;
 419   unsigned int shortform:1;
 420   unsigned int jump:1;
 421   unsigned int jumpdword:1;
 422   unsigned int jumpbyte:1;
 423   unsigned int jumpintersegment:1;
 424   unsigned int floatmf:1;
 425   unsigned int floatr:1;
 426   unsigned int floatd:1;
 427   unsigned int size16:1;
 428   unsigned int size32:1;
 429   unsigned int size64:1;
 430   unsigned int checkregsize:1;
 431   unsigned int ignoresize:1;
 432   unsigned int defaultsize:1;
 433   unsigned int no_bsuf:1;
 434   unsigned int no_wsuf:1;
 435   unsigned int no_lsuf:1;
 436   unsigned int no_ssuf:1;
 437   unsigned int no_qsuf:1;
 438   unsigned int no_ldsuf:1;
 439   unsigned int fwait:1;
 440   unsigned int isstring:1;
 441   unsigned int islockable:1;
 442   unsigned int regkludge:1;
 443   unsigned int firstxmm0:1;
 444   unsigned int implicit1stxmm0:1;
 445   unsigned int hleprefixok:2;
 446   unsigned int todword:1;
 447   unsigned int toqword:1;
 448   unsigned int addrprefixop0:1;
 449   unsigned int isprefix:1;
 450   unsigned int immext:1;
 451   unsigned int norex64:1;
 452   unsigned int rex64:1;
 453   unsigned int ugh:1;
 454   unsigned int vex:2;
 455   unsigned int vexvvvv:2;
 456   unsigned int vexw:2;
 457   unsigned int vexopcode:3;
 458   unsigned int vexsources:2;
 459   unsigned int veximmext:1;
 460   unsigned int vecsib:2;
 461   unsigned int sse2avx:1;
 462   unsigned int noavx:1;
 463   unsigned int oldgcc:1;
 464   unsigned int attmnemonic:1;
 465   unsigned int attsyntax:1;
 466   unsigned int intelsyntax:1;
 467 } i386_opcode_modifier;
 468
 469 /* Position of operand_type bits.  */
 470
 471 enum
 472 {
 473   /* 8bit register */
 474   Reg8 = 0,
 475   /* 16bit register */
 476   Reg16,
 477   /* 32bit register */
 478   Reg32,
 479   /* 64bit register */
 480   Reg64,
 481   /* Floating pointer stack register */
 482   FloatReg,
 483   /* MMX register */
 484   RegMMX,
 485   /* SSE register */
 486   RegXMM,
 487   /* AVX registers */
 488   RegYMM,
 489   /* Control register */
 490   Control,
 491   /* Debug register */
 492   Debug,
 493   /* Test register */
 494   Test,
 495   /* 2 bit segment register */
 496   SReg2,
 497   /* 3 bit segment register */
 498   SReg3,
 499   /* 1 bit immediate */
 500   Imm1,
 501   /* 8 bit immediate */
 502   Imm8,
 503   /* 8 bit immediate sign extended */
 504   Imm8S,
 505   /* 16 bit immediate */
 506   Imm16,
 507   /* 32 bit immediate */
 508   Imm32,
 509   /* 32 bit immediate sign extended */
 510   Imm32S,
 511   /* 64 bit immediate */
 512   Imm64,
 513   /* 8bit/16bit/32bit displacements are used in different ways,
 514      depending on the instruction.  For jumps, they specify the
 515      size of the PC relative displacement, for instructions with
 516      memory operand, they specify the size of the offset relative
 517      to the base register, and for instructions with memory offset
 518      such as `mov 1234,%al' they specify the size of the offset
 519      relative to the segment base.  */
 520   /* 8 bit displacement */
 521   Disp8,
 522   /* 16 bit displacement */
 523   Disp16,
 524   /* 32 bit displacement */
 525   Disp32,
 526   /* 32 bit signed displacement */
 527   Disp32S,
 528   /* 64 bit displacement */
 529   Disp64,
 530   /* Accumulator %al/%ax/%eax/%rax */
 531   Acc,
 532   /* Floating pointer top stack register %st(0) */
 533   FloatAcc,
 534   /* Register which can be used for base or index in memory operand.  */
 535   BaseIndex,
 536   /* Register to hold in/out port addr = dx */
 537   InOutPortReg,
 538   /* Register to hold shift count = cl */
 539   ShiftCount,
 540   /* Absolute address for jump.  */
 541   JumpAbsolute,
 542   /* String insn operand with fixed es segment */
 543   EsSeg,
 544   /* RegMem is for instructions with a modrm byte where the register
 545      destination operand should be encoded in the mod and regmem fields.
 546      Normally, it will be encoded in the reg field. We add a RegMem
 547      flag to the destination register operand to indicate that it should
 548      be encoded in the regmem field.  */
 549   RegMem,
 550   /* Memory.  */
 551   Mem,
 552   /* BYTE memory. */
 553   Byte,
 554   /* WORD memory. 2 byte */
 555   Word,
 556   /* DWORD memory. 4 byte */
 557   Dword,
 558   /* FWORD memory. 6 byte */
 559   Fword,
 560   /* QWORD memory. 8 byte */
 561   Qword,
 562   /* TBYTE memory. 10 byte */
 563   Tbyte,
 564   /* XMMWORD memory. */
 565   Xmmword,
 566   /* YMMWORD memory. */
 567   Ymmword,
 568   /* Unspecified memory size.  */
 569   Unspecified,
 570   /* Any memory size.  */
 571   Anysize,
 572
 573   /* Vector 4 bit immediate.  */
 574   Vec_Imm4,
 575
 576   /* The last bitfield in i386_operand_type.  */
 577   OTMax
 578 };
 579
 580 #define OTNumOfUints \
 581   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 582 #define OTNumOfBits \
 583   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 584
 585 /* If you get a compiler error for zero width of the unused field,
 586    comment it out.  */
 587 #define OTUnused                (OTMax + 1)
 588
 589 typedef union i386_operand_type
 590 {
 591   struct
 592     {
 593       unsigned int reg8:1;
 594       unsigned int reg16:1;
 595       unsigned int reg32:1;
 596       unsigned int reg64:1;
 597       unsigned int floatreg:1;
 598       unsigned int regmmx:1;
 599       unsigned int regxmm:1;
 600       unsigned int regymm:1;
 601       unsigned int control:1;
 602       unsigned int debug:1;
 603       unsigned int test:1;
 604       unsigned int sreg2:1;
 605       unsigned int sreg3:1;
 606       unsigned int imm1:1;
 607       unsigned int imm8:1;
 608       unsigned int imm8s:1;
 609       unsigned int imm16:1;
 610       unsigned int imm32:1;
 611       unsigned int imm32s:1;
 612       unsigned int imm64:1;
 613       unsigned int disp8:1;
 614       unsigned int disp16:1;
 615       unsigned int disp32:1;
 616       unsigned int disp32s:1;
 617       unsigned int disp64:1;
 618       unsigned int acc:1;
 619       unsigned int floatacc:1;
 620       unsigned int baseindex:1;
 621       unsigned int inoutportreg:1;
 622       unsigned int shiftcount:1;
 623       unsigned int jumpabsolute:1;
 624       unsigned int esseg:1;
 625       unsigned int regmem:1;
 626       unsigned int mem:1;
 627       unsigned int byte:1;
 628       unsigned int word:1;
 629       unsigned int dword:1;
 630       unsigned int fword:1;
 631       unsigned int qword:1;
 632       unsigned int tbyte:1;
 633       unsigned int xmmword:1;
 634       unsigned int ymmword:1;
 635       unsigned int unspecified:1;
 636       unsigned int anysize:1;
 637       unsigned int vec_imm4:1;
 638 #ifdef OTUnused
 639       unsigned int unused:(OTNumOfBits - OTUnused);
 640 #endif
 641     } bitfield;
 642   unsigned int array[OTNumOfUints];
 643 } i386_operand_type;
 644
 645 typedef struct insn_template
 646 {
 647   /* instruction name sans width suffix ("mov" for movl insns) */
 648   char *name;
 649
 650   /* how many operands */
 651   unsigned int operands;
 652
 653   /* base_opcode is the fundamental opcode byte without optional
 654      prefix(es).  */
 655   unsigned int base_opcode;
 656 #define Opcode_D        0x2 /* Direction bit:
 657                                set if Reg --> Regmem;
 658                                unset if Regmem --> Reg. */
 659 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 660 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 661
 662   /* extension_opcode is the 3 bit extension for group <n> insns.
 663      This field is also used to store the 8-bit opcode suffix for the
 664      AMD 3DNow! instructions.
 665      If this template has no extension opcode (the usual case) use None
 666      Instructions */
 667   unsigned int extension_opcode;
 668 #define None 0xffff             /* If no extension_opcode is possible.  */
 669
 670   /* Opcode length.  */
 671   unsigned char opcode_length;
 672
 673   /* cpu feature flags */
 674   i386_cpu_flags cpu_flags;
 675
 676   /* the bits in opcode_modifier are used to generate the final opcode from
 677      the base_opcode.  These bits also are used to detect alternate forms of
 678      the same instruction */
 679   i386_opcode_modifier opcode_modifier;
 680
 681   /* operand_types[i] describes the type of operand i.  This is made
 682      by OR'ing together all of the possible type masks.  (e.g.
 683      'operand_types[i] = Reg|Imm' specifies that operand i can be
 684      either a register or an immediate operand.  */
 685   i386_operand_type operand_types[MAX_OPERANDS];
 686 }
 687 insn_template;
 688
 689 extern const insn_template i386_optab[];
 690
 691 /* these are for register name --> number & type hash lookup */
 692 typedef struct
 693 {
 694   char *reg_name;
 695   i386_operand_type reg_type;
 696   unsigned char reg_flags;
 697 #define RegRex      0x1  /* Extended register.  */
 698 #define RegRex64    0x2  /* Extended 8 bit register.  */
 699   unsigned char reg_num;
 700 #define RegRip  ((unsigned char ) ~0)
 701 #define RegEip  (RegRip - 1)
 702 /* EIZ and RIZ are fake index registers.  */
 703 #define RegEiz  (RegEip - 1)
 704 #define RegRiz  (RegEiz - 1)
 705 /* FLAT is a fake segment register (Intel mode).  */
 706 #define RegFlat     ((unsigned char) ~0)
 707   signed char dw2_regnum[2];
 708 #define Dw2Inval (-1)
 709 }
 710 reg_entry;
 711
 712 /* Entries in i386_regtab.  */
 713 #define REGNAM_AL 1
 714 #define REGNAM_AX 25
 715 #define REGNAM_EAX 41
 716
 717 extern const reg_entry i386_regtab[];
 718 extern const unsigned int i386_regtab_size;
 719
 720 typedef struct
 721 {
 722   char *seg_name;
 723   unsigned int seg_prefix;
 724 }
 725 seg_entry;
 726
 727 extern const seg_entry cs;
 728 extern const seg_entry ds;
 729 extern const seg_entry ss;
 730 extern const seg_entry es;
 731 extern const seg_entry fs;
 732 extern const seg_entry gs;