From 5c7604d4797c1fadcb1e0ad860749df58838f5a3 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Fri, 16 Dec 2005 10:23:12 +0000 Subject: [PATCH] Second part of ms1 to mt renaming. * bfd/archures.c (bfd_arch_mt): Renamed. (bfd_mt_arch): Renamed. (bfd_archures_list): Adjusted. * bfd/bfd-in2.h: Rebuilt. * bfd/config.bfd (mt): Remove special case targ_archs. (mt-*-elf): Rename bfd_elf32_mt_vec. * bfd/configure: Rebuilt. * bfd/configure.in (bfd_elf32_mt_vec): Renamed. (selarchs) Remove mt special case. * bfd/cpu-mt.c (arch_info_struct): Adjust. (bfd_mt_arch): Renamed, adjust. * bfd/elf32-mt.c (mt_reloc_type_lookup, mt_info_to_howto_rela, mt_elf_relocate_hi16, mt_final_link_relocate, mt_relocate_section, mt_elf_howto_table): Renamed, adjusted. (mt_elf_gc_mark_hook, mt_elf_gc_sweep_hook, mt_elf_check_relocs, elf32_mt_machine, mt_elf_object_p, mt_elf_set_private_flags, mt_elf_copy_private_bfd_data, mt_elf_merge_private_bfd_data, mt_elf_print_private_bfd_data): Renamed, adjusted. (TARGET_BIG_SYM, TARGET_BIG_NAME, ELF_ARCH, ELF_MACHINE_CODE, ELF_MAXPAGESIZE, elf_info_to_howto, elf_backend_relocate_section, bfd_elf32_bfd_reloc_type_lookup, elf_backend_gc_mark_hook, elf_backend_gc_sweep_hook, elf_backend_check_relocs, eld_backend_object_p, bfd_elf32_bfd_set_private_flags, bfd_elf32_bfd_copy_private_bfd_data, bfd_elf32_bfd_merge_private_bfd_data, bfd_elf32_bfd_print_private_bfd_data): Adjusted. * bfd/libbfd.h: Regenerated. * bfd/reloc.c (BFD_RELOC_MT_PC16, BFD_RELOC_MT_HI16, BFD_RELOC_MT_LO16, BFD_RELOC_MT_GNU_VTINHERIT, BFD_RELOC_MT_GNU_VTENTRY, BFD_RELOC_MT_PCINSN8): Renamed. * bfd/targets.c (bfd_elf32_mt_vec): Renamed. (_bfd_target_vector): Adjusted. * binutils/readelf.c (guess_is_rela): Use EM_MT. (dump_relocations, get_machine_name): Adjust. * cpu/mt.cpu (define-arch, define-isa): Set name to mt. (define-mach): Adjust. * cpu/mt.opc (CGEN_ASM_HASH): Update. (mt_asm_hash, mt_cgen_insn_supported): Renamed. (parse_loopsize, parse_imm16): Adjust. * gas/configure: Rebuilt. * gas/configure.in (mt): Remove special case. * gas/config/tc-mt.c (opcodes/mt-desc.h, opcodes/mt-opc.h): Change #includes. (mt_insn, mt_mach, mt_mach_bitmask, mt_flags, mt_architectures): Rename, adjust. (md_parse_option, md_show_usage, md_begin, md_assemble, md_cgen_lookup_reloc, md_atof): Adjust. (mt_force_relocation, mt_apply_fix, mt_fix_adjustable): Rename, adjust. * gas/config/tc-mt.h (TC_MT): Rename. (LISTING_HEADER, TARGET_ARCH, TARGET_FORMAT): Adjust. (md_apply_fix): Adjust. (mt_apply_fix, mt_fix_adjustable, mt_force_relocation): Rename. (TC_FORCE_RELOCATION, tc_fix_adjustable): Adjust. * gdb/mt-tdep.c (mt_arch_constants, mt_gdb_regnums): Rename, adjust. (mt_register_name, mt_register_type, mt_register_reggroup_p, mt_return_value, mt_skip_prologue, mt_breapoint_from_pc, mt_pseudo_register_read, mt_pseudo_register_write, mt_frame_align, mt_registers_info, mt_push_dummy_call, mt_unwind_cache, mt_frame_unwind_cache, mt_unwind_pc, mt_unwind_dummy_id, mt_frame_this_id, mt_frame_prev_register, mt_frame_base_address, mt_frame_unwind, mt_frame_sniffer, mt_frame_base, mt_gdbarch_init, _initialize_mt_tdep): Rename & adjust. * include/dis-asm.h (print_insn_mt): Renamed. * include/elf/common.h (EM_MT): Renamed. * include/elf/mt.h: Rename relocs, cpu & other defines. * ld/emulparams/elf32mt.sh (ARCH, OUTPUT_FORMAT): Adjust. * opcodes/Makefile.am (HFILES, CFILES, ALL_MACHINES): Adjust. (stamp-mt): Adjust rule. (mt-asm.lo, mt-desc.lo, mt-dis.lo, mt-ibld.lo, mt-opc.lo): Rename & adjust. * opcodes/Makefile.in: Rebuilt. * opcodes/configure: Rebuilt. * opcodes/configure.in (bfd_mt_arch): Rename & adjust. * opcodes/disassemble.c (ARCH_mt): Renamed. (disassembler): Adjust. * opcodes/mt-asm.c: Renamed, rebuilt. * opcodes/mt-desc.c: Renamed, rebuilt. * opcodes/mt-desc.h: Renamed, rebuilt. * opcodes/mt-dis.c: Renamed, rebuilt. * opcodes/mt-ibld.c: Renamed, rebuilt. * opcodes/mt-opc.c: Renamed, rebuilt. * opcodes/mt-opc.h: Renamed, rebuilt. * sid/Makefile.in: Rebuilt. * sid/aclocal.m4: Rebuilt. * sid/configure: Rebuilt. * sid/sid.spec: Adjust. * sid/bsp/Makefile.am: Adjust. * sid/bsp/Makefile.in: Rebuilt. * sid/bsp/aclocal.m4: Rebuilt. * sid/bsp/configrun-sid.in: Adjust. * sid/bsp/pregen/Makefile.in: Rebuilt. * sid/bsp/pregen/mt-gdb.conf: Renamed & rebuilt. * sid/bsp/pregen/mt-gloss.conf: Renamed & rebuilt. * sid/bsp/pregen/pregen-configs.in: Adjust. * sid/component/aclocal.m4: Rebuilt. * sid/component/configure: Rebuilt. * sid/component/tconfig.in: Adjust. * sid/component/bochs/aclocal.m4: Rebuilt. * sid/component/cache/Makefile.in: Rebuilt. * sid/component/cgen-cpu/Makefile.in: Rebuilt. * sid/component/cgen-cpu/aclocal.m4: Rebuilt. * sid/component/cgen-cpu/compCGEN.cxx: Adjust. * sid/component/cgen-cpu/configure: Rebuilt. * sid/component/cgen-cpu/configure.in: Rebult. * sid/component/cgen-cpu/mt/Makefile.am: Adjust. * sid/component/cgen-cpu/mt/Makefile.in: Rebuilt. * sid/component/cgen-cpu/mt/hw-cpu-mt.txt: Adjust. * sid/component/cgen-cpu/mt/mt-cpu.h: Rebuilt. * sid/component/cgen-cpu/mt/mt-decode.cxx: Rebuilt. * sid/component/cgen-cpu/mt/mt-decode.h: Rebuilt. * sid/component/cgen-cpu/mt/mt-defs.h: Rebuilt. * sid/component/cgen-cpu/mt/mt-desc.h: Rebuilt. * sid/component/cgen-cpu/mt/mt-sem.cxx: Rebuilt. * sid/component/cgen-cpu/mt/mt-write.cxx: Rebuilt. * sid/component/cgen-cpu/mt/mt.cxx: Adjust. * sid/component/cgen-cpu/mt/mt.h: Adjust. * sid/component/consoles/Makefile.in: Rebuilt. * sid/component/families/aclocal.m4: Rebuilt. * sid/component/families/configure: Rebuilt. * sid/component/gdb/Makefile.in: Rebuilt. * sid/component/gloss/Makefile.in: Rebuilt. * sid/component/glue/Makefile.in: Rebuilt. * sid/component/ide/Makefile.in: Rebuilt. * sid/component/interrupt/Makefile.in: Rebuilt. * sid/component/lcd/Makefile.in: Rebuilt. * sid/component/lcd/testsuite/Makefile.in: Rebuilt. * sid/component/loader/Makefile.am: Rebuilt. * sid/component/loader/Makefile.in: Rebuilt. * sid/component/mapper/Makefile.in: Rebuilt. * sid/component/mapper/testsuite/Makefile.in: Rebuilt. * sid/component/memory/Makefile.in: Rebuilt. * sid/component/mmu/Makefile.in: Rebuilt. * sid/component/parport/Makefile.in: Rebuilt. * sid/component/profiling/Makefile.in: Rebuilt. * sid/component/rtc/Makefile.in: Rebuilt. * sid/component/sched/Makefile.in: Rebuilt. * sid/component/testsuite/Makefile.in: Rebuilt. * sid/component/timers/aclocal.m4: Rebuilt. * sid/component/timers/configure: Rebuilt. * sid/component/uart/Makefile.in: Rebuilt. * sid/component/uart/testsuite/Makefile.in: Rebuilt. * sid/config/config.sub: Adjust. * sid/config/info.tcl.in: Adjust. * sid/config/sidtargets.m4: Adjust. * sid/doc/Makefile.in: Rebuilt. * sid/main/dynamic/Makefile.am: Rebuilt. * sid/main/dynamic/Makefile.in: Rebuilt. * sid/main/dynamic/aclocal.m4: Rebuilt. * sid/main/dynamic/configure: Rebuilt. --- bfd/ChangeLog | 36 ++ bfd/archures.c | 6 +- bfd/bfd-in2.h | 26 +- bfd/config.bfd | 3 +- bfd/configure | 4 +- bfd/configure.in | 4 +- bfd/cpu-mt.c | 16 +- bfd/elf32-mt.c | 170 ++++----- bfd/libbfd.h | 12 +- bfd/reloc.c | 24 +- bfd/targets.c | 4 +- binutils/ChangeLog | 6 + binutils/readelf.c | 8 +- cpu/ChangeLog | 9 + cpu/mt.cpu | 16 +- cpu/mt.opc | 25 +- gas/ChangeLog | 18 + gas/config/tc-mt.c | 98 +++--- gas/config/tc-mt.h | 26 +- gas/configure | 1 - gas/configure.in | 1 - include/ChangeLog | 5 + include/dis-asm.h | 2 +- include/elf/ChangeLog | 6 + include/elf/common.h | 2 +- include/elf/mt.h | 40 +-- ld/ChangeLog | 5 + ld/emulparams/elf32mt.sh | 4 +- opcodes/ChangeLog | 20 ++ opcodes/Makefile.am | 56 +-- opcodes/Makefile.in | 56 +-- opcodes/configure | 2 +- opcodes/configure.in | 2 +- opcodes/disassemble.c | 8 +- opcodes/{ms1-asm.c => mt-asm.c} | 258 +++++++------- opcodes/{ms1-desc.c => mt-desc.c} | 640 +++++++++++++++++----------------- opcodes/{ms1-desc.h => mt-desc.h} | 108 +++--- opcodes/{ms1-dis.c => mt-dis.c} | 148 ++++---- opcodes/{ms1-ibld.c => mt-ibld.c} | 700 +++++++++++++++++++------------------- opcodes/{ms1-opc.c => mt-opc.c} | 50 +-- opcodes/{ms1-opc.h => mt-opc.h} | 62 ++-- 41 files changed, 1394 insertions(+), 1293 deletions(-) rename opcodes/{ms1-asm.c => mt-asm.c} (72%) rename opcodes/{ms1-desc.c => mt-desc.c} (63%) rename opcodes/{ms1-desc.h => mt-desc.h} (78%) rename opcodes/{ms1-dis.c => mt-dis.c} (88%) rename opcodes/{ms1-ibld.c => mt-ibld.c} (79%) rename opcodes/{ms1-opc.c => mt-opc.c} (96%) rename opcodes/{ms1-opc.h => mt-opc.h} (62%) diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 1cddc7845..5e5e84e0f 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,39 @@ +2005-12-16 Nathan Sidwell + + Second part of ms1 to mt renaming. + * archures.c (bfd_arch_mt): Renamed. + (bfd_mt_arch): Renamed. + (bfd_archures_list): Adjusted. + * bfd-in2.h: Rebuilt. + * config.bfd (mt): Remove special case targ_archs. + (mt-*-elf): Rename bfd_elf32_mt_vec. + * configure: Rebuilt. + * configure.in (bfd_elf32_mt_vec): Renamed. + (selarchs) Remove mt special case. + * cpu-mt.c (arch_info_struct): Adjust. + (bfd_mt_arch): Renamed, adjust. + * elf32-mt.c (mt_reloc_type_lookup, mt_info_to_howto_rela, + mt_elf_relocate_hi16, mt_final_link_relocate, mt_relocate_section, + mt_elf_howto_table): Renamed, adjusted. + (mt_elf_gc_mark_hook, mt_elf_gc_sweep_hook, mt_elf_check_relocs, + elf32_mt_machine, mt_elf_object_p, mt_elf_set_private_flags, + mt_elf_copy_private_bfd_data, mt_elf_merge_private_bfd_data, + mt_elf_print_private_bfd_data): Renamed, adjusted. + (TARGET_BIG_SYM, TARGET_BIG_NAME, ELF_ARCH, ELF_MACHINE_CODE, + ELF_MAXPAGESIZE, elf_info_to_howto, elf_backend_relocate_section, + bfd_elf32_bfd_reloc_type_lookup, elf_backend_gc_mark_hook, + elf_backend_gc_sweep_hook, elf_backend_check_relocs, + eld_backend_object_p, bfd_elf32_bfd_set_private_flags, + bfd_elf32_bfd_copy_private_bfd_data, + bfd_elf32_bfd_merge_private_bfd_data, + bfd_elf32_bfd_print_private_bfd_data): Adjusted. + * libbfd.h: Regenerated. + * reloc.c (BFD_RELOC_MT_PC16, BFD_RELOC_MT_HI16, + BFD_RELOC_MT_LO16, BFD_RELOC_MT_GNU_VTINHERIT, + BFD_RELOC_MT_GNU_VTENTRY, BFD_RELOC_MT_PCINSN8): Renamed. + * targets.c (bfd_elf32_mt_vec): Renamed. + (_bfd_target_vector): Adjusted. + 2005-12-13 H.J. Lu PR ld/2008 diff --git a/bfd/archures.c b/bfd/archures.c index 561ddfc8e..069393a5c 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -317,7 +317,7 @@ DESCRIPTION . bfd_arch_iq2000, {* Vitesse IQ2000. *} .#define bfd_mach_iq2000 1 .#define bfd_mach_iq10 2 -. bfd_arch_ms1, +. bfd_arch_mt, .#define bfd_mach_ms1 1 .#define bfd_mach_mrisc2 2 .#define bfd_mach_ms2 3 @@ -445,7 +445,7 @@ extern const bfd_arch_info_type bfd_mmix_arch; extern const bfd_arch_info_type bfd_mn10200_arch; extern const bfd_arch_info_type bfd_mn10300_arch; extern const bfd_arch_info_type bfd_msp430_arch; -extern const bfd_arch_info_type bfd_ms1_arch; +extern const bfd_arch_info_type bfd_mt_arch; extern const bfd_arch_info_type bfd_ns32k_arch; extern const bfd_arch_info_type bfd_openrisc_arch; extern const bfd_arch_info_type bfd_or32_arch; @@ -510,7 +510,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_mmix_arch, &bfd_mn10200_arch, &bfd_mn10300_arch, - &bfd_ms1_arch, + &bfd_mt_arch, &bfd_msp430_arch, &bfd_ns32k_arch, &bfd_openrisc_arch, diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index ed783232c..0045345fe 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1906,7 +1906,7 @@ enum bfd_architecture bfd_arch_iq2000, /* Vitesse IQ2000. */ #define bfd_mach_iq2000 1 #define bfd_mach_iq10 2 - bfd_arch_ms1, + bfd_arch_mt, #define bfd_mach_ms1 1 #define bfd_mach_mrisc2 2 #define bfd_mach_ms2 3 @@ -3964,23 +3964,23 @@ This is the 5 bits of a value. */ BFD_RELOC_VAX_JMP_SLOT, BFD_RELOC_VAX_RELATIVE, -/* Morpho MS1 - 16 bit immediate relocation. */ - BFD_RELOC_MS1_PC16, +/* Morpho MT - 16 bit immediate relocation. */ + BFD_RELOC_MT_PC16, -/* Morpho MS1 - Hi 16 bits of an address. */ - BFD_RELOC_MS1_HI16, +/* Morpho MT - Hi 16 bits of an address. */ + BFD_RELOC_MT_HI16, -/* Morpho MS1 - Low 16 bits of an address. */ - BFD_RELOC_MS1_LO16, +/* Morpho MT - Low 16 bits of an address. */ + BFD_RELOC_MT_LO16, -/* Morpho MS1 - Used to tell the linker which vtable entries are used. */ - BFD_RELOC_MS1_GNU_VTINHERIT, +/* Morpho MT - Used to tell the linker which vtable entries are used. */ + BFD_RELOC_MT_GNU_VTINHERIT, -/* Morpho MS1 - Used to tell the linker which vtable entries are used. */ - BFD_RELOC_MS1_GNU_VTENTRY, +/* Morpho MT - Used to tell the linker which vtable entries are used. */ + BFD_RELOC_MT_GNU_VTENTRY, -/* Morpho MS1 - 8 bit immediate relocation. */ - BFD_RELOC_MS1_PCINSN8, +/* Morpho MT - 8 bit immediate relocation. */ + BFD_RELOC_MT_PCINSN8, /* msp430 specific relocation codes */ BFD_RELOC_MSP430_10_PCREL, diff --git a/bfd/config.bfd b/bfd/config.bfd index 903be2ad2..6627d7f6f 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -87,7 +87,6 @@ m68*) targ_archs=bfd_m68k_arch ;; m88*) targ_archs=bfd_m88k_arch ;; maxq*) targ_archs=bfd_maxq_arch ;; mips*) targ_archs=bfd_mips_arch ;; -mt) targ_archs=bfd_ms1_arch ;; or32*) targ_archs=bfd_or32_arch ;; pdp11*) targ_archs=bfd_pdp11_arch ;; pj*) targ_archs="bfd_pj_arch bfd_i386_arch";; @@ -927,7 +926,7 @@ case "${targ}" in ;; mt-*-elf) - targ_defvec=bfd_elf32_ms1_vec + targ_defvec=bfd_elf32_mt_vec ;; msp430-*-*) diff --git a/bfd/configure b/bfd/configure index 178fb59d7..5b93fb277 100755 --- a/bfd/configure +++ b/bfd/configure @@ -13022,7 +13022,7 @@ do bfd_elf32_mcore_little_vec) tb="$tb elf32-mcore.lo elf32.lo $elf" ;; bfd_elf32_mn10200_vec) tb="$tb elf-m10200.lo elf32.lo $elf" ;; bfd_elf32_mn10300_vec) tb="$tb elf-m10300.lo elf32.lo $elf" ;; - bfd_elf32_ms1_vec) tb="$tb elf32-mt.lo elf32.lo $elf" ;; + bfd_elf32_mt_vec) tb="$tb elf32-mt.lo elf32.lo $elf" ;; bfd_elf32_msp430_vec) tb="$tb elf32-msp430.lo elf32.lo $elf" ;; bfd_elf32_nbigmips_vec) tb="$tb elfn32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; bfd_elf32_nlittlemips_vec) tb="$tb elfn32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; @@ -13223,7 +13223,7 @@ done # Target architecture .o files. # A couple of CPUs use shorter file names to avoid problems on DOS # filesystems. -ta=`echo $selarchs | sed -e s/_ms1_/_mt_/ -e s/bfd_/cpu-/g -e s/_arch/.lo/g -e s/mn10200/m10200/ -e s/mn10300/m10300/` +ta=`echo $selarchs | sed -e s/bfd_/cpu-/g -e s/_arch/.lo/g -e s/mn10200/m10200/ -e s/mn10300/m10300/` # Weed out duplicate .o files. f="" diff --git a/bfd/configure.in b/bfd/configure.in index 534e3c371..7ebf4b816 100644 --- a/bfd/configure.in +++ b/bfd/configure.in @@ -637,7 +637,7 @@ do bfd_elf32_mcore_little_vec) tb="$tb elf32-mcore.lo elf32.lo $elf" ;; bfd_elf32_mn10200_vec) tb="$tb elf-m10200.lo elf32.lo $elf" ;; bfd_elf32_mn10300_vec) tb="$tb elf-m10300.lo elf32.lo $elf" ;; - bfd_elf32_ms1_vec) tb="$tb elf32-mt.lo elf32.lo $elf" ;; + bfd_elf32_mt_vec) tb="$tb elf32-mt.lo elf32.lo $elf" ;; bfd_elf32_msp430_vec) tb="$tb elf32-msp430.lo elf32.lo $elf" ;; bfd_elf32_nbigmips_vec) tb="$tb elfn32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; bfd_elf32_nlittlemips_vec) tb="$tb elfn32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; @@ -836,7 +836,7 @@ done # Target architecture .o files. # A couple of CPUs use shorter file names to avoid problems on DOS # filesystems. -ta=`echo $selarchs | sed -e s/_ms1_/_mt_/ -e s/bfd_/cpu-/g -e s/_arch/.lo/g -e s/mn10200/m10200/ -e s/mn10300/m10300/` +ta=`echo $selarchs | sed -e s/bfd_/cpu-/g -e s/_arch/.lo/g -e s/mn10200/m10200/ -e s/mn10300/m10300/` # Weed out duplicate .o files. f="" diff --git a/bfd/cpu-mt.c b/bfd/cpu-mt.c index 18d75a0ce..43b442aee 100644 --- a/bfd/cpu-mt.c +++ b/bfd/cpu-mt.c @@ -1,4 +1,4 @@ -/* BFD support for the Morpho Technologies MS1 processor. +/* BFD support for the Morpho Technologies MT processor. Copyright (C) 2001, 2002, 2005 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -27,9 +27,9 @@ const bfd_arch_info_type arch_info_struct[] = 32, /* Bits per word - not really true. */ 32, /* Bits per address. */ 8, /* Bits per byte. */ - bfd_arch_ms1, /* Architecture. */ + bfd_arch_mt, /* Architecture. */ bfd_mach_mrisc2, /* Machine. */ - "ms1", /* Architecture name. */ + "mt", /* Architecture name. */ "ms1-003", /* Printable name. */ 1, /* Section align power. */ FALSE, /* The default ? */ @@ -41,9 +41,9 @@ const bfd_arch_info_type arch_info_struct[] = 32, /* Bits per word - not really true. */ 32, /* Bits per address. */ 8, /* Bits per byte. */ - bfd_arch_ms1, /* Architecture. */ + bfd_arch_mt, /* Architecture. */ bfd_mach_ms2, /* Machine. */ - "ms1", /* Architecture name. */ + "mt", /* Architecture name. */ "ms2", /* Printable name. */ 1, /* Section align power. */ FALSE, /* The default ? */ @@ -53,14 +53,14 @@ const bfd_arch_info_type arch_info_struct[] = }, }; -const bfd_arch_info_type bfd_ms1_arch = +const bfd_arch_info_type bfd_mt_arch = { 32, /* Bits per word - not really true. */ 32, /* Bits per address. */ 8, /* Bits per byte. */ - bfd_arch_ms1, /* Architecture. */ + bfd_arch_mt, /* Architecture. */ bfd_mach_ms1, /* Machine. */ - "ms1", /* Architecture name. */ + "mt", /* Architecture name. */ "ms1", /* Printable name. */ 1, /* Section align power. */ TRUE, /* The default ? */ diff --git a/bfd/elf32-mt.c b/bfd/elf32-mt.c index ff33ca4a0..9f240bb34 100644 --- a/bfd/elf32-mt.c +++ b/bfd/elf32-mt.c @@ -1,4 +1,4 @@ -/* Morpho Technologies MS1 specific support for 32-bit ELF +/* Morpho Technologies MT specific support for 32-bit ELF Copyright 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. @@ -25,28 +25,28 @@ #include "elf/mt.h" /* Prototypes. */ -static reloc_howto_type * ms1_reloc_type_lookup +static reloc_howto_type * mt_reloc_type_lookup (bfd *, bfd_reloc_code_real_type); -static void ms1_info_to_howto_rela +static void mt_info_to_howto_rela (bfd *, arelent *, Elf_Internal_Rela *); -static bfd_reloc_status_type ms1_elf_relocate_hi16 +static bfd_reloc_status_type mt_elf_relocate_hi16 (bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma); -static bfd_reloc_status_type ms1_final_link_relocate +static bfd_reloc_status_type mt_final_link_relocate (reloc_howto_type *, bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, bfd_vma); -static bfd_boolean ms1_elf_relocate_section +static bfd_boolean mt_elf_relocate_section (bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, Elf_Internal_Sym *, asection **); /* Relocation tables. */ -static reloc_howto_type ms1_elf_howto_table [] = +static reloc_howto_type mt_elf_howto_table [] = { /* This reloc does nothing. */ - HOWTO (R_MS1_NONE, /* type */ + HOWTO (R_MT_NONE, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 32, /* bitsize */ @@ -54,14 +54,14 @@ static reloc_howto_type ms1_elf_howto_table [] = 0, /* bitpos */ complain_overflow_dont, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_MS1_NONE", /* name */ + "R_MT_NONE", /* name */ FALSE, /* partial_inplace */ 0 , /* src_mask */ 0, /* dst_mask */ FALSE), /* pcrel_offset */ /* A 16 bit absolute relocation. */ - HOWTO (R_MS1_16, /* type */ + HOWTO (R_MT_16, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 16, /* bitsize */ @@ -69,14 +69,14 @@ static reloc_howto_type ms1_elf_howto_table [] = 0, /* bitpos */ complain_overflow_dont, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_MS1_16", /* name */ + "R_MT_16", /* name */ FALSE, /* partial_inplace */ 0 , /* src_mask */ 0xffff, /* dst_mask */ FALSE), /* pcrel_offset */ /* A 32 bit absolute relocation. */ - HOWTO (R_MS1_32, /* type */ + HOWTO (R_MT_32, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 32, /* bitsize */ @@ -84,14 +84,14 @@ static reloc_howto_type ms1_elf_howto_table [] = 0, /* bitpos */ complain_overflow_dont, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_MS1_32", /* name */ + "R_MT_32", /* name */ FALSE, /* partial_inplace */ 0 , /* src_mask */ 0xffffffff, /* dst_mask */ FALSE), /* pcrel_offset */ /* A 32 bit pc-relative relocation. */ - HOWTO (R_MS1_32_PCREL, /* type */ + HOWTO (R_MT_32_PCREL, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 32, /* bitsize */ @@ -99,14 +99,14 @@ static reloc_howto_type ms1_elf_howto_table [] = 0, /* bitpos */ complain_overflow_dont, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_MS1_32_PCREL", /* name */ + "R_MT_32_PCREL", /* name */ FALSE, /* partial_inplace */ 0 , /* src_mask */ 0xffffffff, /* dst_mask */ TRUE), /* pcrel_offset */ /* A 16 bit pc-relative relocation. */ - HOWTO (R_MS1_PC16, /* type */ + HOWTO (R_MT_PC16, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 16, /* bitsize */ @@ -114,14 +114,14 @@ static reloc_howto_type ms1_elf_howto_table [] = 0, /* bitpos */ complain_overflow_signed, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_MS1_PC16", /* name */ + "R_MT_PC16", /* name */ FALSE, /* partial_inplace */ 0, /* src_mask */ 0xffff, /* dst_mask */ TRUE), /* pcrel_offset */ /* high 16 bits of symbol value. */ - HOWTO (R_MS1_HI16, /* type */ + HOWTO (R_MT_HI16, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 16, /* bitsize */ @@ -129,14 +129,14 @@ static reloc_howto_type ms1_elf_howto_table [] = 0, /* bitpos */ complain_overflow_dont, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_MS1_HI16", /* name */ + "R_MT_HI16", /* name */ FALSE, /* partial_inplace */ 0xffff0000, /* src_mask */ 0xffff0000, /* dst_mask */ FALSE), /* pcrel_offset */ /* Low 16 bits of symbol value. */ - HOWTO (R_MS1_LO16, /* type */ + HOWTO (R_MT_LO16, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 16, /* bitsize */ @@ -144,41 +144,41 @@ static reloc_howto_type ms1_elf_howto_table [] = 0, /* bitpos */ complain_overflow_dont, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_MS1_LO16", /* name */ + "R_MT_LO16", /* name */ FALSE, /* partial_inplace */ 0xffff, /* src_mask */ 0xffff, /* dst_mask */ FALSE), /* pcrel_offset */ }; -/* Map BFD reloc types to MS1 ELF reloc types. */ +/* Map BFD reloc types to MT ELF reloc types. */ static reloc_howto_type * -ms1_reloc_type_lookup +mt_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, bfd_reloc_code_real_type code) { - /* Note that the ms1_elf_howto_table is indxed by the R_ + /* Note that the mt_elf_howto_table is indxed by the R_ constants. Thus, the order that the howto records appear in the table *must* match the order of the relocation types defined in - include/elf/ms1.h. */ + include/elf/mt.h. */ switch (code) { case BFD_RELOC_NONE: - return &ms1_elf_howto_table[ (int) R_MS1_NONE]; + return &mt_elf_howto_table[ (int) R_MT_NONE]; case BFD_RELOC_16: - return &ms1_elf_howto_table[ (int) R_MS1_16]; + return &mt_elf_howto_table[ (int) R_MT_16]; case BFD_RELOC_32: - return &ms1_elf_howto_table[ (int) R_MS1_32]; + return &mt_elf_howto_table[ (int) R_MT_32]; case BFD_RELOC_32_PCREL: - return &ms1_elf_howto_table[ (int) R_MS1_32_PCREL]; + return &mt_elf_howto_table[ (int) R_MT_32_PCREL]; case BFD_RELOC_16_PCREL: - return &ms1_elf_howto_table[ (int) R_MS1_PC16]; + return &mt_elf_howto_table[ (int) R_MT_PC16]; case BFD_RELOC_HI16: - return &ms1_elf_howto_table[ (int) R_MS1_HI16]; + return &mt_elf_howto_table[ (int) R_MT_HI16]; case BFD_RELOC_LO16: - return &ms1_elf_howto_table[ (int) R_MS1_LO16]; + return &mt_elf_howto_table[ (int) R_MT_LO16]; default: /* Pacify gcc -Wall. */ @@ -188,7 +188,7 @@ ms1_reloc_type_lookup } bfd_reloc_status_type -ms1_elf_relocate_hi16 +mt_elf_relocate_hi16 (bfd * input_bfd, Elf_Internal_Rela * relhi, bfd_byte * contents, @@ -209,10 +209,10 @@ ms1_elf_relocate_hi16 /* XXX: The following code is the result of a cut&paste. This unfortunate practice is very widespread in the various target back-end files. */ -/* Set the howto pointer for a MS1 ELF reloc. */ +/* Set the howto pointer for a MT ELF reloc. */ static void -ms1_info_to_howto_rela +mt_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED, arelent * cache_ptr, Elf_Internal_Rela * dst) @@ -220,14 +220,14 @@ ms1_info_to_howto_rela unsigned int r_type; r_type = ELF32_R_TYPE (dst->r_info); - cache_ptr->howto = & ms1_elf_howto_table [r_type]; + cache_ptr->howto = & mt_elf_howto_table [r_type]; } /* Perform a single relocation. By default we use the standard BFD routines. */ static bfd_reloc_status_type -ms1_final_link_relocate +mt_final_link_relocate (reloc_howto_type * howto, bfd * input_bfd, asection * input_section, @@ -240,7 +240,7 @@ ms1_final_link_relocate relocation, rel->r_addend); } -/* Relocate a MS1 ELF section. +/* Relocate a MT ELF section. There is some attempt to make this function usable for many architectures, both USE_REL and USE_RELA ['twould be nice if such a critter existed], if only to serve as a learning tool. @@ -274,7 +274,7 @@ ms1_final_link_relocate accordingly. */ static bfd_boolean -ms1_elf_relocate_section +mt_elf_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED, struct bfd_link_info * info, bfd * input_bfd, @@ -310,7 +310,7 @@ ms1_elf_relocate_section r_symndx = ELF32_R_SYM (rel->r_info); /* This is a final link. */ - howto = ms1_elf_howto_table + ELF32_R_TYPE (rel->r_info); + howto = mt_elf_howto_table + ELF32_R_TYPE (rel->r_info); h = NULL; sym = NULL; sec = NULL; @@ -339,14 +339,14 @@ ms1_elf_relocate_section } - /* Finally, the sole MS1-specific part. */ + /* Finally, the sole MT-specific part. */ switch (r_type) { - case R_MS1_HI16: - r = ms1_elf_relocate_hi16 (input_bfd, rel, contents, relocation); + case R_MT_HI16: + r = mt_elf_relocate_hi16 (input_bfd, rel, contents, relocation); break; default: - r = ms1_final_link_relocate (howto, input_bfd, input_section, + r = mt_final_link_relocate (howto, input_bfd, input_section, contents, rel, relocation); break; } @@ -398,7 +398,7 @@ ms1_elf_relocate_section relocation. */ static asection * -ms1_elf_gc_mark_hook +mt_elf_gc_mark_hook (asection * sec, struct bfd_link_info * info ATTRIBUTE_UNUSED, Elf_Internal_Rela * rel ATTRIBUTE_UNUSED, @@ -436,7 +436,7 @@ ms1_elf_gc_mark_hook removed. */ static bfd_boolean -ms1_elf_gc_sweep_hook +mt_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED, struct bfd_link_info * info ATTRIBUTE_UNUSED, asection * sec ATTRIBUTE_UNUSED, @@ -450,7 +450,7 @@ ms1_elf_gc_sweep_hook virtual table relocs for gc. */ static bfd_boolean -ms1_elf_check_relocs +mt_elf_check_relocs (bfd * abfd, struct bfd_link_info * info, asection * sec, @@ -495,22 +495,22 @@ ms1_elf_check_relocs /* Return the MACH for an e_flags value. */ static int -elf32_ms1_machine (bfd *abfd) +elf32_mt_machine (bfd *abfd) { - switch (elf_elfheader (abfd)->e_flags & EF_MS1_CPU_MASK) + switch (elf_elfheader (abfd)->e_flags & EF_MT_CPU_MASK) { - case EF_MS1_CPU_MRISC: return bfd_mach_ms1; - case EF_MS1_CPU_MRISC2: return bfd_mach_mrisc2; - case EF_MS1_CPU_MS2: return bfd_mach_ms2; + case EF_MT_CPU_MRISC: return bfd_mach_ms1; + case EF_MT_CPU_MRISC2: return bfd_mach_mrisc2; + case EF_MT_CPU_MS2: return bfd_mach_ms2; } return bfd_mach_ms1; } static bfd_boolean -ms1_elf_object_p (bfd * abfd) +mt_elf_object_p (bfd * abfd) { - bfd_default_set_arch_mach (abfd, bfd_arch_ms1, elf32_ms1_machine (abfd)); + bfd_default_set_arch_mach (abfd, bfd_arch_mt, elf32_mt_machine (abfd)); return TRUE; } @@ -518,7 +518,7 @@ ms1_elf_object_p (bfd * abfd) /* Function to set the ELF flag bits. */ static bfd_boolean -ms1_elf_set_private_flags (bfd * abfd, +mt_elf_set_private_flags (bfd * abfd, flagword flags) { elf_elfheader (abfd)->e_flags = flags; @@ -527,7 +527,7 @@ ms1_elf_set_private_flags (bfd * abfd, } static bfd_boolean -ms1_elf_copy_private_bfd_data (bfd * ibfd, bfd * obfd) +mt_elf_copy_private_bfd_data (bfd * ibfd, bfd * obfd) { if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour || bfd_get_flavour (obfd) != bfd_target_elf_flavour) @@ -545,7 +545,7 @@ ms1_elf_copy_private_bfd_data (bfd * ibfd, bfd * obfd) object file when linking. */ static bfd_boolean -ms1_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) +mt_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) { flagword old_flags, new_flags; bfd_boolean error = FALSE; @@ -554,11 +554,11 @@ ms1_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) if (_bfd_generic_verify_endian_match (ibfd, obfd) == FALSE) return FALSE; - /* If they're not both ms1, then merging is meaningless, so just + /* If they're not both mt, then merging is meaningless, so just don't do it. */ - if (strcmp (ibfd->arch_info->arch_name, "ms1") != 0) + if (strcmp (ibfd->arch_info->arch_name, "mt") != 0) return TRUE; - if (strcmp (obfd->arch_info->arch_name, "ms1") != 0) + if (strcmp (obfd->arch_info->arch_name, "mt") != 0) return TRUE; new_flags = elf_elfheader (ibfd)->e_flags; @@ -574,7 +574,7 @@ ms1_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) old_flags = new_flags; elf_flags_init (obfd) = TRUE; } - else if ((new_flags & EF_MS1_CPU_MASK) != (old_flags & EF_MS1_CPU_MASK)) + else if ((new_flags & EF_MT_CPU_MASK) != (old_flags & EF_MT_CPU_MASK)) { /* CPU has changed. This is invalid, because MRISC, MRISC2 and MS2 are not subsets of each other. */ @@ -584,9 +584,9 @@ ms1_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) mixing breaks the build. So we allow merging and use the greater CPU value. This is of course unsafe. */ error = 0; - if ((new_flags & EF_MS1_CPU_MASK) > (old_flags & EF_MS1_CPU_MASK)) - old_flags = ((old_flags & ~EF_MS1_CPU_MASK) - | (new_flags & EF_MS1_CPU_MASK)); + if ((new_flags & EF_MT_CPU_MASK) > (old_flags & EF_MT_CPU_MASK)) + old_flags = ((old_flags & ~EF_MT_CPU_MASK) + | (new_flags & EF_MT_CPU_MASK)); } if (!error) { @@ -598,7 +598,7 @@ ms1_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) } static bfd_boolean -ms1_elf_print_private_bfd_data (bfd * abfd, void * ptr) +mt_elf_print_private_bfd_data (bfd * abfd, void * ptr) { FILE * file = (FILE *) ptr; flagword flags; @@ -611,12 +611,12 @@ ms1_elf_print_private_bfd_data (bfd * abfd, void * ptr) flags = elf_elfheader (abfd)->e_flags; fprintf (file, _("private flags = 0x%lx:"), (long)flags); - switch (flags & EF_MS1_CPU_MASK) + switch (flags & EF_MT_CPU_MASK) { default: - case EF_MS1_CPU_MRISC: fprintf (file, " ms1-16-002"); break; - case EF_MS1_CPU_MRISC2: fprintf (file, " ms1-16-003"); break; - case EF_MS1_CPU_MS2: fprintf (file, " ms2"); break; + case EF_MT_CPU_MRISC: fprintf (file, " ms1-16-002"); break; + case EF_MT_CPU_MRISC2: fprintf (file, " ms1-16-003"); break; + case EF_MT_CPU_MS2: fprintf (file, " ms2"); break; } fputc ('\n', file); @@ -625,31 +625,31 @@ ms1_elf_print_private_bfd_data (bfd * abfd, void * ptr) } -#define TARGET_BIG_SYM bfd_elf32_ms1_vec -#define TARGET_BIG_NAME "elf32-ms1" +#define TARGET_BIG_SYM bfd_elf32_mt_vec +#define TARGET_BIG_NAME "elf32-mt" -#define ELF_ARCH bfd_arch_ms1 -#define ELF_MACHINE_CODE EM_MS1 -#define ELF_MAXPAGESIZE 1 /* No pages on the MS1. */ +#define ELF_ARCH bfd_arch_mt +#define ELF_MACHINE_CODE EM_MT +#define ELF_MAXPAGESIZE 1 /* No pages on the MT. */ #define elf_info_to_howto_rel NULL -#define elf_info_to_howto ms1_info_to_howto_rela +#define elf_info_to_howto mt_info_to_howto_rela -#define elf_backend_relocate_section ms1_elf_relocate_section +#define elf_backend_relocate_section mt_elf_relocate_section -#define bfd_elf32_bfd_reloc_type_lookup ms1_reloc_type_lookup +#define bfd_elf32_bfd_reloc_type_lookup mt_reloc_type_lookup -#define elf_backend_gc_mark_hook ms1_elf_gc_mark_hook -#define elf_backend_gc_sweep_hook ms1_elf_gc_sweep_hook -#define elf_backend_check_relocs ms1_elf_check_relocs -#define elf_backend_object_p ms1_elf_object_p +#define elf_backend_gc_mark_hook mt_elf_gc_mark_hook +#define elf_backend_gc_sweep_hook mt_elf_gc_sweep_hook +#define elf_backend_check_relocs mt_elf_check_relocs +#define elf_backend_object_p mt_elf_object_p #define elf_backend_rela_normal 1 #define elf_backend_can_gc_sections 1 -#define bfd_elf32_bfd_set_private_flags ms1_elf_set_private_flags -#define bfd_elf32_bfd_copy_private_bfd_data ms1_elf_copy_private_bfd_data -#define bfd_elf32_bfd_merge_private_bfd_data ms1_elf_merge_private_bfd_data -#define bfd_elf32_bfd_print_private_bfd_data ms1_elf_print_private_bfd_data +#define bfd_elf32_bfd_set_private_flags mt_elf_set_private_flags +#define bfd_elf32_bfd_copy_private_bfd_data mt_elf_copy_private_bfd_data +#define bfd_elf32_bfd_merge_private_bfd_data mt_elf_merge_private_bfd_data +#define bfd_elf32_bfd_print_private_bfd_data mt_elf_print_private_bfd_data #include "elf32-target.h" diff --git a/bfd/libbfd.h b/bfd/libbfd.h index b3d94039a..5a8c2167b 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -1759,12 +1759,12 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_VAX_GLOB_DAT", "BFD_RELOC_VAX_JMP_SLOT", "BFD_RELOC_VAX_RELATIVE", - "BFD_RELOC_MS1_PC16", - "BFD_RELOC_MS1_HI16", - "BFD_RELOC_MS1_LO16", - "BFD_RELOC_MS1_GNU_VTINHERIT", - "BFD_RELOC_MS1_GNU_VTENTRY", - "BFD_RELOC_MS1_PCINSN8", + "BFD_RELOC_MT_PC16", + "BFD_RELOC_MT_HI16", + "BFD_RELOC_MT_LO16", + "BFD_RELOC_MT_GNU_VTINHERIT", + "BFD_RELOC_MT_GNU_VTENTRY", + "BFD_RELOC_MT_PCINSN8", "BFD_RELOC_MSP430_10_PCREL", "BFD_RELOC_MSP430_16_PCREL", "BFD_RELOC_MSP430_16", diff --git a/bfd/reloc.c b/bfd/reloc.c index 3e43d6c52..14c3392fb 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -4382,29 +4382,29 @@ ENUMDOC Relocations used by VAX ELF. ENUM - BFD_RELOC_MS1_PC16 + BFD_RELOC_MT_PC16 ENUMDOC - Morpho MS1 - 16 bit immediate relocation. + Morpho MT - 16 bit immediate relocation. ENUM - BFD_RELOC_MS1_HI16 + BFD_RELOC_MT_HI16 ENUMDOC - Morpho MS1 - Hi 16 bits of an address. + Morpho MT - Hi 16 bits of an address. ENUM - BFD_RELOC_MS1_LO16 + BFD_RELOC_MT_LO16 ENUMDOC - Morpho MS1 - Low 16 bits of an address. + Morpho MT - Low 16 bits of an address. ENUM - BFD_RELOC_MS1_GNU_VTINHERIT + BFD_RELOC_MT_GNU_VTINHERIT ENUMDOC - Morpho MS1 - Used to tell the linker which vtable entries are used. + Morpho MT - Used to tell the linker which vtable entries are used. ENUM - BFD_RELOC_MS1_GNU_VTENTRY + BFD_RELOC_MT_GNU_VTENTRY ENUMDOC - Morpho MS1 - Used to tell the linker which vtable entries are used. + Morpho MT - Used to tell the linker which vtable entries are used. ENUM - BFD_RELOC_MS1_PCINSN8 + BFD_RELOC_MT_PCINSN8 ENUMDOC - Morpho MS1 - 8 bit immediate relocation. + Morpho MT - 8 bit immediate relocation. ENUM BFD_RELOC_MSP430_10_PCREL diff --git a/bfd/targets.c b/bfd/targets.c index c0372a1d0..6f75bca44 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -603,7 +603,7 @@ extern const bfd_target bfd_elf32_mcore_big_vec; extern const bfd_target bfd_elf32_mcore_little_vec; extern const bfd_target bfd_elf32_mn10200_vec; extern const bfd_target bfd_elf32_mn10300_vec; -extern const bfd_target bfd_elf32_ms1_vec; +extern const bfd_target bfd_elf32_mt_vec; extern const bfd_target bfd_elf32_msp430_vec; extern const bfd_target bfd_elf32_nbigmips_vec; extern const bfd_target bfd_elf32_nlittlemips_vec; @@ -909,7 +909,7 @@ static const bfd_target * const _bfd_target_vector[] = { &bfd_elf32_mcore_little_vec, &bfd_elf32_mn10200_vec, &bfd_elf32_mn10300_vec, - &bfd_elf32_ms1_vec, + &bfd_elf32_mt_vec, &bfd_elf32_msp430_vec, #ifdef BFD64 &bfd_elf32_nbigmips_vec, diff --git a/binutils/ChangeLog b/binutils/ChangeLog index 9e49570f1..563ee5caf 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,9 @@ +2005-12-16 Nathan Sidwell + + Second part of ms1 to mt renaming. + * readelf.c (guess_is_rela): Use EM_MT. + (dump_relocations, get_machine_name): Adjust. + 2005-12-12 Nathan Sidwell * Makefile.am: Replace ms1 files with mt files. diff --git a/binutils/readelf.c b/binutils/readelf.c index 82efa69a1..1110d3bb6 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -609,7 +609,7 @@ guess_is_rela (unsigned long e_machine) case EM_XTENSA_OLD: case EM_M32R: case EM_M32C: - case EM_MS1: + case EM_MT: case EM_BLACKFIN: return TRUE; @@ -1123,8 +1123,8 @@ dump_relocations (FILE *file, rtype = elf_m32c_reloc_type (type); break; - case EM_MS1: - rtype = elf_ms1_reloc_type (type); + case EM_MT: + rtype = elf_mt_reloc_type (type); break; case EM_BLACKFIN: @@ -1687,7 +1687,7 @@ get_machine_name (unsigned e_machine) case EM_XTENSA_OLD: case EM_XTENSA: return "Tensilica Xtensa Processor"; case EM_M32C: return "Renesas M32c"; - case EM_MS1: return "Morpho Techologies MS1 processor"; + case EM_MT: return "Morpho Techologies MT processor"; default: snprintf (buff, sizeof (buff), _(": %x"), e_machine); return buff; diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 86bd136ca..b552d9dcb 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,12 @@ +2005-12-16 Nathan Sidwell + + Second part of ms1 to mt renaming. + * mt.cpu (define-arch, define-isa): Set name to mt. + (define-mach): Adjust. + * mt.opc (CGEN_ASM_HASH): Update. + (mt_asm_hash, mt_cgen_insn_supported): Renamed. + (parse_loopsize, parse_imm16): Adjust. + 2005-12-13 DJ Delorie * m32c.cpu (jsri): Fix order so register names aren't treated as diff --git a/cpu/mt.cpu b/cpu/mt.cpu index 441a93733..a6e0e8ce6 100644 --- a/cpu/mt.cpu +++ b/cpu/mt.cpu @@ -1,4 +1,4 @@ -; Morpho Technologies mRISC CPU description. -*- Scheme -*- +; Morpho Technologies MT Arch description. -*- Scheme -*- ; Copyright 2001 Free Software Foundation, Inc. ; ; Contributed by Red Hat Inc; developed under contract from @@ -28,19 +28,19 @@ ; define-arch must appear first (define-arch - (name ms1) ; name of cpu family + (name mt) ; name of cpu family (comment "Morpho Technologies mRISC family") (default-alignment aligned) (insn-lsb0? #t) (machs ms1 ms1-003 ms2) - (isas ms1) + (isas mt) ) ; Instruction set parameters. (define-isa - (name ms1) - (comment "Morpho Technologies mrisc ISA") + (name mt) + (comment "Morpho Technologies MT ISA") (default-insn-word-bitsize 32) (default-insn-bitsize 32) (base-insn-bitsize 32) @@ -78,21 +78,21 @@ (name ms1) (comment "Morpho Technologies mrisc") (cpu ms1bf) - (isas ms1) + (isas mt) ) (define-mach (name ms1-003) (comment "Morpho Technologies mrisc") (cpu ms1-003bf) - (isas ms1) + (isas mt) ) (define-mach (name ms2) (comment "Morpho Technologies ms2") (cpu ms2bf) - (isas ms1) + (isas mt) ) diff --git a/cpu/mt.opc b/cpu/mt.opc index e3b32db7b..7c394e1f0 100644 --- a/cpu/mt.opc +++ b/cpu/mt.opc @@ -46,11 +46,11 @@ #define CGEN_DIS_HASH(buf, value) (((* (unsigned char *) (buf)) >> 5) % CGEN_DIS_HASH_SIZE) #define CGEN_ASM_HASH_SIZE 127 -#define CGEN_ASM_HASH(insn) ms1_asm_hash (insn) +#define CGEN_ASM_HASH(insn) mt_asm_hash (insn) -extern unsigned int ms1_asm_hash (const char *); +extern unsigned int mt_asm_hash (const char *); -extern int ms1_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); +extern int mt_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); /* -- opc.c */ @@ -59,8 +59,7 @@ extern int ms1_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); /* Special check to ensure that instruction exists for given machine. */ int -ms1_cgen_insn_supported (CGEN_CPU_DESC cd, - const CGEN_INSN *insn) +mt_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) { int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); @@ -74,7 +73,7 @@ ms1_cgen_insn_supported (CGEN_CPU_DESC cd, /* A better hash function for instruction mnemonics. */ unsigned int -ms1_asm_hash (const char* insn) +mt_asm_hash (const char* insn) { unsigned int hash; const char* m = insn; @@ -113,9 +112,9 @@ parse_loopsize (CGEN_CPU_DESC cd, bfd_vma value; /* Is it a control transfer instructions? */ - if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_LOOPSIZE) + if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_LOOPSIZE) { - code = BFD_RELOC_MS1_PCINSN8; + code = BFD_RELOC_MT_PCINSN8; errmsg = cgen_parse_address (cd, strp, opindex, code, & result_type, & value); *valuep = value; @@ -138,7 +137,7 @@ parse_imm16 (CGEN_CPU_DESC cd, bfd_vma value; /* Is it a control transfer instructions? */ - if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16O) + if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16O) { code = BFD_RELOC_16_PCREL; errmsg = cgen_parse_address (cd, strp, opindex, code, @@ -154,7 +153,7 @@ parse_imm16 (CGEN_CPU_DESC cd, /* If it's not a control transfer instruction, then we have to check for %OP relocating operators. */ - if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16L) + if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16L) ; else if (strncmp (*strp, "%hi16", 5) == 0) { @@ -203,7 +202,7 @@ parse_imm16 (CGEN_CPU_DESC cd, { /* Parse hex values like 0xffff as unsigned, and sign extend them manually. */ - int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MS1_OPERAND_IMM16); + int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MT_OPERAND_IMM16); if ((*strp)[0] == '0' && ((*strp)[1] == 'x' || (*strp)[1] == 'X')) @@ -235,10 +234,10 @@ parse_imm16 (CGEN_CPU_DESC cd, } else { - /* MS1_OPERAND_IMM16Z. Parse as an unsigned integer. */ + /* MT_OPERAND_IMM16Z. Parse as an unsigned integer. */ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep); - if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16 + if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16 && *valuep >= 0x8000 && *valuep <= 0xffff) *valuep -= 0x10000; diff --git a/gas/ChangeLog b/gas/ChangeLog index 68e748b00..69ac6830b 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,21 @@ +2005-12-16 Nathan Sidwell + + Second part of ms1 to mt renaming. + * configure: Rebuilt. + * configure.in (mt): Remove special case. + * config/tc-mt.c (opcodes/mt-desc.h, opcodes/mt-opc.h): Change + #includes. + (mt_insn, mt_mach, mt_mach_bitmask, mt_flags, mt_architectures): + Rename, adjust. + (md_parse_option, md_show_usage, md_begin, md_assemble, + md_cgen_lookup_reloc, md_atof): Adjust. + (mt_force_relocation, mt_apply_fix, mt_fix_adjustable): Rename, adjust. + * config/tc-mt.h (TC_MT): Rename. + (LISTING_HEADER, TARGET_ARCH, TARGET_FORMAT): Adjust. + (md_apply_fix): Adjust. + (mt_apply_fix, mt_fix_adjustable, mt_force_relocation): Rename. + (TC_FORCE_RELOCATION, tc_fix_adjustable): Adjust. + 2005-12-14 Jan Beulich * config/tc-i386.c (add_prefix): More fine-grained handling of diff --git a/gas/config/tc-mt.c b/gas/config/tc-mt.c index 48d272fb6..79d3ea5b3 100644 --- a/gas/config/tc-mt.c +++ b/gas/config/tc-mt.c @@ -1,4 +1,4 @@ -/* tc-ms1.c -- Assembler for the Morpho Technologies ms-I. +/* tc-mt.c -- Assembler for the Morpho Technologies mt . Copyright (C) 2005 Free Software Foundation. This file is part of GAS, the GNU Assembler. @@ -23,8 +23,8 @@ #include "dwarf2dbg.h" #include "subsegs.h" #include "symcat.h" -#include "opcodes/ms1-desc.h" -#include "opcodes/ms1-opc.h" +#include "opcodes/mt-desc.h" +#include "opcodes/mt-opc.h" #include "cgen.h" #include "elf/common.h" #include "elf/mt.h" @@ -50,7 +50,7 @@ typedef struct fixS * fixups [GAS_CGEN_MAX_FIXUPS]; int indices [MAX_OPERAND_INSTANCES]; } -ms1_insn; +mt_insn; const char comment_chars[] = ";"; @@ -83,14 +83,14 @@ size_t md_longopts_size = sizeof (md_longopts); const char * md_shortopts = ""; /* Mach selected from command line. */ -static int ms1_mach = bfd_mach_ms1; -static unsigned ms1_mach_bitmask = 1 << MACH_MS1; +static int mt_mach = bfd_mach_ms1; +static unsigned mt_mach_bitmask = 1 << MACH_MS1; /* Flags to set in the elf header */ -static flagword ms1_flags = EF_MS1_CPU_MRISC; +static flagword mt_flags = EF_MT_CPU_MRISC; /* The architecture to use. */ -enum ms1_architectures +enum mt_architectures { ms1_64_001, ms1_16_002, @@ -98,8 +98,8 @@ enum ms1_architectures ms2 }; -/* MS1 architecture we are using for this output file. */ -static enum ms1_architectures ms1_arch = ms1_64_001; +/* MT architecture we are using for this output file. */ +static enum mt_architectures mt_arch = ms1_64_001; int md_parse_option (int c ATTRIBUTE_UNUSED, char * arg) @@ -109,31 +109,31 @@ md_parse_option (int c ATTRIBUTE_UNUSED, char * arg) case OPTION_MARCH: if (strcasecmp (arg, "MS1-64-001") == 0) { - ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MRISC; - ms1_mach = bfd_mach_ms1; - ms1_mach_bitmask = 1 << MACH_MS1; - ms1_arch = ms1_64_001; + mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MRISC; + mt_mach = bfd_mach_ms1; + mt_mach_bitmask = 1 << MACH_MS1; + mt_arch = ms1_64_001; } else if (strcasecmp (arg, "MS1-16-002") == 0) { - ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MRISC; - ms1_mach = bfd_mach_ms1; - ms1_mach_bitmask = 1 << MACH_MS1; - ms1_arch = ms1_16_002; + mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MRISC; + mt_mach = bfd_mach_ms1; + mt_mach_bitmask = 1 << MACH_MS1; + mt_arch = ms1_16_002; } else if (strcasecmp (arg, "MS1-16-003") == 0) { - ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MRISC2; - ms1_mach = bfd_mach_mrisc2; - ms1_mach_bitmask = 1 << MACH_MS1_003; - ms1_arch = ms1_16_003; + mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MRISC2; + mt_mach = bfd_mach_mrisc2; + mt_mach_bitmask = 1 << MACH_MS1_003; + mt_arch = ms1_16_003; } else if (strcasecmp (arg, "MS2") == 0) { - ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MS2; - ms1_mach = bfd_mach_mrisc2; - ms1_mach_bitmask = 1 << MACH_MS2; - ms1_arch = ms2; + mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MS2; + mt_mach = bfd_mach_mrisc2; + mt_mach_bitmask = 1 << MACH_MS2; + mt_arch = ms2; } case OPTION_NO_SCHED_REST: no_scheduling_restrictions = 1; @@ -149,7 +149,7 @@ md_parse_option (int c ATTRIBUTE_UNUSED, char * arg) void md_show_usage (FILE * stream) { - fprintf (stream, _("MS1 specific command line options:\n")); + fprintf (stream, _("MT specific command line options:\n")); fprintf (stream, _(" -march=ms1-64-001 allow ms1-64-001 instructions (default) \n")); fprintf (stream, _(" -march=ms1-16-002 allow ms1-16-002 instructions \n")); fprintf (stream, _(" -march=ms1-16-003 allow ms1-16-003 instructions \n")); @@ -164,21 +164,21 @@ md_begin (void) /* Initialize the `cgen' interface. */ /* Set the machine number and endian. */ - gas_cgen_cpu_desc = ms1_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, ms1_mach_bitmask, - CGEN_CPU_OPEN_ENDIAN, - CGEN_ENDIAN_BIG, - CGEN_CPU_OPEN_END); - ms1_cgen_init_asm (gas_cgen_cpu_desc); + gas_cgen_cpu_desc = mt_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, mt_mach_bitmask, + CGEN_CPU_OPEN_ENDIAN, + CGEN_ENDIAN_BIG, + CGEN_CPU_OPEN_END); + mt_cgen_init_asm (gas_cgen_cpu_desc); /* This is a callback from cgen to gas to parse operands. */ cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); /* Set the ELF flags if desired. */ - if (ms1_flags) - bfd_set_private_flags (stdoutput, ms1_flags); + if (mt_flags) + bfd_set_private_flags (stdoutput, mt_flags); /* Set the machine type. */ - bfd_default_set_arch_mach (stdoutput, bfd_arch_ms1, ms1_mach); + bfd_default_set_arch_mach (stdoutput, bfd_arch_mt, mt_mach); } void @@ -195,13 +195,13 @@ md_assemble (char * str) static int last_insn_was_branch_insn = 0; static int last_insn_was_conditional_branch_insn = 0; - ms1_insn insn; + mt_insn insn; char * errmsg; /* Initialize GAS's cgen interface for a new instruction. */ gas_cgen_init_parse (); - insn.insn = ms1_cgen_assemble_insn + insn.insn = mt_cgen_assemble_insn (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg); if (!insn.insn) @@ -221,7 +221,7 @@ md_assemble (char * str) /* Detect consecutive Memory Accesses. */ if (last_insn_was_memory_access && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MEMORY_ACCESS) - && ms1_mach == ms1_64_001) + && mt_mach == ms1_64_001) as_warn (_("instruction %s may not follow another memory access instruction."), CGEN_INSN_NAME (insn.insn)); @@ -252,7 +252,7 @@ md_assemble (char * str) } /* Detect JAL/RETI hazard */ - if (ms1_mach == ms2 + if (mt_mach == ms2 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_JAL_HAZARD)) { if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1) @@ -275,7 +275,7 @@ md_assemble (char * str) && !last_insn_in_noncond_delay_slot && (delayed_load_register != 0) && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN) - && ms1_arch == ms1_64_001) + && mt_arch == ms1_64_001) { if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1) && insn.fields.f_sr1 == delayed_load_register) @@ -399,20 +399,20 @@ md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED, switch (operand->type) { - case MS1_OPERAND_IMM16O: + case MT_OPERAND_IMM16O: result = BFD_RELOC_16_PCREL; fixP->fx_pcrel = 1; /* fixP->fx_no_overflow = 1; */ break; - case MS1_OPERAND_IMM16: - case MS1_OPERAND_IMM16Z: + case MT_OPERAND_IMM16: + case MT_OPERAND_IMM16Z: /* These may have been processed at parse time. */ if (fixP->fx_cgen.opinfo != 0) result = fixP->fx_cgen.opinfo; fixP->fx_no_overflow = 1; break; - case MS1_OPERAND_LOOPSIZE: - result = BFD_RELOC_MS1_PCINSN8; + case MT_OPERAND_LOOPSIZE: + result = BFD_RELOC_MT_PCINSN8; fixP->fx_pcrel = 1; /* Adjust for the delay slot, which is not part of the loop */ fixP->fx_offset -= 8; @@ -480,7 +480,7 @@ md_atof (type, litP, sizeP) * sizeP = prec * sizeof (LITTLENUM_TYPE); /* This loops outputs the LITTLENUMs in REVERSE order; - in accord with the ms1 endianness. */ + in accord with the mt endianness. */ for (wordP = words; prec--;) { md_number_to_chars (litP, (valueT) (*wordP++), sizeof (LITTLENUM_TYPE)); @@ -493,13 +493,13 @@ md_atof (type, litP, sizeP) /* See whether we need to force a relocation into the output file. */ int -ms1_force_relocation (fixS * fixp ATTRIBUTE_UNUSED) +mt_force_relocation (fixS * fixp ATTRIBUTE_UNUSED) { return 0; } void -ms1_apply_fix (fixS *fixP, valueT *valueP, segT seg) +mt_apply_fix (fixS *fixP, valueT *valueP, segT seg) { if ((fixP->fx_pcrel != 0) && (fixP->fx_r_type == BFD_RELOC_32)) fixP->fx_r_type = BFD_RELOC_32_PCREL; @@ -508,7 +508,7 @@ ms1_apply_fix (fixS *fixP, valueT *valueP, segT seg) } bfd_boolean -ms1_fix_adjustable (fixS * fixP) +mt_fix_adjustable (fixS * fixP) { bfd_reloc_code_real_type reloc_type; diff --git a/gas/config/tc-mt.h b/gas/config/tc-mt.h index ebf953340..3f64988a6 100644 --- a/gas/config/tc-mt.h +++ b/gas/config/tc-mt.h @@ -1,4 +1,4 @@ -/* tc-ms1.h -- Header file for tc-ms1.c. +/* tc-mt.h -- Header file for tc-mt.c. Copyright (C) 2005 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler. @@ -18,14 +18,14 @@ the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#define TC_MS1 +#define TC_MT -#define LISTING_HEADER "MS1 GAS " +#define LISTING_HEADER "MT GAS " /* The target BFD architecture. */ -#define TARGET_ARCH bfd_arch_ms1 +#define TARGET_ARCH bfd_arch_mt -#define TARGET_FORMAT "elf32-ms1" +#define TARGET_FORMAT "elf32-mt" #define TARGET_BYTES_BIG_ENDIAN 1 @@ -38,21 +38,21 @@ /* We don't need to handle .word strangely. */ #define WORKING_DOT_WORD -/* All ms1 instructions are multiples of 32 bits. */ +/* All mt instructions are multiples of 32 bits. */ #define DWARF2_LINE_MIN_INSN_LENGTH 4 #define LITERAL_PREFIXDOLLAR_HEX #define LITERAL_PREFIXPERCENT_BIN -#define md_apply_fix ms1_apply_fix -extern void ms1_apply_fix (struct fix *, valueT *, segT); +#define md_apply_fix mt_apply_fix +extern void mt_apply_fix (struct fix *, valueT *, segT); /* Call md_pcrel_from_section(), not md_pcrel_from(). */ #define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC) extern long md_pcrel_from_section (struct fix *, segT); #define obj_fix_adjustable(fixP) iq2000_fix_adjustable (fixP) -extern bfd_boolean ms1_fix_adjustable (struct fix *); +extern bfd_boolean mt_fix_adjustable (struct fix *); /* Values passed to md_apply_fix don't include the symbol value. */ #define MD_APPLY_SYM_VALUE(FIX) 0 @@ -62,9 +62,9 @@ extern bfd_boolean ms1_fix_adjustable (struct fix *); #define md_operand(x) gas_cgen_md_operand (x) extern void gas_cgen_md_operand (expressionS *); -#define TC_FORCE_RELOCATION(fixp) ms1_force_relocation (fixp) -extern int ms1_force_relocation (struct fix *); +#define TC_FORCE_RELOCATION(fixp) mt_force_relocation (fixp) +extern int mt_force_relocation (struct fix *); -#define tc_fix_adjustable(fixP) ms1_fix_adjustable (fixP) -extern bfd_boolean ms1_fix_adjustable (struct fix *); +#define tc_fix_adjustable(fixP) mt_fix_adjustable (fixP) +extern bfd_boolean mt_fix_adjustable (struct fix *); diff --git a/gas/configure b/gas/configure index 2a890e6a7..c32f16eae 100755 --- a/gas/configure +++ b/gas/configure @@ -4812,7 +4812,6 @@ esac cgen_cpu_prefix="" if test $using_cgen = yes ; then case ${target_cpu} in - mt) cgen_cpu_prefix=ms1 ;; *) cgen_cpu_prefix=${target_cpu} ;; esac diff --git a/gas/configure.in b/gas/configure.in index f0baf767a..9929755a3 100644 --- a/gas/configure.in +++ b/gas/configure.in @@ -433,7 +433,6 @@ esac cgen_cpu_prefix="" if test $using_cgen = yes ; then case ${target_cpu} in - mt) cgen_cpu_prefix=ms1 ;; *) cgen_cpu_prefix=${target_cpu} ;; esac AC_SUBST(cgen_cpu_prefix) diff --git a/include/ChangeLog b/include/ChangeLog index 727d2333d..c20d1cf30 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2005-12-16 Nathan Sidwell + + Second part of ms1 to mt renaming. + * dis-asm.h (print_insn_mt): Renamed. + 2005-12-12 Nathan Sidwell * elf/mt.h: Renamed from ms1.h diff --git a/include/dis-asm.h b/include/dis-asm.h index ca6da9c21..ddb3426a5 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -237,7 +237,7 @@ extern int print_insn_mcore (bfd_vma, disassemble_info *); extern int print_insn_mmix (bfd_vma, disassemble_info *); extern int print_insn_mn10200 (bfd_vma, disassemble_info *); extern int print_insn_mn10300 (bfd_vma, disassemble_info *); -extern int print_insn_ms1 (bfd_vma, disassemble_info *); +extern int print_insn_mt (bfd_vma, disassemble_info *); extern int print_insn_msp430 (bfd_vma, disassemble_info *); extern int print_insn_ns32k (bfd_vma, disassemble_info *); extern int print_insn_crx (bfd_vma, disassemble_info *); diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index a62cb1fb5..55621dc6d 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,9 @@ +2005-12-16 Nathan Sidwell + + Second part of ms1 to mt renaming. + * common.h (EM_MT): Renamed. + * mt.h: Rename relocs, cpu & other defines. + 2005-12-12 Paul Brook * arm.h (elf32_arm_get_eabi_attr_int): Add prototype. diff --git a/include/elf/common.h b/include/elf/common.h index d85a9954f..faed7314c 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -261,7 +261,7 @@ /* Ubicom IP2xxx; no ABI */ #define EM_IP2K_OLD 0x8217 -#define EM_MS1 0x2530 /* Morpho MS1; no ABI */ +#define EM_MT 0x2530 /* Morpho MT; no ABI */ /* MSP430 magic number Written in the absense everything. */ diff --git a/include/elf/mt.h b/include/elf/mt.h index 1cb7ad6ee..974c2def6 100644 --- a/include/elf/mt.h +++ b/include/elf/mt.h @@ -17,30 +17,30 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#ifndef _ELF_MS1_H -#define _ELF_MS1_H +#ifndef _ELF_MT_H +#define _ELF_MT_H #include "elf/reloc-macros.h" /* Relocations. */ -START_RELOC_NUMBERS (elf_ms1_reloc_type) - RELOC_NUMBER (R_MS1_NONE, 0) - RELOC_NUMBER (R_MS1_16, 1) - RELOC_NUMBER (R_MS1_32, 2) - RELOC_NUMBER (R_MS1_32_PCREL, 3) - RELOC_NUMBER (R_MS1_PC16, 4) - RELOC_NUMBER (R_MS1_HI16, 5) - RELOC_NUMBER (R_MS1_LO16, 6) -END_RELOC_NUMBERS(R_MS1_max) - -#define EF_MS1_CPU_MRISC 0x00000001 /* default */ -#define EF_MS1_CPU_MRISC2 0x00000002 /* MRISC2 */ -#define EF_MS1_CPU_MS2 0x00000003 /* MS2 */ -#define EF_MS1_CPU_MASK 0x00000003 /* specific cpu bits */ -#define EF_MS1_ALL_FLAGS (EF_MS1_CPU_MASK) +START_RELOC_NUMBERS (elf_mt_reloc_type) + RELOC_NUMBER (R_MT_NONE, 0) + RELOC_NUMBER (R_MT_16, 1) + RELOC_NUMBER (R_MT_32, 2) + RELOC_NUMBER (R_MT_32_PCREL, 3) + RELOC_NUMBER (R_MT_PC16, 4) + RELOC_NUMBER (R_MT_HI16, 5) + RELOC_NUMBER (R_MT_LO16, 6) +END_RELOC_NUMBERS(R_MT_max) + +#define EF_MT_CPU_MRISC 0x00000001 /* default */ +#define EF_MT_CPU_MRISC2 0x00000002 /* MRISC2 */ +#define EF_MT_CPU_MS2 0x00000003 /* MS2 */ +#define EF_MT_CPU_MASK 0x00000003 /* specific cpu bits */ +#define EF_MT_ALL_FLAGS (EF_MT_CPU_MASK) /* The location of the memory mapped hardware stack. */ -#define MS1_STACK_VALUE 0x0f000000 -#define MS1_STACK_SIZE 0x20 +#define MT_STACK_VALUE 0x0f000000 +#define MT_STACK_SIZE 0x20 -#endif /* _ELF_MS1_H */ +#endif /* _ELF_MT_H */ diff --git a/ld/ChangeLog b/ld/ChangeLog index 389677c00..bd68c9d70 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,8 @@ +2005-12-16 Nathan Sidwell + + Second part of ms1 to mt renaming. + * emulparams/elf32mt.sh (ARCH, OUTPUT_FORMAT): Adjust. + 2005-12-14 Jakub Jelinek * scripttempl/elf.sc: Put .gnu.linkonce.d.rel.ro.* sections into diff --git a/ld/emulparams/elf32mt.sh b/ld/emulparams/elf32mt.sh index c5e7876c5..667979e65 100644 --- a/ld/emulparams/elf32mt.sh +++ b/ld/emulparams/elf32mt.sh @@ -1,9 +1,9 @@ MACHINE= SCRIPT_NAME=elf -OUTPUT_FORMAT="elf32-ms1" +OUTPUT_FORMAT="elf32-mt" # See also `include/elf/mt.h' TEXT_START_ADDR=0x2000 -ARCH=ms1 +ARCH=mt ENTRY=_start EMBEDDED=yes ELFSIZE=32 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 5b4bb15ea..78f495a4f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,23 @@ +2005-12-16 Nathan Sidwell + + Second part of ms1 to mt renaming. + * Makefile.am (HFILES, CFILES, ALL_MACHINES): Adjust. + (stamp-mt): Adjust rule. + (mt-asm.lo, mt-desc.lo, mt-dis.lo, mt-ibld.lo, mt-opc.lo): Rename & + adjust. + * Makefile.in: Rebuilt. + * configure: Rebuilt. + * configure.in (bfd_mt_arch): Rename & adjust. + * disassemble.c (ARCH_mt): Renamed. + (disassembler): Adjust. + * mt-asm.c: Renamed, rebuilt. + * mt-desc.c: Renamed, rebuilt. + * mt-desc.h: Renamed, rebuilt. + * mt-dis.c: Renamed, rebuilt. + * mt-ibld.c: Renamed, rebuilt. + * mt-opc.c: Renamed, rebuilt. + * mt-opc.h: Renamed, rebuilt. + 2005-12-13 DJ Delorie * m32c-desc.c: Regenerate. diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index ff3f0c28a..829aa5287 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -36,7 +36,7 @@ HFILES = \ m32c-desc.h m32c-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ - ms1-desc.h ms1-opc.h \ + mt-desc.h mt-opc.h \ openrisc-desc.h openrisc-opc.h \ sh-opc.h \ sh64-opc.h \ @@ -136,11 +136,11 @@ CFILES = \ m10300-opc.c \ mmix-dis.c \ mmix-opc.c \ - ms1-asm.c \ - ms1-desc.c \ - ms1-dis.c \ - ms1-ibld.c \ - ms1-opc.c \ + mt-asm.c \ + mt-desc.c \ + mt-dis.c \ + mt-ibld.c \ + mt-opc.c \ ns32k-dis.c \ openrisc-asm.c \ openrisc-desc.c \ @@ -262,12 +262,12 @@ ALL_MACHINES = \ mips16-opc.lo \ mmix-dis.lo \ mmix-opc.lo \ - ms1-asm.lo \ - ms1-desc.lo \ - ms1-dis.lo \ - ms1-ibld.lo \ - ms1-opc.lo \ msp430-dis.lo \ + mt-asm.lo \ + mt-desc.lo \ + mt-dis.lo \ + mt-ibld.lo \ + mt-opc.lo \ ns32k-dis.lo \ openrisc-asm.lo \ openrisc-desc.lo \ @@ -484,10 +484,10 @@ stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc $(MAKE) run-cgen arch=frv prefix=frv options= \ archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles= -$(srcdir)/ms1-desc.h $(srcdir)/ms1-desc.c $(srcdir)/ms1-opc.h $(srcdir)/ms1-opc.c $(srcdir)/ms1-ibld.c $(srcdir)/ms1-asm.c $(srcdir)/ms1-dis.c: $(MT_DEPS) +$(srcdir)/mt-desc.h $(srcdir)/mt-desc.c $(srcdir)/mt-opc.h $(srcdir)/mt-opc.c $(srcdir)/mt-ibld.c $(srcdir)/mt-asm.c $(srcdir)/mt-dis.c: $(MT_DEPS) @true stamp-mt: $(CGENDEPS) $(srcdir)/../cpu/mt.cpu $(srcdir)/../cpu/mt.opc - $(MAKE) run-cgen arch=ms1 prefix=ms1 options= \ + $(MAKE) run-cgen arch=mt prefix=mt options= \ archfile=$(srcdir)/../cpu/mt.cpu \ opcfile=$(srcdir)/../cpu/mt.opc extrafiles= @@ -924,33 +924,33 @@ mmix-dis.lo: mmix-dis.c $(INCDIR)/opcode/mmix.h $(INCDIR)/dis-asm.h \ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ $(INCDIR)/ansidecl.h $(BFD_H) opintl.h mmix-opc.lo: mmix-opc.c $(INCDIR)/opcode/mmix.h $(INCDIR)/symcat.h -ms1-asm.lo: ms1-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ +mt-asm.lo: mt-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ - ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ - $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \ + mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \ opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \ $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h -ms1-desc.lo: ms1-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ +mt-desc.lo: mt-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ - ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ - $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \ + mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \ opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ $(INCDIR)/xregex.h $(INCDIR)/xregex2.h -ms1-dis.lo: ms1-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ +mt-dis.lo: mt-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ - ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ - $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \ + mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \ opintl.h -ms1-ibld.lo: ms1-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ +mt-ibld.lo: mt-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ - $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h \ + $(BFD_H) $(INCDIR)/symcat.h mt-desc.h $(INCDIR)/opcode/cgen-bitset.h \ $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \ - ms1-opc.h opintl.h $(INCDIR)/safe-ctype.h -ms1-opc.lo: ms1-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + mt-opc.h opintl.h $(INCDIR)/safe-ctype.h +mt-opc.lo: mt-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ - ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ - $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \ + mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \ $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \ $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/ansidecl.h \ diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 091a85038..5521b4816 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -257,7 +257,7 @@ HFILES = \ m32c-desc.h m32c-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ - ms1-desc.h ms1-opc.h \ + mt-desc.h mt-opc.h \ openrisc-desc.h openrisc-opc.h \ sh-opc.h \ sh64-opc.h \ @@ -358,11 +358,11 @@ CFILES = \ m10300-opc.c \ mmix-dis.c \ mmix-opc.c \ - ms1-asm.c \ - ms1-desc.c \ - ms1-dis.c \ - ms1-ibld.c \ - ms1-opc.c \ + mt-asm.c \ + mt-desc.c \ + mt-dis.c \ + mt-ibld.c \ + mt-opc.c \ ns32k-dis.c \ openrisc-asm.c \ openrisc-desc.c \ @@ -484,12 +484,12 @@ ALL_MACHINES = \ mips16-opc.lo \ mmix-dis.lo \ mmix-opc.lo \ - ms1-asm.lo \ - ms1-desc.lo \ - ms1-dis.lo \ - ms1-ibld.lo \ - ms1-opc.lo \ msp430-dis.lo \ + mt-asm.lo \ + mt-desc.lo \ + mt-dis.lo \ + mt-ibld.lo \ + mt-opc.lo \ ns32k-dis.lo \ openrisc-asm.lo \ openrisc-desc.lo \ @@ -1026,10 +1026,10 @@ stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc $(MAKE) run-cgen arch=frv prefix=frv options= \ archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles= -$(srcdir)/ms1-desc.h $(srcdir)/ms1-desc.c $(srcdir)/ms1-opc.h $(srcdir)/ms1-opc.c $(srcdir)/ms1-ibld.c $(srcdir)/ms1-asm.c $(srcdir)/ms1-dis.c: $(MT_DEPS) +$(srcdir)/mt-desc.h $(srcdir)/mt-desc.c $(srcdir)/mt-opc.h $(srcdir)/mt-opc.c $(srcdir)/mt-ibld.c $(srcdir)/mt-asm.c $(srcdir)/mt-dis.c: $(MT_DEPS) @true stamp-mt: $(CGENDEPS) $(srcdir)/../cpu/mt.cpu $(srcdir)/../cpu/mt.opc - $(MAKE) run-cgen arch=ms1 prefix=ms1 options= \ + $(MAKE) run-cgen arch=mt prefix=mt options= \ archfile=$(srcdir)/../cpu/mt.cpu \ opcfile=$(srcdir)/../cpu/mt.opc extrafiles= @@ -1466,33 +1466,33 @@ mmix-dis.lo: mmix-dis.c $(INCDIR)/opcode/mmix.h $(INCDIR)/dis-asm.h \ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ $(INCDIR)/ansidecl.h $(BFD_H) opintl.h mmix-opc.lo: mmix-opc.c $(INCDIR)/opcode/mmix.h $(INCDIR)/symcat.h -ms1-asm.lo: ms1-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ +mt-asm.lo: mt-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ - ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ - $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \ + mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \ opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \ $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h -ms1-desc.lo: ms1-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ +mt-desc.lo: mt-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ - ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ - $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \ + mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \ opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ $(INCDIR)/xregex.h $(INCDIR)/xregex2.h -ms1-dis.lo: ms1-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ +mt-dis.lo: mt-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ - ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ - $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \ + mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \ opintl.h -ms1-ibld.lo: ms1-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ +mt-ibld.lo: mt-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ - $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h \ + $(BFD_H) $(INCDIR)/symcat.h mt-desc.h $(INCDIR)/opcode/cgen-bitset.h \ $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \ - ms1-opc.h opintl.h $(INCDIR)/safe-ctype.h -ms1-opc.lo: ms1-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + mt-opc.h opintl.h $(INCDIR)/safe-ctype.h +mt-opc.lo: mt-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ - ms1-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ - $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ms1-opc.h \ + mt-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \ $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \ $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/ansidecl.h \ diff --git a/opcodes/configure b/opcodes/configure index fb5acd4ca..0a53eb9b4 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -8733,7 +8733,7 @@ if test x${all_targets} = xfalse ; then bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; - bfd_ms1_arch) ta="$ta ms1-asm.lo ms1-desc.lo ms1-dis.lo ms1-ibld.lo ms1-opc.lo" using_cgen=yes ;; + bfd_mt_arch) ta="$ta mt-asm.lo mt-desc.lo mt-dis.lo mt-ibld.lo mt-opc.lo" using_cgen=yes ;; bfd_msp430_arch) ta="$ta msp430-dis.lo" ;; bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; diff --git a/opcodes/configure.in b/opcodes/configure.in index 7ed93e24c..34bff6429 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -187,7 +187,7 @@ if test x${all_targets} = xfalse ; then bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; - bfd_ms1_arch) ta="$ta mt-asm.lo ms1-desc.lo ms1-dis.lo ms1-ibld.lo ms1-opc.lo" using_cgen=yes ;; + bfd_mt_arch) ta="$ta mt-asm.lo mt-desc.lo mt-dis.lo mt-ibld.lo mt-opc.lo" using_cgen=yes ;; bfd_msp430_arch) ta="$ta msp430-dis.lo" ;; bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 007731a7e..db5b90b56 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -54,7 +54,7 @@ #define ARCH_mmix #define ARCH_mn10200 #define ARCH_mn10300 -#define ARCH_ms1 +#define ARCH_mt #define ARCH_msp430 #define ARCH_ns32k #define ARCH_openrisc @@ -238,9 +238,9 @@ disassembler (abfd) disassemble = print_insn_maxq_little; break; #endif -#ifdef ARCH_ms1 - case bfd_arch_ms1: - disassemble = print_insn_ms1; +#ifdef ARCH_mt + case bfd_arch_mt: + disassemble = print_insn_mt; break; #endif #ifdef ARCH_msp430 diff --git a/opcodes/ms1-asm.c b/opcodes/mt-asm.c similarity index 72% rename from opcodes/ms1-asm.c rename to opcodes/mt-asm.c index 177198e49..85e1249b6 100644 --- a/opcodes/ms1-asm.c +++ b/opcodes/mt-asm.c @@ -31,8 +31,8 @@ #include "ansidecl.h" #include "bfd.h" #include "symcat.h" -#include "ms1-desc.h" -#include "ms1-opc.h" +#include "mt-desc.h" +#include "mt-opc.h" #include "opintl.h" #include "xregex.h" #include "libiberty.h" @@ -73,9 +73,9 @@ parse_loopsize (CGEN_CPU_DESC cd, bfd_vma value; /* Is it a control transfer instructions? */ - if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_LOOPSIZE) + if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_LOOPSIZE) { - code = BFD_RELOC_MS1_PCINSN8; + code = BFD_RELOC_MT_PCINSN8; errmsg = cgen_parse_address (cd, strp, opindex, code, & result_type, & value); *valuep = value; @@ -98,7 +98,7 @@ parse_imm16 (CGEN_CPU_DESC cd, bfd_vma value; /* Is it a control transfer instructions? */ - if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16O) + if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16O) { code = BFD_RELOC_16_PCREL; errmsg = cgen_parse_address (cd, strp, opindex, code, @@ -114,7 +114,7 @@ parse_imm16 (CGEN_CPU_DESC cd, /* If it's not a control transfer instruction, then we have to check for %OP relocating operators. */ - if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16L) + if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16L) ; else if (strncmp (*strp, "%hi16", 5) == 0) { @@ -163,7 +163,7 @@ parse_imm16 (CGEN_CPU_DESC cd, { /* Parse hex values like 0xffff as unsigned, and sign extend them manually. */ - int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MS1_OPERAND_IMM16); + int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MT_OPERAND_IMM16); if ((*strp)[0] == '0' && ((*strp)[1] == 'x' || (*strp)[1] == 'X')) @@ -195,10 +195,10 @@ parse_imm16 (CGEN_CPU_DESC cd, } else { - /* MS1_OPERAND_IMM16Z. Parse as an unsigned integer. */ + /* MT_OPERAND_IMM16Z. Parse as an unsigned integer. */ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep); - if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16 + if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16 && *valuep >= 0x8000 && *valuep <= 0xffff) *valuep -= 0x10000; @@ -398,7 +398,7 @@ parse_type (CGEN_CPU_DESC cd, /* -- dis.c */ -const char * ms1_cgen_parse_operand +const char * mt_cgen_parse_operand (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); /* Main entry point for operand parsing. @@ -415,7 +415,7 @@ const char * ms1_cgen_parse_operand the handlers. */ const char * -ms1_cgen_parse_operand (CGEN_CPU_DESC cd, +mt_cgen_parse_operand (CGEN_CPU_DESC cd, int opindex, const char ** strp, CGEN_FIELDS * fields) @@ -426,167 +426,167 @@ ms1_cgen_parse_operand (CGEN_CPU_DESC cd, switch (opindex) { - case MS1_OPERAND_A23 : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_A23, (unsigned long *) (& fields->f_a23)); + case MT_OPERAND_A23 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_A23, (unsigned long *) (& fields->f_a23)); break; - case MS1_OPERAND_BALL : - errmsg = parse_ball (cd, strp, MS1_OPERAND_BALL, (unsigned long *) (& fields->f_ball)); + case MT_OPERAND_BALL : + errmsg = parse_ball (cd, strp, MT_OPERAND_BALL, (unsigned long *) (& fields->f_ball)); break; - case MS1_OPERAND_BALL2 : - errmsg = parse_ball (cd, strp, MS1_OPERAND_BALL2, (unsigned long *) (& fields->f_ball2)); + case MT_OPERAND_BALL2 : + errmsg = parse_ball (cd, strp, MT_OPERAND_BALL2, (unsigned long *) (& fields->f_ball2)); break; - case MS1_OPERAND_BANKADDR : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_BANKADDR, (unsigned long *) (& fields->f_bankaddr)); + case MT_OPERAND_BANKADDR : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_BANKADDR, (unsigned long *) (& fields->f_bankaddr)); break; - case MS1_OPERAND_BRC : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_BRC, (unsigned long *) (& fields->f_brc)); + case MT_OPERAND_BRC : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_BRC, (unsigned long *) (& fields->f_brc)); break; - case MS1_OPERAND_BRC2 : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_BRC2, (unsigned long *) (& fields->f_brc2)); + case MT_OPERAND_BRC2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_BRC2, (unsigned long *) (& fields->f_brc2)); break; - case MS1_OPERAND_CB1INCR : - errmsg = cgen_parse_signed_integer (cd, strp, MS1_OPERAND_CB1INCR, (long *) (& fields->f_cb1incr)); + case MT_OPERAND_CB1INCR : + errmsg = cgen_parse_signed_integer (cd, strp, MT_OPERAND_CB1INCR, (long *) (& fields->f_cb1incr)); break; - case MS1_OPERAND_CB1SEL : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CB1SEL, (unsigned long *) (& fields->f_cb1sel)); + case MT_OPERAND_CB1SEL : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CB1SEL, (unsigned long *) (& fields->f_cb1sel)); break; - case MS1_OPERAND_CB2INCR : - errmsg = cgen_parse_signed_integer (cd, strp, MS1_OPERAND_CB2INCR, (long *) (& fields->f_cb2incr)); + case MT_OPERAND_CB2INCR : + errmsg = cgen_parse_signed_integer (cd, strp, MT_OPERAND_CB2INCR, (long *) (& fields->f_cb2incr)); break; - case MS1_OPERAND_CB2SEL : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CB2SEL, (unsigned long *) (& fields->f_cb2sel)); + case MT_OPERAND_CB2SEL : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CB2SEL, (unsigned long *) (& fields->f_cb2sel)); break; - case MS1_OPERAND_CBRB : - errmsg = parse_cbrb (cd, strp, MS1_OPERAND_CBRB, (unsigned long *) (& fields->f_cbrb)); + case MT_OPERAND_CBRB : + errmsg = parse_cbrb (cd, strp, MT_OPERAND_CBRB, (unsigned long *) (& fields->f_cbrb)); break; - case MS1_OPERAND_CBS : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CBS, (unsigned long *) (& fields->f_cbs)); + case MT_OPERAND_CBS : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CBS, (unsigned long *) (& fields->f_cbs)); break; - case MS1_OPERAND_CBX : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CBX, (unsigned long *) (& fields->f_cbx)); + case MT_OPERAND_CBX : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CBX, (unsigned long *) (& fields->f_cbx)); break; - case MS1_OPERAND_CCB : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CCB, (unsigned long *) (& fields->f_ccb)); + case MT_OPERAND_CCB : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CCB, (unsigned long *) (& fields->f_ccb)); break; - case MS1_OPERAND_CDB : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CDB, (unsigned long *) (& fields->f_cdb)); + case MT_OPERAND_CDB : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CDB, (unsigned long *) (& fields->f_cdb)); break; - case MS1_OPERAND_CELL : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CELL, (unsigned long *) (& fields->f_cell)); + case MT_OPERAND_CELL : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CELL, (unsigned long *) (& fields->f_cell)); break; - case MS1_OPERAND_COLNUM : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_COLNUM, (unsigned long *) (& fields->f_colnum)); + case MT_OPERAND_COLNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_COLNUM, (unsigned long *) (& fields->f_colnum)); break; - case MS1_OPERAND_CONTNUM : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CONTNUM, (unsigned long *) (& fields->f_contnum)); + case MT_OPERAND_CONTNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CONTNUM, (unsigned long *) (& fields->f_contnum)); break; - case MS1_OPERAND_CR : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CR, (unsigned long *) (& fields->f_cr)); + case MT_OPERAND_CR : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CR, (unsigned long *) (& fields->f_cr)); break; - case MS1_OPERAND_CTXDISP : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_CTXDISP, (unsigned long *) (& fields->f_ctxdisp)); + case MT_OPERAND_CTXDISP : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_CTXDISP, (unsigned long *) (& fields->f_ctxdisp)); break; - case MS1_OPERAND_DUP : - errmsg = parse_dup (cd, strp, MS1_OPERAND_DUP, (unsigned long *) (& fields->f_dup)); + case MT_OPERAND_DUP : + errmsg = parse_dup (cd, strp, MT_OPERAND_DUP, (unsigned long *) (& fields->f_dup)); break; - case MS1_OPERAND_FBDISP : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_FBDISP, (unsigned long *) (& fields->f_fbdisp)); + case MT_OPERAND_FBDISP : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_FBDISP, (unsigned long *) (& fields->f_fbdisp)); break; - case MS1_OPERAND_FBINCR : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_FBINCR, (unsigned long *) (& fields->f_fbincr)); + case MT_OPERAND_FBINCR : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_FBINCR, (unsigned long *) (& fields->f_fbincr)); break; - case MS1_OPERAND_FRDR : - errmsg = cgen_parse_keyword (cd, strp, & ms1_cgen_opval_h_spr, & fields->f_dr); + case MT_OPERAND_FRDR : + errmsg = cgen_parse_keyword (cd, strp, & mt_cgen_opval_h_spr, & fields->f_dr); break; - case MS1_OPERAND_FRDRRR : - errmsg = cgen_parse_keyword (cd, strp, & ms1_cgen_opval_h_spr, & fields->f_drrr); + case MT_OPERAND_FRDRRR : + errmsg = cgen_parse_keyword (cd, strp, & mt_cgen_opval_h_spr, & fields->f_drrr); break; - case MS1_OPERAND_FRSR1 : - errmsg = cgen_parse_keyword (cd, strp, & ms1_cgen_opval_h_spr, & fields->f_sr1); + case MT_OPERAND_FRSR1 : + errmsg = cgen_parse_keyword (cd, strp, & mt_cgen_opval_h_spr, & fields->f_sr1); break; - case MS1_OPERAND_FRSR2 : - errmsg = cgen_parse_keyword (cd, strp, & ms1_cgen_opval_h_spr, & fields->f_sr2); + case MT_OPERAND_FRSR2 : + errmsg = cgen_parse_keyword (cd, strp, & mt_cgen_opval_h_spr, & fields->f_sr2); break; - case MS1_OPERAND_ID : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_ID, (unsigned long *) (& fields->f_id)); + case MT_OPERAND_ID : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_ID, (unsigned long *) (& fields->f_id)); break; - case MS1_OPERAND_IMM16 : - errmsg = parse_imm16 (cd, strp, MS1_OPERAND_IMM16, (long *) (& fields->f_imm16s)); + case MT_OPERAND_IMM16 : + errmsg = parse_imm16 (cd, strp, MT_OPERAND_IMM16, (long *) (& fields->f_imm16s)); break; - case MS1_OPERAND_IMM16L : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_IMM16L, (unsigned long *) (& fields->f_imm16l)); + case MT_OPERAND_IMM16L : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_IMM16L, (unsigned long *) (& fields->f_imm16l)); break; - case MS1_OPERAND_IMM16O : - errmsg = parse_imm16 (cd, strp, MS1_OPERAND_IMM16O, (unsigned long *) (& fields->f_imm16s)); + case MT_OPERAND_IMM16O : + errmsg = parse_imm16 (cd, strp, MT_OPERAND_IMM16O, (unsigned long *) (& fields->f_imm16s)); break; - case MS1_OPERAND_IMM16Z : - errmsg = parse_imm16 (cd, strp, MS1_OPERAND_IMM16Z, (unsigned long *) (& fields->f_imm16u)); + case MT_OPERAND_IMM16Z : + errmsg = parse_imm16 (cd, strp, MT_OPERAND_IMM16Z, (unsigned long *) (& fields->f_imm16u)); break; - case MS1_OPERAND_INCAMT : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_INCAMT, (unsigned long *) (& fields->f_incamt)); + case MT_OPERAND_INCAMT : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_INCAMT, (unsigned long *) (& fields->f_incamt)); break; - case MS1_OPERAND_INCR : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_INCR, (unsigned long *) (& fields->f_incr)); + case MT_OPERAND_INCR : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_INCR, (unsigned long *) (& fields->f_incr)); break; - case MS1_OPERAND_LENGTH : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_LENGTH, (unsigned long *) (& fields->f_length)); + case MT_OPERAND_LENGTH : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_LENGTH, (unsigned long *) (& fields->f_length)); break; - case MS1_OPERAND_LOOPSIZE : - errmsg = parse_loopsize (cd, strp, MS1_OPERAND_LOOPSIZE, (unsigned long *) (& fields->f_loopo)); + case MT_OPERAND_LOOPSIZE : + errmsg = parse_loopsize (cd, strp, MT_OPERAND_LOOPSIZE, (unsigned long *) (& fields->f_loopo)); break; - case MS1_OPERAND_MASK : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_MASK, (unsigned long *) (& fields->f_mask)); + case MT_OPERAND_MASK : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_MASK, (unsigned long *) (& fields->f_mask)); break; - case MS1_OPERAND_MASK1 : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_MASK1, (unsigned long *) (& fields->f_mask1)); + case MT_OPERAND_MASK1 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_MASK1, (unsigned long *) (& fields->f_mask1)); break; - case MS1_OPERAND_MODE : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_MODE, (unsigned long *) (& fields->f_mode)); + case MT_OPERAND_MODE : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_MODE, (unsigned long *) (& fields->f_mode)); break; - case MS1_OPERAND_PERM : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_PERM, (unsigned long *) (& fields->f_perm)); + case MT_OPERAND_PERM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_PERM, (unsigned long *) (& fields->f_perm)); break; - case MS1_OPERAND_RBBC : - errmsg = parse_rbbc (cd, strp, MS1_OPERAND_RBBC, (unsigned long *) (& fields->f_rbbc)); + case MT_OPERAND_RBBC : + errmsg = parse_rbbc (cd, strp, MT_OPERAND_RBBC, (unsigned long *) (& fields->f_rbbc)); break; - case MS1_OPERAND_RC : - errmsg = parse_rc (cd, strp, MS1_OPERAND_RC, (unsigned long *) (& fields->f_rc)); + case MT_OPERAND_RC : + errmsg = parse_rc (cd, strp, MT_OPERAND_RC, (unsigned long *) (& fields->f_rc)); break; - case MS1_OPERAND_RC1 : - errmsg = parse_rc (cd, strp, MS1_OPERAND_RC1, (unsigned long *) (& fields->f_rc1)); + case MT_OPERAND_RC1 : + errmsg = parse_rc (cd, strp, MT_OPERAND_RC1, (unsigned long *) (& fields->f_rc1)); break; - case MS1_OPERAND_RC2 : - errmsg = parse_rc (cd, strp, MS1_OPERAND_RC2, (unsigned long *) (& fields->f_rc2)); + case MT_OPERAND_RC2 : + errmsg = parse_rc (cd, strp, MT_OPERAND_RC2, (unsigned long *) (& fields->f_rc2)); break; - case MS1_OPERAND_RC3 : - errmsg = parse_rc (cd, strp, MS1_OPERAND_RC3, (unsigned long *) (& fields->f_rc3)); + case MT_OPERAND_RC3 : + errmsg = parse_rc (cd, strp, MT_OPERAND_RC3, (unsigned long *) (& fields->f_rc3)); break; - case MS1_OPERAND_RCNUM : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_RCNUM, (unsigned long *) (& fields->f_rcnum)); + case MT_OPERAND_RCNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_RCNUM, (unsigned long *) (& fields->f_rcnum)); break; - case MS1_OPERAND_RDA : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_RDA, (unsigned long *) (& fields->f_rda)); + case MT_OPERAND_RDA : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_RDA, (unsigned long *) (& fields->f_rda)); break; - case MS1_OPERAND_ROWNUM : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_ROWNUM, (unsigned long *) (& fields->f_rownum)); + case MT_OPERAND_ROWNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_ROWNUM, (unsigned long *) (& fields->f_rownum)); break; - case MS1_OPERAND_ROWNUM1 : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_ROWNUM1, (unsigned long *) (& fields->f_rownum1)); + case MT_OPERAND_ROWNUM1 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_ROWNUM1, (unsigned long *) (& fields->f_rownum1)); break; - case MS1_OPERAND_ROWNUM2 : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_ROWNUM2, (unsigned long *) (& fields->f_rownum2)); + case MT_OPERAND_ROWNUM2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_ROWNUM2, (unsigned long *) (& fields->f_rownum2)); break; - case MS1_OPERAND_SIZE : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_SIZE, (unsigned long *) (& fields->f_size)); + case MT_OPERAND_SIZE : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_SIZE, (unsigned long *) (& fields->f_size)); break; - case MS1_OPERAND_TYPE : - errmsg = parse_type (cd, strp, MS1_OPERAND_TYPE, (unsigned long *) (& fields->f_type)); + case MT_OPERAND_TYPE : + errmsg = parse_type (cd, strp, MT_OPERAND_TYPE, (unsigned long *) (& fields->f_type)); break; - case MS1_OPERAND_WR : - errmsg = cgen_parse_unsigned_integer (cd, strp, MS1_OPERAND_WR, (unsigned long *) (& fields->f_wr)); + case MT_OPERAND_WR : + errmsg = cgen_parse_unsigned_integer (cd, strp, MT_OPERAND_WR, (unsigned long *) (& fields->f_wr)); break; - case MS1_OPERAND_XMODE : - errmsg = parse_xmode (cd, strp, MS1_OPERAND_XMODE, (unsigned long *) (& fields->f_xmode)); + case MT_OPERAND_XMODE : + errmsg = parse_xmode (cd, strp, MT_OPERAND_XMODE, (unsigned long *) (& fields->f_xmode)); break; default : @@ -598,18 +598,18 @@ ms1_cgen_parse_operand (CGEN_CPU_DESC cd, return errmsg; } -cgen_parse_fn * const ms1_cgen_parse_handlers[] = +cgen_parse_fn * const mt_cgen_parse_handlers[] = { parse_insn_normal, }; void -ms1_cgen_init_asm (CGEN_CPU_DESC cd) +mt_cgen_init_asm (CGEN_CPU_DESC cd) { - ms1_cgen_init_opcode_table (cd); - ms1_cgen_init_ibld_table (cd); - cd->parse_handlers = & ms1_cgen_parse_handlers[0]; - cd->parse_operand = ms1_cgen_parse_operand; + mt_cgen_init_opcode_table (cd); + mt_cgen_init_ibld_table (cd); + cd->parse_handlers = & mt_cgen_parse_handlers[0]; + cd->parse_operand = mt_cgen_parse_operand; } @@ -621,12 +621,12 @@ ms1_cgen_init_asm (CGEN_CPU_DESC cd) opcode) with the pattern '.*' It then compiles the regex and stores it in the opcode, for - later use by ms1_cgen_assemble_insn + later use by mt_cgen_assemble_insn Returns NULL for success, an error message for failure. */ char * -ms1_cgen_build_insn_regex (CGEN_INSN *insn) +mt_cgen_build_insn_regex (CGEN_INSN *insn) { CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); const char *mnem = CGEN_INSN_MNEMONIC (insn); @@ -890,7 +890,7 @@ parse_insn_normal (CGEN_CPU_DESC cd, mind helps keep the design clean. */ const CGEN_INSN * -ms1_cgen_assemble_insn (CGEN_CPU_DESC cd, +mt_cgen_assemble_insn (CGEN_CPU_DESC cd, const char *str, CGEN_FIELDS *fields, CGEN_INSN_BYTES_PTR buf, @@ -921,7 +921,7 @@ ms1_cgen_assemble_insn (CGEN_CPU_DESC cd, /* Not usually needed as unsupported opcodes shouldn't be in the hash lists. */ /* Is this insn supported by the selected cpu? */ - if (! ms1_cgen_insn_supported (cd, insn)) + if (! mt_cgen_insn_supported (cd, insn)) continue; #endif /* If the RELAXED attribute is set, this is an insn that shouldn't be diff --git a/opcodes/ms1-desc.c b/opcodes/mt-desc.c similarity index 63% rename from opcodes/ms1-desc.c rename to opcodes/mt-desc.c index 6dbff2e55..4bda146e5 100644 --- a/opcodes/ms1-desc.c +++ b/opcodes/mt-desc.c @@ -1,4 +1,4 @@ -/* CPU data for ms1. +/* CPU data for mt. THIS FILE IS MACHINE GENERATED WITH CGEN. @@ -28,8 +28,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "ansidecl.h" #include "bfd.h" #include "symcat.h" -#include "ms1-desc.h" -#include "ms1-opc.h" +#include "mt-desc.h" +#include "mt-opc.h" #include "opintl.h" #include "libiberty.h" #include "xregex.h" @@ -55,12 +55,12 @@ static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = { - { "ms1", ISA_MS1 }, + { "mt", ISA_MT }, { "max", ISA_MAX }, { 0, 0 } }; -const CGEN_ATTR_TABLE ms1_cgen_ifield_attr_table[] = +const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[] = { { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, @@ -72,7 +72,7 @@ const CGEN_ATTR_TABLE ms1_cgen_ifield_attr_table[] = { 0, 0, 0 } }; -const CGEN_ATTR_TABLE ms1_cgen_hardware_attr_table[] = +const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[] = { { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, @@ -82,7 +82,7 @@ const CGEN_ATTR_TABLE ms1_cgen_hardware_attr_table[] = { 0, 0, 0 } }; -const CGEN_ATTR_TABLE ms1_cgen_operand_attr_table[] = +const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[] = { { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, @@ -96,7 +96,7 @@ const CGEN_ATTR_TABLE ms1_cgen_operand_attr_table[] = { 0, 0, 0 } }; -const CGEN_ATTR_TABLE ms1_cgen_insn_attr_table[] = +const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[] = { { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "ALIAS", &bool_attr[0], &bool_attr[0] }, @@ -125,34 +125,34 @@ const CGEN_ATTR_TABLE ms1_cgen_insn_attr_table[] = /* Instruction set variants. */ -static const CGEN_ISA ms1_cgen_isa_table[] = { - { "ms1", 32, 32, 32, 32 }, +static const CGEN_ISA mt_cgen_isa_table[] = { + { "mt", 32, 32, 32, 32 }, { 0, 0, 0, 0, 0 } }; /* Machine variants. */ -static const CGEN_MACH ms1_cgen_mach_table[] = { +static const CGEN_MACH mt_cgen_mach_table[] = { { "ms1", "ms1", MACH_MS1, 0 }, { "ms1-003", "ms1-003", MACH_MS1_003, 0 }, { "ms2", "ms2", MACH_MS2, 0 }, { 0, 0, 0, 0 } }; -static CGEN_KEYWORD_ENTRY ms1_cgen_opval_msys_syms_entries[] = +static CGEN_KEYWORD_ENTRY mt_cgen_opval_msys_syms_entries[] = { { "DUP", 1, {0, {{{0, 0}}}}, 0, 0 }, { "XX", 0, {0, {{{0, 0}}}}, 0, 0 } }; -CGEN_KEYWORD ms1_cgen_opval_msys_syms = +CGEN_KEYWORD mt_cgen_opval_msys_syms = { - & ms1_cgen_opval_msys_syms_entries[0], + & mt_cgen_opval_msys_syms_entries[0], 2, 0, 0, 0, 0, "" }; -static CGEN_KEYWORD_ENTRY ms1_cgen_opval_h_spr_entries[] = +static CGEN_KEYWORD_ENTRY mt_cgen_opval_h_spr_entries[] = { { "R0", 0, {0, {{{0, 0}}}}, 0, 0 }, { "R1", 1, {0, {{{0, 0}}}}, 0, 0 }, @@ -176,9 +176,9 @@ static CGEN_KEYWORD_ENTRY ms1_cgen_opval_h_spr_entries[] = { "ira", 15, {0, {{{0, 0}}}}, 0, 0 } }; -CGEN_KEYWORD ms1_cgen_opval_h_spr = +CGEN_KEYWORD mt_cgen_opval_h_spr = { - & ms1_cgen_opval_h_spr_entries[0], + & mt_cgen_opval_h_spr_entries[0], 20, 0, 0, 0, 0, "" }; @@ -192,14 +192,14 @@ CGEN_KEYWORD ms1_cgen_opval_h_spr = #define A(a) (1 << CGEN_HW_/**/a) #endif -const CGEN_HW_ENTRY ms1_cgen_hw_table[] = +const CGEN_HW_ENTRY mt_cgen_hw_table[] = { { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<machs; - const CGEN_HW_ENTRY *init = & ms1_cgen_hw_table[0]; + const CGEN_HW_ENTRY *init = & mt_cgen_hw_table[0]; /* MAX_HW is only an upper bound on the number of selected entries. However each entry is indexed by it's enum so there can be holes in the table. */ @@ -1042,22 +1042,22 @@ build_hw_table (CGEN_CPU_TABLE *cd) cd->hw_table.num_entries = MAX_HW; } -/* Subroutine of ms1_cgen_cpu_open to build the hardware table. */ +/* Subroutine of mt_cgen_cpu_open to build the hardware table. */ static void build_ifield_table (CGEN_CPU_TABLE *cd) { - cd->ifld_table = & ms1_cgen_ifld_table[0]; + cd->ifld_table = & mt_cgen_ifld_table[0]; } -/* Subroutine of ms1_cgen_cpu_open to build the hardware table. */ +/* Subroutine of mt_cgen_cpu_open to build the hardware table. */ static void build_operand_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; - const CGEN_OPERAND *init = & ms1_cgen_operand_table[0]; + const CGEN_OPERAND *init = & mt_cgen_operand_table[0]; /* MAX_OPERANDS is only an upper bound on the number of selected entries. However each entry is indexed by it's enum so there can be holes in the table. */ @@ -1075,7 +1075,7 @@ build_operand_table (CGEN_CPU_TABLE *cd) cd->operand_table.num_entries = MAX_OPERANDS; } -/* Subroutine of ms1_cgen_cpu_open to build the hardware table. +/* Subroutine of mt_cgen_cpu_open to build the hardware table. ??? This could leave out insns not supported by the specified mach/isa, but that would cause errors like "foo only supported by bar" to become "unknown insn", so for now we include all insns and require the app to @@ -1087,7 +1087,7 @@ static void build_insn_table (CGEN_CPU_TABLE *cd) { int i; - const CGEN_IBASE *ib = & ms1_cgen_insn_table[0]; + const CGEN_IBASE *ib = & mt_cgen_insn_table[0]; CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); @@ -1098,10 +1098,10 @@ build_insn_table (CGEN_CPU_TABLE *cd) cd->insn_table.num_init_entries = MAX_INSNS; } -/* Subroutine of ms1_cgen_cpu_open to rebuild the tables. */ +/* Subroutine of mt_cgen_cpu_open to rebuild the tables. */ static void -ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +mt_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; CGEN_BITSET *isas = cd->isas; @@ -1118,7 +1118,7 @@ ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) for (i = 0; i < MAX_ISAS; ++i) if (cgen_bitset_contains (isas, i)) { - const CGEN_ISA *isa = & ms1_cgen_isa_table[i]; + const CGEN_ISA *isa = & mt_cgen_isa_table[i]; /* Default insn sizes of all selected isas must be equal or we set the result to 0, meaning "unknown". */ @@ -1149,13 +1149,13 @@ ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) for (i = 0; i < MAX_MACHS; ++i) if (((1 << i) & machs) != 0) { - const CGEN_MACH *mach = & ms1_cgen_mach_table[i]; + const CGEN_MACH *mach = & mt_cgen_mach_table[i]; if (mach->insn_chunk_bitsize != 0) { if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) { - fprintf (stderr, "ms1_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + fprintf (stderr, "mt_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); abort (); } @@ -1197,7 +1197,7 @@ ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) K&R will no longer be supported - e.g. GDB is currently trying this. */ CGEN_CPU_DESC -ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +mt_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); static int init_p; @@ -1229,7 +1229,7 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) { const char *name = va_arg (ap, const char *); const CGEN_MACH *mach = - lookup_mach_via_bfd_name (ms1_cgen_mach_table, name); + lookup_mach_via_bfd_name (mt_cgen_mach_table, name); machs |= 1 << mach->num; break; @@ -1238,7 +1238,7 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) endian = va_arg (ap, enum cgen_endian); break; default : - fprintf (stderr, "ms1_cgen_cpu_open: unsupported argument `%d'\n", + fprintf (stderr, "mt_cgen_cpu_open: unsupported argument `%d'\n", arg_type); abort (); /* ??? return NULL? */ } @@ -1254,7 +1254,7 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) if (endian == CGEN_ENDIAN_UNKNOWN) { /* ??? If target has only one, could have a default. */ - fprintf (stderr, "ms1_cgen_cpu_open: no endianness specified\n"); + fprintf (stderr, "mt_cgen_cpu_open: no endianness specified\n"); abort (); } @@ -1268,8 +1268,8 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) cd->insn_endian = endian; /* Table (re)builder. */ - cd->rebuild_tables = ms1_cgen_rebuild_tables; - ms1_cgen_rebuild_tables (cd); + cd->rebuild_tables = mt_cgen_rebuild_tables; + mt_cgen_rebuild_tables (cd); /* Default to not allowing signed overflow. */ cd->signed_overflow_ok_p = 0; @@ -1277,13 +1277,13 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) return (CGEN_CPU_DESC) cd; } -/* Cover fn to ms1_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. +/* Cover fn to mt_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. MACH_NAME is the bfd name of the mach. */ CGEN_CPU_DESC -ms1_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +mt_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) { - return ms1_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + return mt_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, CGEN_CPU_OPEN_ENDIAN, endian, CGEN_CPU_OPEN_END); } @@ -1294,7 +1294,7 @@ ms1_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) place as some simulator ports use this but they don't use libopcodes. */ void -ms1_cgen_cpu_close (CGEN_CPU_DESC cd) +mt_cgen_cpu_close (CGEN_CPU_DESC cd) { unsigned int i; const CGEN_INSN *insns; diff --git a/opcodes/ms1-desc.h b/opcodes/mt-desc.h similarity index 78% rename from opcodes/ms1-desc.h rename to opcodes/mt-desc.h index 909b32388..c4b49fd87 100644 --- a/opcodes/ms1-desc.h +++ b/opcodes/mt-desc.h @@ -1,4 +1,4 @@ -/* CPU data header for ms1. +/* CPU data header for mt. THIS FILE IS MACHINE GENERATED WITH CGEN. @@ -22,18 +22,18 @@ with this program; if not, write to the Free Software Foundation, Inc., */ -#ifndef MS1_CPU_H -#define MS1_CPU_H +#ifndef MT_CPU_H +#define MT_CPU_H #include "opcode/cgen-bitset.h" -#define CGEN_ARCH ms1 +#define CGEN_ARCH mt -/* Given symbol S, return ms1_cgen_. */ +/* Given symbol S, return mt_cgen_. */ #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -#define CGEN_SYM(s) ms1##_cgen_##s +#define CGEN_SYM(s) mt##_cgen_##s #else -#define CGEN_SYM(s) ms1/**/_cgen_/**/s +#define CGEN_SYM(s) mt/**/_cgen_/**/s #endif @@ -114,7 +114,7 @@ typedef enum mach_attr { /* Enum declaration for instruction set selection. */ typedef enum isa_attr { - ISA_MS1, ISA_MAX + ISA_MT, ISA_MAX } ISA_ATTR; /* Number of architecture variants. */ @@ -144,31 +144,31 @@ typedef enum cgen_ifld_attr { #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) -/* Enum declaration for ms1 ifield types. */ +/* Enum declaration for mt ifield types. */ typedef enum ifield_type { - MS1_F_NIL, MS1_F_ANYOF, MS1_F_MSYS, MS1_F_OPC - , MS1_F_IMM, MS1_F_UU24, MS1_F_SR1, MS1_F_SR2 - , MS1_F_DR, MS1_F_DRRR, MS1_F_IMM16U, MS1_F_IMM16S - , MS1_F_IMM16A, MS1_F_UU4A, MS1_F_UU4B, MS1_F_UU12 - , MS1_F_UU8, MS1_F_UU16, MS1_F_UU1, MS1_F_MSOPC - , MS1_F_UU_26_25, MS1_F_MASK, MS1_F_BANKADDR, MS1_F_RDA - , MS1_F_UU_2_25, MS1_F_RBBC, MS1_F_PERM, MS1_F_MODE - , MS1_F_UU_1_24, MS1_F_WR, MS1_F_FBINCR, MS1_F_UU_2_23 - , MS1_F_XMODE, MS1_F_A23, MS1_F_MASK1, MS1_F_CR - , MS1_F_TYPE, MS1_F_INCAMT, MS1_F_CBS, MS1_F_UU_1_19 - , MS1_F_BALL, MS1_F_COLNUM, MS1_F_BRC, MS1_F_INCR - , MS1_F_FBDISP, MS1_F_UU_4_15, MS1_F_LENGTH, MS1_F_UU_1_15 - , MS1_F_RC, MS1_F_RCNUM, MS1_F_ROWNUM, MS1_F_CBX - , MS1_F_ID, MS1_F_SIZE, MS1_F_ROWNUM1, MS1_F_UU_3_11 - , MS1_F_RC1, MS1_F_CCB, MS1_F_CBRB, MS1_F_CDB - , MS1_F_ROWNUM2, MS1_F_CELL, MS1_F_UU_3_9, MS1_F_CONTNUM - , MS1_F_UU_1_6, MS1_F_DUP, MS1_F_RC2, MS1_F_CTXDISP - , MS1_F_IMM16L, MS1_F_LOOPO, MS1_F_CB1SEL, MS1_F_CB2SEL - , MS1_F_CB1INCR, MS1_F_CB2INCR, MS1_F_RC3, MS1_F_MSYSFRSR2 - , MS1_F_BRC2, MS1_F_BALL2, MS1_F_MAX + MT_F_NIL, MT_F_ANYOF, MT_F_MSYS, MT_F_OPC + , MT_F_IMM, MT_F_UU24, MT_F_SR1, MT_F_SR2 + , MT_F_DR, MT_F_DRRR, MT_F_IMM16U, MT_F_IMM16S + , MT_F_IMM16A, MT_F_UU4A, MT_F_UU4B, MT_F_UU12 + , MT_F_UU8, MT_F_UU16, MT_F_UU1, MT_F_MSOPC + , MT_F_UU_26_25, MT_F_MASK, MT_F_BANKADDR, MT_F_RDA + , MT_F_UU_2_25, MT_F_RBBC, MT_F_PERM, MT_F_MODE + , MT_F_UU_1_24, MT_F_WR, MT_F_FBINCR, MT_F_UU_2_23 + , MT_F_XMODE, MT_F_A23, MT_F_MASK1, MT_F_CR + , MT_F_TYPE, MT_F_INCAMT, MT_F_CBS, MT_F_UU_1_19 + , MT_F_BALL, MT_F_COLNUM, MT_F_BRC, MT_F_INCR + , MT_F_FBDISP, MT_F_UU_4_15, MT_F_LENGTH, MT_F_UU_1_15 + , MT_F_RC, MT_F_RCNUM, MT_F_ROWNUM, MT_F_CBX + , MT_F_ID, MT_F_SIZE, MT_F_ROWNUM1, MT_F_UU_3_11 + , MT_F_RC1, MT_F_CCB, MT_F_CBRB, MT_F_CDB + , MT_F_ROWNUM2, MT_F_CELL, MT_F_UU_3_9, MT_F_CONTNUM + , MT_F_UU_1_6, MT_F_DUP, MT_F_RC2, MT_F_CTXDISP + , MT_F_IMM16L, MT_F_LOOPO, MT_F_CB1SEL, MT_F_CB2SEL + , MT_F_CB1INCR, MT_F_CB2INCR, MT_F_RC3, MT_F_MSYSFRSR2 + , MT_F_BRC2, MT_F_BALL2, MT_F_MAX } IFIELD_TYPE; -#define MAX_IFLD ((int) MS1_F_MAX) +#define MAX_IFLD ((int) MT_F_MAX) /* Hardware attribute indices. */ @@ -188,7 +188,7 @@ typedef enum cgen_hw_attr { #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) -/* Enum declaration for ms1 hardware types. */ +/* Enum declaration for mt hardware types. */ typedef enum cgen_hw_type { HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR , HW_H_IADDR, HW_H_SPR, HW_H_PC, HW_MAX @@ -219,22 +219,22 @@ typedef enum cgen_operand_attr { #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) -/* Enum declaration for ms1 operand types. */ +/* Enum declaration for mt operand types. */ typedef enum cgen_operand_type { - MS1_OPERAND_PC, MS1_OPERAND_FRSR1, MS1_OPERAND_FRSR2, MS1_OPERAND_FRDR - , MS1_OPERAND_FRDRRR, MS1_OPERAND_IMM16, MS1_OPERAND_IMM16Z, MS1_OPERAND_IMM16O - , MS1_OPERAND_RC, MS1_OPERAND_RCNUM, MS1_OPERAND_CONTNUM, MS1_OPERAND_RBBC - , MS1_OPERAND_COLNUM, MS1_OPERAND_ROWNUM, MS1_OPERAND_ROWNUM1, MS1_OPERAND_ROWNUM2 - , MS1_OPERAND_RC1, MS1_OPERAND_RC2, MS1_OPERAND_CBRB, MS1_OPERAND_CELL - , MS1_OPERAND_DUP, MS1_OPERAND_CTXDISP, MS1_OPERAND_FBDISP, MS1_OPERAND_TYPE - , MS1_OPERAND_MASK, MS1_OPERAND_BANKADDR, MS1_OPERAND_INCAMT, MS1_OPERAND_XMODE - , MS1_OPERAND_MASK1, MS1_OPERAND_BALL, MS1_OPERAND_BRC, MS1_OPERAND_RDA - , MS1_OPERAND_WR, MS1_OPERAND_BALL2, MS1_OPERAND_BRC2, MS1_OPERAND_PERM - , MS1_OPERAND_A23, MS1_OPERAND_CR, MS1_OPERAND_CBS, MS1_OPERAND_INCR - , MS1_OPERAND_LENGTH, MS1_OPERAND_CBX, MS1_OPERAND_CCB, MS1_OPERAND_CDB - , MS1_OPERAND_MODE, MS1_OPERAND_ID, MS1_OPERAND_SIZE, MS1_OPERAND_FBINCR - , MS1_OPERAND_LOOPSIZE, MS1_OPERAND_IMM16L, MS1_OPERAND_RC3, MS1_OPERAND_CB1SEL - , MS1_OPERAND_CB2SEL, MS1_OPERAND_CB1INCR, MS1_OPERAND_CB2INCR, MS1_OPERAND_MAX + MT_OPERAND_PC, MT_OPERAND_FRSR1, MT_OPERAND_FRSR2, MT_OPERAND_FRDR + , MT_OPERAND_FRDRRR, MT_OPERAND_IMM16, MT_OPERAND_IMM16Z, MT_OPERAND_IMM16O + , MT_OPERAND_RC, MT_OPERAND_RCNUM, MT_OPERAND_CONTNUM, MT_OPERAND_RBBC + , MT_OPERAND_COLNUM, MT_OPERAND_ROWNUM, MT_OPERAND_ROWNUM1, MT_OPERAND_ROWNUM2 + , MT_OPERAND_RC1, MT_OPERAND_RC2, MT_OPERAND_CBRB, MT_OPERAND_CELL + , MT_OPERAND_DUP, MT_OPERAND_CTXDISP, MT_OPERAND_FBDISP, MT_OPERAND_TYPE + , MT_OPERAND_MASK, MT_OPERAND_BANKADDR, MT_OPERAND_INCAMT, MT_OPERAND_XMODE + , MT_OPERAND_MASK1, MT_OPERAND_BALL, MT_OPERAND_BRC, MT_OPERAND_RDA + , MT_OPERAND_WR, MT_OPERAND_BALL2, MT_OPERAND_BRC2, MT_OPERAND_PERM + , MT_OPERAND_A23, MT_OPERAND_CR, MT_OPERAND_CBS, MT_OPERAND_INCR + , MT_OPERAND_LENGTH, MT_OPERAND_CBX, MT_OPERAND_CCB, MT_OPERAND_CDB + , MT_OPERAND_MODE, MT_OPERAND_ID, MT_OPERAND_SIZE, MT_OPERAND_FBINCR + , MT_OPERAND_LOOPSIZE, MT_OPERAND_IMM16L, MT_OPERAND_RC3, MT_OPERAND_CB1SEL + , MT_OPERAND_CB2SEL, MT_OPERAND_CB1INCR, MT_OPERAND_CB2INCR, MT_OPERAND_MAX } CGEN_OPERAND_TYPE; /* Number of operands types. */ @@ -286,20 +286,20 @@ typedef enum cgen_insn_attr { /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" -extern const struct cgen_ifld ms1_cgen_ifld_table[]; +extern const struct cgen_ifld mt_cgen_ifld_table[]; /* Attributes. */ -extern const CGEN_ATTR_TABLE ms1_cgen_hardware_attr_table[]; -extern const CGEN_ATTR_TABLE ms1_cgen_ifield_attr_table[]; -extern const CGEN_ATTR_TABLE ms1_cgen_operand_attr_table[]; -extern const CGEN_ATTR_TABLE ms1_cgen_insn_attr_table[]; +extern const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[]; /* Hardware decls. */ -extern CGEN_KEYWORD ms1_cgen_opval_h_spr; +extern CGEN_KEYWORD mt_cgen_opval_h_spr; -extern const CGEN_HW_ENTRY ms1_cgen_hw_table[]; +extern const CGEN_HW_ENTRY mt_cgen_hw_table[]; -#endif /* MS1_CPU_H */ +#endif /* MT_CPU_H */ diff --git a/opcodes/ms1-dis.c b/opcodes/mt-dis.c similarity index 88% rename from opcodes/ms1-dis.c rename to opcodes/mt-dis.c index bc020de16..25bd00001 100644 --- a/opcodes/ms1-dis.c +++ b/opcodes/mt-dis.c @@ -33,8 +33,8 @@ #include "bfd.h" #include "symcat.h" #include "libiberty.h" -#include "ms1-desc.h" -#include "ms1-opc.h" +#include "mt-desc.h" +#include "mt-opc.h" #include "opintl.h" /* Default text to print if an instruction isn't recognized. */ @@ -91,7 +91,7 @@ print_pcrel (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, /* -- */ -void ms1_cgen_print_operand +void mt_cgen_print_operand (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); /* Main entry point for printing operands. @@ -110,7 +110,7 @@ void ms1_cgen_print_operand the handlers. */ void -ms1_cgen_print_operand (CGEN_CPU_DESC cd, +mt_cgen_print_operand (CGEN_CPU_DESC cd, int opindex, void * xinfo, CGEN_FIELDS *fields, @@ -122,166 +122,166 @@ ms1_cgen_print_operand (CGEN_CPU_DESC cd, switch (opindex) { - case MS1_OPERAND_A23 : + case MT_OPERAND_A23 : print_dollarhex (cd, info, fields->f_a23, 0, pc, length); break; - case MS1_OPERAND_BALL : + case MT_OPERAND_BALL : print_dollarhex (cd, info, fields->f_ball, 0, pc, length); break; - case MS1_OPERAND_BALL2 : + case MT_OPERAND_BALL2 : print_dollarhex (cd, info, fields->f_ball2, 0, pc, length); break; - case MS1_OPERAND_BANKADDR : + case MT_OPERAND_BANKADDR : print_dollarhex (cd, info, fields->f_bankaddr, 0, pc, length); break; - case MS1_OPERAND_BRC : + case MT_OPERAND_BRC : print_dollarhex (cd, info, fields->f_brc, 0, pc, length); break; - case MS1_OPERAND_BRC2 : + case MT_OPERAND_BRC2 : print_dollarhex (cd, info, fields->f_brc2, 0, pc, length); break; - case MS1_OPERAND_CB1INCR : + case MT_OPERAND_CB1INCR : print_dollarhex (cd, info, fields->f_cb1incr, 0|(1<f_cb1sel, 0, pc, length); break; - case MS1_OPERAND_CB2INCR : + case MT_OPERAND_CB2INCR : print_dollarhex (cd, info, fields->f_cb2incr, 0|(1<f_cb2sel, 0, pc, length); break; - case MS1_OPERAND_CBRB : + case MT_OPERAND_CBRB : print_dollarhex (cd, info, fields->f_cbrb, 0, pc, length); break; - case MS1_OPERAND_CBS : + case MT_OPERAND_CBS : print_dollarhex (cd, info, fields->f_cbs, 0, pc, length); break; - case MS1_OPERAND_CBX : + case MT_OPERAND_CBX : print_dollarhex (cd, info, fields->f_cbx, 0, pc, length); break; - case MS1_OPERAND_CCB : + case MT_OPERAND_CCB : print_dollarhex (cd, info, fields->f_ccb, 0, pc, length); break; - case MS1_OPERAND_CDB : + case MT_OPERAND_CDB : print_dollarhex (cd, info, fields->f_cdb, 0, pc, length); break; - case MS1_OPERAND_CELL : + case MT_OPERAND_CELL : print_dollarhex (cd, info, fields->f_cell, 0, pc, length); break; - case MS1_OPERAND_COLNUM : + case MT_OPERAND_COLNUM : print_dollarhex (cd, info, fields->f_colnum, 0, pc, length); break; - case MS1_OPERAND_CONTNUM : + case MT_OPERAND_CONTNUM : print_dollarhex (cd, info, fields->f_contnum, 0, pc, length); break; - case MS1_OPERAND_CR : + case MT_OPERAND_CR : print_dollarhex (cd, info, fields->f_cr, 0, pc, length); break; - case MS1_OPERAND_CTXDISP : + case MT_OPERAND_CTXDISP : print_dollarhex (cd, info, fields->f_ctxdisp, 0, pc, length); break; - case MS1_OPERAND_DUP : + case MT_OPERAND_DUP : print_dollarhex (cd, info, fields->f_dup, 0, pc, length); break; - case MS1_OPERAND_FBDISP : + case MT_OPERAND_FBDISP : print_dollarhex (cd, info, fields->f_fbdisp, 0, pc, length); break; - case MS1_OPERAND_FBINCR : + case MT_OPERAND_FBINCR : print_dollarhex (cd, info, fields->f_fbincr, 0, pc, length); break; - case MS1_OPERAND_FRDR : - print_keyword (cd, info, & ms1_cgen_opval_h_spr, fields->f_dr, 0|(1<f_dr, 0|(1<f_drrr, 0|(1<f_drrr, 0|(1<f_sr1, 0|(1<f_sr1, 0|(1<f_sr2, 0|(1<f_sr2, 0|(1<f_id, 0, pc, length); break; - case MS1_OPERAND_IMM16 : + case MT_OPERAND_IMM16 : print_dollarhex (cd, info, fields->f_imm16s, 0|(1<f_imm16l, 0, pc, length); break; - case MS1_OPERAND_IMM16O : + case MT_OPERAND_IMM16O : print_pcrel (cd, info, fields->f_imm16s, 0|(1<f_imm16u, 0, pc, length); break; - case MS1_OPERAND_INCAMT : + case MT_OPERAND_INCAMT : print_dollarhex (cd, info, fields->f_incamt, 0, pc, length); break; - case MS1_OPERAND_INCR : + case MT_OPERAND_INCR : print_dollarhex (cd, info, fields->f_incr, 0, pc, length); break; - case MS1_OPERAND_LENGTH : + case MT_OPERAND_LENGTH : print_dollarhex (cd, info, fields->f_length, 0, pc, length); break; - case MS1_OPERAND_LOOPSIZE : + case MT_OPERAND_LOOPSIZE : print_pcrel (cd, info, fields->f_loopo, 0|(1<f_mask, 0, pc, length); break; - case MS1_OPERAND_MASK1 : + case MT_OPERAND_MASK1 : print_dollarhex (cd, info, fields->f_mask1, 0, pc, length); break; - case MS1_OPERAND_MODE : + case MT_OPERAND_MODE : print_dollarhex (cd, info, fields->f_mode, 0, pc, length); break; - case MS1_OPERAND_PERM : + case MT_OPERAND_PERM : print_dollarhex (cd, info, fields->f_perm, 0, pc, length); break; - case MS1_OPERAND_RBBC : + case MT_OPERAND_RBBC : print_dollarhex (cd, info, fields->f_rbbc, 0, pc, length); break; - case MS1_OPERAND_RC : + case MT_OPERAND_RC : print_dollarhex (cd, info, fields->f_rc, 0, pc, length); break; - case MS1_OPERAND_RC1 : + case MT_OPERAND_RC1 : print_dollarhex (cd, info, fields->f_rc1, 0, pc, length); break; - case MS1_OPERAND_RC2 : + case MT_OPERAND_RC2 : print_dollarhex (cd, info, fields->f_rc2, 0, pc, length); break; - case MS1_OPERAND_RC3 : + case MT_OPERAND_RC3 : print_dollarhex (cd, info, fields->f_rc3, 0, pc, length); break; - case MS1_OPERAND_RCNUM : + case MT_OPERAND_RCNUM : print_dollarhex (cd, info, fields->f_rcnum, 0, pc, length); break; - case MS1_OPERAND_RDA : + case MT_OPERAND_RDA : print_dollarhex (cd, info, fields->f_rda, 0, pc, length); break; - case MS1_OPERAND_ROWNUM : + case MT_OPERAND_ROWNUM : print_dollarhex (cd, info, fields->f_rownum, 0, pc, length); break; - case MS1_OPERAND_ROWNUM1 : + case MT_OPERAND_ROWNUM1 : print_dollarhex (cd, info, fields->f_rownum1, 0, pc, length); break; - case MS1_OPERAND_ROWNUM2 : + case MT_OPERAND_ROWNUM2 : print_dollarhex (cd, info, fields->f_rownum2, 0, pc, length); break; - case MS1_OPERAND_SIZE : + case MT_OPERAND_SIZE : print_dollarhex (cd, info, fields->f_size, 0, pc, length); break; - case MS1_OPERAND_TYPE : + case MT_OPERAND_TYPE : print_dollarhex (cd, info, fields->f_type, 0, pc, length); break; - case MS1_OPERAND_WR : + case MT_OPERAND_WR : print_dollarhex (cd, info, fields->f_wr, 0, pc, length); break; - case MS1_OPERAND_XMODE : + case MT_OPERAND_XMODE : print_dollarhex (cd, info, fields->f_xmode, 0, pc, length); break; @@ -293,19 +293,19 @@ ms1_cgen_print_operand (CGEN_CPU_DESC cd, } } -cgen_print_fn * const ms1_cgen_print_handlers[] = +cgen_print_fn * const mt_cgen_print_handlers[] = { print_insn_normal, }; void -ms1_cgen_init_dis (CGEN_CPU_DESC cd) +mt_cgen_init_dis (CGEN_CPU_DESC cd) { - ms1_cgen_init_opcode_table (cd); - ms1_cgen_init_ibld_table (cd); - cd->print_handlers = & ms1_cgen_print_handlers[0]; - cd->print_operand = ms1_cgen_print_operand; + mt_cgen_init_opcode_table (cd); + mt_cgen_init_ibld_table (cd); + cd->print_handlers = & mt_cgen_print_handlers[0]; + cd->print_operand = mt_cgen_print_operand; } @@ -415,7 +415,7 @@ print_insn_normal (CGEN_CPU_DESC cd, } /* We have an operand. */ - ms1_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + mt_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, fields, CGEN_INSN_ATTRS (insn), pc, length); } } @@ -494,7 +494,7 @@ print_insn (CGEN_CPU_DESC cd, #ifdef CGEN_VALIDATE_INSN_SUPPORTED /* Not needed as insn shouldn't be in hash lists if not supported. */ /* Supported by this cpu? */ - if (! ms1_cgen_insn_supported (cd, insn)) + if (! mt_cgen_insn_supported (cd, insn)) { insn_list = CGEN_DIS_NEXT_INSN (insn_list); continue; @@ -605,7 +605,7 @@ typedef struct cpu_desc_list } cpu_desc_list; int -print_insn_ms1 (bfd_vma pc, disassemble_info *info) +print_insn_mt (bfd_vma pc, disassemble_info *info) { static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; @@ -623,7 +623,7 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info) /* ??? gdb will set mach but leave the architecture as "unknown" */ #ifndef CGEN_BFD_ARCH -#define CGEN_BFD_ARCH bfd_arch_ms1 +#define CGEN_BFD_ARCH bfd_arch_mt #endif arch = info->arch; if (arch == bfd_arch_unknown) @@ -684,7 +684,7 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info) prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; - cd = ms1_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + cd = mt_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, CGEN_CPU_OPEN_BFDMACH, mach_name, CGEN_CPU_OPEN_ENDIAN, prev_endian, CGEN_CPU_OPEN_END); @@ -700,7 +700,7 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info) cl->next = cd_list; cd_list = cl; - ms1_cgen_init_dis (cd); + mt_cgen_init_dis (cd); } /* We try to have as much common code as possible. diff --git a/opcodes/ms1-ibld.c b/opcodes/mt-ibld.c similarity index 79% rename from opcodes/ms1-ibld.c rename to opcodes/mt-ibld.c index 4640211ff..6778ac4ce 100644 --- a/opcodes/ms1-ibld.c +++ b/opcodes/mt-ibld.c @@ -1,4 +1,4 @@ -/* Instruction building/extraction support for ms1. -*- C -*- +/* Instruction building/extraction support for mt. -*- C -*- THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. - the resultant file is machine generated, cgen-ibld.in isn't @@ -31,8 +31,8 @@ #include "dis-asm.h" #include "bfd.h" #include "symcat.h" -#include "ms1-desc.h" -#include "ms1-opc.h" +#include "mt-desc.h" +#include "mt-opc.h" #include "opintl.h" #include "safe-ctype.h" @@ -529,7 +529,7 @@ extract_insn_normal (CGEN_CPU_DESC cd, /* Machine generated code added here. */ -const char * ms1_cgen_insert_operand +const char * mt_cgen_insert_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); /* Main entry point for operand insertion. @@ -547,7 +547,7 @@ const char * ms1_cgen_insert_operand resolved during parsing. */ const char * -ms1_cgen_insert_operand (CGEN_CPU_DESC cd, +mt_cgen_insert_operand (CGEN_CPU_DESC cd, int opindex, CGEN_FIELDS * fields, CGEN_INSN_BYTES_PTR buffer, @@ -558,178 +558,178 @@ ms1_cgen_insert_operand (CGEN_CPU_DESC cd, switch (opindex) { - case MS1_OPERAND_A23 : + case MT_OPERAND_A23 : errmsg = insert_normal (cd, fields->f_a23, 0, 0, 23, 1, 32, total_length, buffer); break; - case MS1_OPERAND_BALL : + case MT_OPERAND_BALL : errmsg = insert_normal (cd, fields->f_ball, 0, 0, 19, 1, 32, total_length, buffer); break; - case MS1_OPERAND_BALL2 : + case MT_OPERAND_BALL2 : errmsg = insert_normal (cd, fields->f_ball2, 0, 0, 15, 1, 32, total_length, buffer); break; - case MS1_OPERAND_BANKADDR : + case MT_OPERAND_BANKADDR : errmsg = insert_normal (cd, fields->f_bankaddr, 0, 0, 25, 13, 32, total_length, buffer); break; - case MS1_OPERAND_BRC : + case MT_OPERAND_BRC : errmsg = insert_normal (cd, fields->f_brc, 0, 0, 18, 3, 32, total_length, buffer); break; - case MS1_OPERAND_BRC2 : + case MT_OPERAND_BRC2 : errmsg = insert_normal (cd, fields->f_brc2, 0, 0, 14, 3, 32, total_length, buffer); break; - case MS1_OPERAND_CB1INCR : + case MT_OPERAND_CB1INCR : errmsg = insert_normal (cd, fields->f_cb1incr, 0|(1<f_cb1sel, 0, 0, 25, 3, 32, total_length, buffer); break; - case MS1_OPERAND_CB2INCR : + case MT_OPERAND_CB2INCR : errmsg = insert_normal (cd, fields->f_cb2incr, 0|(1<f_cb2sel, 0, 0, 22, 3, 32, total_length, buffer); break; - case MS1_OPERAND_CBRB : + case MT_OPERAND_CBRB : errmsg = insert_normal (cd, fields->f_cbrb, 0, 0, 10, 1, 32, total_length, buffer); break; - case MS1_OPERAND_CBS : + case MT_OPERAND_CBS : errmsg = insert_normal (cd, fields->f_cbs, 0, 0, 19, 2, 32, total_length, buffer); break; - case MS1_OPERAND_CBX : + case MT_OPERAND_CBX : errmsg = insert_normal (cd, fields->f_cbx, 0, 0, 14, 3, 32, total_length, buffer); break; - case MS1_OPERAND_CCB : + case MT_OPERAND_CCB : errmsg = insert_normal (cd, fields->f_ccb, 0, 0, 11, 1, 32, total_length, buffer); break; - case MS1_OPERAND_CDB : + case MT_OPERAND_CDB : errmsg = insert_normal (cd, fields->f_cdb, 0, 0, 10, 1, 32, total_length, buffer); break; - case MS1_OPERAND_CELL : + case MT_OPERAND_CELL : errmsg = insert_normal (cd, fields->f_cell, 0, 0, 9, 3, 32, total_length, buffer); break; - case MS1_OPERAND_COLNUM : + case MT_OPERAND_COLNUM : errmsg = insert_normal (cd, fields->f_colnum, 0, 0, 18, 3, 32, total_length, buffer); break; - case MS1_OPERAND_CONTNUM : + case MT_OPERAND_CONTNUM : errmsg = insert_normal (cd, fields->f_contnum, 0, 0, 8, 9, 32, total_length, buffer); break; - case MS1_OPERAND_CR : + case MT_OPERAND_CR : errmsg = insert_normal (cd, fields->f_cr, 0, 0, 22, 3, 32, total_length, buffer); break; - case MS1_OPERAND_CTXDISP : + case MT_OPERAND_CTXDISP : errmsg = insert_normal (cd, fields->f_ctxdisp, 0, 0, 5, 6, 32, total_length, buffer); break; - case MS1_OPERAND_DUP : + case MT_OPERAND_DUP : errmsg = insert_normal (cd, fields->f_dup, 0, 0, 6, 1, 32, total_length, buffer); break; - case MS1_OPERAND_FBDISP : + case MT_OPERAND_FBDISP : errmsg = insert_normal (cd, fields->f_fbdisp, 0, 0, 15, 6, 32, total_length, buffer); break; - case MS1_OPERAND_FBINCR : + case MT_OPERAND_FBINCR : errmsg = insert_normal (cd, fields->f_fbincr, 0, 0, 23, 4, 32, total_length, buffer); break; - case MS1_OPERAND_FRDR : + case MT_OPERAND_FRDR : errmsg = insert_normal (cd, fields->f_dr, 0|(1<f_drrr, 0|(1<f_sr1, 0|(1<f_sr2, 0|(1<f_id, 0, 0, 14, 1, 32, total_length, buffer); break; - case MS1_OPERAND_IMM16 : + case MT_OPERAND_IMM16 : { long value = fields->f_imm16s; value = ((value) + (0)); errmsg = insert_normal (cd, value, 0|(1<f_imm16l, 0, 0, 23, 16, 32, total_length, buffer); break; - case MS1_OPERAND_IMM16O : + case MT_OPERAND_IMM16O : { long value = fields->f_imm16s; value = ((value) + (0)); errmsg = insert_normal (cd, value, 0|(1<f_imm16u, 0, 0, 15, 16, 32, total_length, buffer); break; - case MS1_OPERAND_INCAMT : + case MT_OPERAND_INCAMT : errmsg = insert_normal (cd, fields->f_incamt, 0, 0, 19, 8, 32, total_length, buffer); break; - case MS1_OPERAND_INCR : + case MT_OPERAND_INCR : errmsg = insert_normal (cd, fields->f_incr, 0, 0, 17, 6, 32, total_length, buffer); break; - case MS1_OPERAND_LENGTH : + case MT_OPERAND_LENGTH : errmsg = insert_normal (cd, fields->f_length, 0, 0, 15, 3, 32, total_length, buffer); break; - case MS1_OPERAND_LOOPSIZE : + case MT_OPERAND_LOOPSIZE : { long value = fields->f_loopo; value = ((unsigned int) (value) >> (2)); errmsg = insert_normal (cd, value, 0, 0, 7, 8, 32, total_length, buffer); } break; - case MS1_OPERAND_MASK : + case MT_OPERAND_MASK : errmsg = insert_normal (cd, fields->f_mask, 0, 0, 25, 16, 32, total_length, buffer); break; - case MS1_OPERAND_MASK1 : + case MT_OPERAND_MASK1 : errmsg = insert_normal (cd, fields->f_mask1, 0, 0, 22, 3, 32, total_length, buffer); break; - case MS1_OPERAND_MODE : + case MT_OPERAND_MODE : errmsg = insert_normal (cd, fields->f_mode, 0, 0, 25, 2, 32, total_length, buffer); break; - case MS1_OPERAND_PERM : + case MT_OPERAND_PERM : errmsg = insert_normal (cd, fields->f_perm, 0, 0, 25, 2, 32, total_length, buffer); break; - case MS1_OPERAND_RBBC : + case MT_OPERAND_RBBC : errmsg = insert_normal (cd, fields->f_rbbc, 0, 0, 25, 2, 32, total_length, buffer); break; - case MS1_OPERAND_RC : + case MT_OPERAND_RC : errmsg = insert_normal (cd, fields->f_rc, 0, 0, 15, 1, 32, total_length, buffer); break; - case MS1_OPERAND_RC1 : + case MT_OPERAND_RC1 : errmsg = insert_normal (cd, fields->f_rc1, 0, 0, 11, 1, 32, total_length, buffer); break; - case MS1_OPERAND_RC2 : + case MT_OPERAND_RC2 : errmsg = insert_normal (cd, fields->f_rc2, 0, 0, 6, 1, 32, total_length, buffer); break; - case MS1_OPERAND_RC3 : + case MT_OPERAND_RC3 : errmsg = insert_normal (cd, fields->f_rc3, 0, 0, 7, 1, 32, total_length, buffer); break; - case MS1_OPERAND_RCNUM : + case MT_OPERAND_RCNUM : errmsg = insert_normal (cd, fields->f_rcnum, 0, 0, 14, 3, 32, total_length, buffer); break; - case MS1_OPERAND_RDA : + case MT_OPERAND_RDA : errmsg = insert_normal (cd, fields->f_rda, 0, 0, 25, 1, 32, total_length, buffer); break; - case MS1_OPERAND_ROWNUM : + case MT_OPERAND_ROWNUM : errmsg = insert_normal (cd, fields->f_rownum, 0, 0, 14, 3, 32, total_length, buffer); break; - case MS1_OPERAND_ROWNUM1 : + case MT_OPERAND_ROWNUM1 : errmsg = insert_normal (cd, fields->f_rownum1, 0, 0, 12, 3, 32, total_length, buffer); break; - case MS1_OPERAND_ROWNUM2 : + case MT_OPERAND_ROWNUM2 : errmsg = insert_normal (cd, fields->f_rownum2, 0, 0, 9, 3, 32, total_length, buffer); break; - case MS1_OPERAND_SIZE : + case MT_OPERAND_SIZE : errmsg = insert_normal (cd, fields->f_size, 0, 0, 13, 14, 32, total_length, buffer); break; - case MS1_OPERAND_TYPE : + case MT_OPERAND_TYPE : errmsg = insert_normal (cd, fields->f_type, 0, 0, 21, 2, 32, total_length, buffer); break; - case MS1_OPERAND_WR : + case MT_OPERAND_WR : errmsg = insert_normal (cd, fields->f_wr, 0, 0, 24, 1, 32, total_length, buffer); break; - case MS1_OPERAND_XMODE : + case MT_OPERAND_XMODE : errmsg = insert_normal (cd, fields->f_xmode, 0, 0, 23, 1, 32, total_length, buffer); break; @@ -743,7 +743,7 @@ ms1_cgen_insert_operand (CGEN_CPU_DESC cd, return errmsg; } -int ms1_cgen_extract_operand +int mt_cgen_extract_operand (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); /* Main entry point for operand extraction. @@ -762,7 +762,7 @@ int ms1_cgen_extract_operand the handlers. */ int -ms1_cgen_extract_operand (CGEN_CPU_DESC cd, +mt_cgen_extract_operand (CGEN_CPU_DESC cd, int opindex, CGEN_EXTRACT_INFO *ex_info, CGEN_INSN_INT insn_value, @@ -775,91 +775,91 @@ ms1_cgen_extract_operand (CGEN_CPU_DESC cd, switch (opindex) { - case MS1_OPERAND_A23 : + case MT_OPERAND_A23 : length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 1, 32, total_length, pc, & fields->f_a23); break; - case MS1_OPERAND_BALL : + case MT_OPERAND_BALL : length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_ball); break; - case MS1_OPERAND_BALL2 : + case MT_OPERAND_BALL2 : length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_ball2); break; - case MS1_OPERAND_BANKADDR : + case MT_OPERAND_BANKADDR : length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 13, 32, total_length, pc, & fields->f_bankaddr); break; - case MS1_OPERAND_BRC : + case MT_OPERAND_BRC : length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 3, 32, total_length, pc, & fields->f_brc); break; - case MS1_OPERAND_BRC2 : + case MT_OPERAND_BRC2 : length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_brc2); break; - case MS1_OPERAND_CB1INCR : + case MT_OPERAND_CB1INCR : length = extract_normal (cd, ex_info, insn_value, 0|(1<f_cb1incr); break; - case MS1_OPERAND_CB1SEL : + case MT_OPERAND_CB1SEL : length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_cb1sel); break; - case MS1_OPERAND_CB2INCR : + case MT_OPERAND_CB2INCR : length = extract_normal (cd, ex_info, insn_value, 0|(1<f_cb2incr); break; - case MS1_OPERAND_CB2SEL : + case MT_OPERAND_CB2SEL : length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 3, 32, total_length, pc, & fields->f_cb2sel); break; - case MS1_OPERAND_CBRB : + case MT_OPERAND_CBRB : length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_cbrb); break; - case MS1_OPERAND_CBS : + case MT_OPERAND_CBS : length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 2, 32, total_length, pc, & fields->f_cbs); break; - case MS1_OPERAND_CBX : + case MT_OPERAND_CBX : length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_cbx); break; - case MS1_OPERAND_CCB : + case MT_OPERAND_CCB : length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_ccb); break; - case MS1_OPERAND_CDB : + case MT_OPERAND_CDB : length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_cdb); break; - case MS1_OPERAND_CELL : + case MT_OPERAND_CELL : length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_cell); break; - case MS1_OPERAND_COLNUM : + case MT_OPERAND_COLNUM : length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 3, 32, total_length, pc, & fields->f_colnum); break; - case MS1_OPERAND_CONTNUM : + case MT_OPERAND_CONTNUM : length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 9, 32, total_length, pc, & fields->f_contnum); break; - case MS1_OPERAND_CR : + case MT_OPERAND_CR : length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 3, 32, total_length, pc, & fields->f_cr); break; - case MS1_OPERAND_CTXDISP : + case MT_OPERAND_CTXDISP : length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_ctxdisp); break; - case MS1_OPERAND_DUP : + case MT_OPERAND_DUP : length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 1, 32, total_length, pc, & fields->f_dup); break; - case MS1_OPERAND_FBDISP : + case MT_OPERAND_FBDISP : length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_fbdisp); break; - case MS1_OPERAND_FBINCR : + case MT_OPERAND_FBINCR : length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 4, 32, total_length, pc, & fields->f_fbincr); break; - case MS1_OPERAND_FRDR : + case MT_OPERAND_FRDR : length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dr); break; - case MS1_OPERAND_FRDRRR : + case MT_OPERAND_FRDRRR : length = extract_normal (cd, ex_info, insn_value, 0|(1<f_drrr); break; - case MS1_OPERAND_FRSR1 : + case MT_OPERAND_FRSR1 : length = extract_normal (cd, ex_info, insn_value, 0|(1<f_sr1); break; - case MS1_OPERAND_FRSR2 : + case MT_OPERAND_FRSR2 : length = extract_normal (cd, ex_info, insn_value, 0|(1<f_sr2); break; - case MS1_OPERAND_ID : + case MT_OPERAND_ID : length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 1, 32, total_length, pc, & fields->f_id); break; - case MS1_OPERAND_IMM16 : + case MT_OPERAND_IMM16 : { long value; length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm16s = value; } break; - case MS1_OPERAND_IMM16L : + case MT_OPERAND_IMM16L : length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 16, 32, total_length, pc, & fields->f_imm16l); break; - case MS1_OPERAND_IMM16O : + case MT_OPERAND_IMM16O : { long value; length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm16s = value; } break; - case MS1_OPERAND_IMM16Z : + case MT_OPERAND_IMM16Z : length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm16u); break; - case MS1_OPERAND_INCAMT : + case MT_OPERAND_INCAMT : length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 8, 32, total_length, pc, & fields->f_incamt); break; - case MS1_OPERAND_INCR : + case MT_OPERAND_INCR : length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_incr); break; - case MS1_OPERAND_LENGTH : + case MT_OPERAND_LENGTH : length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_length); break; - case MS1_OPERAND_LOOPSIZE : + case MT_OPERAND_LOOPSIZE : { long value; length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 32, total_length, pc, & value); @@ -898,58 +898,58 @@ ms1_cgen_extract_operand (CGEN_CPU_DESC cd, fields->f_loopo = value; } break; - case MS1_OPERAND_MASK : + case MT_OPERAND_MASK : length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 16, 32, total_length, pc, & fields->f_mask); break; - case MS1_OPERAND_MASK1 : + case MT_OPERAND_MASK1 : length = extract_normal (cd, ex_info, insn_value, 0, 0, 22, 3, 32, total_length, pc, & fields->f_mask1); break; - case MS1_OPERAND_MODE : + case MT_OPERAND_MODE : length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_mode); break; - case MS1_OPERAND_PERM : + case MT_OPERAND_PERM : length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_perm); break; - case MS1_OPERAND_RBBC : + case MT_OPERAND_RBBC : length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 2, 32, total_length, pc, & fields->f_rbbc); break; - case MS1_OPERAND_RC : + case MT_OPERAND_RC : length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_rc); break; - case MS1_OPERAND_RC1 : + case MT_OPERAND_RC1 : length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_rc1); break; - case MS1_OPERAND_RC2 : + case MT_OPERAND_RC2 : length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 1, 32, total_length, pc, & fields->f_rc2); break; - case MS1_OPERAND_RC3 : + case MT_OPERAND_RC3 : length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_rc3); break; - case MS1_OPERAND_RCNUM : + case MT_OPERAND_RCNUM : length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_rcnum); break; - case MS1_OPERAND_RDA : + case MT_OPERAND_RDA : length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_rda); break; - case MS1_OPERAND_ROWNUM : + case MT_OPERAND_ROWNUM : length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_rownum); break; - case MS1_OPERAND_ROWNUM1 : + case MT_OPERAND_ROWNUM1 : length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rownum1); break; - case MS1_OPERAND_ROWNUM2 : + case MT_OPERAND_ROWNUM2 : length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rownum2); break; - case MS1_OPERAND_SIZE : + case MT_OPERAND_SIZE : length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 14, 32, total_length, pc, & fields->f_size); break; - case MS1_OPERAND_TYPE : + case MT_OPERAND_TYPE : length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 2, 32, total_length, pc, & fields->f_type); break; - case MS1_OPERAND_WR : + case MT_OPERAND_WR : length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 1, 32, total_length, pc, & fields->f_wr); break; - case MS1_OPERAND_XMODE : + case MT_OPERAND_XMODE : length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 1, 32, total_length, pc, & fields->f_xmode); break; @@ -963,18 +963,18 @@ ms1_cgen_extract_operand (CGEN_CPU_DESC cd, return length; } -cgen_insert_fn * const ms1_cgen_insert_handlers[] = +cgen_insert_fn * const mt_cgen_insert_handlers[] = { insert_insn_normal, }; -cgen_extract_fn * const ms1_cgen_extract_handlers[] = +cgen_extract_fn * const mt_cgen_extract_handlers[] = { extract_insn_normal, }; -int ms1_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); -bfd_vma ms1_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +int mt_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma mt_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); /* Getting values from cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they return. @@ -982,7 +982,7 @@ bfd_vma ms1_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); not appropriate. */ int -ms1_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, +mt_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, int opindex, const CGEN_FIELDS * fields) { @@ -990,166 +990,166 @@ ms1_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, switch (opindex) { - case MS1_OPERAND_A23 : + case MT_OPERAND_A23 : value = fields->f_a23; break; - case MS1_OPERAND_BALL : + case MT_OPERAND_BALL : value = fields->f_ball; break; - case MS1_OPERAND_BALL2 : + case MT_OPERAND_BALL2 : value = fields->f_ball2; break; - case MS1_OPERAND_BANKADDR : + case MT_OPERAND_BANKADDR : value = fields->f_bankaddr; break; - case MS1_OPERAND_BRC : + case MT_OPERAND_BRC : value = fields->f_brc; break; - case MS1_OPERAND_BRC2 : + case MT_OPERAND_BRC2 : value = fields->f_brc2; break; - case MS1_OPERAND_CB1INCR : + case MT_OPERAND_CB1INCR : value = fields->f_cb1incr; break; - case MS1_OPERAND_CB1SEL : + case MT_OPERAND_CB1SEL : value = fields->f_cb1sel; break; - case MS1_OPERAND_CB2INCR : + case MT_OPERAND_CB2INCR : value = fields->f_cb2incr; break; - case MS1_OPERAND_CB2SEL : + case MT_OPERAND_CB2SEL : value = fields->f_cb2sel; break; - case MS1_OPERAND_CBRB : + case MT_OPERAND_CBRB : value = fields->f_cbrb; break; - case MS1_OPERAND_CBS : + case MT_OPERAND_CBS : value = fields->f_cbs; break; - case MS1_OPERAND_CBX : + case MT_OPERAND_CBX : value = fields->f_cbx; break; - case MS1_OPERAND_CCB : + case MT_OPERAND_CCB : value = fields->f_ccb; break; - case MS1_OPERAND_CDB : + case MT_OPERAND_CDB : value = fields->f_cdb; break; - case MS1_OPERAND_CELL : + case MT_OPERAND_CELL : value = fields->f_cell; break; - case MS1_OPERAND_COLNUM : + case MT_OPERAND_COLNUM : value = fields->f_colnum; break; - case MS1_OPERAND_CONTNUM : + case MT_OPERAND_CONTNUM : value = fields->f_contnum; break; - case MS1_OPERAND_CR : + case MT_OPERAND_CR : value = fields->f_cr; break; - case MS1_OPERAND_CTXDISP : + case MT_OPERAND_CTXDISP : value = fields->f_ctxdisp; break; - case MS1_OPERAND_DUP : + case MT_OPERAND_DUP : value = fields->f_dup; break; - case MS1_OPERAND_FBDISP : + case MT_OPERAND_FBDISP : value = fields->f_fbdisp; break; - case MS1_OPERAND_FBINCR : + case MT_OPERAND_FBINCR : value = fields->f_fbincr; break; - case MS1_OPERAND_FRDR : + case MT_OPERAND_FRDR : value = fields->f_dr; break; - case MS1_OPERAND_FRDRRR : + case MT_OPERAND_FRDRRR : value = fields->f_drrr; break; - case MS1_OPERAND_FRSR1 : + case MT_OPERAND_FRSR1 : value = fields->f_sr1; break; - case MS1_OPERAND_FRSR2 : + case MT_OPERAND_FRSR2 : value = fields->f_sr2; break; - case MS1_OPERAND_ID : + case MT_OPERAND_ID : value = fields->f_id; break; - case MS1_OPERAND_IMM16 : + case MT_OPERAND_IMM16 : value = fields->f_imm16s; break; - case MS1_OPERAND_IMM16L : + case MT_OPERAND_IMM16L : value = fields->f_imm16l; break; - case MS1_OPERAND_IMM16O : + case MT_OPERAND_IMM16O : value = fields->f_imm16s; break; - case MS1_OPERAND_IMM16Z : + case MT_OPERAND_IMM16Z : value = fields->f_imm16u; break; - case MS1_OPERAND_INCAMT : + case MT_OPERAND_INCAMT : value = fields->f_incamt; break; - case MS1_OPERAND_INCR : + case MT_OPERAND_INCR : value = fields->f_incr; break; - case MS1_OPERAND_LENGTH : + case MT_OPERAND_LENGTH : value = fields->f_length; break; - case MS1_OPERAND_LOOPSIZE : + case MT_OPERAND_LOOPSIZE : value = fields->f_loopo; break; - case MS1_OPERAND_MASK : + case MT_OPERAND_MASK : value = fields->f_mask; break; - case MS1_OPERAND_MASK1 : + case MT_OPERAND_MASK1 : value = fields->f_mask1; break; - case MS1_OPERAND_MODE : + case MT_OPERAND_MODE : value = fields->f_mode; break; - case MS1_OPERAND_PERM : + case MT_OPERAND_PERM : value = fields->f_perm; break; - case MS1_OPERAND_RBBC : + case MT_OPERAND_RBBC : value = fields->f_rbbc; break; - case MS1_OPERAND_RC : + case MT_OPERAND_RC : value = fields->f_rc; break; - case MS1_OPERAND_RC1 : + case MT_OPERAND_RC1 : value = fields->f_rc1; break; - case MS1_OPERAND_RC2 : + case MT_OPERAND_RC2 : value = fields->f_rc2; break; - case MS1_OPERAND_RC3 : + case MT_OPERAND_RC3 : value = fields->f_rc3; break; - case MS1_OPERAND_RCNUM : + case MT_OPERAND_RCNUM : value = fields->f_rcnum; break; - case MS1_OPERAND_RDA : + case MT_OPERAND_RDA : value = fields->f_rda; break; - case MS1_OPERAND_ROWNUM : + case MT_OPERAND_ROWNUM : value = fields->f_rownum; break; - case MS1_OPERAND_ROWNUM1 : + case MT_OPERAND_ROWNUM1 : value = fields->f_rownum1; break; - case MS1_OPERAND_ROWNUM2 : + case MT_OPERAND_ROWNUM2 : value = fields->f_rownum2; break; - case MS1_OPERAND_SIZE : + case MT_OPERAND_SIZE : value = fields->f_size; break; - case MS1_OPERAND_TYPE : + case MT_OPERAND_TYPE : value = fields->f_type; break; - case MS1_OPERAND_WR : + case MT_OPERAND_WR : value = fields->f_wr; break; - case MS1_OPERAND_XMODE : + case MT_OPERAND_XMODE : value = fields->f_xmode; break; @@ -1164,7 +1164,7 @@ ms1_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, } bfd_vma -ms1_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, +mt_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, int opindex, const CGEN_FIELDS * fields) { @@ -1172,166 +1172,166 @@ ms1_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, switch (opindex) { - case MS1_OPERAND_A23 : + case MT_OPERAND_A23 : value = fields->f_a23; break; - case MS1_OPERAND_BALL : + case MT_OPERAND_BALL : value = fields->f_ball; break; - case MS1_OPERAND_BALL2 : + case MT_OPERAND_BALL2 : value = fields->f_ball2; break; - case MS1_OPERAND_BANKADDR : + case MT_OPERAND_BANKADDR : value = fields->f_bankaddr; break; - case MS1_OPERAND_BRC : + case MT_OPERAND_BRC : value = fields->f_brc; break; - case MS1_OPERAND_BRC2 : + case MT_OPERAND_BRC2 : value = fields->f_brc2; break; - case MS1_OPERAND_CB1INCR : + case MT_OPERAND_CB1INCR : value = fields->f_cb1incr; break; - case MS1_OPERAND_CB1SEL : + case MT_OPERAND_CB1SEL : value = fields->f_cb1sel; break; - case MS1_OPERAND_CB2INCR : + case MT_OPERAND_CB2INCR : value = fields->f_cb2incr; break; - case MS1_OPERAND_CB2SEL : + case MT_OPERAND_CB2SEL : value = fields->f_cb2sel; break; - case MS1_OPERAND_CBRB : + case MT_OPERAND_CBRB : value = fields->f_cbrb; break; - case MS1_OPERAND_CBS : + case MT_OPERAND_CBS : value = fields->f_cbs; break; - case MS1_OPERAND_CBX : + case MT_OPERAND_CBX : value = fields->f_cbx; break; - case MS1_OPERAND_CCB : + case MT_OPERAND_CCB : value = fields->f_ccb; break; - case MS1_OPERAND_CDB : + case MT_OPERAND_CDB : value = fields->f_cdb; break; - case MS1_OPERAND_CELL : + case MT_OPERAND_CELL : value = fields->f_cell; break; - case MS1_OPERAND_COLNUM : + case MT_OPERAND_COLNUM : value = fields->f_colnum; break; - case MS1_OPERAND_CONTNUM : + case MT_OPERAND_CONTNUM : value = fields->f_contnum; break; - case MS1_OPERAND_CR : + case MT_OPERAND_CR : value = fields->f_cr; break; - case MS1_OPERAND_CTXDISP : + case MT_OPERAND_CTXDISP : value = fields->f_ctxdisp; break; - case MS1_OPERAND_DUP : + case MT_OPERAND_DUP : value = fields->f_dup; break; - case MS1_OPERAND_FBDISP : + case MT_OPERAND_FBDISP : value = fields->f_fbdisp; break; - case MS1_OPERAND_FBINCR : + case MT_OPERAND_FBINCR : value = fields->f_fbincr; break; - case MS1_OPERAND_FRDR : + case MT_OPERAND_FRDR : value = fields->f_dr; break; - case MS1_OPERAND_FRDRRR : + case MT_OPERAND_FRDRRR : value = fields->f_drrr; break; - case MS1_OPERAND_FRSR1 : + case MT_OPERAND_FRSR1 : value = fields->f_sr1; break; - case MS1_OPERAND_FRSR2 : + case MT_OPERAND_FRSR2 : value = fields->f_sr2; break; - case MS1_OPERAND_ID : + case MT_OPERAND_ID : value = fields->f_id; break; - case MS1_OPERAND_IMM16 : + case MT_OPERAND_IMM16 : value = fields->f_imm16s; break; - case MS1_OPERAND_IMM16L : + case MT_OPERAND_IMM16L : value = fields->f_imm16l; break; - case MS1_OPERAND_IMM16O : + case MT_OPERAND_IMM16O : value = fields->f_imm16s; break; - case MS1_OPERAND_IMM16Z : + case MT_OPERAND_IMM16Z : value = fields->f_imm16u; break; - case MS1_OPERAND_INCAMT : + case MT_OPERAND_INCAMT : value = fields->f_incamt; break; - case MS1_OPERAND_INCR : + case MT_OPERAND_INCR : value = fields->f_incr; break; - case MS1_OPERAND_LENGTH : + case MT_OPERAND_LENGTH : value = fields->f_length; break; - case MS1_OPERAND_LOOPSIZE : + case MT_OPERAND_LOOPSIZE : value = fields->f_loopo; break; - case MS1_OPERAND_MASK : + case MT_OPERAND_MASK : value = fields->f_mask; break; - case MS1_OPERAND_MASK1 : + case MT_OPERAND_MASK1 : value = fields->f_mask1; break; - case MS1_OPERAND_MODE : + case MT_OPERAND_MODE : value = fields->f_mode; break; - case MS1_OPERAND_PERM : + case MT_OPERAND_PERM : value = fields->f_perm; break; - case MS1_OPERAND_RBBC : + case MT_OPERAND_RBBC : value = fields->f_rbbc; break; - case MS1_OPERAND_RC : + case MT_OPERAND_RC : value = fields->f_rc; break; - case MS1_OPERAND_RC1 : + case MT_OPERAND_RC1 : value = fields->f_rc1; break; - case MS1_OPERAND_RC2 : + case MT_OPERAND_RC2 : value = fields->f_rc2; break; - case MS1_OPERAND_RC3 : + case MT_OPERAND_RC3 : value = fields->f_rc3; break; - case MS1_OPERAND_RCNUM : + case MT_OPERAND_RCNUM : value = fields->f_rcnum; break; - case MS1_OPERAND_RDA : + case MT_OPERAND_RDA : value = fields->f_rda; break; - case MS1_OPERAND_ROWNUM : + case MT_OPERAND_ROWNUM : value = fields->f_rownum; break; - case MS1_OPERAND_ROWNUM1 : + case MT_OPERAND_ROWNUM1 : value = fields->f_rownum1; break; - case MS1_OPERAND_ROWNUM2 : + case MT_OPERAND_ROWNUM2 : value = fields->f_rownum2; break; - case MS1_OPERAND_SIZE : + case MT_OPERAND_SIZE : value = fields->f_size; break; - case MS1_OPERAND_TYPE : + case MT_OPERAND_TYPE : value = fields->f_type; break; - case MS1_OPERAND_WR : + case MT_OPERAND_WR : value = fields->f_wr; break; - case MS1_OPERAND_XMODE : + case MT_OPERAND_XMODE : value = fields->f_xmode; break; @@ -1345,8 +1345,8 @@ ms1_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, return value; } -void ms1_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); -void ms1_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); +void mt_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void mt_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); /* Stuffing values in cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they accept. @@ -1354,173 +1354,173 @@ void ms1_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); not appropriate. */ void -ms1_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, +mt_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, int opindex, CGEN_FIELDS * fields, int value) { switch (opindex) { - case MS1_OPERAND_A23 : + case MT_OPERAND_A23 : fields->f_a23 = value; break; - case MS1_OPERAND_BALL : + case MT_OPERAND_BALL : fields->f_ball = value; break; - case MS1_OPERAND_BALL2 : + case MT_OPERAND_BALL2 : fields->f_ball2 = value; break; - case MS1_OPERAND_BANKADDR : + case MT_OPERAND_BANKADDR : fields->f_bankaddr = value; break; - case MS1_OPERAND_BRC : + case MT_OPERAND_BRC : fields->f_brc = value; break; - case MS1_OPERAND_BRC2 : + case MT_OPERAND_BRC2 : fields->f_brc2 = value; break; - case MS1_OPERAND_CB1INCR : + case MT_OPERAND_CB1INCR : fields->f_cb1incr = value; break; - case MS1_OPERAND_CB1SEL : + case MT_OPERAND_CB1SEL : fields->f_cb1sel = value; break; - case MS1_OPERAND_CB2INCR : + case MT_OPERAND_CB2INCR : fields->f_cb2incr = value; break; - case MS1_OPERAND_CB2SEL : + case MT_OPERAND_CB2SEL : fields->f_cb2sel = value; break; - case MS1_OPERAND_CBRB : + case MT_OPERAND_CBRB : fields->f_cbrb = value; break; - case MS1_OPERAND_CBS : + case MT_OPERAND_CBS : fields->f_cbs = value; break; - case MS1_OPERAND_CBX : + case MT_OPERAND_CBX : fields->f_cbx = value; break; - case MS1_OPERAND_CCB : + case MT_OPERAND_CCB : fields->f_ccb = value; break; - case MS1_OPERAND_CDB : + case MT_OPERAND_CDB : fields->f_cdb = value; break; - case MS1_OPERAND_CELL : + case MT_OPERAND_CELL : fields->f_cell = value; break; - case MS1_OPERAND_COLNUM : + case MT_OPERAND_COLNUM : fields->f_colnum = value; break; - case MS1_OPERAND_CONTNUM : + case MT_OPERAND_CONTNUM : fields->f_contnum = value; break; - case MS1_OPERAND_CR : + case MT_OPERAND_CR : fields->f_cr = value; break; - case MS1_OPERAND_CTXDISP : + case MT_OPERAND_CTXDISP : fields->f_ctxdisp = value; break; - case MS1_OPERAND_DUP : + case MT_OPERAND_DUP : fields->f_dup = value; break; - case MS1_OPERAND_FBDISP : + case MT_OPERAND_FBDISP : fields->f_fbdisp = value; break; - case MS1_OPERAND_FBINCR : + case MT_OPERAND_FBINCR : fields->f_fbincr = value; break; - case MS1_OPERAND_FRDR : + case MT_OPERAND_FRDR : fields->f_dr = value; break; - case MS1_OPERAND_FRDRRR : + case MT_OPERAND_FRDRRR : fields->f_drrr = value; break; - case MS1_OPERAND_FRSR1 : + case MT_OPERAND_FRSR1 : fields->f_sr1 = value; break; - case MS1_OPERAND_FRSR2 : + case MT_OPERAND_FRSR2 : fields->f_sr2 = value; break; - case MS1_OPERAND_ID : + case MT_OPERAND_ID : fields->f_id = value; break; - case MS1_OPERAND_IMM16 : + case MT_OPERAND_IMM16 : fields->f_imm16s = value; break; - case MS1_OPERAND_IMM16L : + case MT_OPERAND_IMM16L : fields->f_imm16l = value; break; - case MS1_OPERAND_IMM16O : + case MT_OPERAND_IMM16O : fields->f_imm16s = value; break; - case MS1_OPERAND_IMM16Z : + case MT_OPERAND_IMM16Z : fields->f_imm16u = value; break; - case MS1_OPERAND_INCAMT : + case MT_OPERAND_INCAMT : fields->f_incamt = value; break; - case MS1_OPERAND_INCR : + case MT_OPERAND_INCR : fields->f_incr = value; break; - case MS1_OPERAND_LENGTH : + case MT_OPERAND_LENGTH : fields->f_length = value; break; - case MS1_OPERAND_LOOPSIZE : + case MT_OPERAND_LOOPSIZE : fields->f_loopo = value; break; - case MS1_OPERAND_MASK : + case MT_OPERAND_MASK : fields->f_mask = value; break; - case MS1_OPERAND_MASK1 : + case MT_OPERAND_MASK1 : fields->f_mask1 = value; break; - case MS1_OPERAND_MODE : + case MT_OPERAND_MODE : fields->f_mode = value; break; - case MS1_OPERAND_PERM : + case MT_OPERAND_PERM : fields->f_perm = value; break; - case MS1_OPERAND_RBBC : + case MT_OPERAND_RBBC : fields->f_rbbc = value; break; - case MS1_OPERAND_RC : + case MT_OPERAND_RC : fields->f_rc = value; break; - case MS1_OPERAND_RC1 : + case MT_OPERAND_RC1 : fields->f_rc1 = value; break; - case MS1_OPERAND_RC2 : + case MT_OPERAND_RC2 : fields->f_rc2 = value; break; - case MS1_OPERAND_RC3 : + case MT_OPERAND_RC3 : fields->f_rc3 = value; break; - case MS1_OPERAND_RCNUM : + case MT_OPERAND_RCNUM : fields->f_rcnum = value; break; - case MS1_OPERAND_RDA : + case MT_OPERAND_RDA : fields->f_rda = value; break; - case MS1_OPERAND_ROWNUM : + case MT_OPERAND_ROWNUM : fields->f_rownum = value; break; - case MS1_OPERAND_ROWNUM1 : + case MT_OPERAND_ROWNUM1 : fields->f_rownum1 = value; break; - case MS1_OPERAND_ROWNUM2 : + case MT_OPERAND_ROWNUM2 : fields->f_rownum2 = value; break; - case MS1_OPERAND_SIZE : + case MT_OPERAND_SIZE : fields->f_size = value; break; - case MS1_OPERAND_TYPE : + case MT_OPERAND_TYPE : fields->f_type = value; break; - case MS1_OPERAND_WR : + case MT_OPERAND_WR : fields->f_wr = value; break; - case MS1_OPERAND_XMODE : + case MT_OPERAND_XMODE : fields->f_xmode = value; break; @@ -1533,173 +1533,173 @@ ms1_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, } void -ms1_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, +mt_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, int opindex, CGEN_FIELDS * fields, bfd_vma value) { switch (opindex) { - case MS1_OPERAND_A23 : + case MT_OPERAND_A23 : fields->f_a23 = value; break; - case MS1_OPERAND_BALL : + case MT_OPERAND_BALL : fields->f_ball = value; break; - case MS1_OPERAND_BALL2 : + case MT_OPERAND_BALL2 : fields->f_ball2 = value; break; - case MS1_OPERAND_BANKADDR : + case MT_OPERAND_BANKADDR : fields->f_bankaddr = value; break; - case MS1_OPERAND_BRC : + case MT_OPERAND_BRC : fields->f_brc = value; break; - case MS1_OPERAND_BRC2 : + case MT_OPERAND_BRC2 : fields->f_brc2 = value; break; - case MS1_OPERAND_CB1INCR : + case MT_OPERAND_CB1INCR : fields->f_cb1incr = value; break; - case MS1_OPERAND_CB1SEL : + case MT_OPERAND_CB1SEL : fields->f_cb1sel = value; break; - case MS1_OPERAND_CB2INCR : + case MT_OPERAND_CB2INCR : fields->f_cb2incr = value; break; - case MS1_OPERAND_CB2SEL : + case MT_OPERAND_CB2SEL : fields->f_cb2sel = value; break; - case MS1_OPERAND_CBRB : + case MT_OPERAND_CBRB : fields->f_cbrb = value; break; - case MS1_OPERAND_CBS : + case MT_OPERAND_CBS : fields->f_cbs = value; break; - case MS1_OPERAND_CBX : + case MT_OPERAND_CBX : fields->f_cbx = value; break; - case MS1_OPERAND_CCB : + case MT_OPERAND_CCB : fields->f_ccb = value; break; - case MS1_OPERAND_CDB : + case MT_OPERAND_CDB : fields->f_cdb = value; break; - case MS1_OPERAND_CELL : + case MT_OPERAND_CELL : fields->f_cell = value; break; - case MS1_OPERAND_COLNUM : + case MT_OPERAND_COLNUM : fields->f_colnum = value; break; - case MS1_OPERAND_CONTNUM : + case MT_OPERAND_CONTNUM : fields->f_contnum = value; break; - case MS1_OPERAND_CR : + case MT_OPERAND_CR : fields->f_cr = value; break; - case MS1_OPERAND_CTXDISP : + case MT_OPERAND_CTXDISP : fields->f_ctxdisp = value; break; - case MS1_OPERAND_DUP : + case MT_OPERAND_DUP : fields->f_dup = value; break; - case MS1_OPERAND_FBDISP : + case MT_OPERAND_FBDISP : fields->f_fbdisp = value; break; - case MS1_OPERAND_FBINCR : + case MT_OPERAND_FBINCR : fields->f_fbincr = value; break; - case MS1_OPERAND_FRDR : + case MT_OPERAND_FRDR : fields->f_dr = value; break; - case MS1_OPERAND_FRDRRR : + case MT_OPERAND_FRDRRR : fields->f_drrr = value; break; - case MS1_OPERAND_FRSR1 : + case MT_OPERAND_FRSR1 : fields->f_sr1 = value; break; - case MS1_OPERAND_FRSR2 : + case MT_OPERAND_FRSR2 : fields->f_sr2 = value; break; - case MS1_OPERAND_ID : + case MT_OPERAND_ID : fields->f_id = value; break; - case MS1_OPERAND_IMM16 : + case MT_OPERAND_IMM16 : fields->f_imm16s = value; break; - case MS1_OPERAND_IMM16L : + case MT_OPERAND_IMM16L : fields->f_imm16l = value; break; - case MS1_OPERAND_IMM16O : + case MT_OPERAND_IMM16O : fields->f_imm16s = value; break; - case MS1_OPERAND_IMM16Z : + case MT_OPERAND_IMM16Z : fields->f_imm16u = value; break; - case MS1_OPERAND_INCAMT : + case MT_OPERAND_INCAMT : fields->f_incamt = value; break; - case MS1_OPERAND_INCR : + case MT_OPERAND_INCR : fields->f_incr = value; break; - case MS1_OPERAND_LENGTH : + case MT_OPERAND_LENGTH : fields->f_length = value; break; - case MS1_OPERAND_LOOPSIZE : + case MT_OPERAND_LOOPSIZE : fields->f_loopo = value; break; - case MS1_OPERAND_MASK : + case MT_OPERAND_MASK : fields->f_mask = value; break; - case MS1_OPERAND_MASK1 : + case MT_OPERAND_MASK1 : fields->f_mask1 = value; break; - case MS1_OPERAND_MODE : + case MT_OPERAND_MODE : fields->f_mode = value; break; - case MS1_OPERAND_PERM : + case MT_OPERAND_PERM : fields->f_perm = value; break; - case MS1_OPERAND_RBBC : + case MT_OPERAND_RBBC : fields->f_rbbc = value; break; - case MS1_OPERAND_RC : + case MT_OPERAND_RC : fields->f_rc = value; break; - case MS1_OPERAND_RC1 : + case MT_OPERAND_RC1 : fields->f_rc1 = value; break; - case MS1_OPERAND_RC2 : + case MT_OPERAND_RC2 : fields->f_rc2 = value; break; - case MS1_OPERAND_RC3 : + case MT_OPERAND_RC3 : fields->f_rc3 = value; break; - case MS1_OPERAND_RCNUM : + case MT_OPERAND_RCNUM : fields->f_rcnum = value; break; - case MS1_OPERAND_RDA : + case MT_OPERAND_RDA : fields->f_rda = value; break; - case MS1_OPERAND_ROWNUM : + case MT_OPERAND_ROWNUM : fields->f_rownum = value; break; - case MS1_OPERAND_ROWNUM1 : + case MT_OPERAND_ROWNUM1 : fields->f_rownum1 = value; break; - case MS1_OPERAND_ROWNUM2 : + case MT_OPERAND_ROWNUM2 : fields->f_rownum2 = value; break; - case MS1_OPERAND_SIZE : + case MT_OPERAND_SIZE : fields->f_size = value; break; - case MS1_OPERAND_TYPE : + case MT_OPERAND_TYPE : fields->f_type = value; break; - case MS1_OPERAND_WR : + case MT_OPERAND_WR : fields->f_wr = value; break; - case MS1_OPERAND_XMODE : + case MT_OPERAND_XMODE : fields->f_xmode = value; break; @@ -1714,16 +1714,16 @@ ms1_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, /* Function to call before using the instruction builder tables. */ void -ms1_cgen_init_ibld_table (CGEN_CPU_DESC cd) +mt_cgen_init_ibld_table (CGEN_CPU_DESC cd) { - cd->insert_handlers = & ms1_cgen_insert_handlers[0]; - cd->extract_handlers = & ms1_cgen_extract_handlers[0]; + cd->insert_handlers = & mt_cgen_insert_handlers[0]; + cd->extract_handlers = & mt_cgen_extract_handlers[0]; - cd->insert_operand = ms1_cgen_insert_operand; - cd->extract_operand = ms1_cgen_extract_operand; + cd->insert_operand = mt_cgen_insert_operand; + cd->extract_operand = mt_cgen_extract_operand; - cd->get_int_operand = ms1_cgen_get_int_operand; - cd->set_int_operand = ms1_cgen_set_int_operand; - cd->get_vma_operand = ms1_cgen_get_vma_operand; - cd->set_vma_operand = ms1_cgen_set_vma_operand; + cd->get_int_operand = mt_cgen_get_int_operand; + cd->set_int_operand = mt_cgen_set_int_operand; + cd->get_vma_operand = mt_cgen_get_vma_operand; + cd->set_vma_operand = mt_cgen_set_vma_operand; } diff --git a/opcodes/ms1-opc.c b/opcodes/mt-opc.c similarity index 96% rename from opcodes/ms1-opc.c rename to opcodes/mt-opc.c index b30db0182..ef7d7fd69 100644 --- a/opcodes/ms1-opc.c +++ b/opcodes/mt-opc.c @@ -1,4 +1,4 @@ -/* Instruction opcode table for ms1. +/* Instruction opcode table for mt. THIS FILE IS MACHINE GENERATED WITH CGEN. @@ -26,8 +26,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "ansidecl.h" #include "bfd.h" #include "symcat.h" -#include "ms1-desc.h" -#include "ms1-opc.h" +#include "mt-desc.h" +#include "mt-opc.h" #include "libiberty.h" /* -- opc.c */ @@ -36,8 +36,8 @@ with this program; if not, write to the Free Software Foundation, Inc., /* Special check to ensure that instruction exists for given machine. */ int -ms1_cgen_insn_supported (CGEN_CPU_DESC cd, - const CGEN_INSN *insn) +mt_cgen_insn_supported (CGEN_CPU_DESC cd, + const CGEN_INSN *insn) { int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); @@ -51,7 +51,7 @@ ms1_cgen_insn_supported (CGEN_CPU_DESC cd, /* A better hash function for instruction mnemonics. */ unsigned int -ms1_asm_hash (const char* insn) +mt_asm_hash (const char* insn) { unsigned int hash; const char* m = insn; @@ -77,9 +77,9 @@ static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); /* Instruction formats. */ #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -#define F(f) & ms1_cgen_ifld_table[MS1_##f] +#define F(f) & mt_cgen_ifld_table[MT_##f] #else -#define F(f) & ms1_cgen_ifld_table[MS1_/**/f] +#define F(f) & mt_cgen_ifld_table[MT_/**/f] #endif static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { 0, 0, 0x0, { { 0 } } @@ -265,16 +265,16 @@ static const CGEN_IFMT ifmt_dfbr ATTRIBUTE_UNUSED = { #define A(a) (1 << CGEN_INSN_/**/a) #endif #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -#define OPERAND(op) MS1_OPERAND_##op +#define OPERAND(op) MT_OPERAND_##op #else -#define OPERAND(op) MS1_OPERAND_/**/op +#define OPERAND(op) MT_OPERAND_/**/op #endif #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) /* The instruction table. */ -static const CGEN_OPCODE ms1_cgen_insn_opcode_table[MAX_INSNS] = +static const CGEN_OPCODE mt_cgen_insn_opcode_table[MAX_INSNS] = { /* Special null first entry. A `num' value of zero is thus invalid. @@ -788,9 +788,9 @@ static const CGEN_OPCODE ms1_cgen_insn_opcode_table[MAX_INSNS] = /* Formats for ALIAS macro-insns. */ #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -#define F(f) & ms1_cgen_ifld_table[MS1_##f] +#define F(f) & mt_cgen_ifld_table[MT_##f] #else -#define F(f) & ms1_cgen_ifld_table[MS1_/**/f] +#define F(f) & mt_cgen_ifld_table[MT_/**/f] #endif #undef F @@ -802,22 +802,22 @@ static const CGEN_OPCODE ms1_cgen_insn_opcode_table[MAX_INSNS] = #define A(a) (1 << CGEN_INSN_/**/a) #endif #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -#define OPERAND(op) MS1_OPERAND_##op +#define OPERAND(op) MT_OPERAND_##op #else -#define OPERAND(op) MS1_OPERAND_/**/op +#define OPERAND(op) MT_OPERAND_/**/op #endif #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) /* The macro instruction table. */ -static const CGEN_IBASE ms1_cgen_macro_insn_table[] = +static const CGEN_IBASE mt_cgen_macro_insn_table[] = { }; /* The macro instruction opcode table. */ -static const CGEN_OPCODE ms1_cgen_macro_insn_opcode_table[] = +static const CGEN_OPCODE mt_cgen_macro_insn_opcode_table[] = { }; @@ -907,13 +907,13 @@ set_fields_bitsize (CGEN_FIELDS *fields, int size) This plugs the opcode entries and macro instructions into the cpu table. */ void -ms1_cgen_init_opcode_table (CGEN_CPU_DESC cd) +mt_cgen_init_opcode_table (CGEN_CPU_DESC cd) { int i; - int num_macros = (sizeof (ms1_cgen_macro_insn_table) / - sizeof (ms1_cgen_macro_insn_table[0])); - const CGEN_IBASE *ib = & ms1_cgen_macro_insn_table[0]; - const CGEN_OPCODE *oc = & ms1_cgen_macro_insn_opcode_table[0]; + int num_macros = (sizeof (mt_cgen_macro_insn_table) / + sizeof (mt_cgen_macro_insn_table[0])); + const CGEN_IBASE *ib = & mt_cgen_macro_insn_table[0]; + const CGEN_OPCODE *oc = & mt_cgen_macro_insn_opcode_table[0]; CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); memset (insns, 0, num_macros * sizeof (CGEN_INSN)); @@ -921,18 +921,18 @@ ms1_cgen_init_opcode_table (CGEN_CPU_DESC cd) { insns[i].base = &ib[i]; insns[i].opcode = &oc[i]; - ms1_cgen_build_insn_regex (& insns[i]); + mt_cgen_build_insn_regex (& insns[i]); } cd->macro_insn_table.init_entries = insns; cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); cd->macro_insn_table.num_init_entries = num_macros; - oc = & ms1_cgen_insn_opcode_table[0]; + oc = & mt_cgen_insn_opcode_table[0]; insns = (CGEN_INSN *) cd->insn_table.init_entries; for (i = 0; i < MAX_INSNS; ++i) { insns[i].opcode = &oc[i]; - ms1_cgen_build_insn_regex (& insns[i]); + mt_cgen_build_insn_regex (& insns[i]); } cd->sizeof_fields = sizeof (CGEN_FIELDS); diff --git a/opcodes/ms1-opc.h b/opcodes/mt-opc.h similarity index 62% rename from opcodes/ms1-opc.h rename to opcodes/mt-opc.h index dc575845d..31657a81d 100644 --- a/opcodes/ms1-opc.h +++ b/opcodes/mt-opc.h @@ -1,4 +1,4 @@ -/* Instruction opcode header for ms1. +/* Instruction opcode header for mt. THIS FILE IS MACHINE GENERATED WITH CGEN. @@ -22,8 +22,8 @@ with this program; if not, write to the Free Software Foundation, Inc., */ -#ifndef MS1_OPC_H -#define MS1_OPC_H +#ifndef MT_OPC_H +#define MT_OPC_H /* -- opc.h */ @@ -39,44 +39,44 @@ with this program; if not, write to the Free Software Foundation, Inc., #define CGEN_DIS_HASH(buf, value) (((* (unsigned char *) (buf)) >> 5) % CGEN_DIS_HASH_SIZE) #define CGEN_ASM_HASH_SIZE 127 -#define CGEN_ASM_HASH(insn) ms1_asm_hash (insn) +#define CGEN_ASM_HASH(insn) mt_asm_hash (insn) -extern unsigned int ms1_asm_hash (const char *); +extern unsigned int mt_asm_hash (const char *); -extern int ms1_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); +extern int mt_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); /* -- opc.c */ -/* Enum declaration for ms1 instruction types. */ +/* Enum declaration for mt instruction types. */ typedef enum cgen_insn_type { - MS1_INSN_INVALID, MS1_INSN_ADD, MS1_INSN_ADDU, MS1_INSN_ADDI - , MS1_INSN_ADDUI, MS1_INSN_SUB, MS1_INSN_SUBU, MS1_INSN_SUBI - , MS1_INSN_SUBUI, MS1_INSN_MUL, MS1_INSN_MULI, MS1_INSN_AND - , MS1_INSN_ANDI, MS1_INSN_OR, MS1_INSN_NOP, MS1_INSN_ORI - , MS1_INSN_XOR, MS1_INSN_XORI, MS1_INSN_NAND, MS1_INSN_NANDI - , MS1_INSN_NOR, MS1_INSN_NORI, MS1_INSN_XNOR, MS1_INSN_XNORI - , MS1_INSN_LDUI, MS1_INSN_LSL, MS1_INSN_LSLI, MS1_INSN_LSR - , MS1_INSN_LSRI, MS1_INSN_ASR, MS1_INSN_ASRI, MS1_INSN_BRLT - , MS1_INSN_BRLE, MS1_INSN_BREQ, MS1_INSN_BRNE, MS1_INSN_JMP - , MS1_INSN_JAL, MS1_INSN_DBNZ, MS1_INSN_EI, MS1_INSN_DI - , MS1_INSN_SI, MS1_INSN_RETI, MS1_INSN_LDW, MS1_INSN_STW - , MS1_INSN_BREAK, MS1_INSN_IFLUSH, MS1_INSN_LDCTXT, MS1_INSN_LDFB - , MS1_INSN_STFB, MS1_INSN_FBCB, MS1_INSN_MFBCB, MS1_INSN_FBCCI - , MS1_INSN_FBRCI, MS1_INSN_FBCRI, MS1_INSN_FBRRI, MS1_INSN_MFBCCI - , MS1_INSN_MFBRCI, MS1_INSN_MFBCRI, MS1_INSN_MFBRRI, MS1_INSN_FBCBDR - , MS1_INSN_RCFBCB, MS1_INSN_MRCFBCB, MS1_INSN_CBCAST, MS1_INSN_DUPCBCAST - , MS1_INSN_WFBI, MS1_INSN_WFB, MS1_INSN_RCRISC, MS1_INSN_FBCBINC - , MS1_INSN_RCXMODE, MS1_INSN_INTERLEAVER, MS1_INSN_WFBINC, MS1_INSN_MWFBINC - , MS1_INSN_WFBINCR, MS1_INSN_MWFBINCR, MS1_INSN_FBCBINCS, MS1_INSN_MFBCBINCS - , MS1_INSN_FBCBINCRS, MS1_INSN_MFBCBINCRS, MS1_INSN_LOOP, MS1_INSN_LOOPI - , MS1_INSN_DFBC, MS1_INSN_DWFB, MS1_INSN_FBWFB, MS1_INSN_DFBR + MT_INSN_INVALID, MT_INSN_ADD, MT_INSN_ADDU, MT_INSN_ADDI + , MT_INSN_ADDUI, MT_INSN_SUB, MT_INSN_SUBU, MT_INSN_SUBI + , MT_INSN_SUBUI, MT_INSN_MUL, MT_INSN_MULI, MT_INSN_AND + , MT_INSN_ANDI, MT_INSN_OR, MT_INSN_NOP, MT_INSN_ORI + , MT_INSN_XOR, MT_INSN_XORI, MT_INSN_NAND, MT_INSN_NANDI + , MT_INSN_NOR, MT_INSN_NORI, MT_INSN_XNOR, MT_INSN_XNORI + , MT_INSN_LDUI, MT_INSN_LSL, MT_INSN_LSLI, MT_INSN_LSR + , MT_INSN_LSRI, MT_INSN_ASR, MT_INSN_ASRI, MT_INSN_BRLT + , MT_INSN_BRLE, MT_INSN_BREQ, MT_INSN_BRNE, MT_INSN_JMP + , MT_INSN_JAL, MT_INSN_DBNZ, MT_INSN_EI, MT_INSN_DI + , MT_INSN_SI, MT_INSN_RETI, MT_INSN_LDW, MT_INSN_STW + , MT_INSN_BREAK, MT_INSN_IFLUSH, MT_INSN_LDCTXT, MT_INSN_LDFB + , MT_INSN_STFB, MT_INSN_FBCB, MT_INSN_MFBCB, MT_INSN_FBCCI + , MT_INSN_FBRCI, MT_INSN_FBCRI, MT_INSN_FBRRI, MT_INSN_MFBCCI + , MT_INSN_MFBRCI, MT_INSN_MFBCRI, MT_INSN_MFBRRI, MT_INSN_FBCBDR + , MT_INSN_RCFBCB, MT_INSN_MRCFBCB, MT_INSN_CBCAST, MT_INSN_DUPCBCAST + , MT_INSN_WFBI, MT_INSN_WFB, MT_INSN_RCRISC, MT_INSN_FBCBINC + , MT_INSN_RCXMODE, MT_INSN_INTERLEAVER, MT_INSN_WFBINC, MT_INSN_MWFBINC + , MT_INSN_WFBINCR, MT_INSN_MWFBINCR, MT_INSN_FBCBINCS, MT_INSN_MFBCBINCS + , MT_INSN_FBCBINCRS, MT_INSN_MFBCBINCRS, MT_INSN_LOOP, MT_INSN_LOOPI + , MT_INSN_DFBC, MT_INSN_DWFB, MT_INSN_FBWFB, MT_INSN_DFBR } CGEN_INSN_TYPE; /* Index of `invalid' insn place holder. */ -#define CGEN_INSN_INVALID MS1_INSN_INVALID +#define CGEN_INSN_INVALID MT_INSN_INVALID /* Total number of insns in table. */ -#define MAX_INSNS ((int) MS1_INSN_DFBR + 1) +#define MAX_INSNS ((int) MT_INSN_DFBR + 1) /* This struct records data prior to insertion or after extraction. */ struct cgen_fields @@ -176,4 +176,4 @@ struct cgen_fields } -#endif /* MS1_OPC_H */ +#endif /* MT_OPC_H */ -- 2.11.4.GIT