board/freescale/warpboard/patches/linux/0002-replace-uart2-by-uart5.patch

   1 From: Fabio Estevam <fabio.estevam@freescale.com>
   2 Date: Fri, 29 May 2015 16:19:39 -0300
   3 Subject: [PATCH] ARM: dts: imx6sl-warp: Add changes for rev1.12
   4
   5 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
   6 ---
   7  arch/arm/boot/dts/imx6sl-warp.dts | 32 +++++++++++++++++++-------------
   8  1 file changed, 19 insertions(+), 13 deletions(-)
   9
  10 diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts
  11 index 0da906b..bdfa82b 100644
  12 --- a/arch/arm/boot/dts/imx6sl-warp.dts
  13 +++ b/arch/arm/boot/dts/imx6sl-warp.dts
  14 @@ -61,7 +61,9 @@
  15         usdhc3_pwrseq: usdhc3_pwrseq {
  16                 compatible = "mmc-pwrseq-simple";
  17                 reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>,       /* WL_REG_ON */
  18 +                             <&gpio4 7 GPIO_ACTIVE_LOW>,       /* WL_HOSTWAKE */
  19                               <&gpio3 25 GPIO_ACTIVE_LOW>,      /* BT_REG_ON */
  20 +                             <&gpio3 27 GPIO_ACTIVE_LOW>,      /* BT_HOSTWAKE */
  21                               <&gpio4 4 GPIO_ACTIVE_LOW>,       /* BT_WAKE */
  22                               <&gpio4 6 GPIO_ACTIVE_LOW>;       /* BT_RST_N */
  23         };
  24 @@ -73,16 +75,16 @@
  25         status = "okay";
  26  };
  27
  28 -&uart2 {
  29 +&uart3 {
  30         pinctrl-names = "default";
  31 -       pinctrl-0 = <&pinctrl_uart2>;
  32 -       fsl,uart-has-rtscts;
  33 +       pinctrl-0 = <&pinctrl_uart3>;
  34         status = "okay";
  35  };
  36
  37 -&uart3 {
  38 +&uart5 {
  39         pinctrl-names = "default";
  40 -       pinctrl-0 = <&pinctrl_uart3>;
  41 +       pinctrl-0 = <&pinctrl_uart5>;
  42 +       fsl,uart-has-rtscts;
  43         status = "okay";
  44  };
  45
  46 @@ -130,14 +132,6 @@
  47                         >;
  48                 };
  49
  50 -               pinctrl_uart2: uart2grp {
  51 -                       fsl,pins = <
  52 -                               MX6SL_PAD_EPDC_D12__UART2_RX_DATA       0x41b0b1
  53 -                               MX6SL_PAD_EPDC_D13__UART2_TX_DATA       0x41b0b1
  54 -                               MX6SL_PAD_EPDC_D14__UART2_RTS_B         0x4130B1
  55 -                               MX6SL_PAD_EPDC_D15__UART2_CTS_B         0x4130B1
  56 -                       >;
  57 -               };
  58
  59                 pinctrl_uart3: uart3grp {
  60                         fsl,pins = <
  61 @@ -146,6 +140,15 @@
  62                         >;
  63                 };
  64
  65 +               pinctrl_uart5: uart5grp {
  66 +                       fsl,pins = <
  67 +                               MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA    0x41b0b1
  68 +                               MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA    0x41b0b1
  69 +                               MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B      0x4130b1
  70 +                               MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B       0x4130b1
  71 +                       >;
  72 +               };
  73 +
  74                 pinctrl_usdhc2: usdhc2grp {
  75                         fsl,pins = <
  76                                 MX6SL_PAD_SD2_CMD__SD2_CMD              0x417059
  77 @@ -158,6 +161,7 @@
  78                                 MX6SL_PAD_SD2_DAT5__SD2_DATA5           0x417059
  79                                 MX6SL_PAD_SD2_DAT6__SD2_DATA6           0x417059
  80                                 MX6SL_PAD_SD2_DAT7__SD2_DATA7           0x417059
  81 +                               MX6SL_PAD_SD2_RST__SD2_RESET            0x417059
  82                         >;
  83                 };
  84
  85 @@ -173,6 +177,7 @@
  86                                 MX6SL_PAD_SD2_DAT5__SD2_DATA5           0x4170b9
  87                                 MX6SL_PAD_SD2_DAT6__SD2_DATA6           0x4170b9
  88                                 MX6SL_PAD_SD2_DAT7__SD2_DATA7           0x4170b9
  89 +                               MX6SL_PAD_SD2_RST__SD2_RESET            0x4170b9
  90                         >;
  91                 };
  92
  93 @@ -188,6 +193,7 @@
  94                                 MX6SL_PAD_SD2_DAT5__SD2_DATA5           0x4170f9
  95                                 MX6SL_PAD_SD2_DAT6__SD2_DATA6           0x4170f9
  96                                 MX6SL_PAD_SD2_DAT7__SD2_DATA7           0x4170f9
  97 +                               MX6SL_PAD_SD2_RST__SD2_RESET            0x4170f9
  98                         >;
  99                 };
 100
 101 --
 102 1.9.1
 103