arch/arm/mach-omap1/timer32k.c

   1 /*
   2  * linux/arch/arm/mach-omap1/timer32k.c
   3  *
   4  * OMAP 32K Timer
   5  *
   6  * Copyright (C) 2004 - 2005 Nokia Corporation
   7  * Partial timer rewrite and additional dynamic tick timer support by
   8  * Tony Lindgen <tony@atomide.com> and
   9  * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  * OMAP Dual-mode timer framework support by Timo Teras
  11  *
  12  * MPU timer code based on the older MPU timer code for OMAP
  13  * Copyright (C) 2000 RidgeRun, Inc.
  14  * Author: Greg Lonnon <glonnon@ridgerun.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify it
  17  * under the terms of the GNU General Public License as published by the
  18  * Free Software Foundation; either version 2 of the License, or (at your
  19  * option) any later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  24  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  27  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  28  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * You should have received a copy of the  GNU General Public License along
  33  * with this program; if not, write  to the Free Software Foundation, Inc.,
  34  * 675 Mass Ave, Cambridge, MA 02139, USA.
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/init.h>
  39 #include <linux/delay.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/sched.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/err.h>
  44 #include <linux/clk.h>
  45 #include <linux/clocksource.h>
  46 #include <linux/clockchips.h>
  47 #include <linux/io.h>
  48
  49 #include <asm/system.h>
  50 #include <mach/hardware.h>
  51 #include <asm/leds.h>
  52 #include <asm/irq.h>
  53 #include <asm/mach/irq.h>
  54 #include <asm/mach/time.h>
  55 #include <plat/common.h>
  56
  57 /*
  58  * ---------------------------------------------------------------------------
  59  * 32KHz OS timer
  60  *
  61  * This currently works only on 16xx, as 1510 does not have the continuous
  62  * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
  63  * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
  64  * on 1510 would be possible, but the timer would not be as accurate as
  65  * with the 32KHz synchronized timer.
  66  * ---------------------------------------------------------------------------
  67  */
  68
  69 /* 16xx specific defines */
  70 #define OMAP1_32K_TIMER_BASE            0xfffb9000
  71 #define OMAP1_32K_TIMER_CR              0x08
  72 #define OMAP1_32K_TIMER_TVR             0x00
  73 #define OMAP1_32K_TIMER_TCR             0x04
  74
  75 #define OMAP_32K_TICKS_PER_SEC          (32768)
  76
  77 /*
  78  * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
  79  * so with HZ = 128, TVR = 255.
  80  */
  81 #define OMAP_32K_TIMER_TICK_PERIOD      ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
  82
  83 #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate)                     \
  84                                 (((nr_jiffies) * (clock_rate)) / HZ)
  85
  86 static inline void omap_32k_timer_write(int val, int reg)
  87 {
  88         omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
  89 }
  90
  91 static inline unsigned long omap_32k_timer_read(int reg)
  92 {
  93         return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
  94 }
  95
  96 static inline void omap_32k_timer_start(unsigned long load_val)
  97 {
  98         if (!load_val)
  99                 load_val = 1;
 100         omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
 101         omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
 102 }
 103
 104 static inline void omap_32k_timer_stop(void)
 105 {
 106         omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
 107 }
 108
 109 #define omap_32k_timer_ack_irq()
 110
 111 static int omap_32k_timer_set_next_event(unsigned long delta,
 112                                          struct clock_event_device *dev)
 113 {
 114         omap_32k_timer_start(delta);
 115
 116         return 0;
 117 }
 118
 119 static void omap_32k_timer_set_mode(enum clock_event_mode mode,
 120                                     struct clock_event_device *evt)
 121 {
 122         omap_32k_timer_stop();
 123
 124         switch (mode) {
 125         case CLOCK_EVT_MODE_PERIODIC:
 126                 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
 127                 break;
 128         case CLOCK_EVT_MODE_ONESHOT:
 129         case CLOCK_EVT_MODE_UNUSED:
 130         case CLOCK_EVT_MODE_SHUTDOWN:
 131                 break;
 132         case CLOCK_EVT_MODE_RESUME:
 133                 break;
 134         }
 135 }
 136
 137 static struct clock_event_device clockevent_32k_timer = {
 138         .name           = "32k-timer",
 139         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 140         .shift          = 32,
 141         .set_next_event = omap_32k_timer_set_next_event,
 142         .set_mode       = omap_32k_timer_set_mode,
 143 };
 144
 145 static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
 146 {
 147         struct clock_event_device *evt = &clockevent_32k_timer;
 148         omap_32k_timer_ack_irq();
 149
 150         evt->event_handler(evt);
 151
 152         return IRQ_HANDLED;
 153 }
 154
 155 static struct irqaction omap_32k_timer_irq = {
 156         .name           = "32KHz timer",
 157         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 158         .handler        = omap_32k_timer_interrupt,
 159 };
 160
 161 static __init void omap_init_32k_timer(void)
 162 {
 163         setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
 164
 165         clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
 166                                            NSEC_PER_SEC,
 167                                            clockevent_32k_timer.shift);
 168         clockevent_32k_timer.max_delta_ns =
 169                 clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer);
 170         clockevent_32k_timer.min_delta_ns =
 171                 clockevent_delta2ns(1, &clockevent_32k_timer);
 172
 173         clockevent_32k_timer.cpumask = cpumask_of(0);
 174         clockevents_register_device(&clockevent_32k_timer);
 175 }
 176
 177 /*
 178  * ---------------------------------------------------------------------------
 179  * Timer initialization
 180  * ---------------------------------------------------------------------------
 181  */
 182 bool __init omap_32k_timer_init(void)
 183 {
 184         omap_init_clocksource_32k();
 185
 186         omap_init_32k_timer();
 187
 188         return true;
 189 }