arch/arm/mach-omap2/lpddr2_elpida_data.c

   1 /*
   2  * LPDDR2 data as per JESD209-2
   3  *
   4  * Copyright (C) 2010 Texas Instruments, Inc.
   5  *
   6  * Aneesh V <aneesh@ti.com>
   7  * Santosh Shilimkar <santosh.shilimkar@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <mach/emif.h>
  15 #include <mach/lpddr2-elpida.h>
  16
  17 const struct lpddr2_timings lpddr2_elpida_timings_400_mhz = {
  18         .max_freq       = 400000000,
  19         .RL             = 6,
  20         .tRPab          = 21,
  21         .tRCD           = 18,
  22         .tWR            = 15,
  23         .tRASmin        = 42,
  24         .tRRD           = 10,
  25         .tWTRx2         = 15,
  26         .tXSR           = 140,
  27         .tXPx2          = 15,
  28         .tRFCab         = 130,
  29         .tRTPx2         = 15,
  30         .tCKE           = 3,
  31         .tCKESR         = 15,
  32         .tZQCS          = 90,
  33         .tZQCL          = 360,
  34         .tZQINIT        = 1000,
  35         .tDQSCKMAXx2    = 11,
  36         .tRASmax        = 70,
  37         .tFAW           = 50
  38 };
  39
  40 const struct lpddr2_timings lpddr2_elpida_timings_333_mhz = {
  41         .max_freq       = 333000000,
  42         .RL             = 5,
  43         .tRPab          = 21,
  44         .tRCD           = 18,
  45         .tWR            = 15,
  46         .tRASmin        = 42,
  47         .tRRD           = 10,
  48         .tWTRx2         = 15,
  49         .tXSR           = 140,
  50         .tXPx2          = 15,
  51         .tRFCab         = 130,
  52         .tRTPx2         = 15,
  53         .tCKE           = 3,
  54         .tCKESR         = 15,
  55         .tZQCS          = 90,
  56         .tZQCL          = 360,
  57         .tZQINIT        = 1000,
  58         .tDQSCKMAXx2    = 11,
  59         .tRASmax        = 70,
  60         .tFAW           = 50
  61 };
  62
  63 const struct lpddr2_timings lpddr2_elpida_timings_200_mhz = {
  64         .max_freq       = 200000000,
  65         .RL             = 3,
  66         .tRPab          = 21,
  67         .tRCD           = 18,
  68         .tWR            = 15,
  69         .tRASmin        = 42,
  70         .tRRD           = 10,
  71         .tWTRx2         = 20,
  72         .tXSR           = 140,
  73         .tXPx2          = 15,
  74         .tRFCab         = 130,
  75         .tRTPx2         = 15,
  76         .tCKE           = 3,
  77         .tCKESR         = 15,
  78         .tZQCS          = 90,
  79         .tZQCL          = 360,
  80         .tZQINIT        = 1000,
  81         .tDQSCKMAXx2    = 11,
  82         .tRASmax        = 70,
  83         .tFAW           = 50
  84 };
  85
  86 const struct lpddr2_min_tck lpddr2_elpida_min_tck = {
  87         .tRL            = 3,
  88         .tRP_AB         = 3,
  89         .tRCD           = 3,
  90         .tWR            = 3,
  91         .tRAS_MIN       = 3,
  92         .tRRD           = 2,
  93         .tWTR           = 2,
  94         .tXP            = 2,
  95         .tRTP           = 2,
  96         .tCKE           = 3,
  97         .tCKESR         = 3,
  98         .tFAW           = 8
  99 };
 100
 101 struct lpddr2_device_info lpddr2_elpida_2G_S4_dev = {
 102         .device_timings = {
 103                 &lpddr2_elpida_timings_200_mhz,
 104                 &lpddr2_elpida_timings_333_mhz,
 105                 &lpddr2_elpida_timings_400_mhz
 106         },
 107         .min_tck        = &lpddr2_elpida_min_tck,
 108         .type           = LPDDR2_TYPE_S4,
 109         .density        = LPDDR2_DENSITY_2Gb,
 110         .io_width       = LPDDR2_IO_WIDTH_32
 111 };