arch/arm/mach-omap2/mailbox.c

   1 /*
   2  * Mailbox reservation modules for OMAP2/3
   3  *
   4  * Copyright (C) 2006-2009 Nokia Corporation
   5  * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
   6  *        and  Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/err.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/io.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/pm_runtime.h>
  20 #include <plat/mailbox.h>
  21 #include <mach/irqs.h>
  22
  23 #define MAILBOX_REVISION                0x000
  24 #define MAILBOX_SYSCONFIG               0x10
  25 #define MAILBOX_MESSAGE(m)              (0x040 + 0x4 * (m))
  26 #define MAILBOX_FIFOSTATUS(m)           (0x080 + 0x4 * (m))
  27 #define MAILBOX_MSGSTATUS(m)            (0x0c0 + 0x4 * (m))
  28 #define MAILBOX_IRQSTATUS(u)            (0x100 + 0x8 * (u))
  29 #define MAILBOX_IRQENABLE(u)            (0x104 + 0x8 * (u))
  30
  31 #define OMAP4_MAILBOX_IRQSTATUS(u)      (0x104 + 0x10 * (u))
  32 #define OMAP4_MAILBOX_IRQENABLE(u)      (0x108 + 0x10 * (u))
  33 #define OMAP4_MAILBOX_IRQENABLE_CLR(u)  (0x10c + 0x10 * (u))
  34
  35 #define MAILBOX_IRQ_NEWMSG(m)           (1 << (2 * (m)))
  36 #define MAILBOX_IRQ_NOTFULL(m)          (1 << (2 * (m) + 1))
  37 #define MAILBOX_SOFTRESET               1
  38
  39 #define MBOX_NUM_USER                  2
  40 #define OMAP4_MBOX_NUM_USER            3
  41 #define MBOX_NR_REGS                   2
  42 #define OMAP4_MBOX_NR_REGS             3
  43
  44 static void __iomem *mbox_base;
  45
  46 static u32 *mbox_ctx;
  47 static int nr_mbox_users;
  48 static bool context_saved;
  49
  50 struct omap_mbox2_fifo {
  51         unsigned long msg;
  52         unsigned long fifo_stat;
  53         unsigned long msg_stat;
  54 };
  55
  56 struct omap_mbox2_priv {
  57         struct omap_mbox2_fifo tx_fifo;
  58         struct omap_mbox2_fifo rx_fifo;
  59         unsigned long irqenable;
  60         unsigned long irqstatus;
  61         u32 newmsg_bit;
  62         u32 notfull_bit;
  63         unsigned long irqdisable;
  64 };
  65
  66 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
  67                                   omap_mbox_type_t irq);
  68
  69 static inline unsigned int mbox_read_reg(size_t ofs)
  70 {
  71         return __raw_readl(mbox_base + ofs);
  72 }
  73
  74 static inline void mbox_write_reg(u32 val, size_t ofs)
  75 {
  76         __raw_writel(val, mbox_base + ofs);
  77 }
  78
  79 static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
  80 {
  81         int i;
  82
  83         if (context_saved)
  84                 return;
  85
  86         /* Save irqs per user */
  87         for (i = 0; i < nr_mbox_users; i++) {
  88                 if (cpu_is_omap44xx())
  89                         mbox_ctx[i] = mbox_read_reg(OMAP4_MAILBOX_IRQENABLE(i));
  90                 else
  91                         mbox_ctx[i] = mbox_read_reg(MAILBOX_IRQENABLE(i));
  92
  93                 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
  94                                                         i, mbox_ctx[i]);
  95         }
  96
  97         context_saved = true;
  98 }
  99
 100 static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
 101 {
 102         int i;
 103
 104         if (!context_saved)
 105                 return;
 106
 107         /* Restore irqs per user */
 108         for (i = 0; i < nr_mbox_users; i++) {
 109                 if (cpu_is_omap44xx())
 110                         mbox_write_reg(mbox_ctx[i], OMAP4_MAILBOX_IRQENABLE(i));
 111                 else
 112                         mbox_write_reg(mbox_ctx[i], MAILBOX_IRQENABLE(i));
 113
 114                 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
 115                                                         i, mbox_ctx[i]);
 116         }
 117
 118         context_saved = false;
 119 }
 120
 121 /* Mailbox H/W preparations */
 122 static int omap2_mbox_startup(struct omap_mbox *mbox)
 123 {
 124         u32 l;
 125         u32 max_iter = 100;
 126
 127         pm_runtime_enable(mbox->dev->parent);
 128         pm_runtime_get_sync(mbox->dev->parent);
 129
 130         mbox_write_reg(MAILBOX_SOFTRESET, MAILBOX_SYSCONFIG);
 131         while (mbox_read_reg(MAILBOX_SYSCONFIG) & MAILBOX_SOFTRESET) {
 132                 if (WARN_ON(!max_iter--))
 133                         break;
 134                 udelay(1);
 135         }
 136
 137         omap2_mbox_restore_ctx(mbox);
 138
 139         l = mbox_read_reg(MAILBOX_REVISION);
 140         pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
 141
 142         omap2_mbox_enable_irq(mbox, IRQ_RX);
 143
 144         return 0;
 145 }
 146
 147 static void omap2_mbox_shutdown(struct omap_mbox *mbox)
 148 {
 149         omap2_mbox_save_ctx(mbox);
 150         pm_runtime_put_sync(mbox->dev->parent);
 151         pm_runtime_disable(mbox->dev->parent);
 152 }
 153
 154 /* Mailbox FIFO handle functions */
 155 static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
 156 {
 157         struct omap_mbox2_fifo *fifo =
 158                 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
 159         return (mbox_msg_t) mbox_read_reg(fifo->msg);
 160 }
 161
 162 static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
 163 {
 164         struct omap_mbox2_fifo *fifo =
 165                 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
 166         mbox_write_reg(msg, fifo->msg);
 167 }
 168
 169 static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
 170 {
 171         struct omap_mbox2_fifo *fifo =
 172                 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
 173         return (mbox_read_reg(fifo->msg_stat) == 0);
 174 }
 175
 176 static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
 177 {
 178         struct omap_mbox2_fifo *fifo =
 179                 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
 180         return mbox_read_reg(fifo->fifo_stat);
 181 }
 182
 183 /* Mailbox IRQ handle functions */
 184 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
 185                 omap_mbox_type_t irq)
 186 {
 187         struct omap_mbox2_priv *p = mbox->priv;
 188         u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 189
 190         l = mbox_read_reg(p->irqenable);
 191         l |= bit;
 192         mbox_write_reg(l, p->irqenable);
 193 }
 194
 195 static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
 196                 omap_mbox_type_t irq)
 197 {
 198         struct omap_mbox2_priv *p = mbox->priv;
 199         u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 200
 201         if (!cpu_is_omap44xx())
 202                 bit = mbox_read_reg(p->irqdisable) & ~bit;
 203
 204         mbox_write_reg(bit, p->irqdisable);
 205 }
 206
 207 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
 208                 omap_mbox_type_t irq)
 209 {
 210         struct omap_mbox2_priv *p = mbox->priv;
 211         u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 212
 213         mbox_write_reg(bit, p->irqstatus);
 214
 215         /* Flush posted write for irq status to avoid spurious interrupts */
 216         mbox_read_reg(p->irqstatus);
 217 }
 218
 219 static int omap2_mbox_is_irq(struct omap_mbox *mbox,
 220                 omap_mbox_type_t irq)
 221 {
 222         struct omap_mbox2_priv *p = mbox->priv;
 223         u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 224         u32 enable = mbox_read_reg(p->irqenable);
 225         u32 status = mbox_read_reg(p->irqstatus);
 226
 227         return (int)(enable & status & bit);
 228 }
 229
 230 static struct omap_mbox_ops omap2_mbox_ops = {
 231         .type           = OMAP_MBOX_TYPE2,
 232         .startup        = omap2_mbox_startup,
 233         .shutdown       = omap2_mbox_shutdown,
 234         .fifo_read      = omap2_mbox_fifo_read,
 235         .fifo_write     = omap2_mbox_fifo_write,
 236         .fifo_empty     = omap2_mbox_fifo_empty,
 237         .fifo_full      = omap2_mbox_fifo_full,
 238         .enable_irq     = omap2_mbox_enable_irq,
 239         .disable_irq    = omap2_mbox_disable_irq,
 240         .ack_irq        = omap2_mbox_ack_irq,
 241         .is_irq         = omap2_mbox_is_irq,
 242         .save_ctx       = omap2_mbox_save_ctx,
 243         .restore_ctx    = omap2_mbox_restore_ctx,
 244 };
 245
 246 /*
 247  * MAILBOX 0: ARM -> DSP,
 248  * MAILBOX 1: ARM <- DSP.
 249  * MAILBOX 2: ARM -> IVA,
 250  * MAILBOX 3: ARM <- IVA.
 251  */
 252
 253 /* FIXME: the following structs should be filled automatically by the user id */
 254
 255 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
 256 /* DSP */
 257 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
 258         .tx_fifo = {
 259                 .msg            = MAILBOX_MESSAGE(0),
 260                 .fifo_stat      = MAILBOX_FIFOSTATUS(0),
 261         },
 262         .rx_fifo = {
 263                 .msg            = MAILBOX_MESSAGE(1),
 264                 .msg_stat       = MAILBOX_MSGSTATUS(1),
 265         },
 266         .irqenable      = MAILBOX_IRQENABLE(0),
 267         .irqstatus      = MAILBOX_IRQSTATUS(0),
 268         .notfull_bit    = MAILBOX_IRQ_NOTFULL(0),
 269         .newmsg_bit     = MAILBOX_IRQ_NEWMSG(1),
 270         .irqdisable     = MAILBOX_IRQENABLE(0),
 271 };
 272
 273 struct omap_mbox mbox_dsp_info = {
 274         .name   = "dsp",
 275         .ops    = &omap2_mbox_ops,
 276         .priv   = &omap2_mbox_dsp_priv,
 277 };
 278 #endif
 279
 280 #if defined(CONFIG_ARCH_OMAP3)
 281 struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
 282 #endif
 283
 284 #if defined(CONFIG_SOC_OMAP2420)
 285 /* IVA */
 286 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
 287         .tx_fifo = {
 288                 .msg            = MAILBOX_MESSAGE(2),
 289                 .fifo_stat      = MAILBOX_FIFOSTATUS(2),
 290         },
 291         .rx_fifo = {
 292                 .msg            = MAILBOX_MESSAGE(3),
 293                 .msg_stat       = MAILBOX_MSGSTATUS(3),
 294         },
 295         .irqenable      = MAILBOX_IRQENABLE(3),
 296         .irqstatus      = MAILBOX_IRQSTATUS(3),
 297         .notfull_bit    = MAILBOX_IRQ_NOTFULL(2),
 298         .newmsg_bit     = MAILBOX_IRQ_NEWMSG(3),
 299         .irqdisable     = MAILBOX_IRQENABLE(3),
 300 };
 301
 302 static struct omap_mbox mbox_iva_info = {
 303         .name   = "iva",
 304         .ops    = &omap2_mbox_ops,
 305         .priv   = &omap2_mbox_iva_priv,
 306 };
 307
 308 struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
 309 #endif
 310
 311 #if defined(CONFIG_ARCH_OMAP4)
 312 /* OMAP4 */
 313 static struct omap_mbox2_priv omap2_mbox_1_priv = {
 314         .tx_fifo = {
 315                 .msg            = MAILBOX_MESSAGE(0),
 316                 .fifo_stat      = MAILBOX_FIFOSTATUS(0),
 317         },
 318         .rx_fifo = {
 319                 .msg            = MAILBOX_MESSAGE(1),
 320                 .msg_stat       = MAILBOX_MSGSTATUS(1),
 321         },
 322         .irqenable      = OMAP4_MAILBOX_IRQENABLE(0),
 323         .irqstatus      = OMAP4_MAILBOX_IRQSTATUS(0),
 324         .notfull_bit    = MAILBOX_IRQ_NOTFULL(0),
 325         .newmsg_bit     = MAILBOX_IRQ_NEWMSG(1),
 326         .irqdisable     = OMAP4_MAILBOX_IRQENABLE_CLR(0),
 327 };
 328
 329 struct omap_mbox mbox_1_info = {
 330         .name   = "mailbox-1",
 331         .ops    = &omap2_mbox_ops,
 332         .priv   = &omap2_mbox_1_priv,
 333 };
 334
 335 static struct omap_mbox2_priv omap2_mbox_2_priv = {
 336         .tx_fifo = {
 337                 .msg            = MAILBOX_MESSAGE(3),
 338                 .fifo_stat      = MAILBOX_FIFOSTATUS(3),
 339         },
 340         .rx_fifo = {
 341                 .msg            = MAILBOX_MESSAGE(2),
 342                 .msg_stat       = MAILBOX_MSGSTATUS(2),
 343         },
 344         .irqenable      = OMAP4_MAILBOX_IRQENABLE(0),
 345         .irqstatus      = OMAP4_MAILBOX_IRQSTATUS(0),
 346         .notfull_bit    = MAILBOX_IRQ_NOTFULL(3),
 347         .newmsg_bit     = MAILBOX_IRQ_NEWMSG(2),
 348         .irqdisable     = OMAP4_MAILBOX_IRQENABLE_CLR(0),
 349 };
 350
 351 struct omap_mbox mbox_2_info = {
 352         .name   = "mailbox-2",
 353         .ops    = &omap2_mbox_ops,
 354         .priv   = &omap2_mbox_2_priv,
 355 };
 356
 357 struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
 358 #endif
 359
 360 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 361 {
 362         struct resource *mem;
 363         int ret;
 364         struct omap_mbox **list;
 365
 366         if (false)
 367                 ;
 368 #if defined(CONFIG_ARCH_OMAP3)
 369         else if (cpu_is_omap34xx()) {
 370                 list = omap3_mboxes;
 371
 372                 list[0]->irq = platform_get_irq(pdev, 0);
 373         }
 374 #endif
 375 #if defined(CONFIG_ARCH_OMAP2)
 376         else if (cpu_is_omap2430()) {
 377                 list = omap2_mboxes;
 378
 379                 list[0]->irq = platform_get_irq(pdev, 0);
 380         } else if (cpu_is_omap2420()) {
 381                 list = omap2_mboxes;
 382
 383                 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
 384                 list[1]->irq = platform_get_irq_byname(pdev, "iva");
 385         }
 386 #endif
 387 #if defined(CONFIG_ARCH_OMAP4)
 388         else if (cpu_is_omap44xx()) {
 389                 list = omap4_mboxes;
 390
 391                 list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
 392         }
 393 #endif
 394         else {
 395                 pr_err("%s: platform not supported\n", __func__);
 396                 return -ENODEV;
 397         }
 398
 399         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 400         if (!mem)
 401                 return -ENODEV;
 402
 403         mbox_base = ioremap(mem->start, resource_size(mem));
 404         if (!mbox_base)
 405                 return -ENOMEM;
 406
 407         nr_mbox_users = cpu_is_omap44xx() ? OMAP4_MBOX_NUM_USER : MBOX_NUM_USER;
 408         mbox_ctx = kzalloc(sizeof(u32) * nr_mbox_users, GFP_KERNEL);
 409         if (!mbox_ctx) {
 410                 ret = -ENOMEM;
 411                 goto unmap_base;
 412         }
 413
 414         ret = omap_mbox_register(&pdev->dev, list);
 415         if (ret)
 416                 goto free_ctx;
 417
 418         return 0;
 419
 420 free_ctx:
 421         kfree(mbox_ctx);
 422 unmap_base:
 423         iounmap(mbox_base);
 424         return ret;
 425 }
 426
 427 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
 428 {
 429         omap_mbox_unregister();
 430         iounmap(mbox_base);
 431         return 0;
 432 }
 433
 434 static struct platform_driver omap2_mbox_driver = {
 435         .probe = omap2_mbox_probe,
 436         .remove = __devexit_p(omap2_mbox_remove),
 437         .driver = {
 438                 .name = "omap-mailbox",
 439         },
 440 };
 441
 442 static int __init omap2_mbox_init(void)
 443 {
 444         return platform_driver_register(&omap2_mbox_driver);
 445 }
 446
 447 static void __exit omap2_mbox_exit(void)
 448 {
 449         platform_driver_unregister(&omap2_mbox_driver);
 450 }
 451
 452 module_init(omap2_mbox_init);
 453 module_exit(omap2_mbox_exit);
 454
 455 MODULE_LICENSE("GPL v2");
 456 MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
 457 MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
 458 MODULE_AUTHOR("Paul Mundt");
 459 MODULE_ALIAS("platform:omap2-mailbox");