arch/arm/mach-omap2/omap4-sar-layout.h

   1 /*
   2  * omap4-sar-layout.h: OMAP4 SAR RAM layout header file
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  * Santosh Shilimkar <santosh.shilimkar@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H
  12 #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
  13
  14 #include <mach/hardware.h>
  15 #include <mach/omap4-common.h>
  16 #include <mach/emif-44xx.h>
  17 #include <mach/dmm-44xx.h>
  18 #include <mach/ctrl_module_pad_core_44xx.h>
  19
  20 #include "cm1_44xx.h"
  21 #include "cm2_44xx.h"
  22 #include "prcm-common.h"
  23
  24 /*
  25  * The SAR RAM is maintained during Device OFF mode.
  26  * It is split into 4 banks with different privilege accesses
  27  *
  28  * ---------------------------------------------------------------------
  29  * Access mode                  Bank    Address Range
  30  * ---------------------------------------------------------------------
  31  * HS/GP : Public               1       0x4A32_6000 - 0x4A32_6FFF (4kB)
  32  * HS/GP : Public, Secured
  33  * if padconfaccdisable=1       2       0x4A32_7000 - 0x4A32_73FF (1kB)
  34  * HS/EMU : Secured
  35  * GP : Public                  3       0x4A32_8000 - 0x4A32_87FF (2kB)
  36  * HS/GP :
  37  * Secure Priviledge,
  38  * write once.                  4       0x4A32_9000 - 0x4A32_93FF (1kB)
  39  * ---------------------------------------------------------------------
  40  * The SAR RAM save regiter layout is fixed since restore is done by hardware.
  41  */
  42
  43 #define MODULE_ADDR_IDX                         0
  44 #define MODULE_OFFSET_IDX                       1
  45 #define MODULE_NB_REGS_IDX                      2
  46 #define SAR_RAM_OFFSET_IDX                      3
  47
  48 /*
  49  * Module Index used to lookup VA using index
  50  */
  51 #define MAX_SAR_MODULES                         14
  52 #define EMIF1_INDEX                             0
  53 #define EMIF2_INDEX                             1
  54 #define DMM_INDEX                               2
  55 #define CM1_INDEX                               3
  56 #define CM2_INDEX                               4
  57 #define C2C_INDEX                               5
  58 #define CTRL_MODULE_PAD_CORE_INDEX              6
  59 #define L3_CLK1_INDEX                           7
  60 #define L3_CLK2_INDEX                           8
  61 #define L3_CLK3_INDEX                           9
  62 #define USBTLL_INDEX                            10
  63 #define UHH_INDEX                               11
  64 #define L4CORE_INDEX                            12
  65 #define L4PER_INDEX                             13
  66
  67 /*
  68  * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
  69  */
  70 #define SAR_BANK1_OFFSET                0x0000
  71 #define SAR_BANK2_OFFSET                0x1000
  72 #define SAR_BANK3_OFFSET                0x2000
  73 #define SAR_BANK4_OFFSET                0x3000
  74
  75 /* Scratch pad memory offsets from SAR_BANK1 */
  76 #define CPU0_SAVE_OFFSET                        0xb00
  77 #define CPU1_SAVE_OFFSET                        0xc00
  78 #define MMU_OFFSET0                             0xd00
  79 #define MMU_OFFSET1                             0xd10
  80 #define SCU_OFFSET0                             0xd20
  81 #define SCU_OFFSET1                             0xd24
  82 #define L2X0_AUXCTRL_OFFSET                     0xd28
  83 #define OMAP_TYPE_OFFSET                        0xd2c
  84 #define L2X0_LOCKDOWN_OFFSET0                   0xd30
  85 #define L2X0_PREFETCHCTRL_OFFSET                0xd34
  86 #define L2X0_SAVE_OFFSET0                       0xd38
  87 #define L2X0_SAVE_OFFSET1                       0xd3c
  88
  89 /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
  90 #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET           0xa04
  91 #define CPU1_WAKEUP_NS_PA_ADDR_OFFSET           0xa08
  92
  93 /* GIC save restore offset from SAR_BANK3 */
  94 #define SAR_BACKUP_STATUS_OFFSET                (SAR_BANK3_OFFSET + 0x500)
  95 #define SAR_SECURE_RAM_SIZE_OFFSET              (SAR_BANK3_OFFSET + 0x504)
  96 #define SAR_SECRAM_SAVED_AT_OFFSET              (SAR_BANK3_OFFSET + 0x508)
  97 #define ICDISR_CPU0_OFFSET                      (SAR_BANK3_OFFSET + 0x50c)
  98 #define ICDISR_CPU1_OFFSET                      (SAR_BANK3_OFFSET + 0x510)
  99 #define ICDISR_SPI_OFFSET                       (SAR_BANK3_OFFSET + 0x514)
 100 #define ICDISER_CPU0_OFFSET                     (SAR_BANK3_OFFSET + 0x524)
 101 #define ICDISER_CPU1_OFFSET                     (SAR_BANK3_OFFSET + 0x528)
 102 #define ICDISER_SPI_OFFSET                      (SAR_BANK3_OFFSET + 0x52c)
 103 #define ICDIPR_SFI_CPU0_OFFSET                  (SAR_BANK3_OFFSET + 0x53c)
 104 #define ICDIPR_PPI_CPU0_OFFSET                  (SAR_BANK3_OFFSET + 0x54c)
 105 #define ICDIPR_SFI_CPU1_OFFSET                  (SAR_BANK3_OFFSET + 0x550)
 106 #define ICDIPR_PPI_CPU1_OFFSET                  (SAR_BANK3_OFFSET + 0x560)
 107 #define ICDIPR_SPI_OFFSET                       (SAR_BANK3_OFFSET + 0x564)
 108 #define ICDIPTR_SPI_OFFSET                      (SAR_BANK3_OFFSET + 0x5e4)
 109 #define ICDICFR_OFFSET                          (SAR_BANK3_OFFSET + 0x664)
 110 #define SAR_BACKUP_STATUS_GIC_CPU0              0x1
 111 #define SAR_BACKUP_STATUS_GIC_CPU1              0x2
 112
 113 /* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */
 114 #define WAKEUPGENENB_OFFSET_CPU0                (SAR_BANK3_OFFSET + 0x684)
 115 #define WAKEUPGENENB_SECURE_OFFSET_CPU0         (SAR_BANK3_OFFSET + 0x694)
 116 #define WAKEUPGENENB_OFFSET_CPU1                (SAR_BANK3_OFFSET + 0x6a4)
 117 #define WAKEUPGENENB_SECURE_OFFSET_CPU1         (SAR_BANK3_OFFSET + 0x6b4)
 118 #define AUXCOREBOOT0_OFFSET                     (SAR_BANK3_OFFSET + 0x6c4)
 119 #define AUXCOREBOOT1_OFFSET                     (SAR_BANK3_OFFSET + 0x6c8)
 120 #define PTMSYNCREQ_MASK_OFFSET                  (SAR_BANK3_OFFSET + 0x6cc)
 121 #define PTMSYNCREQ_EN_OFFSET                    (SAR_BANK3_OFFSET + 0x6d0)
 122 #define SAR_BACKUP_STATUS_WAKEUPGEN             0x10
 123
 124 #endif