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ARM: cpu topology: Add debugfs interface for cpu_power
[cmplus.git] / arch / arm / mach-omap2 / omap_hwmod_2430_data.c
blob84d3341a717cec74d63a42e7fd3fb12e1bfc216d
1 /*
2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
3 *
4 * Copyright (C) 2009-2010 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
13 */
14 #include <plat/omap_hwmod.h>
15 #include <mach/irqs.h>
16 #include <plat/cpu.h>
17 #include <plat/dma.h>
18 #include <plat/serial.h>
19 #include <plat/i2c.h>
20 #include <plat/gpio.h>
21 #include <plat/mcbsp.h>
22 #include <plat/mcspi.h>
23 #include <plat/dmtimer.h>
24 #include <plat/mmc.h>
25 #include <plat/l3_2xxx.h>
26
27 #include "omap_hwmod_common_data.h"
28
29 #include "prm-regbits-24xx.h"
30 #include "cm-regbits-24xx.h"
31 #include "wd_timer.h"
32
33 /*
34 * OMAP2430 hardware module integration data
35 *
36 * ALl of the data in this section should be autogeneratable from the
37 * TI hardware database or other technical documentation. Data that
38 * is driver-specific or driver-kernel integration-specific belongs
39 * elsewhere.
40 */
41
42 static struct omap_hwmod omap2430_mpu_hwmod;
43 static struct omap_hwmod omap2430_iva_hwmod;
44 static struct omap_hwmod omap2430_l3_main_hwmod;
45 static struct omap_hwmod omap2430_l4_core_hwmod;
46 static struct omap_hwmod omap2430_dss_core_hwmod;
47 static struct omap_hwmod omap2430_dss_dispc_hwmod;
48 static struct omap_hwmod omap2430_dss_rfbi_hwmod;
49 static struct omap_hwmod omap2430_dss_venc_hwmod;
50 static struct omap_hwmod omap2430_wd_timer2_hwmod;
51 static struct omap_hwmod omap2430_gpio1_hwmod;
52 static struct omap_hwmod omap2430_gpio2_hwmod;
53 static struct omap_hwmod omap2430_gpio3_hwmod;
54 static struct omap_hwmod omap2430_gpio4_hwmod;
55 static struct omap_hwmod omap2430_gpio5_hwmod;
56 static struct omap_hwmod omap2430_dma_system_hwmod;
57 static struct omap_hwmod omap2430_mcbsp1_hwmod;
58 static struct omap_hwmod omap2430_mcbsp2_hwmod;
59 static struct omap_hwmod omap2430_mcbsp3_hwmod;
60 static struct omap_hwmod omap2430_mcbsp4_hwmod;
61 static struct omap_hwmod omap2430_mcbsp5_hwmod;
62 static struct omap_hwmod omap2430_mcspi1_hwmod;
63 static struct omap_hwmod omap2430_mcspi2_hwmod;
64 static struct omap_hwmod omap2430_mcspi3_hwmod;
65 static struct omap_hwmod omap2430_mmc1_hwmod;
66 static struct omap_hwmod omap2430_mmc2_hwmod;
67
68 /* L3 -> L4_CORE interface */
69 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
70 .master = &omap2430_l3_main_hwmod,
71 .slave = &omap2430_l4_core_hwmod,
72 .user = OCP_USER_MPU | OCP_USER_SDMA,
73 };
74
75 /* MPU -> L3 interface */
76 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
77 .master = &omap2430_mpu_hwmod,
78 .slave = &omap2430_l3_main_hwmod,
79 .user = OCP_USER_MPU,
80 };
81
82 /* Slave interfaces on the L3 interconnect */
83 static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
84 &omap2430_mpu__l3_main,
85 };
86
87 /* DSS -> l3 */
88 static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
89 .master = &omap2430_dss_core_hwmod,
90 .slave = &omap2430_l3_main_hwmod,
91 .fw = {
92 .omap2 = {
93 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
94 .flags = OMAP_FIREWALL_L3,
95 }
96 },
97 .user = OCP_USER_MPU | OCP_USER_SDMA,
98 };
99
100 /* Master interfaces on the L3 interconnect */
101 static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
102 &omap2430_l3_main__l4_core,
103 };
104
105 /* L3 */
106 static struct omap_hwmod omap2430_l3_main_hwmod = {
107 .name = "l3_main",
108 .class = &l3_hwmod_class,
109 .masters = omap2430_l3_main_masters,
110 .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters),
111 .slaves = omap2430_l3_main_slaves,
112 .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves),
113 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
114 .flags = HWMOD_NO_IDLEST,
115 };
116
117 static struct omap_hwmod omap2430_l4_wkup_hwmod;
118 static struct omap_hwmod omap2430_uart1_hwmod;
119 static struct omap_hwmod omap2430_uart2_hwmod;
120 static struct omap_hwmod omap2430_uart3_hwmod;
121 static struct omap_hwmod omap2430_i2c1_hwmod;
122 static struct omap_hwmod omap2430_i2c2_hwmod;
123
124 static struct omap_hwmod omap2430_usbhsotg_hwmod;
125
126 /* l3_core -> usbhsotg interface */
127 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
128 .master = &omap2430_usbhsotg_hwmod,
129 .slave = &omap2430_l3_main_hwmod,
130 .clk = "core_l3_ck",
131 .user = OCP_USER_MPU,
132 };
133
134 /* I2C IP block address space length (in bytes) */
135 #define OMAP2_I2C_AS_LEN 128
136
137 /* L4 CORE -> I2C1 interface */
138 static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
139 {
140 .pa_start = 0x48070000,
141 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
142 .flags = ADDR_TYPE_RT,
143 },
144 };
145
146 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
147 .master = &omap2430_l4_core_hwmod,
148 .slave = &omap2430_i2c1_hwmod,
149 .clk = "i2c1_ick",
150 .addr = omap2430_i2c1_addr_space,
151 .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space),
152 .user = OCP_USER_MPU | OCP_USER_SDMA,
153 };
154
155 /* L4 CORE -> I2C2 interface */
156 static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
157 {
158 .pa_start = 0x48072000,
159 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
160 .flags = ADDR_TYPE_RT,
161 },
162 };
163
164 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
165 .master = &omap2430_l4_core_hwmod,
166 .slave = &omap2430_i2c2_hwmod,
167 .clk = "i2c2_ick",
168 .addr = omap2430_i2c2_addr_space,
169 .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space),
170 .user = OCP_USER_MPU | OCP_USER_SDMA,
171 };
172
173 /* L4_CORE -> L4_WKUP interface */
174 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
175 .master = &omap2430_l4_core_hwmod,
176 .slave = &omap2430_l4_wkup_hwmod,
177 .user = OCP_USER_MPU | OCP_USER_SDMA,
178 };
179
180 /* L4 CORE -> UART1 interface */
181 static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
182 {
183 .pa_start = OMAP2_UART1_BASE,
184 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
185 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
186 },
187 };
188
189 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
190 .master = &omap2430_l4_core_hwmod,
191 .slave = &omap2430_uart1_hwmod,
192 .clk = "uart1_ick",
193 .addr = omap2430_uart1_addr_space,
194 .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space),
195 .user = OCP_USER_MPU | OCP_USER_SDMA,
196 };
197
198 /* L4 CORE -> UART2 interface */
199 static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
200 {
201 .pa_start = OMAP2_UART2_BASE,
202 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
203 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
204 },
205 };
206
207 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
208 .master = &omap2430_l4_core_hwmod,
209 .slave = &omap2430_uart2_hwmod,
210 .clk = "uart2_ick",
211 .addr = omap2430_uart2_addr_space,
212 .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space),
213 .user = OCP_USER_MPU | OCP_USER_SDMA,
214 };
215
216 /* L4 PER -> UART3 interface */
217 static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
218 {
219 .pa_start = OMAP2_UART3_BASE,
220 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
221 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
222 },
223 };
224
225 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
226 .master = &omap2430_l4_core_hwmod,
227 .slave = &omap2430_uart3_hwmod,
228 .clk = "uart3_ick",
229 .addr = omap2430_uart3_addr_space,
230 .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space),
231 .user = OCP_USER_MPU | OCP_USER_SDMA,
232 };
233
234 /*
235 * usbhsotg interface data
236 */
237 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
238 {
239 .pa_start = OMAP243X_HS_BASE,
240 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
241 .flags = ADDR_TYPE_RT
242 },
243 };
244
245 /* l4_core ->usbhsotg interface */
246 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
247 .master = &omap2430_l4_core_hwmod,
248 .slave = &omap2430_usbhsotg_hwmod,
249 .clk = "usb_l4_ick",
250 .addr = omap2430_usbhsotg_addrs,
251 .addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs),
252 .user = OCP_USER_MPU,
253 };
254
255 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
256 &omap2430_usbhsotg__l3,
257 };
258
259 static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
260 &omap2430_l4_core__usbhsotg,
261 };
262
263 /* L4 CORE -> MMC1 interface */
264 static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
265 {
266 .pa_start = 0x4809c000,
267 .pa_end = 0x4809c1ff,
268 .flags = ADDR_TYPE_RT,
269 },
270 };
271
272 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
273 .master = &omap2430_l4_core_hwmod,
274 .slave = &omap2430_mmc1_hwmod,
275 .clk = "mmchs1_ick",
276 .addr = omap2430_mmc1_addr_space,
277 .addr_cnt = ARRAY_SIZE(omap2430_mmc1_addr_space),
278 .user = OCP_USER_MPU | OCP_USER_SDMA,
279 };
280
281 /* L4 CORE -> MMC2 interface */
282 static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
283 {
284 .pa_start = 0x480b4000,
285 .pa_end = 0x480b41ff,
286 .flags = ADDR_TYPE_RT,
287 },
288 };
289
290 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
291 .master = &omap2430_l4_core_hwmod,
292 .slave = &omap2430_mmc2_hwmod,
293 .addr = omap2430_mmc2_addr_space,
294 .clk = "mmchs2_ick",
295 .addr_cnt = ARRAY_SIZE(omap2430_mmc2_addr_space),
296 .user = OCP_USER_MPU | OCP_USER_SDMA,
297 };
298
299 /* Slave interfaces on the L4_CORE interconnect */
300 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
301 &omap2430_l3_main__l4_core,
302 };
303
304 /* Master interfaces on the L4_CORE interconnect */
305 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
306 &omap2430_l4_core__l4_wkup,
307 &omap2430_l4_core__mmc1,
308 &omap2430_l4_core__mmc2,
309 };
310
311 /* L4 CORE */
312 static struct omap_hwmod omap2430_l4_core_hwmod = {
313 .name = "l4_core",
314 .class = &l4_hwmod_class,
315 .masters = omap2430_l4_core_masters,
316 .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters),
317 .slaves = omap2430_l4_core_slaves,
318 .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves),
319 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
320 .flags = HWMOD_NO_IDLEST,
321 };
322
323 /* Slave interfaces on the L4_WKUP interconnect */
324 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
325 &omap2430_l4_core__l4_wkup,
326 &omap2_l4_core__uart1,
327 &omap2_l4_core__uart2,
328 &omap2_l4_core__uart3,
329 };
330
331 /* Master interfaces on the L4_WKUP interconnect */
332 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
333 };
334
335 /* l4 core -> mcspi1 interface */
336 static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
337 {
338 .pa_start = 0x48098000,
339 .pa_end = 0x480980ff,
340 .flags = ADDR_TYPE_RT,
341 },
342 };
343
344 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
345 .master = &omap2430_l4_core_hwmod,
346 .slave = &omap2430_mcspi1_hwmod,
347 .clk = "mcspi1_ick",
348 .addr = omap2430_mcspi1_addr_space,
349 .addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space),
350 .user = OCP_USER_MPU | OCP_USER_SDMA,
351 };
352
353 /* l4 core -> mcspi2 interface */
354 static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
355 {
356 .pa_start = 0x4809a000,
357 .pa_end = 0x4809a0ff,
358 .flags = ADDR_TYPE_RT,
359 },
360 };
361
362 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
363 .master = &omap2430_l4_core_hwmod,
364 .slave = &omap2430_mcspi2_hwmod,
365 .clk = "mcspi2_ick",
366 .addr = omap2430_mcspi2_addr_space,
367 .addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space),
368 .user = OCP_USER_MPU | OCP_USER_SDMA,
369 };
370
371 /* l4 core -> mcspi3 interface */
372 static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
373 {
374 .pa_start = 0x480b8000,
375 .pa_end = 0x480b80ff,
376 .flags = ADDR_TYPE_RT,
377 },
378 };
379
380 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
381 .master = &omap2430_l4_core_hwmod,
382 .slave = &omap2430_mcspi3_hwmod,
383 .clk = "mcspi3_ick",
384 .addr = omap2430_mcspi3_addr_space,
385 .addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space),
386 .user = OCP_USER_MPU | OCP_USER_SDMA,
387 };
388
389 /* L4 WKUP */
390 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
391 .name = "l4_wkup",
392 .class = &l4_hwmod_class,
393 .masters = omap2430_l4_wkup_masters,
394 .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters),
395 .slaves = omap2430_l4_wkup_slaves,
396 .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves),
397 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
398 .flags = HWMOD_NO_IDLEST,
399 };
400
401 /* Master interfaces on the MPU device */
402 static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
403 &omap2430_mpu__l3_main,
404 };
405
406 /* MPU */
407 static struct omap_hwmod omap2430_mpu_hwmod = {
408 .name = "mpu",
409 .class = &mpu_hwmod_class,
410 .main_clk = "mpu_ck",
411 .masters = omap2430_mpu_masters,
412 .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters),
413 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
414 };
415
416 /*
417 * IVA2_1 interface data
418 */
419
420 /* IVA2 <- L3 interface */
421 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
422 .master = &omap2430_l3_main_hwmod,
423 .slave = &omap2430_iva_hwmod,
424 .clk = "dsp_fck",
425 .user = OCP_USER_MPU | OCP_USER_SDMA,
426 };
427
428 static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
429 &omap2430_l3__iva,
430 };
431
432 /*
433 * IVA2 (IVA2)
434 */
435
436 static struct omap_hwmod omap2430_iva_hwmod = {
437 .name = "iva",
438 .class = &iva_hwmod_class,
439 .masters = omap2430_iva_masters,
440 .masters_cnt = ARRAY_SIZE(omap2430_iva_masters),
441 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
442 };
443
444 /* Timer Common */
445 static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
446 .rev_offs = 0x0000,
447 .sysc_offs = 0x0010,
448 .syss_offs = 0x0014,
449 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
450 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
451 SYSC_HAS_AUTOIDLE),
452 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
453 .sysc_fields = &omap_hwmod_sysc_type1,
454 };
455
456 static struct omap_hwmod_class omap2430_timer_hwmod_class = {
457 .name = "timer",
458 .sysc = &omap2430_timer_sysc,
459 .rev = OMAP_TIMER_IP_VERSION_1,
460 };
461
462 /* timer1 */
463 static struct omap_hwmod omap2430_timer1_hwmod;
464 static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
465 { .irq = 37, },
466 };
467
468 static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
469 {
470 .pa_start = 0x49018000,
471 .pa_end = 0x49018000 + SZ_1K - 1,
472 .flags = ADDR_TYPE_RT
473 },
474 };
475
476 /* l4_wkup -> timer1 */
477 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
478 .master = &omap2430_l4_wkup_hwmod,
479 .slave = &omap2430_timer1_hwmod,
480 .clk = "gpt1_ick",
481 .addr = omap2430_timer1_addrs,
482 .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs),
483 .user = OCP_USER_MPU | OCP_USER_SDMA,
484 };
485
486 /* timer1 slave port */
487 static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
488 &omap2430_l4_wkup__timer1,
489 };
490
491 /* timer1 hwmod */
492 static struct omap_hwmod omap2430_timer1_hwmod = {
493 .name = "timer1",
494 .mpu_irqs = omap2430_timer1_mpu_irqs,
495 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
496 .main_clk = "gpt1_fck",
497 .prcm = {
498 .omap2 = {
499 .prcm_reg_id = 1,
500 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
501 .module_offs = WKUP_MOD,
502 .idlest_reg_id = 1,
503 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
504 },
505 },
506 .slaves = omap2430_timer1_slaves,
507 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
508 .class = &omap2430_timer_hwmod_class,
509 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
510 };
511
512 /* timer2 */
513 static struct omap_hwmod omap2430_timer2_hwmod;
514 static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
515 { .irq = 38, },
516 };
517
518 static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
519 {
520 .pa_start = 0x4802a000,
521 .pa_end = 0x4802a000 + SZ_1K - 1,
522 .flags = ADDR_TYPE_RT
523 },
524 };
525
526 /* l4_core -> timer2 */
527 static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
528 .master = &omap2430_l4_core_hwmod,
529 .slave = &omap2430_timer2_hwmod,
530 .clk = "gpt2_ick",
531 .addr = omap2430_timer2_addrs,
532 .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs),
533 .user = OCP_USER_MPU | OCP_USER_SDMA,
534 };
535
536 /* timer2 slave port */
537 static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
538 &omap2430_l4_core__timer2,
539 };
540
541 /* timer2 hwmod */
542 static struct omap_hwmod omap2430_timer2_hwmod = {
543 .name = "timer2",
544 .mpu_irqs = omap2430_timer2_mpu_irqs,
545 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
546 .main_clk = "gpt2_fck",
547 .prcm = {
548 .omap2 = {
549 .prcm_reg_id = 1,
550 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
551 .module_offs = CORE_MOD,
552 .idlest_reg_id = 1,
553 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
554 },
555 },
556 .slaves = omap2430_timer2_slaves,
557 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
558 .class = &omap2430_timer_hwmod_class,
559 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
560 };
561
562 /* timer3 */
563 static struct omap_hwmod omap2430_timer3_hwmod;
564 static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
565 { .irq = 39, },
566 };
567
568 static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
569 {
570 .pa_start = 0x48078000,
571 .pa_end = 0x48078000 + SZ_1K - 1,
572 .flags = ADDR_TYPE_RT
573 },
574 };
575
576 /* l4_core -> timer3 */
577 static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
578 .master = &omap2430_l4_core_hwmod,
579 .slave = &omap2430_timer3_hwmod,
580 .clk = "gpt3_ick",
581 .addr = omap2430_timer3_addrs,
582 .addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs),
583 .user = OCP_USER_MPU | OCP_USER_SDMA,
584 };
585
586 /* timer3 slave port */
587 static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
588 &omap2430_l4_core__timer3,
589 };
590
591 /* timer3 hwmod */
592 static struct omap_hwmod omap2430_timer3_hwmod = {
593 .name = "timer3",
594 .mpu_irqs = omap2430_timer3_mpu_irqs,
595 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
596 .main_clk = "gpt3_fck",
597 .prcm = {
598 .omap2 = {
599 .prcm_reg_id = 1,
600 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
601 .module_offs = CORE_MOD,
602 .idlest_reg_id = 1,
603 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
604 },
605 },
606 .slaves = omap2430_timer3_slaves,
607 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
608 .class = &omap2430_timer_hwmod_class,
609 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
610 };
611
612 /* timer4 */
613 static struct omap_hwmod omap2430_timer4_hwmod;
614 static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
615 { .irq = 40, },
616 };
617
618 static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
619 {
620 .pa_start = 0x4807a000,
621 .pa_end = 0x4807a000 + SZ_1K - 1,
622 .flags = ADDR_TYPE_RT
623 },
624 };
625
626 /* l4_core -> timer4 */
627 static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
628 .master = &omap2430_l4_core_hwmod,
629 .slave = &omap2430_timer4_hwmod,
630 .clk = "gpt4_ick",
631 .addr = omap2430_timer4_addrs,
632 .addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs),
633 .user = OCP_USER_MPU | OCP_USER_SDMA,
634 };
635
636 /* timer4 slave port */
637 static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
638 &omap2430_l4_core__timer4,
639 };
640
641 /* timer4 hwmod */
642 static struct omap_hwmod omap2430_timer4_hwmod = {
643 .name = "timer4",
644 .mpu_irqs = omap2430_timer4_mpu_irqs,
645 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
646 .main_clk = "gpt4_fck",
647 .prcm = {
648 .omap2 = {
649 .prcm_reg_id = 1,
650 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
651 .module_offs = CORE_MOD,
652 .idlest_reg_id = 1,
653 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
654 },
655 },
656 .slaves = omap2430_timer4_slaves,
657 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
658 .class = &omap2430_timer_hwmod_class,
659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
660 };
661
662 /* timer5 */
663 static struct omap_hwmod omap2430_timer5_hwmod;
664 static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
665 { .irq = 41, },
666 };
667
668 static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
669 {
670 .pa_start = 0x4807c000,
671 .pa_end = 0x4807c000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT
673 },
674 };
675
676 /* l4_core -> timer5 */
677 static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
678 .master = &omap2430_l4_core_hwmod,
679 .slave = &omap2430_timer5_hwmod,
680 .clk = "gpt5_ick",
681 .addr = omap2430_timer5_addrs,
682 .addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs),
683 .user = OCP_USER_MPU | OCP_USER_SDMA,
684 };
685
686 /* timer5 slave port */
687 static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
688 &omap2430_l4_core__timer5,
689 };
690
691 /* timer5 hwmod */
692 static struct omap_hwmod omap2430_timer5_hwmod = {
693 .name = "timer5",
694 .mpu_irqs = omap2430_timer5_mpu_irqs,
695 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
696 .main_clk = "gpt5_fck",
697 .prcm = {
698 .omap2 = {
699 .prcm_reg_id = 1,
700 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
701 .module_offs = CORE_MOD,
702 .idlest_reg_id = 1,
703 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
704 },
705 },
706 .slaves = omap2430_timer5_slaves,
707 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
708 .class = &omap2430_timer_hwmod_class,
709 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
710 };
711
712 /* timer6 */
713 static struct omap_hwmod omap2430_timer6_hwmod;
714 static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
715 { .irq = 42, },
716 };
717
718 static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
719 {
720 .pa_start = 0x4807e000,
721 .pa_end = 0x4807e000 + SZ_1K - 1,
722 .flags = ADDR_TYPE_RT
723 },
724 };
725
726 /* l4_core -> timer6 */
727 static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
728 .master = &omap2430_l4_core_hwmod,
729 .slave = &omap2430_timer6_hwmod,
730 .clk = "gpt6_ick",
731 .addr = omap2430_timer6_addrs,
732 .addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs),
733 .user = OCP_USER_MPU | OCP_USER_SDMA,
734 };
735
736 /* timer6 slave port */
737 static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
738 &omap2430_l4_core__timer6,
739 };
740
741 /* timer6 hwmod */
742 static struct omap_hwmod omap2430_timer6_hwmod = {
743 .name = "timer6",
744 .mpu_irqs = omap2430_timer6_mpu_irqs,
745 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
746 .main_clk = "gpt6_fck",
747 .prcm = {
748 .omap2 = {
749 .prcm_reg_id = 1,
750 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
751 .module_offs = CORE_MOD,
752 .idlest_reg_id = 1,
753 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
754 },
755 },
756 .slaves = omap2430_timer6_slaves,
757 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
758 .class = &omap2430_timer_hwmod_class,
759 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
760 };
761
762 /* timer7 */
763 static struct omap_hwmod omap2430_timer7_hwmod;
764 static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
765 { .irq = 43, },
766 };
767
768 static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
769 {
770 .pa_start = 0x48080000,
771 .pa_end = 0x48080000 + SZ_1K - 1,
772 .flags = ADDR_TYPE_RT
773 },
774 };
775
776 /* l4_core -> timer7 */
777 static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
778 .master = &omap2430_l4_core_hwmod,
779 .slave = &omap2430_timer7_hwmod,
780 .clk = "gpt7_ick",
781 .addr = omap2430_timer7_addrs,
782 .addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs),
783 .user = OCP_USER_MPU | OCP_USER_SDMA,
784 };
785
786 /* timer7 slave port */
787 static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
788 &omap2430_l4_core__timer7,
789 };
790
791 /* timer7 hwmod */
792 static struct omap_hwmod omap2430_timer7_hwmod = {
793 .name = "timer7",
794 .mpu_irqs = omap2430_timer7_mpu_irqs,
795 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
796 .main_clk = "gpt7_fck",
797 .prcm = {
798 .omap2 = {
799 .prcm_reg_id = 1,
800 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
801 .module_offs = CORE_MOD,
802 .idlest_reg_id = 1,
803 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
804 },
805 },
806 .slaves = omap2430_timer7_slaves,
807 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
808 .class = &omap2430_timer_hwmod_class,
809 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
810 };
811
812 /* timer8 */
813 static struct omap_hwmod omap2430_timer8_hwmod;
814 static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
815 { .irq = 44, },
816 };
817
818 static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
819 {
820 .pa_start = 0x48082000,
821 .pa_end = 0x48082000 + SZ_1K - 1,
822 .flags = ADDR_TYPE_RT
823 },
824 };
825
826 /* l4_core -> timer8 */
827 static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
828 .master = &omap2430_l4_core_hwmod,
829 .slave = &omap2430_timer8_hwmod,
830 .clk = "gpt8_ick",
831 .addr = omap2430_timer8_addrs,
832 .addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs),
833 .user = OCP_USER_MPU | OCP_USER_SDMA,
834 };
835
836 /* timer8 slave port */
837 static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
838 &omap2430_l4_core__timer8,
839 };
840
841 /* timer8 hwmod */
842 static struct omap_hwmod omap2430_timer8_hwmod = {
843 .name = "timer8",
844 .mpu_irqs = omap2430_timer8_mpu_irqs,
845 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
846 .main_clk = "gpt8_fck",
847 .prcm = {
848 .omap2 = {
849 .prcm_reg_id = 1,
850 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
851 .module_offs = CORE_MOD,
852 .idlest_reg_id = 1,
853 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
854 },
855 },
856 .slaves = omap2430_timer8_slaves,
857 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
858 .class = &omap2430_timer_hwmod_class,
859 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
860 };
861
862 /* timer9 */
863 static struct omap_hwmod omap2430_timer9_hwmod;
864 static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
865 { .irq = 45, },
866 };
867
868 static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
869 {
870 .pa_start = 0x48084000,
871 .pa_end = 0x48084000 + SZ_1K - 1,
872 .flags = ADDR_TYPE_RT
873 },
874 };
875
876 /* l4_core -> timer9 */
877 static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
878 .master = &omap2430_l4_core_hwmod,
879 .slave = &omap2430_timer9_hwmod,
880 .clk = "gpt9_ick",
881 .addr = omap2430_timer9_addrs,
882 .addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs),
883 .user = OCP_USER_MPU | OCP_USER_SDMA,
884 };
885
886 /* timer9 slave port */
887 static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
888 &omap2430_l4_core__timer9,
889 };
890
891 /* timer9 hwmod */
892 static struct omap_hwmod omap2430_timer9_hwmod = {
893 .name = "timer9",
894 .mpu_irqs = omap2430_timer9_mpu_irqs,
895 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
896 .main_clk = "gpt9_fck",
897 .prcm = {
898 .omap2 = {
899 .prcm_reg_id = 1,
900 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
901 .module_offs = CORE_MOD,
902 .idlest_reg_id = 1,
903 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
904 },
905 },
906 .slaves = omap2430_timer9_slaves,
907 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
908 .class = &omap2430_timer_hwmod_class,
909 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
910 };
911
912 /* timer10 */
913 static struct omap_hwmod omap2430_timer10_hwmod;
914 static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
915 { .irq = 46, },
916 };
917
918 static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
919 {
920 .pa_start = 0x48086000,
921 .pa_end = 0x48086000 + SZ_1K - 1,
922 .flags = ADDR_TYPE_RT
923 },
924 };
925
926 /* l4_core -> timer10 */
927 static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
928 .master = &omap2430_l4_core_hwmod,
929 .slave = &omap2430_timer10_hwmod,
930 .clk = "gpt10_ick",
931 .addr = omap2430_timer10_addrs,
932 .addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs),
933 .user = OCP_USER_MPU | OCP_USER_SDMA,
934 };
935
936 /* timer10 slave port */
937 static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
938 &omap2430_l4_core__timer10,
939 };
940
941 /* timer10 hwmod */
942 static struct omap_hwmod omap2430_timer10_hwmod = {
943 .name = "timer10",
944 .mpu_irqs = omap2430_timer10_mpu_irqs,
945 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
946 .main_clk = "gpt10_fck",
947 .prcm = {
948 .omap2 = {
949 .prcm_reg_id = 1,
950 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
951 .module_offs = CORE_MOD,
952 .idlest_reg_id = 1,
953 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
954 },
955 },
956 .slaves = omap2430_timer10_slaves,
957 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
958 .class = &omap2430_timer_hwmod_class,
959 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
960 };
961
962 /* timer11 */
963 static struct omap_hwmod omap2430_timer11_hwmod;
964 static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
965 { .irq = 47, },
966 };
967
968 static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
969 {
970 .pa_start = 0x48088000,
971 .pa_end = 0x48088000 + SZ_1K - 1,
972 .flags = ADDR_TYPE_RT
973 },
974 };
975
976 /* l4_core -> timer11 */
977 static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
978 .master = &omap2430_l4_core_hwmod,
979 .slave = &omap2430_timer11_hwmod,
980 .clk = "gpt11_ick",
981 .addr = omap2430_timer11_addrs,
982 .addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs),
983 .user = OCP_USER_MPU | OCP_USER_SDMA,
984 };
985
986 /* timer11 slave port */
987 static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
988 &omap2430_l4_core__timer11,
989 };
990
991 /* timer11 hwmod */
992 static struct omap_hwmod omap2430_timer11_hwmod = {
993 .name = "timer11",
994 .mpu_irqs = omap2430_timer11_mpu_irqs,
995 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
996 .main_clk = "gpt11_fck",
997 .prcm = {
998 .omap2 = {
999 .prcm_reg_id = 1,
1000 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
1001 .module_offs = CORE_MOD,
1002 .idlest_reg_id = 1,
1003 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
1004 },
1005 },
1006 .slaves = omap2430_timer11_slaves,
1007 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
1008 .class = &omap2430_timer_hwmod_class,
1009 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1010 };
1011
1012 /* timer12 */
1013 static struct omap_hwmod omap2430_timer12_hwmod;
1014 static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
1015 { .irq = 48, },
1016 };
1017
1018 static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
1019 {
1020 .pa_start = 0x4808a000,
1021 .pa_end = 0x4808a000 + SZ_1K - 1,
1022 .flags = ADDR_TYPE_RT
1023 },
1024 };
1025
1026 /* l4_core -> timer12 */
1027 static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
1028 .master = &omap2430_l4_core_hwmod,
1029 .slave = &omap2430_timer12_hwmod,
1030 .clk = "gpt12_ick",
1031 .addr = omap2430_timer12_addrs,
1032 .addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs),
1033 .user = OCP_USER_MPU | OCP_USER_SDMA,
1034 };
1035
1036 /* timer12 slave port */
1037 static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
1038 &omap2430_l4_core__timer12,
1039 };
1040
1041 /* timer12 hwmod */
1042 static struct omap_hwmod omap2430_timer12_hwmod = {
1043 .name = "timer12",
1044 .mpu_irqs = omap2430_timer12_mpu_irqs,
1045 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
1046 .main_clk = "gpt12_fck",
1047 .prcm = {
1048 .omap2 = {
1049 .prcm_reg_id = 1,
1050 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
1051 .module_offs = CORE_MOD,
1052 .idlest_reg_id = 1,
1053 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
1054 },
1055 },
1056 .slaves = omap2430_timer12_slaves,
1057 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
1058 .class = &omap2430_timer_hwmod_class,
1059 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1060 };
1061
1062 /* l4_wkup -> wd_timer2 */
1063 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
1064 {
1065 .pa_start = 0x49016000,
1066 .pa_end = 0x4901607f,
1067 .flags = ADDR_TYPE_RT
1068 },
1069 };
1070
1071 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
1072 .master = &omap2430_l4_wkup_hwmod,
1073 .slave = &omap2430_wd_timer2_hwmod,
1074 .clk = "mpu_wdt_ick",
1075 .addr = omap2430_wd_timer2_addrs,
1076 .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs),
1077 .user = OCP_USER_MPU | OCP_USER_SDMA,
1078 };
1079
1080 /*
1081 * 'wd_timer' class
1082 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1083 * overflow condition
1084 */
1085
1086 static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
1087 .rev_offs = 0x0,
1088 .sysc_offs = 0x0010,
1089 .syss_offs = 0x0014,
1090 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
1091 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1092 .sysc_fields = &omap_hwmod_sysc_type1,
1093 };
1094
1095 static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
1096 .name = "wd_timer",
1097 .sysc = &omap2430_wd_timer_sysc,
1098 .pre_shutdown = &omap2_wd_timer_disable
1099 };
1100
1101 /* wd_timer2 */
1102 static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
1103 &omap2430_l4_wkup__wd_timer2,
1104 };
1105
1106 static struct omap_hwmod omap2430_wd_timer2_hwmod = {
1107 .name = "wd_timer2",
1108 .class = &omap2430_wd_timer_hwmod_class,
1109 .main_clk = "mpu_wdt_fck",
1110 .prcm = {
1111 .omap2 = {
1112 .prcm_reg_id = 1,
1113 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1114 .module_offs = WKUP_MOD,
1115 .idlest_reg_id = 1,
1116 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
1117 },
1118 },
1119 .slaves = omap2430_wd_timer2_slaves,
1120 .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves),
1121 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1122 };
1123
1124 /* UART */
1125
1126 static struct omap_hwmod_class_sysconfig uart_sysc = {
1127 .rev_offs = 0x50,
1128 .sysc_offs = 0x54,
1129 .syss_offs = 0x58,
1130 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1131 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1132 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1133 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1134 .sysc_fields = &omap_hwmod_sysc_type1,
1135 };
1136
1137 static struct omap_hwmod_class uart_class = {
1138 .name = "uart",
1139 .sysc = &uart_sysc,
1140 };
1141
1142 /* UART1 */
1143
1144 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1145 { .irq = INT_24XX_UART1_IRQ, },
1146 };
1147
1148 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1149 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1150 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1151 };
1152
1153 static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
1154 &omap2_l4_core__uart1,
1155 };
1156
1157 static struct omap_hwmod omap2430_uart1_hwmod = {
1158 .name = "uart1",
1159 .mpu_irqs = uart1_mpu_irqs,
1160 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
1161 .sdma_reqs = uart1_sdma_reqs,
1162 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1163 .main_clk = "uart1_fck",
1164 .prcm = {
1165 .omap2 = {
1166 .module_offs = CORE_MOD,
1167 .prcm_reg_id = 1,
1168 .module_bit = OMAP24XX_EN_UART1_SHIFT,
1169 .idlest_reg_id = 1,
1170 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
1171 },
1172 },
1173 .slaves = omap2430_uart1_slaves,
1174 .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
1175 .class = &uart_class,
1176 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1177 };
1178
1179 /* UART2 */
1180
1181 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1182 { .irq = INT_24XX_UART2_IRQ, },
1183 };
1184
1185 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1186 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1187 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1188 };
1189
1190 static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
1191 &omap2_l4_core__uart2,
1192 };
1193
1194 static struct omap_hwmod omap2430_uart2_hwmod = {
1195 .name = "uart2",
1196 .mpu_irqs = uart2_mpu_irqs,
1197 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
1198 .sdma_reqs = uart2_sdma_reqs,
1199 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1200 .main_clk = "uart2_fck",
1201 .prcm = {
1202 .omap2 = {
1203 .module_offs = CORE_MOD,
1204 .prcm_reg_id = 1,
1205 .module_bit = OMAP24XX_EN_UART2_SHIFT,
1206 .idlest_reg_id = 1,
1207 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
1208 },
1209 },
1210 .slaves = omap2430_uart2_slaves,
1211 .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
1212 .class = &uart_class,
1213 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1214 };
1215
1216 /* UART3 */
1217
1218 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1219 { .irq = INT_24XX_UART3_IRQ, },
1220 };
1221
1222 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1223 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1224 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1225 };
1226
1227 static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
1228 &omap2_l4_core__uart3,
1229 };
1230
1231 static struct omap_hwmod omap2430_uart3_hwmod = {
1232 .name = "uart3",
1233 .mpu_irqs = uart3_mpu_irqs,
1234 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
1235 .sdma_reqs = uart3_sdma_reqs,
1236 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1237 .main_clk = "uart3_fck",
1238 .prcm = {
1239 .omap2 = {
1240 .module_offs = CORE_MOD,
1241 .prcm_reg_id = 2,
1242 .module_bit = OMAP24XX_EN_UART3_SHIFT,
1243 .idlest_reg_id = 2,
1244 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
1245 },
1246 },
1247 .slaves = omap2430_uart3_slaves,
1248 .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
1249 .class = &uart_class,
1250 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1251 };
1252
1253 /*
1254 * 'dss' class
1255 * display sub-system
1256 */
1257
1258 static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
1259 .rev_offs = 0x0000,
1260 .sysc_offs = 0x0010,
1261 .syss_offs = 0x0014,
1262 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1263 .sysc_fields = &omap_hwmod_sysc_type1,
1264 };
1265
1266 static struct omap_hwmod_class omap2430_dss_hwmod_class = {
1267 .name = "dss",
1268 .sysc = &omap2430_dss_sysc,
1269 };
1270
1271 static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
1272 { .name = "dispc", .dma_req = 5 },
1273 };
1274
1275 /* dss */
1276 /* dss master ports */
1277 static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
1278 &omap2430_dss__l3,
1279 };
1280
1281 static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
1282 {
1283 .pa_start = 0x48050000,
1284 .pa_end = 0x480503FF,
1285 .flags = ADDR_TYPE_RT
1286 },
1287 };
1288
1289 /* l4_core -> dss */
1290 static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
1291 .master = &omap2430_l4_core_hwmod,
1292 .slave = &omap2430_dss_core_hwmod,
1293 .clk = "dss_ick",
1294 .addr = omap2430_dss_addrs,
1295 .addr_cnt = ARRAY_SIZE(omap2430_dss_addrs),
1296 .user = OCP_USER_MPU | OCP_USER_SDMA,
1297 };
1298
1299 /* dss slave ports */
1300 static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
1301 &omap2430_l4_core__dss,
1302 };
1303
1304 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1305 { .role = "dss_clk", .clk = "dss1_fck" },
1306 { .role = "tv_clk", .clk = "dss_54m_fck" },
1307 { .role = "sys_clk", .clk = "dss2_fck" },
1308 };
1309
1310 static struct omap_hwmod omap2430_dss_core_hwmod = {
1311 .name = "dss_core",
1312 .class = &omap2430_dss_hwmod_class,
1313 .main_clk = "dss1_fck", /* instead of dss_fck */
1314 .sdma_reqs = omap2430_dss_sdma_chs,
1315 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs),
1316 .prcm = {
1317 .omap2 = {
1318 .prcm_reg_id = 1,
1319 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1320 .module_offs = CORE_MOD,
1321 .idlest_reg_id = 1,
1322 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1323 },
1324 },
1325 .opt_clks = dss_opt_clks,
1326 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1327 .slaves = omap2430_dss_slaves,
1328 .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),
1329 .masters = omap2430_dss_masters,
1330 .masters_cnt = ARRAY_SIZE(omap2430_dss_masters),
1331 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1332 .flags = HWMOD_NO_IDLEST,
1333 };
1334
1335 /*
1336 * 'dispc' class
1337 * display controller
1338 */
1339
1340 static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
1341 .rev_offs = 0x0000,
1342 .sysc_offs = 0x0010,
1343 .syss_offs = 0x0014,
1344 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1345 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1346 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1347 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1348 .sysc_fields = &omap_hwmod_sysc_type1,
1349 };
1350
1351 static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
1352 .name = "dispc",
1353 .sysc = &omap2430_dispc_sysc,
1354 };
1355
1356 static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = {
1357 { .irq = 25 },
1358 };
1359
1360 static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
1361 {
1362 .pa_start = 0x48050400,
1363 .pa_end = 0x480507FF,
1364 .flags = ADDR_TYPE_RT
1365 },
1366 };
1367
1368 /* l4_core -> dss_dispc */
1369 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
1370 .master = &omap2430_l4_core_hwmod,
1371 .slave = &omap2430_dss_dispc_hwmod,
1372 .clk = "dss_ick",
1373 .addr = omap2430_dss_dispc_addrs,
1374 .addr_cnt = ARRAY_SIZE(omap2430_dss_dispc_addrs),
1375 .user = OCP_USER_MPU | OCP_USER_SDMA,
1376 };
1377
1378 /* dss_dispc slave ports */
1379 static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
1380 &omap2430_l4_core__dss_dispc,
1381 };
1382
1383 static struct omap_hwmod_opt_clk dispc_opt_clks[] = {
1384 { .role = "dss_clk", .clk = "dss1_fck" },
1385 };
1386
1387 static struct omap_hwmod omap2430_dss_dispc_hwmod = {
1388 .name = "dss_dispc",
1389 .class = &omap2430_dispc_hwmod_class,
1390 .mpu_irqs = omap2430_dispc_irqs,
1391 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dispc_irqs),
1392 .main_clk = "dss1_fck",
1393 .prcm = {
1394 .omap2 = {
1395 .prcm_reg_id = 1,
1396 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1397 .module_offs = CORE_MOD,
1398 .idlest_reg_id = 1,
1399 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1400 },
1401 },
1402 .opt_clks = dispc_opt_clks,
1403 .opt_clks_cnt = ARRAY_SIZE(dispc_opt_clks),
1404 .slaves = omap2430_dss_dispc_slaves,
1405 .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1406 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1407 .flags = HWMOD_NO_IDLEST,
1408 };
1409
1410 /*
1411 * 'rfbi' class
1412 * remote frame buffer interface
1413 */
1414
1415 static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
1416 .rev_offs = 0x0000,
1417 .sysc_offs = 0x0010,
1418 .syss_offs = 0x0014,
1419 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1420 SYSC_HAS_AUTOIDLE),
1421 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1422 .sysc_fields = &omap_hwmod_sysc_type1,
1423 };
1424
1425 static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
1426 .name = "rfbi",
1427 .sysc = &omap2430_rfbi_sysc,
1428 };
1429
1430 static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
1431 {
1432 .pa_start = 0x48050800,
1433 .pa_end = 0x48050BFF,
1434 .flags = ADDR_TYPE_RT
1435 },
1436 };
1437
1438 /* l4_core -> dss_rfbi */
1439 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1440 .master = &omap2430_l4_core_hwmod,
1441 .slave = &omap2430_dss_rfbi_hwmod,
1442 .clk = "dss_ick",
1443 .addr = omap2430_dss_rfbi_addrs,
1444 .addr_cnt = ARRAY_SIZE(omap2430_dss_rfbi_addrs),
1445 .user = OCP_USER_MPU | OCP_USER_SDMA,
1446 };
1447
1448 /* dss_rfbi slave ports */
1449 static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1450 &omap2430_l4_core__dss_rfbi,
1451 };
1452
1453 static struct omap_hwmod_opt_clk rfbi_opt_clks[] = {
1454 { .role = "rfbi_iclk", .clk = "dss_ick" },
1455 };
1456
1457 static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1458 .name = "dss_rfbi",
1459 .class = &omap2430_rfbi_hwmod_class,
1460 .main_clk = "dss1_fck",
1461 .prcm = {
1462 .omap2 = {
1463 .prcm_reg_id = 1,
1464 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1465 .module_offs = CORE_MOD,
1466 },
1467 },
1468 .opt_clks = rfbi_opt_clks,
1469 .opt_clks_cnt = ARRAY_SIZE(rfbi_opt_clks),
1470 .slaves = omap2430_dss_rfbi_slaves,
1471 .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1472 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1473 .flags = HWMOD_NO_IDLEST,
1474 };
1475
1476 /*
1477 * 'venc' class
1478 * video encoder
1479 */
1480
1481 static struct omap_hwmod_class omap2430_venc_hwmod_class = {
1482 .name = "venc",
1483 };
1484
1485 /* dss_venc */
1486 static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
1487 {
1488 .pa_start = 0x48050C00,
1489 .pa_end = 0x48050FFF,
1490 .flags = ADDR_TYPE_RT
1491 },
1492 };
1493
1494 /* l4_core -> dss_venc */
1495 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1496 .master = &omap2430_l4_core_hwmod,
1497 .slave = &omap2430_dss_venc_hwmod,
1498 .clk = "dss_54m_fck",
1499 .addr = omap2430_dss_venc_addrs,
1500 .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs),
1501 .flags = OCPIF_SWSUP_IDLE,
1502 .user = OCP_USER_MPU | OCP_USER_SDMA,
1503 };
1504
1505 /* dss_venc slave ports */
1506 static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1507 &omap2430_l4_core__dss_venc,
1508 };
1509
1510 static struct omap_hwmod_opt_clk venc_opt_clks[] = {
1511 { .role = "tv_clk", .clk = "dss_54m_fck" },
1512 };
1513
1514 static struct omap_hwmod omap2430_dss_venc_hwmod = {
1515 .name = "dss_venc",
1516 .class = &omap2430_venc_hwmod_class,
1517 .main_clk = "dss1_fck",
1518 .prcm = {
1519 .omap2 = {
1520 .prcm_reg_id = 1,
1521 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1522 .module_offs = CORE_MOD,
1523 },
1524 },
1525 .opt_clks = venc_opt_clks,
1526 .opt_clks_cnt = ARRAY_SIZE(venc_opt_clks),
1527 .slaves = omap2430_dss_venc_slaves,
1528 .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves),
1529 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1530 .flags = HWMOD_NO_IDLEST,
1531 };
1532
1533 /* I2C common */
1534 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1535 .rev_offs = 0x00,
1536 .sysc_offs = 0x20,
1537 .syss_offs = 0x10,
1538 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1539 SYSS_HAS_RESET_STATUS),
1540 .sysc_fields = &omap_hwmod_sysc_type1,
1541 };
1542
1543 static struct omap_hwmod_class i2c_class = {
1544 .name = "i2c",
1545 .sysc = &i2c_sysc,
1546 .rev = OMAP_I2C_IP_VERSION_1,
1547 .reset = &omap_i2c_reset,
1548 };
1549
1550 static struct omap_i2c_dev_attr i2c_dev_attr = {
1551 .fifo_depth = 8, /* bytes */
1552 };
1553
1554 /* I2C1 */
1555
1556 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1557 { .irq = INT_24XX_I2C1_IRQ, },
1558 };
1559
1560 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1561 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1562 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1563 };
1564
1565 static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
1566 &omap2430_l4_core__i2c1,
1567 };
1568
1569 static struct omap_hwmod omap2430_i2c1_hwmod = {
1570 .name = "i2c1",
1571 .mpu_irqs = i2c1_mpu_irqs,
1572 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
1573 .sdma_reqs = i2c1_sdma_reqs,
1574 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1575 .main_clk = "i2chs1_fck",
1576 .prcm = {
1577 .omap2 = {
1578 /*
1579 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
1580 * I2CHS IP's do not follow the usual pattern.
1581 * prcm_reg_id alone cannot be used to program
1582 * the iclk and fclk. Needs to be handled using
1583 * additional flags when clk handling is moved
1584 * to hwmod framework.
1585 */
1586 .module_offs = CORE_MOD,
1587 .prcm_reg_id = 1,
1588 .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
1589 .idlest_reg_id = 1,
1590 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
1591 },
1592 },
1593 .slaves = omap2430_i2c1_slaves,
1594 .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves),
1595 .class = &i2c_class,
1596 .dev_attr = &i2c_dev_attr,
1597 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1598 };
1599
1600 /* I2C2 */
1601
1602 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1603 { .irq = INT_24XX_I2C2_IRQ, },
1604 };
1605
1606 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1607 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1608 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1609 };
1610
1611 static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
1612 &omap2430_l4_core__i2c2,
1613 };
1614
1615 static struct omap_hwmod omap2430_i2c2_hwmod = {
1616 .name = "i2c2",
1617 .mpu_irqs = i2c2_mpu_irqs,
1618 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
1619 .sdma_reqs = i2c2_sdma_reqs,
1620 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1621 .main_clk = "i2chs2_fck",
1622 .prcm = {
1623 .omap2 = {
1624 .module_offs = CORE_MOD,
1625 .prcm_reg_id = 1,
1626 .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
1627 .idlest_reg_id = 1,
1628 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
1629 },
1630 },
1631 .slaves = omap2430_i2c2_slaves,
1632 .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves),
1633 .class = &i2c_class,
1634 .dev_attr = &i2c_dev_attr,
1635 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1636 };
1637
1638 /* l4_wkup -> gpio1 */
1639 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
1640 {
1641 .pa_start = 0x4900C000,
1642 .pa_end = 0x4900C1ff,
1643 .flags = ADDR_TYPE_RT
1644 },
1645 };
1646
1647 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
1648 .master = &omap2430_l4_wkup_hwmod,
1649 .slave = &omap2430_gpio1_hwmod,
1650 .clk = "gpios_ick",
1651 .addr = omap2430_gpio1_addr_space,
1652 .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space),
1653 .user = OCP_USER_MPU | OCP_USER_SDMA,
1654 };
1655
1656 /* l4_wkup -> gpio2 */
1657 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
1658 {
1659 .pa_start = 0x4900E000,
1660 .pa_end = 0x4900E1ff,
1661 .flags = ADDR_TYPE_RT
1662 },
1663 };
1664
1665 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
1666 .master = &omap2430_l4_wkup_hwmod,
1667 .slave = &omap2430_gpio2_hwmod,
1668 .clk = "gpios_ick",
1669 .addr = omap2430_gpio2_addr_space,
1670 .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space),
1671 .user = OCP_USER_MPU | OCP_USER_SDMA,
1672 };
1673
1674 /* l4_wkup -> gpio3 */
1675 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
1676 {
1677 .pa_start = 0x49010000,
1678 .pa_end = 0x490101ff,
1679 .flags = ADDR_TYPE_RT
1680 },
1681 };
1682
1683 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1684 .master = &omap2430_l4_wkup_hwmod,
1685 .slave = &omap2430_gpio3_hwmod,
1686 .clk = "gpios_ick",
1687 .addr = omap2430_gpio3_addr_space,
1688 .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space),
1689 .user = OCP_USER_MPU | OCP_USER_SDMA,
1690 };
1691
1692 /* l4_wkup -> gpio4 */
1693 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1694 {
1695 .pa_start = 0x49012000,
1696 .pa_end = 0x490121ff,
1697 .flags = ADDR_TYPE_RT
1698 },
1699 };
1700
1701 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1702 .master = &omap2430_l4_wkup_hwmod,
1703 .slave = &omap2430_gpio4_hwmod,
1704 .clk = "gpios_ick",
1705 .addr = omap2430_gpio4_addr_space,
1706 .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space),
1707 .user = OCP_USER_MPU | OCP_USER_SDMA,
1708 };
1709
1710 /* l4_core -> gpio5 */
1711 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1712 {
1713 .pa_start = 0x480B6000,
1714 .pa_end = 0x480B61ff,
1715 .flags = ADDR_TYPE_RT
1716 },
1717 };
1718
1719 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1720 .master = &omap2430_l4_core_hwmod,
1721 .slave = &omap2430_gpio5_hwmod,
1722 .clk = "gpio5_ick",
1723 .addr = omap2430_gpio5_addr_space,
1724 .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space),
1725 .user = OCP_USER_MPU | OCP_USER_SDMA,
1726 };
1727
1728 /* gpio dev_attr */
1729 static struct omap_gpio_dev_attr gpio_dev_attr = {
1730 .bank_width = 32,
1731 .dbck_flag = false,
1732 };
1733
1734 static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
1735 .rev_offs = 0x0000,
1736 .sysc_offs = 0x0010,
1737 .syss_offs = 0x0014,
1738 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1739 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1740 SYSS_HAS_RESET_STATUS),
1741 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1742 .sysc_fields = &omap_hwmod_sysc_type1,
1743 };
1744
1745 /*
1746 * 'gpio' class
1747 * general purpose io module
1748 */
1749 static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
1750 .name = "gpio",
1751 .sysc = &omap243x_gpio_sysc,
1752 .rev = 0,
1753 };
1754
1755 /* gpio1 */
1756 static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
1757 { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
1758 };
1759
1760 static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1761 &omap2430_l4_wkup__gpio1,
1762 };
1763
1764 static struct omap_hwmod omap2430_gpio1_hwmod = {
1765 .name = "gpio1",
1766 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1767 .mpu_irqs = omap243x_gpio1_irqs,
1768 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs),
1769 .main_clk = "gpios_fck",
1770 .prcm = {
1771 .omap2 = {
1772 .prcm_reg_id = 1,
1773 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1774 .module_offs = WKUP_MOD,
1775 .idlest_reg_id = 1,
1776 .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
1777 },
1778 },
1779 .slaves = omap2430_gpio1_slaves,
1780 .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
1781 .class = &omap243x_gpio_hwmod_class,
1782 .dev_attr = &gpio_dev_attr,
1783 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1784 };
1785
1786 /* gpio2 */
1787 static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
1788 { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
1789 };
1790
1791 static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1792 &omap2430_l4_wkup__gpio2,
1793 };
1794
1795 static struct omap_hwmod omap2430_gpio2_hwmod = {
1796 .name = "gpio2",
1797 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1798 .mpu_irqs = omap243x_gpio2_irqs,
1799 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs),
1800 .main_clk = "gpios_fck",
1801 .prcm = {
1802 .omap2 = {
1803 .prcm_reg_id = 1,
1804 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1805 .module_offs = WKUP_MOD,
1806 .idlest_reg_id = 1,
1807 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1808 },
1809 },
1810 .slaves = omap2430_gpio2_slaves,
1811 .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
1812 .class = &omap243x_gpio_hwmod_class,
1813 .dev_attr = &gpio_dev_attr,
1814 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1815 };
1816
1817 /* gpio3 */
1818 static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
1819 { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
1820 };
1821
1822 static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1823 &omap2430_l4_wkup__gpio3,
1824 };
1825
1826 static struct omap_hwmod omap2430_gpio3_hwmod = {
1827 .name = "gpio3",
1828 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1829 .mpu_irqs = omap243x_gpio3_irqs,
1830 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs),
1831 .main_clk = "gpios_fck",
1832 .prcm = {
1833 .omap2 = {
1834 .prcm_reg_id = 1,
1835 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1836 .module_offs = WKUP_MOD,
1837 .idlest_reg_id = 1,
1838 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1839 },
1840 },
1841 .slaves = omap2430_gpio3_slaves,
1842 .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
1843 .class = &omap243x_gpio_hwmod_class,
1844 .dev_attr = &gpio_dev_attr,
1845 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1846 };
1847
1848 /* gpio4 */
1849 static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
1850 { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
1851 };
1852
1853 static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1854 &omap2430_l4_wkup__gpio4,
1855 };
1856
1857 static struct omap_hwmod omap2430_gpio4_hwmod = {
1858 .name = "gpio4",
1859 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1860 .mpu_irqs = omap243x_gpio4_irqs,
1861 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs),
1862 .main_clk = "gpios_fck",
1863 .prcm = {
1864 .omap2 = {
1865 .prcm_reg_id = 1,
1866 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1867 .module_offs = WKUP_MOD,
1868 .idlest_reg_id = 1,
1869 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1870 },
1871 },
1872 .slaves = omap2430_gpio4_slaves,
1873 .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
1874 .class = &omap243x_gpio_hwmod_class,
1875 .dev_attr = &gpio_dev_attr,
1876 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1877 };
1878
1879 /* gpio5 */
1880 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1881 { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1882 };
1883
1884 static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
1885 &omap2430_l4_core__gpio5,
1886 };
1887
1888 static struct omap_hwmod omap2430_gpio5_hwmod = {
1889 .name = "gpio5",
1890 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1891 .mpu_irqs = omap243x_gpio5_irqs,
1892 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs),
1893 .main_clk = "gpio5_fck",
1894 .prcm = {
1895 .omap2 = {
1896 .prcm_reg_id = 2,
1897 .module_bit = OMAP2430_EN_GPIO5_SHIFT,
1898 .module_offs = CORE_MOD,
1899 .idlest_reg_id = 2,
1900 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
1901 },
1902 },
1903 .slaves = omap2430_gpio5_slaves,
1904 .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
1905 .class = &omap243x_gpio_hwmod_class,
1906 .dev_attr = &gpio_dev_attr,
1907 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1908 };
1909
1910 /* dma_system */
1911 static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
1912 .rev_offs = 0x0000,
1913 .sysc_offs = 0x002c,
1914 .syss_offs = 0x0028,
1915 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1916 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1917 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1918 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1919 .sysc_fields = &omap_hwmod_sysc_type1,
1920 };
1921
1922 static struct omap_hwmod_class omap2430_dma_hwmod_class = {
1923 .name = "dma",
1924 .sysc = &omap2430_dma_sysc,
1925 };
1926
1927 /* dma attributes */
1928 static struct omap_dma_dev_attr dma_dev_attr = {
1929 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1930 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1931 .lch_count = 32,
1932 };
1933
1934 static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
1935 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1936 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1937 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1938 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1939 };
1940
1941 static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
1942 {
1943 .pa_start = 0x48056000,
1944 .pa_end = 0x48056fff,
1945 .flags = ADDR_TYPE_RT
1946 },
1947 };
1948
1949 /* dma_system -> L3 */
1950 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1951 .master = &omap2430_dma_system_hwmod,
1952 .slave = &omap2430_l3_main_hwmod,
1953 .clk = "core_l3_ck",
1954 .user = OCP_USER_MPU | OCP_USER_SDMA,
1955 };
1956
1957 /* dma_system master ports */
1958 static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
1959 &omap2430_dma_system__l3,
1960 };
1961
1962 /* l4_core -> dma_system */
1963 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1964 .master = &omap2430_l4_core_hwmod,
1965 .slave = &omap2430_dma_system_hwmod,
1966 .clk = "sdma_ick",
1967 .addr = omap2430_dma_system_addrs,
1968 .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs),
1969 .user = OCP_USER_MPU | OCP_USER_SDMA,
1970 };
1971
1972 /* dma_system slave ports */
1973 static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1974 &omap2430_l4_core__dma_system,
1975 };
1976
1977 static struct omap_hwmod omap2430_dma_system_hwmod = {
1978 .name = "dma",
1979 .class = &omap2430_dma_hwmod_class,
1980 .mpu_irqs = omap2430_dma_system_irqs,
1981 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs),
1982 .main_clk = "core_l3_ck",
1983 .slaves = omap2430_dma_system_slaves,
1984 .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
1985 .masters = omap2430_dma_system_masters,
1986 .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters),
1987 .dev_attr = &dma_dev_attr,
1988 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1989 .flags = HWMOD_NO_IDLEST,
1990 };
1991
1992 /*
1993 * 'mailbox' class
1994 * mailbox module allowing communication between the on-chip processors
1995 * using a queued mailbox-interrupt mechanism.
1996 */
1997
1998 static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
1999 .rev_offs = 0x000,
2000 .sysc_offs = 0x010,
2001 .syss_offs = 0x014,
2002 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2003 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2004 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2005 .sysc_fields = &omap_hwmod_sysc_type1,
2006 };
2007
2008 static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
2009 .name = "mailbox",
2010 .sysc = &omap2430_mailbox_sysc,
2011 };
2012
2013 /* mailbox */
2014 static struct omap_hwmod omap2430_mailbox_hwmod;
2015 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
2016 { .irq = 26 },
2017 };
2018
2019 static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
2020 {
2021 .pa_start = 0x48094000,
2022 .pa_end = 0x480941ff,
2023 .flags = ADDR_TYPE_RT,
2024 },
2025 };
2026
2027 /* l4_core -> mailbox */
2028 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
2029 .master = &omap2430_l4_core_hwmod,
2030 .slave = &omap2430_mailbox_hwmod,
2031 .addr = omap2430_mailbox_addrs,
2032 .addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs),
2033 .user = OCP_USER_MPU | OCP_USER_SDMA,
2034 };
2035
2036 /* mailbox slave ports */
2037 static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
2038 &omap2430_l4_core__mailbox,
2039 };
2040
2041 static struct omap_hwmod omap2430_mailbox_hwmod = {
2042 .name = "mailbox",
2043 .class = &omap2430_mailbox_hwmod_class,
2044 .mpu_irqs = omap2430_mailbox_irqs,
2045 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs),
2046 .main_clk = "mailboxes_ick",
2047 .prcm = {
2048 .omap2 = {
2049 .prcm_reg_id = 1,
2050 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2051 .module_offs = CORE_MOD,
2052 .idlest_reg_id = 1,
2053 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
2054 },
2055 },
2056 .slaves = omap2430_mailbox_slaves,
2057 .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves),
2058 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2059 };
2060
2061 /*
2062 * 'mcspi' class
2063 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2064 * bus
2065 */
2066
2067 static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
2068 .rev_offs = 0x0000,
2069 .sysc_offs = 0x0010,
2070 .syss_offs = 0x0014,
2071 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2072 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2073 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2074 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2075 .sysc_fields = &omap_hwmod_sysc_type1,
2076 };
2077
2078 static struct omap_hwmod_class omap2430_mcspi_class = {
2079 .name = "mcspi",
2080 .sysc = &omap2430_mcspi_sysc,
2081 .rev = OMAP2_MCSPI_REV,
2082 };
2083
2084 /* mcspi1 */
2085 static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
2086 { .irq = 65 },
2087 };
2088
2089 static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
2090 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
2091 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
2092 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
2093 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
2094 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
2095 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
2096 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
2097 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
2098 };
2099
2100 static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
2101 &omap2430_l4_core__mcspi1,
2102 };
2103
2104 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2105 .num_chipselect = 4,
2106 };
2107
2108 static struct omap_hwmod omap2430_mcspi1_hwmod = {
2109 .name = "mcspi1_hwmod",
2110 .mpu_irqs = omap2430_mcspi1_mpu_irqs,
2111 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
2112 .sdma_reqs = omap2430_mcspi1_sdma_reqs,
2113 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
2114 .main_clk = "mcspi1_fck",
2115 .prcm = {
2116 .omap2 = {
2117 .module_offs = CORE_MOD,
2118 .prcm_reg_id = 1,
2119 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
2120 .idlest_reg_id = 1,
2121 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
2122 },
2123 },
2124 .slaves = omap2430_mcspi1_slaves,
2125 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
2126 .class = &omap2430_mcspi_class,
2127 .dev_attr = &omap_mcspi1_dev_attr,
2128 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2129 };
2130
2131 /* mcspi2 */
2132 static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
2133 { .irq = 66 },
2134 };
2135
2136 static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
2137 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
2138 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
2139 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
2140 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
2141 };
2142
2143 static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
2144 &omap2430_l4_core__mcspi2,
2145 };
2146
2147 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2148 .num_chipselect = 2,
2149 };
2150
2151 static struct omap_hwmod omap2430_mcspi2_hwmod = {
2152 .name = "mcspi2_hwmod",
2153 .mpu_irqs = omap2430_mcspi2_mpu_irqs,
2154 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
2155 .sdma_reqs = omap2430_mcspi2_sdma_reqs,
2156 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
2157 .main_clk = "mcspi2_fck",
2158 .prcm = {
2159 .omap2 = {
2160 .module_offs = CORE_MOD,
2161 .prcm_reg_id = 1,
2162 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
2163 .idlest_reg_id = 1,
2164 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
2165 },
2166 },
2167 .slaves = omap2430_mcspi2_slaves,
2168 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
2169 .class = &omap2430_mcspi_class,
2170 .dev_attr = &omap_mcspi2_dev_attr,
2171 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2172 };
2173
2174 /* mcspi3 */
2175 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
2176 { .irq = 91 },
2177 };
2178
2179 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
2180 { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
2181 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
2182 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
2183 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
2184 };
2185
2186 static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
2187 &omap2430_l4_core__mcspi3,
2188 };
2189
2190 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2191 .num_chipselect = 2,
2192 };
2193
2194 static struct omap_hwmod omap2430_mcspi3_hwmod = {
2195 .name = "mcspi3_hwmod",
2196 .mpu_irqs = omap2430_mcspi3_mpu_irqs,
2197 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
2198 .sdma_reqs = omap2430_mcspi3_sdma_reqs,
2199 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
2200 .main_clk = "mcspi3_fck",
2201 .prcm = {
2202 .omap2 = {
2203 .module_offs = CORE_MOD,
2204 .prcm_reg_id = 2,
2205 .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
2206 .idlest_reg_id = 2,
2207 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
2208 },
2209 },
2210 .slaves = omap2430_mcspi3_slaves,
2211 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
2212 .class = &omap2430_mcspi_class,
2213 .dev_attr = &omap_mcspi3_dev_attr,
2214 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2215 };
2216
2217 /*
2218 * usbhsotg
2219 */
2220 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
2221 .rev_offs = 0x0400,
2222 .sysc_offs = 0x0404,
2223 .syss_offs = 0x0408,
2224 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2225 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2226 SYSC_HAS_AUTOIDLE),
2227 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2228 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2229 .sysc_fields = &omap_hwmod_sysc_type1,
2230 };
2231
2232 static struct omap_hwmod_class usbotg_class = {
2233 .name = "usbotg",
2234 .sysc = &omap2430_usbhsotg_sysc,
2235 };
2236
2237 /* usb_otg_hs */
2238 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
2239
2240 { .name = "mc", .irq = 92 },
2241 { .name = "dma", .irq = 93 },
2242 };
2243
2244 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
2245 .name = "usb_otg_hs",
2246 .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
2247 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
2248 .main_clk = "usbhs_ick",
2249 .prcm = {
2250 .omap2 = {
2251 .prcm_reg_id = 1,
2252 .module_bit = OMAP2430_EN_USBHS_MASK,
2253 .module_offs = CORE_MOD,
2254 .idlest_reg_id = 1,
2255 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
2256 },
2257 },
2258 .masters = omap2430_usbhsotg_masters,
2259 .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters),
2260 .slaves = omap2430_usbhsotg_slaves,
2261 .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves),
2262 .class = &usbotg_class,
2263 /*
2264 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
2265 * broken when autoidle is enabled
2266 * workaround is to disable the autoidle bit at module level.
2267 */
2268 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
2269 | HWMOD_SWSUP_MSTANDBY,
2270 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
2271 };
2272
2273 /*
2274 * 'mcbsp' class
2275 * multi channel buffered serial port controller
2276 */
2277
2278 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
2279 .rev_offs = 0x007C,
2280 .sysc_offs = 0x008C,
2281 .sysc_flags = (SYSC_HAS_SOFTRESET),
2282 .sysc_fields = &omap_hwmod_sysc_type1,
2283 };
2284
2285 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
2286 .name = "mcbsp",
2287 .sysc = &omap2430_mcbsp_sysc,
2288 .rev = MCBSP_CONFIG_TYPE2,
2289 };
2290
2291 /* mcbsp1 */
2292 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
2293 { .name = "tx", .irq = 59 },
2294 { .name = "rx", .irq = 60 },
2295 { .name = "ovr", .irq = 61 },
2296 { .name = "common", .irq = 64 },
2297 };
2298
2299 static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
2300 { .name = "rx", .dma_req = 32 },
2301 { .name = "tx", .dma_req = 31 },
2302 };
2303
2304 static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
2305 {
2306 .name = "mpu",
2307 .pa_start = 0x48074000,
2308 .pa_end = 0x480740ff,
2309 .flags = ADDR_TYPE_RT
2310 },
2311 };
2312
2313 /* l4_core -> mcbsp1 */
2314 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
2315 .master = &omap2430_l4_core_hwmod,
2316 .slave = &omap2430_mcbsp1_hwmod,
2317 .clk = "mcbsp1_ick",
2318 .addr = omap2430_mcbsp1_addrs,
2319 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp1_addrs),
2320 .user = OCP_USER_MPU | OCP_USER_SDMA,
2321 };
2322
2323 /* mcbsp1 slave ports */
2324 static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
2325 &omap2430_l4_core__mcbsp1,
2326 };
2327
2328 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
2329 .name = "mcbsp1",
2330 .class = &omap2430_mcbsp_hwmod_class,
2331 .mpu_irqs = omap2430_mcbsp1_irqs,
2332 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs),
2333 .sdma_reqs = omap2430_mcbsp1_sdma_chs,
2334 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
2335 .main_clk = "mcbsp1_fck",
2336 .prcm = {
2337 .omap2 = {
2338 .prcm_reg_id = 1,
2339 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
2340 .module_offs = CORE_MOD,
2341 .idlest_reg_id = 1,
2342 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
2343 },
2344 },
2345 .slaves = omap2430_mcbsp1_slaves,
2346 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves),
2347 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2348 };
2349
2350 /* mcbsp2 */
2351 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
2352 { .name = "tx", .irq = 62 },
2353 { .name = "rx", .irq = 63 },
2354 { .name = "common", .irq = 16 },
2355 };
2356
2357 static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
2358 { .name = "rx", .dma_req = 34 },
2359 { .name = "tx", .dma_req = 33 },
2360 };
2361
2362 static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
2363 {
2364 .name = "mpu",
2365 .pa_start = 0x48076000,
2366 .pa_end = 0x480760ff,
2367 .flags = ADDR_TYPE_RT
2368 },
2369 };
2370
2371 /* l4_core -> mcbsp2 */
2372 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
2373 .master = &omap2430_l4_core_hwmod,
2374 .slave = &omap2430_mcbsp2_hwmod,
2375 .clk = "mcbsp2_ick",
2376 .addr = omap2430_mcbsp2_addrs,
2377 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp2_addrs),
2378 .user = OCP_USER_MPU | OCP_USER_SDMA,
2379 };
2380
2381 /* mcbsp2 slave ports */
2382 static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
2383 &omap2430_l4_core__mcbsp2,
2384 };
2385
2386 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
2387 .name = "mcbsp2",
2388 .class = &omap2430_mcbsp_hwmod_class,
2389 .mpu_irqs = omap2430_mcbsp2_irqs,
2390 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_irqs),
2391 .sdma_reqs = omap2430_mcbsp2_sdma_chs,
2392 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
2393 .main_clk = "mcbsp2_fck",
2394 .prcm = {
2395 .omap2 = {
2396 .prcm_reg_id = 1,
2397 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
2398 .module_offs = CORE_MOD,
2399 .idlest_reg_id = 1,
2400 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
2401 },
2402 },
2403 .slaves = omap2430_mcbsp2_slaves,
2404 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves),
2405 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2406 };
2407
2408 /* mcbsp3 */
2409 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
2410 { .name = "tx", .irq = 89 },
2411 { .name = "rx", .irq = 90 },
2412 { .name = "common", .irq = 17 },
2413 };
2414
2415 static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
2416 { .name = "rx", .dma_req = 18 },
2417 { .name = "tx", .dma_req = 17 },
2418 };
2419
2420 static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
2421 {
2422 .name = "mpu",
2423 .pa_start = 0x4808C000,
2424 .pa_end = 0x4808C0ff,
2425 .flags = ADDR_TYPE_RT
2426 },
2427 };
2428
2429 /* l4_core -> mcbsp3 */
2430 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
2431 .master = &omap2430_l4_core_hwmod,
2432 .slave = &omap2430_mcbsp3_hwmod,
2433 .clk = "mcbsp3_ick",
2434 .addr = omap2430_mcbsp3_addrs,
2435 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp3_addrs),
2436 .user = OCP_USER_MPU | OCP_USER_SDMA,
2437 };
2438
2439 /* mcbsp3 slave ports */
2440 static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
2441 &omap2430_l4_core__mcbsp3,
2442 };
2443
2444 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
2445 .name = "mcbsp3",
2446 .class = &omap2430_mcbsp_hwmod_class,
2447 .mpu_irqs = omap2430_mcbsp3_irqs,
2448 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_irqs),
2449 .sdma_reqs = omap2430_mcbsp3_sdma_chs,
2450 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
2451 .main_clk = "mcbsp3_fck",
2452 .prcm = {
2453 .omap2 = {
2454 .prcm_reg_id = 1,
2455 .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
2456 .module_offs = CORE_MOD,
2457 .idlest_reg_id = 2,
2458 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
2459 },
2460 },
2461 .slaves = omap2430_mcbsp3_slaves,
2462 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves),
2463 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2464 };
2465
2466 /* mcbsp4 */
2467 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
2468 { .name = "tx", .irq = 54 },
2469 { .name = "rx", .irq = 55 },
2470 { .name = "common", .irq = 18 },
2471 };
2472
2473 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
2474 { .name = "rx", .dma_req = 20 },
2475 { .name = "tx", .dma_req = 19 },
2476 };
2477
2478 static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
2479 {
2480 .name = "mpu",
2481 .pa_start = 0x4808E000,
2482 .pa_end = 0x4808E0ff,
2483 .flags = ADDR_TYPE_RT
2484 },
2485 };
2486
2487 /* l4_core -> mcbsp4 */
2488 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
2489 .master = &omap2430_l4_core_hwmod,
2490 .slave = &omap2430_mcbsp4_hwmod,
2491 .clk = "mcbsp4_ick",
2492 .addr = omap2430_mcbsp4_addrs,
2493 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp4_addrs),
2494 .user = OCP_USER_MPU | OCP_USER_SDMA,
2495 };
2496
2497 /* mcbsp4 slave ports */
2498 static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
2499 &omap2430_l4_core__mcbsp4,
2500 };
2501
2502 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
2503 .name = "mcbsp4",
2504 .class = &omap2430_mcbsp_hwmod_class,
2505 .mpu_irqs = omap2430_mcbsp4_irqs,
2506 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_irqs),
2507 .sdma_reqs = omap2430_mcbsp4_sdma_chs,
2508 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
2509 .main_clk = "mcbsp4_fck",
2510 .prcm = {
2511 .omap2 = {
2512 .prcm_reg_id = 1,
2513 .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
2514 .module_offs = CORE_MOD,
2515 .idlest_reg_id = 2,
2516 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
2517 },
2518 },
2519 .slaves = omap2430_mcbsp4_slaves,
2520 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves),
2521 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2522 };
2523
2524 /* mcbsp5 */
2525 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
2526 { .name = "tx", .irq = 81 },
2527 { .name = "rx", .irq = 82 },
2528 { .name = "common", .irq = 19 },
2529 };
2530
2531 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
2532 { .name = "rx", .dma_req = 22 },
2533 { .name = "tx", .dma_req = 21 },
2534 };
2535
2536 static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
2537 {
2538 .name = "mpu",
2539 .pa_start = 0x48096000,
2540 .pa_end = 0x480960ff,
2541 .flags = ADDR_TYPE_RT
2542 },
2543 };
2544
2545 /* l4_core -> mcbsp5 */
2546 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
2547 .master = &omap2430_l4_core_hwmod,
2548 .slave = &omap2430_mcbsp5_hwmod,
2549 .clk = "mcbsp5_ick",
2550 .addr = omap2430_mcbsp5_addrs,
2551 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp5_addrs),
2552 .user = OCP_USER_MPU | OCP_USER_SDMA,
2553 };
2554
2555 /* mcbsp5 slave ports */
2556 static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
2557 &omap2430_l4_core__mcbsp5,
2558 };
2559
2560 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
2561 .name = "mcbsp5",
2562 .class = &omap2430_mcbsp_hwmod_class,
2563 .mpu_irqs = omap2430_mcbsp5_irqs,
2564 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_irqs),
2565 .sdma_reqs = omap2430_mcbsp5_sdma_chs,
2566 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
2567 .main_clk = "mcbsp5_fck",
2568 .prcm = {
2569 .omap2 = {
2570 .prcm_reg_id = 1,
2571 .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
2572 .module_offs = CORE_MOD,
2573 .idlest_reg_id = 2,
2574 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
2575 },
2576 },
2577 .slaves = omap2430_mcbsp5_slaves,
2578 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves),
2579 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2580 };
2581
2582 /* MMC/SD/SDIO common */
2583
2584 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
2585 .rev_offs = 0x1fc,
2586 .sysc_offs = 0x10,
2587 .syss_offs = 0x14,
2588 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2589 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2590 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2591 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2592 .sysc_fields = &omap_hwmod_sysc_type1,
2593 };
2594
2595 static struct omap_hwmod_class omap2430_mmc_class = {
2596 .name = "mmc",
2597 .sysc = &omap2430_mmc_sysc,
2598 };
2599
2600 /* MMC/SD/SDIO1 */
2601
2602 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
2603 { .irq = 83 },
2604 };
2605
2606 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
2607 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
2608 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
2609 };
2610
2611 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
2612 { .role = "dbck", .clk = "mmchsdb1_fck" },
2613 };
2614
2615 static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
2616 &omap2430_l4_core__mmc1,
2617 };
2618
2619 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2620 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2621 };
2622
2623 static struct omap_hwmod omap2430_mmc1_hwmod = {
2624 .name = "mmc1",
2625 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2626 .mpu_irqs = omap2430_mmc1_mpu_irqs,
2627 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
2628 .sdma_reqs = omap2430_mmc1_sdma_reqs,
2629 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
2630 .opt_clks = omap2430_mmc1_opt_clks,
2631 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
2632 .main_clk = "mmchs1_fck",
2633 .prcm = {
2634 .omap2 = {
2635 .module_offs = CORE_MOD,
2636 .prcm_reg_id = 2,
2637 .module_bit = OMAP2430_EN_MMCHS1_SHIFT,
2638 .idlest_reg_id = 2,
2639 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
2640 },
2641 },
2642 .dev_attr = &mmc1_dev_attr,
2643 .slaves = omap2430_mmc1_slaves,
2644 .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves),
2645 .class = &omap2430_mmc_class,
2646 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2647 };
2648
2649 /* MMC/SD/SDIO2 */
2650
2651 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
2652 { .irq = 86 },
2653 };
2654
2655 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
2656 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
2657 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
2658 };
2659
2660 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
2661 { .role = "dbck", .clk = "mmchsdb2_fck" },
2662 };
2663
2664 static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
2665 &omap2430_l4_core__mmc2,
2666 };
2667
2668 static struct omap_hwmod omap2430_mmc2_hwmod = {
2669 .name = "mmc2",
2670 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2671 .mpu_irqs = omap2430_mmc2_mpu_irqs,
2672 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
2673 .sdma_reqs = omap2430_mmc2_sdma_reqs,
2674 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
2675 .opt_clks = omap2430_mmc2_opt_clks,
2676 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
2677 .main_clk = "mmchs2_fck",
2678 .prcm = {
2679 .omap2 = {
2680 .module_offs = CORE_MOD,
2681 .prcm_reg_id = 2,
2682 .module_bit = OMAP2430_EN_MMCHS2_SHIFT,
2683 .idlest_reg_id = 2,
2684 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
2685 },
2686 },
2687 .slaves = omap2430_mmc2_slaves,
2688 .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves),
2689 .class = &omap2430_mmc_class,
2690 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2691 };
2692
2693 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
2694 &omap2430_l3_main_hwmod,
2695 &omap2430_l4_core_hwmod,
2696 &omap2430_l4_wkup_hwmod,
2697 &omap2430_mpu_hwmod,
2698 &omap2430_iva_hwmod,
2699
2700 &omap2430_timer1_hwmod,
2701 &omap2430_timer2_hwmod,
2702 &omap2430_timer3_hwmod,
2703 &omap2430_timer4_hwmod,
2704 &omap2430_timer5_hwmod,
2705 &omap2430_timer6_hwmod,
2706 &omap2430_timer7_hwmod,
2707 &omap2430_timer8_hwmod,
2708 &omap2430_timer9_hwmod,
2709 &omap2430_timer10_hwmod,
2710 &omap2430_timer11_hwmod,
2711 &omap2430_timer12_hwmod,
2712
2713 &omap2430_wd_timer2_hwmod,
2714 &omap2430_uart1_hwmod,
2715 &omap2430_uart2_hwmod,
2716 &omap2430_uart3_hwmod,
2717 /* dss class */
2718 &omap2430_dss_core_hwmod,
2719 &omap2430_dss_dispc_hwmod,
2720 &omap2430_dss_rfbi_hwmod,
2721 &omap2430_dss_venc_hwmod,
2722 /* i2c class */
2723 &omap2430_i2c1_hwmod,
2724 &omap2430_i2c2_hwmod,
2725 &omap2430_mmc1_hwmod,
2726 &omap2430_mmc2_hwmod,
2727
2728 /* gpio class */
2729 &omap2430_gpio1_hwmod,
2730 &omap2430_gpio2_hwmod,
2731 &omap2430_gpio3_hwmod,
2732 &omap2430_gpio4_hwmod,
2733 &omap2430_gpio5_hwmod,
2734
2735 /* dma_system class*/
2736 &omap2430_dma_system_hwmod,
2737
2738 /* mcbsp class */
2739 &omap2430_mcbsp1_hwmod,
2740 &omap2430_mcbsp2_hwmod,
2741 &omap2430_mcbsp3_hwmod,
2742 &omap2430_mcbsp4_hwmod,
2743 &omap2430_mcbsp5_hwmod,
2744
2745 /* mailbox class */
2746 &omap2430_mailbox_hwmod,
2747
2748 /* mcspi class */
2749 &omap2430_mcspi1_hwmod,
2750 &omap2430_mcspi2_hwmod,
2751 &omap2430_mcspi3_hwmod,
2752
2753 /* usbotg class*/
2754 &omap2430_usbhsotg_hwmod,
2755
2756 NULL,
2757 };
2758
2759 int __init omap2430_hwmod_init(void)
2760 {
2761 return omap_hwmod_register(omap2430_hwmods);
2762 }