arch/arm/mach-omap2/powerdomain44xx.c

   1 /*
   2  * OMAP4 powerdomain control
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2009 Nokia Corporation
   6  *
   7  * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
   8  * Rajendra Nayak <rnayak@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/io.h>
  16 #include <linux/errno.h>
  17 #include <linux/delay.h>
  18
  19 #include "powerdomain.h"
  20 #include <plat/prcm.h>
  21 #include "prm2xxx_3xxx.h"
  22 #include "cminst44xx.h"
  23 #include "prm44xx.h"
  24 #include "prcm44xx.h"
  25 #include "prminst44xx.h"
  26 #include "prm-regbits-44xx.h"
  27 #include "cm-regbits-44xx.h"
  28 #include "cm2_44xx.h"
  29
  30 static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
  31 {
  32         omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
  33                                         (pwrst << OMAP_POWERSTATE_SHIFT),
  34                                         pwrdm->prcm_partition,
  35                                         pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
  36         return 0;
  37 }
  38
  39 static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
  40 {
  41         u32 v;
  42
  43         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
  44                                         OMAP4_PM_PWSTCTRL);
  45         v &= OMAP_POWERSTATE_MASK;
  46         v >>= OMAP_POWERSTATE_SHIFT;
  47
  48         return v;
  49 }
  50
  51 static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
  52 {
  53         u32 v;
  54
  55         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
  56                                         OMAP4_PM_PWSTST);
  57         v &= OMAP_POWERSTATEST_MASK;
  58         v >>= OMAP_POWERSTATEST_SHIFT;
  59
  60         return v;
  61 }
  62
  63 static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
  64 {
  65         u32 v;
  66
  67         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
  68                                         OMAP4_PM_PWSTST);
  69         v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
  70         v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
  71
  72         return v;
  73 }
  74
  75 static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
  76 {
  77         omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
  78                                         (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
  79                                         pwrdm->prcm_partition,
  80                                         pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
  81         return 0;
  82 }
  83
  84 static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
  85 {
  86         omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
  87                                         OMAP4430_LASTPOWERSTATEENTERED_MASK,
  88                                         pwrdm->prcm_partition,
  89                                         pwrdm->prcm_offs, OMAP4_PM_PWSTST);
  90         return 0;
  91 }
  92
  93 static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
  94 {
  95         u32 v;
  96
  97         v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
  98         omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
  99                                         pwrdm->prcm_partition, pwrdm->prcm_offs,
 100                                         OMAP4_PM_PWSTCTRL);
 101
 102         return 0;
 103 }
 104
 105 static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
 106                                     u8 pwrst)
 107 {
 108         u32 m;
 109
 110         m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
 111
 112         omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
 113                                         pwrdm->prcm_partition, pwrdm->prcm_offs,
 114                                         OMAP4_PM_PWSTCTRL);
 115
 116         return 0;
 117 }
 118
 119 static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
 120                                      u8 pwrst)
 121 {
 122         u32 m;
 123
 124         m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
 125
 126         omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
 127                                         pwrdm->prcm_partition, pwrdm->prcm_offs,
 128                                         OMAP4_PM_PWSTCTRL);
 129
 130         return 0;
 131 }
 132
 133 static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
 134 {
 135         u32 v;
 136
 137         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 138                                         OMAP4_PM_PWSTST);
 139         v &= OMAP4430_LOGICSTATEST_MASK;
 140         v >>= OMAP4430_LOGICSTATEST_SHIFT;
 141
 142         return v;
 143 }
 144
 145 static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
 146 {
 147         u32 v;
 148
 149         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 150                                         OMAP4_PM_PWSTCTRL);
 151         v &= OMAP4430_LOGICRETSTATE_MASK;
 152         v >>= OMAP4430_LOGICRETSTATE_SHIFT;
 153
 154         return v;
 155 }
 156
 157 static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 158 {
 159         u32 m, v;
 160
 161         m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
 162
 163         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 164                                         OMAP4_PM_PWSTST);
 165         v &= m;
 166         v >>= __ffs(m);
 167
 168         return v;
 169 }
 170
 171 static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
 172 {
 173         u32 m, v;
 174
 175         m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
 176
 177         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 178                                         OMAP4_PM_PWSTCTRL);
 179         v &= m;
 180         v >>= __ffs(m);
 181
 182         return v;
 183 }
 184
 185 static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
 186 {
 187         u32 c = 0;
 188
 189         /*
 190          * REVISIT: pwrdm_wait_transition() may be better implemented
 191          * via a callback and a periodic timer check -- how long do we expect
 192          * powerdomain transitions to take?
 193          */
 194
 195         /* XXX Is this udelay() value meaningful? */
 196         while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
 197                                             pwrdm->prcm_offs,
 198                                             OMAP4_PM_PWSTST) &
 199                 OMAP_INTRANSITION_MASK) &&
 200                (c++ < PWRDM_TRANSITION_BAILOUT))
 201                 udelay(1);
 202
 203         if (c > PWRDM_TRANSITION_BAILOUT) {
 204                 printk(KERN_ERR "powerdomain: waited too long for "
 205                        "powerdomain %s to complete transition\n", pwrdm->name);
 206                 return -EAGAIN;
 207         }
 208
 209         pr_debug("powerdomain: completed transition in %d loops\n", c);
 210
 211         return 0;
 212 }
 213
 214 static int omap4_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
 215 {
 216         /*
 217          * FIXME: This should be fixed right way by moving it into HWMOD
 218          * or clock framework since sar control is moved to module level
 219          */
 220         omap4_cminst_rmw_inst_reg_bits(OMAP4430_SAR_MODE_MASK,
 221                 1 << OMAP4430_SAR_MODE_SHIFT, OMAP4430_CM2_PARTITION,
 222                 OMAP4430_CM2_L3INIT_INST,
 223                 OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET);
 224         omap4_cminst_rmw_inst_reg_bits(OMAP4430_SAR_MODE_MASK,
 225                 1 << OMAP4430_SAR_MODE_SHIFT, OMAP4430_CM2_PARTITION,
 226                 OMAP4430_CM2_L3INIT_INST,
 227                 OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET);
 228         return 0;
 229 }
 230
 231 static int omap4_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
 232 {
 233         /*
 234          * FIXME: This should be fixed right way by moving it into HWMOD
 235          * or clock framework since sar control is moved to module level
 236          */
 237         omap4_cminst_rmw_inst_reg_bits(OMAP4430_SAR_MODE_MASK,
 238                 0 << OMAP4430_SAR_MODE_SHIFT, OMAP4430_CM2_PARTITION,
 239                 OMAP4430_CM2_L3INIT_INST,
 240                 OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET);
 241         omap4_cminst_rmw_inst_reg_bits(OMAP4430_SAR_MODE_MASK,
 242                 0 << OMAP4430_SAR_MODE_SHIFT, OMAP4430_CM2_PARTITION,
 243                 OMAP4430_CM2_L3INIT_INST,
 244                 OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET);
 245
 246         return 0;
 247 }
 248
 249 struct pwrdm_ops omap4_pwrdm_operations = {
 250         .pwrdm_set_next_pwrst   = omap4_pwrdm_set_next_pwrst,
 251         .pwrdm_read_next_pwrst  = omap4_pwrdm_read_next_pwrst,
 252         .pwrdm_read_pwrst       = omap4_pwrdm_read_pwrst,
 253         .pwrdm_read_prev_pwrst  = omap4_pwrdm_read_prev_pwrst,
 254         .pwrdm_set_lowpwrstchange       = omap4_pwrdm_set_lowpwrstchange,
 255         .pwrdm_clear_all_prev_pwrst     = omap4_pwrdm_clear_all_prev_pwrst,
 256         .pwrdm_set_logic_retst  = omap4_pwrdm_set_logic_retst,
 257         .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
 258         .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
 259         .pwrdm_read_mem_pwrst   = omap4_pwrdm_read_mem_pwrst,
 260         .pwrdm_read_mem_retst   = omap4_pwrdm_read_mem_retst,
 261         .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
 262         .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
 263         .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
 264         .pwrdm_enable_hdwr_sar  = omap4_pwrdm_enable_hdwr_sar,
 265         .pwrdm_disable_hdwr_sar = omap4_pwrdm_disable_hdwr_sar,
 266 };