arch/arm/mach-omap2/prm2xxx_3xxx.c

   1 /*
   2  * OMAP2/3 PRM module functions
   3  *
   4  * Copyright (C) 2010 Texas Instruments, Inc.
   5  * Copyright (C) 2010 Nokia Corporation
   6  * Benoît Cousson
   7  * Paul Walmsley
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/errno.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18
  19 #include <plat/common.h>
  20 #include <plat/cpu.h>
  21 #include <plat/prcm.h>
  22
  23 #include "vp.h"
  24
  25 #include "prm2xxx_3xxx.h"
  26 #include "cm2xxx_3xxx.h"
  27 #include "prm-regbits-24xx.h"
  28 #include "prm-regbits-34xx.h"
  29
  30 u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
  31 {
  32         return __raw_readl(prm_base + module + idx);
  33 }
  34
  35 void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
  36 {
  37         __raw_writel(val, prm_base + module + idx);
  38 }
  39
  40 /* Read-modify-write a register in a PRM module. Caller must lock */
  41 u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
  42 {
  43         u32 v;
  44
  45         v = omap2_prm_read_mod_reg(module, idx);
  46         v &= ~mask;
  47         v |= bits;
  48         omap2_prm_write_mod_reg(v, module, idx);
  49
  50         return v;
  51 }
  52
  53 /* Read a PRM register, AND it, and shift the result down to bit 0 */
  54 u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
  55 {
  56         u32 v;
  57
  58         v = omap2_prm_read_mod_reg(domain, idx);
  59         v &= mask;
  60         v >>= __ffs(mask);
  61
  62         return v;
  63 }
  64
  65 u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
  66 {
  67         return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
  68 }
  69
  70 u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
  71 {
  72         return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
  73 }
  74
  75
  76 /**
  77  * omap2_prm_is_hardreset_asserted - read the HW reset line state of
  78  * submodules contained in the hwmod module
  79  * @prm_mod: PRM submodule base (e.g. CORE_MOD)
  80  * @shift: register bit shift corresponding to the reset line to check
  81  *
  82  * Returns 1 if the (sub)module hardreset line is currently asserted,
  83  * 0 if the (sub)module hardreset line is not currently asserted, or
  84  * -EINVAL if called while running on a non-OMAP2/3 chip.
  85  */
  86 int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
  87 {
  88         if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
  89                 return -EINVAL;
  90
  91         return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
  92                                        (1 << shift));
  93 }
  94
  95 /**
  96  * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
  97  * @prm_mod: PRM submodule base (e.g. CORE_MOD)
  98  * @shift: register bit shift corresponding to the reset line to assert
  99  *
 100  * Some IPs like dsp or iva contain processors that require an HW
 101  * reset line to be asserted / deasserted in order to fully enable the
 102  * IP.  These modules may have multiple hard-reset lines that reset
 103  * different 'submodules' inside the IP block.  This function will
 104  * place the submodule into reset.  Returns 0 upon success or -EINVAL
 105  * upon an argument error.
 106  */
 107 int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
 108 {
 109         u32 mask;
 110
 111         if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
 112                 return -EINVAL;
 113
 114         mask = 1 << shift;
 115         omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
 116
 117         return 0;
 118 }
 119
 120 /**
 121  * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
 122  * @prm_mod: PRM submodule base (e.g. CORE_MOD)
 123  * @rst_shift: register bit shift corresponding to the reset line to deassert
 124  * @st_shift: register bit shift for the status of the deasserted submodule
 125  *
 126  * Some IPs like dsp or iva contain processors that require an HW
 127  * reset line to be asserted / deasserted in order to fully enable the
 128  * IP.  These modules may have multiple hard-reset lines that reset
 129  * different 'submodules' inside the IP block.  This function will
 130  * take the submodule out of reset and wait until the PRCM indicates
 131  * that the reset has completed before returning.  Returns 0 upon success or
 132  * -EINVAL upon an argument error, -EEXIST if the submodule was already out
 133  * of reset, or -EBUSY if the submodule did not exit reset promptly.
 134  */
 135 int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
 136 {
 137         u32 rst, st;
 138         int c;
 139
 140         if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
 141                 return -EINVAL;
 142
 143         rst = 1 << rst_shift;
 144         st = 1 << st_shift;
 145
 146         /* Check the current status to avoid de-asserting the line twice */
 147         if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0)
 148                 return -EEXIST;
 149
 150         /* Clear the reset status by writing 1 to the status bit */
 151         omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST);
 152         /* de-assert the reset control line */
 153         omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL);
 154         /* wait the status to be set */
 155         omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
 156                                                   st),
 157                           MAX_MODULE_HARDRESET_WAIT, c);
 158
 159         return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 160 }
 161
 162 /* PRM VP */
 163
 164 /*
 165  * struct omap3_prm_irq - OMAP3 PRM IRQ register access description.
 166  * @vp_tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
 167  * @abb_tranxdone_status: ABB_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
 168  *                        (ONLY for OMAP3630)
 169  */
 170 struct omap3_prm_irq {
 171         u32 vp_tranxdone_status;
 172         u32 abb_tranxdone_status;
 173 };
 174
 175 static struct omap3_prm_irq omap3_prm_irqs[] = {
 176         [OMAP3_PRM_IRQ_VDD_MPU_ID] = {
 177                 .vp_tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
 178                 .abb_tranxdone_status = OMAP3630_ABB_LDO_TRANXDONE_ST_MASK,
 179         },
 180         [OMAP3_PRM_IRQ_VDD_CORE_ID] = {
 181                 .vp_tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
 182                 /* no abb for core */
 183         },
 184 };
 185
 186 #define MAX_VP_ID ARRAY_SIZE(omap3_vp);
 187
 188 u32 omap3_prm_vp_check_txdone(u8 irq_id)
 189 {
 190         struct omap3_prm_irq *irq = &omap3_prm_irqs[irq_id];
 191         u32 irqstatus;
 192
 193         irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
 194                                            OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 195         return irqstatus & irq->vp_tranxdone_status;
 196 }
 197
 198 void omap3_prm_vp_clear_txdone(u8 irq_id)
 199 {
 200         struct omap3_prm_irq *irq = &omap3_prm_irqs[irq_id];
 201
 202         omap2_prm_write_mod_reg(irq->vp_tranxdone_status,
 203                                 OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 204 }
 205
 206 u32 omap36xx_prm_abb_check_txdone(u8 irq_id)
 207 {
 208         struct omap3_prm_irq *irq = &omap3_prm_irqs[irq_id];
 209         u32 irqstatus;
 210
 211         irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
 212                                            OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 213         return irqstatus & irq->abb_tranxdone_status;
 214 }
 215
 216 void omap36xx_prm_abb_clear_txdone(u8 irq_id)
 217 {
 218         struct omap3_prm_irq *irq = &omap3_prm_irqs[irq_id];
 219
 220         omap2_prm_write_mod_reg(irq->abb_tranxdone_status,
 221                                 OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 222 }
 223
 224 u32 omap3_prm_vcvp_read(u8 offset)
 225 {
 226         return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
 227 }
 228
 229 void omap3_prm_vcvp_write(u32 val, u8 offset)
 230 {
 231         omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
 232 }
 233
 234 u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 235 {
 236         return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
 237 }