1 * Freescale 83xx DMA Controller
3 Freescale PowerPC 83xx have on chip general purpose DMA controllers.
7 - compatible : compatible list, contains 2 entries, first is
8 "fsl,CHIP-dma", where CHIP is the processor
9 (mpc8349, mpc8360, etc.) and the second is
11 - reg : <registers mapping for DMA general status reg>
12 - ranges : Should be defined as specified in 1) to describe the
13 DMA controller channels.
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : <interrupt mapping for DMA IRQ>
16 - interrupt-parent : optional, if needed for interrupt mapping
20 - compatible : compatible list, contains 2 entries, first is
21 "fsl,CHIP-dma-channel", where CHIP is the processor
22 (mpc8349, mpc8350, etc.) and the second is
23 "fsl,elo-dma-channel". However, see note below.
24 - reg : <registers mapping for channel>
25 - cell-index : dma channel index starts at 0.
28 - interrupts : <interrupt mapping for DMA channel IRQ>
29 (on 83xx this is expected to be identical to
30 the interrupts property of the parent node)
31 - interrupt-parent : optional, if needed for interrupt mapping
37 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
39 ranges = <0 0x8100 0x1a4>;
40 interrupt-parent = <&ipic>;
44 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
49 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
54 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
59 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
65 * Freescale 85xx/86xx DMA Controller
67 Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.
71 - compatible : compatible list, contains 2 entries, first is
72 "fsl,CHIP-dma", where CHIP is the processor
73 (mpc8540, mpc8540, etc.) and the second is
75 - reg : <registers mapping for DMA general status reg>
76 - cell-index : controller index. 0 for controller @ 0x21000,
77 1 for controller @ 0xc000
78 - ranges : Should be defined as specified in 1) to describe the
79 DMA controller channels.
82 - compatible : compatible list, contains 2 entries, first is
83 "fsl,CHIP-dma-channel", where CHIP is the processor
84 (mpc8540, mpc8560, etc.) and the second is
85 "fsl,eloplus-dma-channel". However, see note below.
86 - cell-index : dma channel index starts at 0.
87 - reg : <registers mapping for channel>
88 - interrupts : <interrupt mapping for DMA channel IRQ>
89 - interrupt-parent : optional, if needed for interrupt mapping
95 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
97 ranges = <0 0x21100 0x200>;
100 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
103 interrupt-parent = <&mpic>;
107 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
110 interrupt-parent = <&mpic>;
114 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
117 interrupt-parent = <&mpic>;
121 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
124 interrupt-parent = <&mpic>;
129 Note on DMA channel compatible properties: The compatible property must say
130 "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
131 driver (fsldma). Any DMA channel used by fsldma cannot be used by another
132 DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA
133 channel that should be used for another driver should not use
134 "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
135 example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt
136 for more information.