src/soc/intel/alderlake/bootblock/pch.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on Intel Alder Lake Processor PCH Datasheet
   5  * Document number: 621483
   6  * Chapter number: 2, 3, 4, 27, 28
   7  */
   8
   9 #include <device/mmio.h>
  10 #include <device/device.h>
  11 #include <device/pci_ops.h>
  12 #include <intelblocks/fast_spi.h>
  13 #include <intelblocks/gspi.h>
  14 #include <intelblocks/lpc_lib.h>
  15 #include <intelblocks/p2sb.h>
  16 #include <intelblocks/pcr.h>
  17 #include <intelblocks/pmclib.h>
  18 #include <intelblocks/rtc.h>
  19 #include <soc/bootblock.h>
  20 #include <soc/soc_chip.h>
  21 #include <soc/espi.h>
  22 #include <soc/iomap.h>
  23 #include <soc/p2sb.h>
  24 #include <soc/pci_devs.h>
  25 #include <soc/pcr_ids.h>
  26 #include <soc/pm.h>
  27
  28 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
  29 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE       0x1080
  30 #else
  31 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE       0x1100
  32 #endif
  33
  34 #define PCR_PSFX_TO_SHDW_BAR0               0
  35 #define PCR_PSFX_TO_SHDW_BAR1               0x4
  36 #define PCR_PSFX_TO_SHDW_BAR2               0x8
  37 #define PCR_PSFX_TO_SHDW_BAR3               0xC
  38 #define PCR_PSFX_TO_SHDW_BAR4               0x10
  39 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN         0x01
  40 #define PCR_PSFX_T0_SHDW_PCIEN              0x1C
  41
  42 static void soc_config_pwrmbase(void)
  43 {
  44         /*
  45          * Assign Resources to PWRMBASE
  46          * Clear BIT 1-2 Command Register
  47          */
  48         pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
  49
  50         /* Program PWRM Base */
  51         pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
  52
  53         /* Enable Bus Master and MMIO Space */
  54         pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
  55
  56         /* Enable PWRM in PMC */
  57         setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
  58 }
  59
  60 void bootblock_pch_early_init(void)
  61 {
  62         /*
  63          * Perform P2SB configuration before any another controller initialization as the
  64          * controller might want to perform PCR settings.
  65          */
  66         p2sb_enable_bar();
  67         p2sb_configure_hpet();
  68
  69         fast_spi_early_init(SPI_BASE_ADDRESS);
  70         gspi_early_bar_init();
  71
  72         /*
  73          * Enabling PWRM Base for accessing
  74          * Global Reset Cause Register.
  75          */
  76         soc_config_pwrmbase();
  77 }
  78
  79 static void soc_config_acpibase(void)
  80 {
  81         uint32_t pmc_reg_value;
  82         uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE;
  83
  84         pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
  85
  86         if (pmc_reg_value != 0xffffffff) {
  87                 /* Disable Io Space before changing the address */
  88                 pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
  89                                 ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
  90                 /* Program ABASE in PSF3 PMC space BAR4*/
  91                 pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4,
  92                                 ACPI_BASE_ADDRESS);
  93                 /* Enable IO Space */
  94                 pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
  95                                 ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
  96         }
  97 }
  98
  99 void pch_early_iorange_init(void)
 100 {
 101         uint16_t io_enables = LPC_IOE_COMA_EN | LPC_IOE_COMB_EN |
 102                               LPC_IOE_LPT_EN | LPC_IOE_FDD_EN |
 103                               LPC_IOE_LGE_200 | LPC_IOE_HGE_208 |
 104                               LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 |
 105                               LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F;
 106
 107         /* IO Decode Range */
 108         if (CONFIG(DRIVERS_UART_8250IO))
 109                 lpc_io_setup_comm_a_b();
 110
 111         /* IO Decode Enable */
 112         lpc_enable_fixed_io_ranges(io_enables);
 113
 114         /* Program generic IO Decode Range */
 115         pch_enable_lpc();
 116 }
 117
 118 void bootblock_pch_init(void)
 119 {
 120         /*
 121          * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
 122          * GPE0_STS, GPE0_EN registers.
 123          */
 124         soc_config_acpibase();
 125
 126         /* Set up GPE configuration */
 127         pmc_gpe_init();
 128
 129         enable_rtc_upper_bank();
 130 }