src/soc/intel/alderlake/chip.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/pci.h>
   5 #include <fsp/api.h>
   6 #include <fsp/util.h>
   7 #include <gpio.h>
   8 #include <intelblocks/acpi.h>
   9 #include <intelblocks/cfg.h>
  10 #include <intelblocks/cse.h>
  11 #include <intelblocks/irq.h>
  12 #include <intelblocks/itss.h>
  13 #include <intelblocks/pcie_rp.h>
  14 #include <intelblocks/systemagent.h>
  15 #include <intelblocks/xdci.h>
  16 #include <soc/hsphy.h>
  17 #include <soc/intel/common/vbt.h>
  18 #include <soc/itss.h>
  19 #include <soc/p2sb.h>
  20 #include <soc/pci_devs.h>
  21 #include <soc/pcie.h>
  22 #include <soc/ramstage.h>
  23 #include <soc/soc_chip.h>
  24
  25 #if CONFIG(HAVE_ACPI_TABLES)
  26 const char *soc_acpi_name(const struct device *dev)
  27 {
  28         if (dev->path.type == DEVICE_PATH_DOMAIN)
  29                 return "PCI0";
  30
  31         if (dev->path.type == DEVICE_PATH_USB) {
  32                 switch (dev->path.usb.port_type) {
  33                 case 0:
  34                         /* Root Hub */
  35                         return "RHUB";
  36                 case 2:
  37                         /* USB2 ports */
  38                         switch (dev->path.usb.port_id) {
  39                         case 0: return "HS01";
  40                         case 1: return "HS02";
  41                         case 2: return "HS03";
  42                         case 3: return "HS04";
  43                         case 4: return "HS05";
  44                         case 5: return "HS06";
  45                         case 6: return "HS07";
  46                         case 7: return "HS08";
  47                         case 8: return "HS09";
  48                         case 9: return "HS10";
  49                         case 10: return "HS11";
  50                         case 11: return "HS12";
  51                         case 12: return "HS13";
  52                         case 13: return "HS14";
  53                         }
  54                         break;
  55                 case 3:
  56                         /* USB3 ports */
  57                         switch (dev->path.usb.port_id) {
  58                         case 0: return "SS01";
  59                         case 1: return "SS02";
  60                         case 2: return "SS03";
  61                         case 3: return "SS04";
  62                         case 4: return "SS05";
  63                         case 5: return "SS06";
  64                         case 6: return "SS07";
  65                         case 7: return "SS08";
  66                         case 8: return "SS09";
  67                         case 9: return "SS10";
  68                         }
  69                         break;
  70                 }
  71                 return NULL;
  72         }
  73         if (dev->path.type != DEVICE_PATH_PCI)
  74                 return NULL;
  75
  76         switch (dev->path.pci.devfn) {
  77         case SA_DEVFN_ROOT:             return "MCHC";
  78 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
  79         case SA_DEVFN_CPU_PCIE1_0:      return "PEG1";
  80         case SA_DEVFN_CPU_PCIE1_1:      return "PEG2";
  81         case SA_DEVFN_CPU_PCIE6_0:      return "PEG0";
  82 #else
  83         case SA_DEVFN_CPU_PCIE1_0:      return "PEG2";
  84         case SA_DEVFN_CPU_PCIE6_0:      return "PEG0";
  85         case SA_DEVFN_CPU_PCIE6_2:      return "PEG1";
  86 #endif
  87         case SA_DEVFN_IGD:              return "GFX0";
  88         case SA_DEVFN_TCSS_XHCI:        return "TXHC";
  89         case SA_DEVFN_TCSS_XDCI:        return "TXDC";
  90         case SA_DEVFN_TCSS_DMA0:        return "TDM0";
  91         case SA_DEVFN_TCSS_DMA1:        return "TDM1";
  92         case SA_DEVFN_TBT0:             return "TRP0";
  93         case SA_DEVFN_TBT1:             return "TRP1";
  94         case SA_DEVFN_TBT2:             return "TRP2";
  95         case SA_DEVFN_TBT3:             return "TRP3";
  96         case SA_DEVFN_IPU:              return "IPU0";
  97         case SA_DEVFN_GNA:              return "GNA";
  98         case SA_DEVFN_DPTF:             return "TCPU";
  99         case PCH_DEVFN_ISH:             return "ISHB";
 100         case PCH_DEVFN_XHCI:            return "XHCI";
 101         case PCH_DEVFN_I2C0:            return "I2C0";
 102         case PCH_DEVFN_I2C1:            return "I2C1";
 103         case PCH_DEVFN_I2C2:            return "I2C2";
 104         case PCH_DEVFN_I2C3:            return "I2C3";
 105         case PCH_DEVFN_I2C4:            return "I2C4";
 106         case PCH_DEVFN_I2C5:            return "I2C5";
 107         case PCH_DEVFN_I2C6:            return "I2C6";
 108         case PCH_DEVFN_I2C7:            return "I2C7";
 109         case PCH_DEVFN_SATA:            return "SATA";
 110         case PCH_DEVFN_PCIE1:           return "RP01";
 111         case PCH_DEVFN_PCIE2:           return "RP02";
 112         case PCH_DEVFN_PCIE3:           return "RP03";
 113         case PCH_DEVFN_PCIE4:           return "RP04";
 114         case PCH_DEVFN_PCIE5:           return "RP05";
 115         case PCH_DEVFN_PCIE6:           return "RP06";
 116         case PCH_DEVFN_PCIE7:           return "RP07";
 117         case PCH_DEVFN_PCIE8:           return "RP08";
 118         case PCH_DEVFN_PCIE9:           return "RP09";
 119         case PCH_DEVFN_PCIE10:          return "RP10";
 120         case PCH_DEVFN_PCIE11:          return "RP11";
 121         case PCH_DEVFN_PCIE12:          return "RP12";
 122         case PCH_DEVFN_PCIE13:          return "RP13";
 123         case PCH_DEVFN_PCIE14:          return "RP14";
 124         case PCH_DEVFN_PCIE15:          return "RP15";
 125         case PCH_DEVFN_PCIE16:          return "RP16";
 126         case PCH_DEVFN_PCIE17:          return "RP17";
 127         case PCH_DEVFN_PCIE18:          return "RP18";
 128         case PCH_DEVFN_PCIE19:          return "RP19";
 129         case PCH_DEVFN_PCIE20:          return "RP20";
 130         case PCH_DEVFN_PCIE21:          return "RP21";
 131         case PCH_DEVFN_PCIE22:          return "RP22";
 132         case PCH_DEVFN_PCIE23:          return "RP23";
 133         case PCH_DEVFN_PCIE24:          return "RP24";
 134 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
 135         /* Avoid conflicts with PCH-N eMMC */
 136         case PCH_DEVFN_PCIE25:          return "RP25";
 137         case PCH_DEVFN_PCIE26:          return "RP26";
 138         case PCH_DEVFN_PCIE27:          return "RP27";
 139         case PCH_DEVFN_PCIE28:          return "RP28";
 140 #endif
 141         case PCH_DEVFN_PMC:             return "PMC";
 142         case PCH_DEVFN_UART0:           return "UAR0";
 143         case PCH_DEVFN_UART1:           return "UAR1";
 144         case PCH_DEVFN_UART2:           return "UAR2";
 145         case PCH_DEVFN_GSPI0:           return "SPI0";
 146         case PCH_DEVFN_GSPI1:           return "SPI1";
 147         case PCH_DEVFN_GSPI2:           return "SPI2";
 148         case PCH_DEVFN_GSPI3:           return "SPI3";
 149         /* Keeping ACPI device name coherent with ec.asl */
 150         case PCH_DEVFN_ESPI:            return "LPCB";
 151         case PCH_DEVFN_HDA:             return "HDAS";
 152         case PCH_DEVFN_SMBUS:           return "SBUS";
 153         case PCH_DEVFN_GBE:             return "GLAN";
 154         case PCH_DEVFN_SRAM:            return "SRAM";
 155         case PCH_DEVFN_SPI:             return "FSPI";
 156         case PCH_DEVFN_CSE:             return "HEC1";
 157 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
 158         case PCH_DEVFN_EMMC:            return "EMMC";
 159 #endif
 160         }
 161
 162         return NULL;
 163 }
 164 #endif
 165
 166 #if CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION)
 167 /*
 168  * SoC override API to identify if ISH Firmware existed inside CSE FPT.
 169  *
 170  * SoC with UFS enabled would like to keep ISH enabled as well, hence
 171  * identifying the UFS enabled device is enough to conclude that the ISH
 172  * partition also is available.
 173  */
 174 bool soc_is_ish_partition_enabled(void)
 175 {
 176         struct device *ufs = pcidev_path_on_root(PCH_DEVFN_UFS);
 177         uint16_t ufs_pci_id = ufs ? pci_read_config16(ufs, PCI_DEVICE_ID) : 0xFFFF;
 178
 179         if (ufs_pci_id == 0xFFFF)
 180                 return false;
 181
 182         return true;
 183 }
 184 #endif
 185
 186 /* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */
 187 static void soc_fill_gpio_pm_configuration(void)
 188 {
 189         uint8_t value[TOTAL_GPIO_COMM];
 190         const config_t *config = config_of_soc();
 191
 192         if (config->gpio_override_pm)
 193                 memcpy(value, config->gpio_pm, sizeof(value));
 194         else
 195                 memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value));
 196
 197         gpio_pm_configure(value, TOTAL_GPIO_COMM);
 198 }
 199
 200 void soc_init_pre_device(void *chip_info)
 201 {
 202         /* HSPHY FW needs to be loaded before FSP silicon init */
 203         load_and_init_hsphy();
 204
 205         /* Perform silicon specific init. */
 206         fsp_silicon_init();
 207
 208          /* Display FIRMWARE_VERSION_INFO_HOB */
 209         fsp_display_fvi_version_hob();
 210
 211         soc_fill_gpio_pm_configuration();
 212
 213         /* Swap enabled PCI ports in device tree if needed. */
 214         pcie_rp_update_devicetree(get_pch_pcie_rp_table());
 215
 216         /* Swap enabled TBT root ports in device tree if needed. */
 217         pcie_rp_update_devicetree(get_tbt_pcie_rp_table());
 218
 219         /*
 220          * Earlier when coreboot used to send EOP at late as possible caused
 221          * issue of delayed response from CSE since CSE was busy loading payload.
 222          * To resolve the issue, EOP should be sent earlier than current sequence
 223          * in the boot sequence at BS_DEV_INIT.
 224          * Intel CSE team recommends to send EOP close to FW init (between FSP-S exit and
 225          * current boot sequence) to reduce message response time from CSE hence moving
 226          * sending EOP to earlier stage.
 227          */
 228         if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY) ||
 229             CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) {
 230                 printk(BIOS_INFO, "Sending EOP early from SoC\n");
 231                 cse_send_end_of_post();
 232         }
 233 }
 234
 235 static void cpu_fill_ssdt(const struct device *dev)
 236 {
 237         if (!generate_pin_irq_map())
 238                 printk(BIOS_ERR, "Failed to generate ACPI _PRT table!\n");
 239
 240         generate_cpu_entries(dev);
 241 }
 242
 243 static void cpu_set_north_irqs(struct device *dev)
 244 {
 245         irq_program_non_pch();
 246 }
 247
 248 static struct device_operations pci_domain_ops = {
 249         .read_resources   = &pci_domain_read_resources,
 250         .set_resources    = &pci_domain_set_resources,
 251         .scan_bus         = &pci_host_bridge_scan_bus,
 252 #if CONFIG(HAVE_ACPI_TABLES)
 253         .acpi_name        = &soc_acpi_name,
 254         .acpi_fill_ssdt   = ssdt_set_above_4g_pci,
 255 #endif
 256 };
 257
 258 static struct device_operations cpu_bus_ops = {
 259         .read_resources   = noop_read_resources,
 260         .set_resources    = noop_set_resources,
 261         .enable_resources = cpu_set_north_irqs,
 262 #if CONFIG(HAVE_ACPI_TABLES)
 263         .acpi_fill_ssdt   = cpu_fill_ssdt,
 264 #endif
 265 };
 266
 267 static void soc_enable(struct device *dev)
 268 {
 269         struct device_operations *soc_p2sb_ops = (struct device_operations *)&p2sb_ops;
 270         /*
 271          * Set the operations if it is a special bus type or a hidden PCI
 272          * device.
 273          */
 274         if (dev->path.type == DEVICE_PATH_DOMAIN)
 275                 dev->ops = &pci_domain_ops;
 276         else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
 277                 dev->ops = &cpu_bus_ops;
 278         else if (dev->path.type == DEVICE_PATH_PCI &&
 279                  dev->path.pci.devfn == PCH_DEVFN_PMC)
 280                 dev->ops = &pmc_ops;
 281         else if (dev->path.type == DEVICE_PATH_PCI &&
 282                  dev->path.pci.devfn == PCH_DEVFN_P2SB)
 283                 dev->ops = soc_p2sb_ops;
 284         else if (dev->path.type == DEVICE_PATH_GPIO)
 285                 block_gpio_enable(dev);
 286 }
 287
 288 struct chip_operations soc_intel_alderlake_ops = {
 289         .name = "Intel Alderlake",
 290         .enable_dev     = &soc_enable,
 291         .init           = &soc_init_pre_device,
 292 };