src/soc/intel/apollolake/ahci.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/pci_ops.h>
   5 #include <soc/ahci.h>
   6 #include <soc/pci_devs.h>
   7 #include <soc/soc_chip.h>
   8 #include <types.h>
   9
  10 void ahci_set_speed(enum sata_speed_limit speed)
  11 {
  12         if (speed == SATA_DEFAULT)
  13                 return;
  14
  15         /* Setup temporary base address for BAR5. */
  16         pci_write_config32(PCH_DEV_SATA, PCI_BASE_ADDRESS_5, AHCI_TMP_BASE_ADDR);
  17         /* Enable memory access for pci_dev. */
  18         pci_or_config16(PCH_DEV_SATA, PCI_COMMAND, PCI_COMMAND_MEMORY);
  19
  20         printk(BIOS_DEBUG, "AHCI: Set SATA speed to Gen %d\n", speed);
  21         clrsetbits32((void *)(AHCI_TMP_BASE_ADDR + AHCI_CAP), AHCI_CAP_ISS_MASK,
  22                         AHCI_SPEED(speed));
  23
  24         /* Disable memory access for pci_dev. */
  25         pci_and_config16(PCH_DEV_SATA, PCI_COMMAND, ~PCI_COMMAND_MEMORY);
  26         /* Clear temporary base address for BAR5. */
  27         pci_write_config32(PCH_DEV_SATA, PCI_BASE_ADDRESS_5, 0);
  28 }