mb/system76/cml-u/dt: Make use of chipset devicetree
[coreboot.git] / src / soc / intel / elkhartlake / espi.c
blob3c9e81b94d5b6b15fb2efe704b1ea2764f8f79c8
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <arch/ioapic.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ops.h>
7 #include <intelblocks/itss.h>
8 #include <intelblocks/lpc_lib.h>
9 #include <pc80/isa-dma.h>
10 #include <pc80/i8259.h>
11 #include <soc/espi.h>
12 #include <soc/iomap.h>
13 #include <soc/irq.h>
14 #include <soc/pci_devs.h>
15 #include <soc/pcr_ids.h>
16 #include <soc/soc_chip.h>
18 void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
20 const config_t *config = config_of_soc();
22 gen_io_dec[0] = config->gen1_dec;
23 gen_io_dec[1] = config->gen2_dec;
24 gen_io_dec[2] = config->gen3_dec;
25 gen_io_dec[3] = config->gen4_dec;
28 #if ENV_RAMSTAGE
29 void lpc_soc_init(struct device *dev)
31 /* Legacy initialization */
32 isa_dma_init();
33 pch_misc_init();
35 /* Enable CLKRUN_EN for power gating ESPI */
36 lpc_enable_pci_clk_cntl();
38 /* Set ESPI Serial IRQ mode */
39 if (CONFIG(SERIRQ_CONTINUOUS_MODE))
40 lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
41 else
42 lpc_set_serirq_mode(SERIRQ_QUIET);
44 /* Interrupt configuration */
45 pch_enable_ioapic();
46 pch_pirq_init();
47 setup_i8259();
48 i8259_configure_irq_trigger(9, 1);
51 #endif