src/soc/intel/jasperlake/finalize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootstate.h>
   4 #include <commonlib/console/post_codes.h>
   5 #include <console/console.h>
   6 #include <cpu/x86/smm.h>
   7 #include <device/mmio.h>
   8 #include <device/pci.h>
   9 #include <intelblocks/lpc_lib.h>
  10 #include <intelblocks/pcr.h>
  11 #include <intelblocks/pmclib.h>
  12 #include <intelblocks/systemagent.h>
  13 #include <intelblocks/tco.h>
  14 #include <soc/p2sb.h>
  15 #include <soc/pci_devs.h>
  16 #include <soc/pcr_ids.h>
  17 #include <soc/pm.h>
  18 #include <soc/smbus.h>
  19 #include <soc/soc_chip.h>
  20 #include <soc/systemagent.h>
  21 #include <spi-generic.h>
  22
  23 #define CAMERA1_CLK             0x8000 /* Camera 1 Clock */
  24 #define CAMERA2_CLK             0x8080 /* Camera 2 Clock */
  25 #define CAM_CLK_EN              (1 << 1)
  26 #define MIPI_CLK                (1 << 0)
  27 #define HDPLL_CLK               (0 << 0)
  28
  29 static void pch_enable_isclk(void)
  30 {
  31         pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);
  32         pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK);
  33 }
  34
  35 static void pch_handle_sideband(config_t *config)
  36 {
  37         if (config->pch_isclk)
  38                 pch_enable_isclk();
  39 }
  40
  41 static void pch_finalize(void)
  42 {
  43         uint32_t reg32;
  44         uint8_t *pmcbase;
  45         config_t *config = config_of_soc();
  46
  47         /* TCO Lock down */
  48         tco_lockdown();
  49
  50         /* TODO: Add Thermal Configuration */
  51
  52         pmcbase = pmc_mmio_regs();
  53         if (config->s0ix_enable) {
  54                 /*
  55                  * Enable USBSUSPGQDIS qualification to ensure USB2 PHY SUS is power gated
  56                  * before entering s0ix.
  57                  */
  58                 reg32 = read32(pmcbase + CPPMVRIC3);
  59                 reg32 &= ~USBSUSPGQDIS;
  60                 write32(pmcbase + CPPMVRIC3, reg32);
  61
  62                 if (config->cnvi_reduce_s0ix_pwr_usage) {
  63                         setbits32(pmcbase + CPPMVRIC2, CNVIVNNAONREQQDIS);
  64                         setbits32(pmcbase + CORE_SPARE_GCR_0, BIT(0));
  65                 }
  66         }
  67
  68         pch_handle_sideband(config);
  69
  70         pmc_clear_pmcon_sts();
  71 }
  72
  73 static void soc_finalize(void *unused)
  74 {
  75         printk(BIOS_DEBUG, "Finalizing chipset.\n");
  76
  77         pch_finalize();
  78         apm_control(APM_CNT_FINALIZE);
  79
  80         /* Indicate finalize step with post code */
  81         post_code(POSTCODE_OS_BOOT);
  82 }
  83
  84 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
  85 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);