src/soc/intel/jasperlake/pmc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootstate.h>
   4 #include <console/console.h>
   5 #include <device/mmio.h>
   6 #include <device/device.h>
   7 #include <intelblocks/acpi.h>
   8 #include <intelblocks/pmc.h>
   9 #include <intelblocks/pmclib.h>
  10 #include <intelblocks/rtc.h>
  11 #include <soc/pci_devs.h>
  12 #include <soc/pm.h>
  13 #include <soc/soc_chip.h>
  14
  15 static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
  16 {
  17         uint32_t reg;
  18         uint8_t *pmcbase = pmc_mmio_regs();
  19
  20         printk(BIOS_DEBUG, "%sabling Deep S%c\n",
  21                 enable ? "En" : "Dis", sx + '0');
  22         reg = read32(pmcbase + offset);
  23         if (enable)
  24                 reg |= mask;
  25         else
  26                 reg &= ~mask;
  27         write32(pmcbase + offset, reg);
  28 }
  29
  30 static void config_deep_s5(int on_ac, int on_dc)
  31 {
  32         /* Treat S4 the same as S5. */
  33         config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac);
  34         config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc);
  35         config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac);
  36         config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc);
  37 }
  38
  39 static void config_deep_s3(int on_ac, int on_dc)
  40 {
  41         config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac);
  42         config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc);
  43 }
  44
  45 static void config_deep_sx(uint32_t deepsx_config)
  46 {
  47         uint32_t reg;
  48         uint8_t *pmcbase = pmc_mmio_regs();
  49
  50         reg = read32(pmcbase + DSX_CFG);
  51         reg &= ~DSX_CFG_MASK;
  52         reg |= deepsx_config;
  53         write32(pmcbase + DSX_CFG, reg);
  54 }
  55
  56 static void soc_pmc_enable(struct device *dev)
  57 {
  58         const config_t *config = config_of_soc();
  59
  60         rtc_init();
  61
  62         pmc_set_power_failure_state(true);
  63         pmc_gpe_init();
  64
  65         config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
  66         config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
  67         config_deep_sx(config->deep_sx_config);
  68 }
  69
  70 static void soc_pmc_read_resources(struct device *dev)
  71 {
  72         struct resource *res;
  73
  74         mmio_range(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
  75
  76         res = new_resource(dev, 1);
  77         res->base = (resource_t)ACPI_BASE_ADDRESS;
  78         res->size = (resource_t)ACPI_BASE_SIZE;
  79         res->limit = res->base + res->size - 1;
  80         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  81 }
  82
  83 static void soc_pmc_init(struct device *dev)
  84 {
  85         /*
  86          * pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order
  87          * to ensure the ordering does not break the assumptions that other
  88          * drivers make about ACPI mode (e.g. Chrome EC). Since it disables
  89          * ACPI mode, other drivers may take different actions based on this
  90          * (e.g. Chrome EC will flush any pending hostevent bits). Because
  91          * JSL has its PMC device available for device_operations, it can be
  92          * done from the "ops->init" callback.
  93          */
  94         pmc_set_acpi_mode();
  95
  96         /*
  97          * Disable ACPI PM timer based on Kconfig
  98          *
  99          * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
 100          * Disabling ACPI PM timer also switches off TCO
 101          */
 102         if (!CONFIG(USE_PM_ACPI_TIMER))
 103                 setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
 104 }
 105
 106 static void pm1_enable_pwrbtn_smi(void *unused)
 107 {
 108         /* Enable power button SMI after BS_DEV_INIT_CHIPS (FSP-S) is done. */
 109         pmc_update_pm1_enable(PWRBTN_EN);
 110 }
 111
 112 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
 113
 114 static void pmc_fill_ssdt(const struct device *dev)
 115 {
 116         if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP))
 117                 generate_acpi_power_engine();
 118 }
 119
 120 /*
 121  * `pmc_final` function is native implementation of equivalent events performed by
 122  * each FSP NotifyPhase() API invocations.
 123  *
 124  *
 125  * Clear PMCON status bits (Global Reset/Power Failure/Host Reset Status bits)
 126  *
 127  * Perform the PMCON status bit clear operation from `.final`
 128  * to cover any such chances where later boot stage requested a global
 129  * reset and PMCON status bit remains set.
 130  */
 131 static void pmc_final(struct device *dev)
 132 {
 133         pmc_clear_pmcon_sts();
 134 }
 135
 136 struct device_operations pmc_ops = {
 137         .read_resources         = soc_pmc_read_resources,
 138         .set_resources          = noop_set_resources,
 139         .init                   = soc_pmc_init,
 140         .enable                 = soc_pmc_enable,
 141 #if CONFIG(HAVE_ACPI_TABLES)
 142         .acpi_fill_ssdt         = pmc_fill_ssdt,
 143 #endif
 144         .final                  = pmc_final,
 145 };