src/soc/intel/tigerlake/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef _SOC_CHIP_H_
   4 #define _SOC_CHIP_H_
   5
   6 #include <drivers/i2c/designware/dw_i2c.h>
   7 #include <drivers/intel/gma/gma.h>
   8 #include <gpio.h>
   9 #include <intelblocks/cfg.h>
  10 #include <intelblocks/gspi.h>
  11 #include <intelblocks/lpc_lib.h>
  12 #include <intelblocks/pcie_rp.h>
  13 #include <intelblocks/power_limit.h>
  14 #include <intelblocks/tcss.h>
  15 #include <soc/gpe.h>
  16 #include <soc/pch.h>
  17 #include <soc/pci_devs.h>
  18 #include <soc/pmc.h>
  19 #include <soc/serialio.h>
  20 #include <soc/usb.h>
  21 #include <types.h>
  22
  23 #define MAX_HD_AUDIO_DMIC_LINKS 2
  24 #define MAX_HD_AUDIO_SNDW_LINKS 4
  25 #define MAX_HD_AUDIO_SSP_LINKS  6
  26
  27 /* Define config parameters for In-Band ECC (IBECC). */
  28 #define MAX_IBECC_REGIONS       8
  29
  30 enum ibecc_mode {
  31         IBECC_PER_REGION,
  32         IBECC_NONE,
  33         IBECC_ALL
  34 };
  35
  36 struct ibecc_config {
  37         bool enable;
  38         bool parity_en;
  39         enum ibecc_mode mode;
  40         bool region_enable[MAX_IBECC_REGIONS];
  41         uint16_t region_base[MAX_IBECC_REGIONS];
  42         uint16_t region_mask[MAX_IBECC_REGIONS];
  43 };
  44
  45 /* The first two are for TGL-U */
  46 enum soc_intel_tigerlake_power_limits {
  47         POWER_LIMITS_U_2_CORE,
  48         POWER_LIMITS_U_4_CORE,
  49         POWER_LIMITS_Y_2_CORE,
  50         POWER_LIMITS_Y_4_CORE,
  51         POWER_LIMITS_H_6_CORE,
  52         POWER_LIMITS_H_8_CORE,
  53         POWER_LIMITS_MAX
  54 };
  55
  56 /*
  57  * Enable External V1P05 Rail in: BIT0:S0i1/S0i2,
  58  * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5
  59  */
  60 enum fivr_enable_states {
  61         FIVR_ENABLE_S0i1_S0i2   = BIT(0),
  62         FIVR_ENABLE_S0i3        = BIT(1),
  63         FIVR_ENABLE_S3          = BIT(2),
  64         FIVR_ENABLE_S4          = BIT(3),
  65         FIVR_ENABLE_S5          = BIT(4),
  66 };
  67
  68 /*
  69  * Enable the following for External V1p05 rail
  70  * BIT1: Normal Active voltage supported
  71  * BIT2: Minimum active voltage supported
  72  * BIT3: Minimum Retention voltage supported
  73  */
  74 enum fivr_voltage_supported {
  75         FIVR_VOLTAGE_NORMAL             = BIT(1),
  76         FIVR_VOLTAGE_MIN_ACTIVE         = BIT(2),
  77         FIVR_VOLTAGE_MIN_RETENTION      = BIT(3),
  78 };
  79
  80 #define FIVR_ENABLE_ALL_SX (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 |  \
  81                             FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5)
  82
  83 /* Bit values for use in LpmStateEnableMask. */
  84 enum lpm_state_mask {
  85         LPM_S0i2_0 = BIT(0),
  86         LPM_S0i2_1 = BIT(1),
  87         LPM_S0i2_2 = BIT(2),
  88         LPM_S0i3_0 = BIT(3),
  89         LPM_S0i3_1 = BIT(4),
  90         LPM_S0i3_2 = BIT(5),
  91         LPM_S0i3_3 = BIT(6),
  92         LPM_S0i3_4 = BIT(7),
  93         LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2
  94                      | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4,
  95 };
  96
  97 /*
  98  * Slew Rate configuration for Deep Package C States for VR domain.
  99  * They are fast time divided by 2.
 100  * 0 - Fast/2
 101  * 1 - Fast/4
 102  * 2 - Fast/8
 103  * 3 - Fast/16
 104  */
 105 enum slew_rate {
 106         SLEW_FAST_2,
 107         SLEW_FAST_4,
 108         SLEW_FAST_8,
 109         SLEW_FAST_16
 110 };
 111
 112 enum ddi_port_config {
 113         DDI_PORT_CFG_NO_LFP     = 0,
 114         DDI_PORT_CFG_EDP        = 1,
 115         DDI_PORT_CFG_MIPI_DSI   = 2,
 116 };
 117
 118 struct soc_intel_tigerlake_config {
 119         /* Common struct containing soc config data required by common code */
 120         struct soc_intel_common_config common_soc_config;
 121
 122         /* Common struct containing power limits configuration information */
 123         struct soc_power_limits_config power_limits_config[POWER_LIMITS_MAX];
 124
 125         /* Configuration for boot TDP selection; */
 126         uint8_t ConfigTdpLevel;
 127
 128         /* Gpio group routed to each dword of the GPE0 block. Values are
 129          * of the form PMC_GPP_[A:U] or GPD. */
 130         uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
 131         uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */
 132         uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */
 133
 134         /* LPC fixed enables and ranges */
 135         uint32_t lpc_ioe;
 136
 137         /* Generic IO decode ranges */
 138         uint32_t gen1_dec;
 139         uint32_t gen2_dec;
 140         uint32_t gen3_dec;
 141         uint32_t gen4_dec;
 142
 143         /* Enable S0iX support */
 144         int s0ix_enable;
 145         /* S0iX: Selectively disable individual sub-states, by default all are enabled. */
 146         enum lpm_state_mask LpmStateDisableMask;
 147
 148         /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
 149         uint8_t TcssD3HotDisable;
 150
 151         /* Enable DPTF support */
 152         int dptf_enable;
 153
 154         /* Deep SX enable for both AC and DC */
 155         int deep_s3_enable_ac;
 156         int deep_s3_enable_dc;
 157         int deep_s5_enable_ac;
 158         int deep_s5_enable_dc;
 159
 160         /* Deep Sx Configuration
 161          *  DSX_EN_WAKE_PIN       - Enable WAKE# pin
 162          *  DSX_EN_LAN_WAKE_PIN   - Enable LAN_WAKE# pin
 163          *  DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */
 164         uint32_t deep_sx_config;
 165
 166         /* TCC activation offset */
 167         uint32_t tcc_offset;
 168
 169         /* In-Band ECC (IBECC) configuration */
 170         struct ibecc_config ibecc;
 171
 172         /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
 173          * When enabled memory will be training at two different frequencies.
 174          * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2,
 175          * 4:FixedPoint3, 5:Enabled */
 176         enum {
 177                 SaGv_Disabled,
 178                 SaGv_FixedPoint0,
 179                 SaGv_FixedPoint1,
 180                 SaGv_FixedPoint2,
 181                 SaGv_FixedPoint3,
 182                 SaGv_Enabled,
 183         } SaGv;
 184
 185         /* Rank Margin Tool. 1:Enable, 0:Disable */
 186         uint8_t RMT;
 187
 188         /* Command Pins Mirrored */
 189         uint32_t CmdMirror;
 190
 191         /* USB related */
 192         struct usb2_port_config usb2_ports[16];
 193         struct usb3_port_config usb3_ports[10];
 194         /* Wake Enable Bitmap for USB2 ports */
 195         uint16_t usb2_wake_enable_bitmap;
 196         /* Wake Enable Bitmap for USB3 ports */
 197         uint16_t usb3_wake_enable_bitmap;
 198         /* PCH USB2 PHY Power Gating disable */
 199         uint8_t usb2_phy_sus_pg_disable;
 200         /* Program OC pins for TCSS */
 201         struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS];
 202
 203         /*
 204          * Acoustic Noise Mitigation
 205          * 0 - Disable
 206          * 1 - Enable noise mitigation
 207          */
 208         uint8_t AcousticNoiseMitigation;
 209
 210         /*
 211          * Offset 0x054B - Disable Fast Slew Rate for Deep Package
 212          * C States for VCCin in VR domain. Disable Fast Slew Rate
 213          * for Deep Package C States based on Acoustic Noise
 214          * Mitigation feature enabled.
 215          * 0 - False
 216          * 1 - True
 217          */
 218         uint8_t FastPkgCRampDisable;
 219
 220         /*
 221          * Offset 0x0550 - Slew Rate configuration for Deep Package
 222          * C States for VCCin in VR domain. Slew Rate configuration
 223          * for Deep Package C States for VR domain based on Acoustic
 224          * Noise Mitigation feature enabled.
 225          */
 226         uint8_t SlowSlewRate;
 227
 228         /* SATA related */
 229         uint8_t SataMode;
 230         uint8_t SataSalpSupport;
 231         uint8_t SataPortsEnable[8];
 232         uint8_t SataPortsDevSlp[8];
 233
 234         /*
 235          * Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
 236          * Default 0. Setting this to 1 disables the SATA Power Optimizer.
 237          */
 238         uint8_t SataPwrOptimizeDisable;
 239
 240         /*
 241          * SATA Port Enable Dito Config.
 242          * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
 243          */
 244         uint8_t SataPortsEnableDitoConfig[8];
 245
 246         /* SataPortsDmVal is the DITO multiplier. Default is 15. */
 247         uint8_t SataPortsDmVal[8];
 248         /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */
 249         uint16_t SataPortsDitoVal[8];
 250
 251         /* Audio related */
 252         uint8_t PchHdaDspEnable;
 253         uint8_t PchHdaAudioLinkHdaEnable;
 254         uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];
 255         uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS];
 256         uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
 257         uint8_t PchHdaIDispCodecDisconnect;
 258
 259         /* PCIe Root Ports */
 260         uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
 261         /* Implemented as slot or built-in? */
 262         uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS];
 263         /* PCIe output clocks type to PCIe devices.
 264          * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 265          * 0xFF: not used */
 266         uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC];
 267         /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
 268          * clksrc. */
 269         uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC];
 270
 271         /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
 272         uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
 273
 274         /* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */
 275         uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS];
 276
 277         /* PCIe RP L1 substate */
 278         enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
 279
 280         /* PCIe LTR: Enable (1) / Disable (0) */
 281         uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
 282
 283         /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
 284         uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
 285
 286         /* Gfx related */
 287         uint8_t SkipExtGfxScan;
 288
 289         /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
 290         uint8_t eist_enable;
 291
 292         /* Enable C6 DRAM */
 293         uint8_t enable_c6dram;
 294
 295         /*
 296          * SerialIO device mode selection:
 297          * PchSerialIoDisabled,
 298          * PchSerialIoPci,
 299          * PchSerialIoHidden,
 300          * PchSerialIoLegacyUart,
 301          * PchSerialIoSkipInit
 302          */
 303         uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
 304         uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 305         uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX];
 306         /*
 307          * GSPIn Default Chip Select Mode:
 308          * 0:Hardware Mode,
 309          * 1:Software Mode
 310          */
 311         uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 312         /*
 313          * GSPIn Default Chip Select State:
 314          * 0: Low,
 315          * 1: High
 316          */
 317         uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 318
 319         /*
 320          * TraceHubMode config
 321          * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
 322          */
 323         uint8_t TraceHubMode;
 324
 325         /* Debug interface selection */
 326         enum {
 327                 DEBUG_INTERFACE_RAM = (1 << 0),
 328                 DEBUG_INTERFACE_UART_8250IO = (1 << 1),
 329                 DEBUG_INTERFACE_USB3 = (1 << 3),
 330                 DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4),
 331                 DEBUG_INTERFACE_TRACEHUB = (1 << 5),
 332         } debug_interface_flag;
 333
 334         /* CNVi BT Core Enable/Disable */
 335         bool CnviBtCore;
 336
 337         /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
 338         bool CnviBtAudioOffload;
 339
 340         /* TCSS USB */
 341         uint8_t TcssXhciEn;
 342         uint8_t TcssXdciEn;
 343
 344         /*
 345          * Specifies which Type-C Ports are enabled on the system
 346          * each bit represents a port starting at 0
 347          * Example: set value to 0x3 for ports 0 and 1 to be enabled
 348          */
 349         uint8_t UsbTcPortEn;
 350
 351         /*
 352          * These GPIOs will be programmed by the IOM to handle biasing of the
 353          * Type-C aux (SBU) signals when certain alternate modes are used.
 354          * `pad_auxn_dc` should be assigned to the GPIO pad providing negative
 355          * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly,
 356          * `pad_auxp_dc` should be assigned to the GPIO providing positive bias
 357          * (name often contains `AUXP_DC` or `_AUX_P`).
 358          */
 359         struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS];
 360
 361         /*
 362          * SOC Aux orientation override:
 363          * This is a bitfield that corresponds to up to 4 TCSS ports on TGL.
 364          * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC.
 365          * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines
 366          * on the motherboard.
 367          */
 368         uint16_t TcssAuxOri;
 369
 370         /* Connect Topology Command timeout value */
 371         uint16_t ITbtConnectTopologyTimeoutInMs;
 372
 373         /*
 374          * Override GPIO PM configuration:
 375          * 0: Use FSP default GPIO PM program,
 376          * 1: coreboot to override GPIO PM program
 377          */
 378         uint8_t gpio_override_pm;
 379
 380         /*
 381          * GPIO PM configuration: 0 to disable, 1 to enable power gating
 382          * Bit 6-7: Reserved
 383          * Bit 5: MISCCFG_GPSIDEDPCGEN
 384          * Bit 4: MISCCFG_GPRCOMPCDLCGEN
 385          * Bit 3: MISCCFG_GPRTCDLCGEN
 386          * Bit 2: MISCCFG_GSXLCGEN
 387          * Bit 1: MISCCFG_GPDPCGEN
 388          * Bit 0: MISCCFG_GPDLCGEN
 389          */
 390         uint8_t gpio_pm[TOTAL_GPIO_COMM];
 391
 392         /* DDI port config */
 393         enum ddi_port_config DdiPortAConfig;
 394         enum ddi_port_config DdiPortBConfig;
 395
 396         /* Enable(1)/Disable(0) HPD */
 397         uint8_t DdiPortAHpd;
 398         uint8_t DdiPortBHpd;
 399         uint8_t DdiPortCHpd;
 400         uint8_t DdiPort1Hpd;
 401         uint8_t DdiPort2Hpd;
 402         uint8_t DdiPort3Hpd;
 403         uint8_t DdiPort4Hpd;
 404
 405         /* Enable(1)/Disable(0) DDC */
 406         uint8_t DdiPortADdc;
 407         uint8_t DdiPortBDdc;
 408         uint8_t DdiPortCDdc;
 409         uint8_t DdiPort1Ddc;
 410         uint8_t DdiPort2Ddc;
 411         uint8_t DdiPort3Ddc;
 412         uint8_t DdiPort4Ddc;
 413
 414         /* Hybrid storage mode enable (1) / disable (0)
 415          * This mode makes FSP detect Optane and NVME and set PCIe lane mode
 416          * accordingly */
 417         uint8_t HybridStorageMode;
 418
 419         /*
 420          * Override CPU flex ratio value:
 421          * CPU ratio value controls the maximum processor non-turbo ratio.
 422          * Valid Range 0 to 63.
 423          * In general descriptor provides option to set default cpu flex ratio.
 424          * Default cpu flex ratio 0 ensures booting with non-turbo max frequency.
 425          * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
 426          * Only override CPU flex ratio to not boot with non-turbo max.
 427          */
 428         uint8_t cpu_ratio_override;
 429
 430         /*
 431          * Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
 432          * Default 0. Setting this to 1 disables the DMI Power Optimizer.
 433          */
 434         uint8_t DmiPwrOptimizeDisable;
 435
 436         /* structure containing various settings for PCH FIVRs */
 437         struct {
 438                 bool configure_ext_fivr;
 439                 enum fivr_enable_states v1p05_enable_bitmap;
 440                 enum fivr_enable_states vnn_enable_bitmap;
 441                 enum fivr_voltage_supported v1p05_supported_voltage_bitmap;
 442                 enum fivr_voltage_supported vnn_supported_voltage_bitmap;
 443                 /* External Icc Max for V1p05 rail in mA  */
 444                 int v1p05_icc_max_ma;
 445                 /* External Vnn Voltage in mV */
 446                 int vnn_sx_voltage_mv;
 447         } ext_fivr_settings;
 448
 449         /*
 450          * Enable(1)/Disable(0) CPU Replacement check.
 451          * Default 0. Setting this to 1 to check CPU replacement.
 452          */
 453         uint8_t CpuReplacementCheck;
 454
 455         /*
 456          * SLP_S3 Minimum Assertion Width Policy
 457          *  1 = 60us
 458          *  2 = 1ms
 459          *  3 = 50ms (default)
 460          *  4 = 2s
 461          */
 462         uint8_t PchPmSlpS3MinAssert;
 463
 464         /*
 465          * SLP_S4 Minimum Assertion Width Policy
 466          *  1 = 1s (default)
 467          *  2 = 2s
 468          *  3 = 3s
 469          *  4 = 4s
 470          */
 471         uint8_t PchPmSlpS4MinAssert;
 472
 473         /*
 474          * SLP_SUS Minimum Assertion Width Policy
 475          *  1 = 0ms
 476          *  2 = 500ms
 477          *  3 = 1s
 478          *  4 = 4s (default)
 479          */
 480         uint8_t PchPmSlpSusMinAssert;
 481
 482         /*
 483          * SLP_A Minimum Assertion Width Policy
 484          *  1 = 0ms
 485          *  2 = 4s
 486          *  3 = 98ms
 487          *  4 = 2s (default)
 488          */
 489         uint8_t PchPmSlpAMinAssert;
 490
 491         /*
 492          * PCH PM Reset Power Cycle Duration
 493          *  0 = 4s (default)
 494          *  1 = 1s
 495          *  2 = 2s
 496          *  3 = 3s
 497          *  4 = 4s
 498          *
 499          * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
 500          * stretch duration programmed in the following registers:
 501          *  - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
 502          *  - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
 503          *  - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
 504          *  - PM_CFG.SLP_LAN_MIN_ASST_WDTH
 505          */
 506         uint8_t PchPmPwrCycDur;
 507
 508         /*
 509          * External Clock Gate
 510          * true = Mainboard design uses external clock gating
 511          * false = Mainboard design does not use external clock gating
 512          *
 513          */
 514         bool external_clk_gated;
 515
 516         /*
 517          * External PHY Gate
 518          * true = Mainboard design uses external phy gating
 519          * false = Mainboard design does not use external phy gating
 520          *
 521          */
 522         bool external_phy_gated;
 523
 524         /*
 525          * External Bypass Enable
 526          * true = Mainboard design uses external bypass rail
 527          * false = Mainboard design does not use external bypass rail
 528          *
 529          */
 530         bool external_bypass;
 531
 532         /* i915 struct for GMA backlight control */
 533         struct i915_gpu_controller_info gfx;
 534 };
 535
 536 typedef struct soc_intel_tigerlake_config config_t;
 537
 538 #endif