src/soc/intel/tigerlake/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <gpio.h>
   4 #include <intelblocks/pcr.h>
   5 #include <soc/pcr_ids.h>
   6 #include <soc/pmc.h>
   7
   8 #define DEFAULT_VW_BASE         0x10
   9
  10 /*
  11  * This file is created based on Intel Tiger Lake Processor PCH Datasheet
  12  * Document number: 575857
  13  * Chapter number: 27
  14  */
  15
  16 static const struct reset_mapping rst_map[] = {
  17         { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
  18         { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
  19         { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
  20 };
  21 static const struct reset_mapping rst_map_com2[] = {
  22         { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
  23         { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
  24         { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
  25         { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
  26 };
  27
  28 /*
  29  * The GPIO pinctrl driver for Tiger Lake on Linux expects 32 GPIOs per pad
  30  * group, regardless of whether or not there is a physical pad for each
  31  * exposed GPIO number.
  32  *
  33  * This results in the OS having a sparse GPIO map, and devices that need
  34  * to export an ACPI GPIO must use the OS expected number.
  35  *
  36  * Not all pins are usable as GPIO and those groups do not have a pad base.
  37  *
  38  * This layout matches the Linux kernel pinctrl map for TGL at:
  39  * linux/drivers/pinctrl/intel/pinctrl-tigerlake.c
  40  */
  41 static const struct pad_group tgl_community0_groups[] = {
  42         INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B25, 0),                     /* GPP_B */
  43         INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32),                    /* GPP_T */
  44         INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_A24, 64),                    /* GPP_A */
  45 };
  46
  47 static const struct vw_entries tgl_community0_vw[] = {
  48         {GPP_A0, GPP_A23},
  49         {GPP_B0, GPP_B23},
  50 };
  51
  52 static const struct pad_group tgl_community1_groups[] = {
  53         INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96),                     /* GPP_S */
  54         INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128),                   /* GPP_H */
  55         INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160),      /* GPP_D */
  56         INTEL_GPP_BASE(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK, 192),      /* GPP_U */
  57         INTEL_GPP_BASE(GPP_S0, CNV_BTEN, vI2S2_RXD, 224),               /* GPP_VGPIO */
  58 };
  59
  60 static const struct vw_entries tgl_community1_vw[] = {
  61         {GPP_D0, GPP_D19},
  62         {GPP_H0, GPP_H23},
  63 };
  64
  65 /* This community is not visible to the OS */
  66 static const struct pad_group tgl_community2_groups[] = {
  67         INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB),                         /* GPD */
  68 };
  69
  70 static const struct pad_group tgl_community4_groups[] = {
  71         INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256),                   /* GPP_C */
  72         INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288),          /* GPP_F */
  73         INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB),                  /* GPP_HVCMOS */
  74         INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320),          /* GPP_E */
  75         INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE),                 /* GPP_JTAG */
  76 };
  77
  78 static const struct vw_entries tgl_community4_vw[] = {
  79         {GPP_F0, GPP_F23},
  80         {GPP_C0, GPP_C23},
  81         {GPP_E0, GPP_E23},
  82 };
  83
  84 static const struct pad_group tgl_community5_groups[] = {
  85         INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352),                    /* GPP_R */
  86         INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK),                /* GPP_SPI */
  87 };
  88
  89 static const struct pad_community tgl_communities[] = {
  90         [COMM_0] = { /* GPP B, T, A */
  91                 .port = PID_GPIOCOM0,
  92                 .cpu_port = PID_CPU_GPIOCOM0,
  93                 .first_pad = GPP_B0,
  94                 .last_pad = GPP_A24,
  95                 .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
  96                 .pad_cfg_base = PAD_CFG_BASE,
  97                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
  98                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
  99                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 100                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 101                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 102                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 103                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 104                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
 105                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
 106                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 107                 .name = "GPP_BTA",
 108                 .acpi_path = "\\_SB.PCI0.GPIO",
 109                 .reset_map = rst_map,
 110                 .num_reset_vals = ARRAY_SIZE(rst_map),
 111                 .groups = tgl_community0_groups,
 112                 .num_groups = ARRAY_SIZE(tgl_community0_groups),
 113                 .vw_base = DEFAULT_VW_BASE,
 114                 .vw_entries = tgl_community0_vw,
 115                 .num_vw_entries = ARRAY_SIZE(tgl_community0_vw),
 116         },
 117         [COMM_1] = { /* GPP S, D, H, U, VGPIO */
 118                 .port = PID_GPIOCOM1,
 119                 .cpu_port = PID_CPU_GPIOCOM1,
 120                 .first_pad = GPP_S0,
 121                 .last_pad = vI2S2_RXD,
 122                 .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
 123                 .pad_cfg_base = PAD_CFG_BASE,
 124                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 125                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 126                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 127                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 128                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 129                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 130                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 131                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
 132                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
 133                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 134                 .name = "GPP_SDHU",
 135                 .acpi_path = "\\_SB.PCI0.GPIO",
 136                 .reset_map = rst_map,
 137                 .num_reset_vals = ARRAY_SIZE(rst_map),
 138                 .groups = tgl_community1_groups,
 139                 .num_groups = ARRAY_SIZE(tgl_community1_groups),
 140                 .vw_base = DEFAULT_VW_BASE,
 141                 .vw_entries = tgl_community1_vw,
 142                 .num_vw_entries = ARRAY_SIZE(tgl_community1_vw),
 143         },
 144         [COMM_2] = { /* GPD */
 145                 .port = PID_GPIOCOM2,
 146                 .first_pad = GPD0,
 147                 .last_pad = GPD_DRAM_RESETB,
 148                 .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
 149                 .pad_cfg_base = PAD_CFG_BASE,
 150                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 151                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 152                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 153                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 154                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 155                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 156                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 157                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
 158                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
 159                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 160                 .name = "GPD",
 161                 .acpi_path = "\\_SB.PCI0.GPIO",
 162                 .reset_map = rst_map_com2,
 163                 .num_reset_vals = ARRAY_SIZE(rst_map_com2),
 164                 .groups = tgl_community2_groups,
 165                 .num_groups = ARRAY_SIZE(tgl_community2_groups),
 166         },
 167         [COMM_4] = { /* GPP F, C, HVCOS, E, JTAG */
 168                 .port = PID_GPIOCOM4,
 169                 .cpu_port = PID_CPU_GPIOCOM4,
 170                 .first_pad = GPP_C0,
 171                 .last_pad = GPP_DBG_PMODE,
 172                 .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
 173                 .pad_cfg_base = PAD_CFG_BASE,
 174                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 175                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 176                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 177                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 178                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 179                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 180                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 181                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
 182                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
 183                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 184                 .name = "GPP_FCE",
 185                 .acpi_path = "\\_SB.PCI0.GPIO",
 186                 .reset_map = rst_map,
 187                 .num_reset_vals = ARRAY_SIZE(rst_map),
 188                 .groups = tgl_community4_groups,
 189                 .num_groups = ARRAY_SIZE(tgl_community4_groups),
 190                 .vw_base = DEFAULT_VW_BASE,
 191                 .vw_entries = tgl_community4_vw,
 192                 .num_vw_entries = ARRAY_SIZE(tgl_community4_vw),
 193         },
 194         [COMM_5] = { /* GPP R, SPI */
 195                 .port = PID_GPIOCOM5,
 196                 .cpu_port = PID_CPU_GPIOCOM5,
 197                 .first_pad = GPP_R0,
 198                 .last_pad = GPP_CLK_LOOPBK,
 199                 .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
 200                 .pad_cfg_base = PAD_CFG_BASE,
 201                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 202                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 203                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 204                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 205                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 206                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 207                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 208                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
 209                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
 210                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 211                 .name = "GPP_CPU_VBPIO",
 212                 .acpi_path = "\\_SB.PCI0.GPIO",
 213                 .reset_map = rst_map,
 214                 .num_reset_vals = ARRAY_SIZE(rst_map),
 215                 .groups = tgl_community5_groups,
 216                 .num_groups = ARRAY_SIZE(tgl_community5_groups),
 217         }
 218 };
 219
 220 const struct pad_community *soc_gpio_get_community(size_t *num_communities)
 221 {
 222         *num_communities = ARRAY_SIZE(tgl_communities);
 223         return tgl_communities;
 224 }
 225
 226 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
 227 {
 228         static const struct pmc_to_gpio_route routes[] = {
 229                 { PMC_GPP_B, GPP_B },
 230                 { PMC_GPP_T, GPP_T },
 231                 { PMC_GPP_A, GPP_A },
 232                 { PMC_GPP_R, GPP_R },
 233                 { PMC_GPD, GPD },
 234                 { PMC_GPP_S, GPP_S },
 235                 { PMC_GPP_H, GPP_H },
 236                 { PMC_GPP_D, GPP_D },
 237                 { PMC_GPP_U, GPP_U },
 238                 { PMC_GPP_F, GPP_F },
 239                 { PMC_GPP_C, GPP_C },
 240                 { PMC_GPP_E, GPP_E },
 241         };
 242         *num = ARRAY_SIZE(routes);
 243         return routes;
 244 }