src/soc/intel/xeon_sp/finalize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootstate.h>
   4 #include <console/console.h>
   5 #include <console/debug.h>
   6 #include <cpu/x86/mp.h>
   7 #include <cpu/x86/smm.h>
   8 #include <device/pci.h>
   9 #include <intelpch/lockdown.h>
  10 #include <soc/msr.h>
  11 #include <soc/pci_devs.h>
  12 #include <soc/pm.h>
  13 #include <soc/util.h>
  14 #include <soc/soc_util.h>
  15 #include <smp/spinlock.h>
  16
  17 #include "chip.h"
  18
  19 DECLARE_SPIN_LOCK(msr_ppin_lock);
  20
  21 static void lock_msr_ppin_ctl(void *unused)
  22 {
  23         msr_t msr;
  24
  25         msr = rdmsr(MSR_PLATFORM_INFO);
  26         if ((msr.lo & MSR_PPIN_CAP) == 0)
  27                 return;
  28
  29         spin_lock(&msr_ppin_lock);
  30
  31         msr = rdmsr(MSR_PPIN_CTL);
  32         if (msr.lo & MSR_PPIN_CTL_LOCK) {
  33                 spin_unlock(&msr_ppin_lock);
  34                 return;
  35         }
  36
  37         /* Clear enable and lock it */
  38         msr.lo &= ~MSR_PPIN_CTL_ENABLE;
  39         msr.lo |= MSR_PPIN_CTL_LOCK;
  40         wrmsr(MSR_PPIN_CTL, msr);
  41
  42         spin_unlock(&msr_ppin_lock);
  43 }
  44
  45 static void soc_finalize(void *unused)
  46 {
  47         printk(BIOS_DEBUG, "Finalizing chipset.\n");
  48
  49         /*
  50          * Disable ACPI PM timer based on Kconfig
  51          *
  52          * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
  53          * Disabling ACPI PM timer also switches off TCO.
  54          *
  55          * Note: In contrast to other platforms supporting PM timer emulation,
  56          * disabling the PM timer must be done *after* FSP has run on Xeon-SP,
  57          * because FSP makes use of the PM timer.
  58          */
  59         if (!CONFIG(USE_PM_ACPI_TIMER))
  60                 setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS);
  61
  62         apm_control(APM_CNT_FINALIZE);
  63         lock_pam0123();
  64
  65         if (CONFIG_MAX_SOCKET > 1) {
  66                 /* This MSR is package scope but run for all cpus for code simplicity */
  67                 if (mp_run_on_all_cpus(&lock_msr_ppin_ctl, NULL) != CB_SUCCESS)
  68                         printk(BIOS_ERR, "Lock PPIN CTL MSR failed\n");
  69         } else {
  70                 lock_msr_ppin_ctl(NULL);
  71         }
  72
  73         post_code(POSTCODE_OS_BOOT);
  74 }
  75
  76 static void bios_done_finalize(void *unused)
  77 {
  78         if (!CONFIG(SOC_INTEL_HAS_BIOS_DONE_MSR))
  79                 return;
  80
  81         printk(BIOS_DEBUG, "Setting BIOS_DONE\n");
  82         /* bios_done_msr() only defined for some Xeon-SP, such as SPR-SP */
  83         if (mp_run_on_all_cpus(&bios_done_msr, NULL) != CB_SUCCESS)
  84                 printk(BIOS_ERR, "Fail to set BIOS_DONE MSR\n");
  85 }
  86
  87 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, soc_finalize, NULL);
  88 /* FSP programs certain registers via Notify phase ReadyToBoot that can only be programmed
  89    before BIOS_DONE MSR is set, so coreboot sets BIOS_DONE as late as possible. */
  90 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, bios_done_finalize, NULL);