src/soc/mediatek/common/rtc_osc_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <soc/rtc.h>
   4 #include <soc/rtc_common.h>
   5
   6 /* 32k clock calibration */
   7 static int rtc_eosc_cali(void)
   8 {
   9         u16 diff_left, diff_right, cksel;
  10         u16 val = 0;
  11         u16 middle;
  12         u16 left = RTC_XOSCCALI_START;
  13         u16 right = RTC_XOSCCALI_END;
  14
  15         rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel);
  16         cksel &= ~PMIC_FQMTR_CKSEL_MASK;
  17         /* select EOSC_32 as fixed clock */
  18         rtc_write(PMIC_RG_FQMTR_CKSEL, cksel | PMIC_FQMTR_FIX_CLK_EOSC_32K);
  19         rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel);
  20         rtc_info("PMIC_RG_FQMTR_CKSEL=%#x\n", cksel);
  21
  22         while (left <= right) {
  23                 middle = (right + left) / 2;
  24                 if (middle == left)
  25                         break;
  26
  27                 /* select 26M as target clock */
  28                 val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0);
  29                 if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE)
  30                         break;
  31
  32                 if (val > RTC_FQMTR_HIGH_BASE)
  33                         right = middle;
  34                 else
  35                         left = middle;
  36         }
  37
  38         if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE)
  39                 return middle;
  40
  41         val = rtc_get_frequency_meter(left, PMIC_FQMTR_CON0_FQM26M_CK, 0);
  42         diff_left = ABS(val - RTC_FQMTR_LOW_BASE);
  43
  44         val = rtc_get_frequency_meter(right, PMIC_FQMTR_CON0_FQM26M_CK, 0);
  45         diff_right = ABS(val - RTC_FQMTR_LOW_BASE);
  46
  47         rtc_info("left: %d, middle: %d, right: %d\n", left, middle, right);
  48         if (diff_left < diff_right)
  49                 return left;
  50         else
  51                 return right;
  52 }
  53
  54 void rtc_osc_init(void)
  55 {
  56         u16 osc32con;
  57
  58         /* enable 32K export */
  59         rtc_gpio_init();
  60         /* calibrate eosc32 for powerdown clock */
  61         rtc_read(RTC_OSC32CON, &osc32con);
  62         rtc_info("osc32con val = %#x\n", osc32con);
  63         osc32con &= ~RTC_XOSCCALI_MASK;
  64         osc32con |= rtc_eosc_cali() & RTC_XOSCCALI_MASK;
  65         rtc_xosc_write(osc32con);
  66         rtc_info("EOSC32 cali val = %#x\n", osc32con);
  67 }