src/soc/qualcomm/sc7280/display/disp.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <soc/clock.h>
   5 #include <soc/display/mdssreg.h>
   6
   7 void enable_mdss_clk(void)
   8 {
   9         mdss_clock_enable(GCC_DISP_AHB);
  10
  11         // enable gdsc before enabling clocks.
  12         clock_enable_gdsc(MDSS_CORE_GDSC);
  13
  14         mdss_clock_enable(GCC_DISP_HF_AXI);
  15         mdss_clock_enable(GCC_DISP_SF_AXI);
  16         mdss_clock_enable(MDSS_CLK_AHB);
  17         mdss_clock_configure(MDSS_CLK_MDP, 400 * MHz, 0, 0, 0, 0, 0);
  18         mdss_clock_enable(MDSS_CLK_MDP);
  19         mdss_clock_configure(MDSS_CLK_VSYNC, 0, 0, 0, 0, 0, 0);
  20         mdss_clock_enable(MDSS_CLK_VSYNC);
  21 }
  22
  23 void mdss_intf_tg_setup(struct edid *edid)
  24 {
  25         uint32_t hsync_period, vsync_period;
  26         uint32_t active_vstart, active_vend, active_hctl;
  27         uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
  28
  29         hsync_period = edid->mode.ha + edid->mode.hbl;
  30         vsync_period = edid->mode.va + edid->mode.vbl;
  31         display_vstart = (edid->mode.vbl - edid->mode.vso) * hsync_period +
  32                           edid->mode.hbl - edid->mode.hso;
  33         display_vend = ((vsync_period - edid->mode.vso) * hsync_period) - edid->mode.hso - 1;
  34         hsync_ctl = (hsync_period << 16) | edid->mode.hspw;
  35         active_vstart = display_vstart;
  36         active_vend = active_vstart + (edid->mode.va * hsync_period) - 1;
  37         active_hctl = ((edid->mode.hbl - edid->mode.hso + edid->mode.ha - 1) << 16) |
  38                        (edid->mode.hbl - edid->mode.hso);
  39         display_hctl = active_hctl;
  40
  41         write32(&mdp_intf->intf_active_v_start_f0, active_vstart);
  42         write32(&mdp_intf->intf_active_v_end_f0, active_vend);
  43         write32(&mdp_intf->intf_active_hctl, active_hctl);
  44         write32(&mdp_intf->display_data_hctl, display_hctl);
  45         write32(&mdp_intf->intf_hsync_ctl, hsync_ctl);
  46         write32(&mdp_intf->intf_vysnc_period_f0, vsync_period * hsync_period);
  47         write32(&mdp_intf->intf_vysnc_pulse_width_f0, edid->mode.vspw * hsync_period);
  48         write32(&mdp_intf->intf_disp_hctl, display_hctl);
  49         write32(&mdp_intf->intf_disp_v_start_f0, display_vstart);
  50         write32(&mdp_intf->intf_disp_v_end_f0, display_vend);
  51         write32(&mdp_intf->intf_underflow_color, 0x00);
  52 }
  53
  54 void mdss_ctrl_config(void)
  55 {
  56         /* Select vigo pipe active */
  57         write32(&mdp_ctl->ctl_fetch_pipe_active, FETCH_PIPE_VIG0_ACTIVE);
  58
  59         /* PPB0 to INTF1 */
  60         write32(&mdp_ctl->ctl_intf_active, INTF_ACTIVE_5);
  61 }