src/mainboard/intel/adlrvp/memory_rpl.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/variants.h>
   4 #include <soc/romstage.h>
   5
   6 #include "board_id.h"
   7
   8 void rpl_memory_params(FSPM_UPD *memupd)
   9 {
  10         FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
  11
  12         int board_id = get_board_id();
  13
  14         switch (board_id) {
  15         case ADL_P_LP4_1:
  16         case ADL_P_LP4_2:
  17         case ADL_P_DDR4_1:
  18         case ADL_P_DDR4_2:
  19         case ADL_P_DDR5_1:
  20         case ADL_P_DDR5_2:
  21                 return;
  22         case ADL_P_LP5_1:
  23         case ADL_P_LP5_2:
  24                 mem_cfg->Lp5BankMode = 1;
  25                 return;
  26         default:
  27         }
  28 }