src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb

   1 chip soc/intel/alderlake
   2
   3         device cpu_cluster 0 on
   4                 device lapic 0 on end
   5         end
   6
   7         # GPE configuration
   8         # Note that GPE events called out in ASL code rely on this
   9         # route. i.e. If this route changes then the affected GPE
  10         # offset bits also need to be changed.
  11         register "pmc_gpe0_dw0" = "GPP_C"
  12         register "pmc_gpe0_dw1" = "GPP_D"
  13         register "pmc_gpe0_dw2" = "GPP_E"
  14
  15         # TCSS
  16         register "tcss_aux_ori" = "1"
  17         register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A5, .pad_auxn_dc = GPP_A6}"
  18
  19         # Enable CNVi Bluetooth
  20         register "cnvi_bt_core" = "true"
  21
  22         # FSP configuration
  23         register "sagv" = "SaGv_Enabled"
  24
  25         # S0ix enable
  26         register "s0ix_enable" = "1"
  27
  28         register "usb2_ports[0]" = "USB2_PORT_MID(OC1)"         # Type-A Port A0
  29         register "usb2_ports[1]" = "USB2_PORT_MID(OC2)"         # Type-A Port A1
  30         register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"     # M.2 WWAN
  31         register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"         # Type-A / Type-C Cl
  32         register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"     # M.2 Camera
  33         register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"         # Type-A / Type-C Co
  34         register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"     # M.2 Bluetooth
  35
  36         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"     # USB3/2 Type A port A0
  37         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"     # USB3/2 Type A port A1
  38         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
  39
  40         # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
  41         register "gen1_dec" = "0x00fc0801"
  42         register "gen2_dec" = "0x000c0201"
  43         # EC memory map range is 0x900-0x9ff
  44         register "gen3_dec" = "0x00fc0901"
  45
  46         # Enable PCH PCIE RP 5 using CLK 1
  47         register "pch_pcie_rp[PCH_RP(5)]" = "{
  48                 .clk_src = 1,
  49                 .clk_req = 1,
  50                 .flags = PCIE_RP_CLK_REQ_DETECT,
  51         }"
  52
  53         # Enable NVMe PCIE 9 using clk 0
  54         register "pch_pcie_rp[PCH_RP(9)]" = "{
  55                 .clk_src = 0,
  56                 .clk_req = 0,
  57                 .flags = PCIE_RP_LTR,
  58         }"
  59
  60         # Enable SD Card PCIE 8 using clk 3
  61         register "pch_pcie_rp[PCH_RP(8)]" = "{
  62                 .clk_src = 3,
  63                 .clk_req = 3,
  64                 .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR,
  65         }"
  66
  67         # Enable SATA
  68         register "sata_mode" = "0"
  69         register "sata_salp_support" = "1"
  70         register "sata_ports_enable[0]" = "0"
  71         register "sata_ports_enable[1]" = "1"
  72         register "sata_ports_dev_slp[0]" = "0"
  73         register "sata_ports_dev_slp[1]" = "1"
  74         register "sata_ports_enable_dito_config[1]" = "1"
  75
  76         register "serial_io_i2c_mode" = "{
  77                 [PchSerialIoIndexI2C0]  = PchSerialIoPci,
  78                 [PchSerialIoIndexI2C1]  = PchSerialIoPci,
  79                 [PchSerialIoIndexI2C2]  = PchSerialIoPci,
  80                 [PchSerialIoIndexI2C3]  = PchSerialIoPci,
  81                 [PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
  82                 [PchSerialIoIndexI2C5]  = PchSerialIoPci,
  83         }"
  84
  85         register "serial_io_gspi_mode" = "{
  86                 [PchSerialIoIndexGSPI0] = PchSerialIoPci,
  87                 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
  88                 [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
  89                 [PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
  90         }"
  91
  92         register "serial_io_gspi_cs_mode" = "{
  93                 [PchSerialIoIndexGSPI0] = 1,
  94         }"
  95
  96         register "serial_io_gspi_cs_state" = "{
  97                 [PchSerialIoIndexGSPI0] = 1,
  98         }"
  99
 100         register "serial_io_uart_mode" = "{
 101                 [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
 102                 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
 103                 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
 104         }"
 105
 106         # HD Audio
 107         register "pch_hda_dsp_enable" = "1"
 108         register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
 109         register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
 110         register "pch_hda_idisp_codec_enable" = "1"
 111
 112         # DP port
 113         register "ddi_portA_config" = "1"       # eDP
 114         register "ddi_portB_config" = "0"
 115
 116         # Enable Display Port Configuration
 117         register "ddi_ports_config" = "{
 118                 [DDI_PORT_A] = DDI_ENABLE_HPD,
 119                 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
 120                 [DDI_PORT_1] = DDI_ENABLE_HPD,
 121                 [DDI_PORT_2] = DDI_ENABLE_HPD,
 122         }"
 123
 124         # Intel Common SoC Config
 125         #+-------------------+---------------------------+
 126         #| Field             |  Value                    |
 127         #+-------------------+---------------------------+
 128         #| GSPI0             | cr50 TPM. Early init is   |
 129         #|                   | required to set up a BAR  |
 130         #|                   | for TPM communication     |
 131         #|                   | before memory is up       |
 132         #| GSPI1             | Fingerprint MCU           |
 133         #| I2C0              | SAR0, WWAN, HDMI          |
 134         #| I2C1              | Camera                    |
 135         #| I2C2              | Audio                     |
 136         #| I2C3              | Touchscreen, USI          |
 137         #| I2C5              | Trackpad                  |
 138         #+-------------------+---------------------------+
 139         register "common_soc_config" = "{
 140                 .gspi[0] = {
 141                         .speed_mhz = 1,
 142                         .early_init = 1,
 143                 },
 144                 .i2c[0] = {
 145                         .speed = I2C_SPEED_FAST,
 146                 },
 147                 .i2c[1] = {
 148                         .speed = I2C_SPEED_FAST,
 149                 },
 150                 .i2c[2] = {
 151                         .speed = I2C_SPEED_FAST,
 152                 },
 153                 .i2c[3] = {
 154                         .speed = I2C_SPEED_FAST,
 155                 },
 156                 .i2c[5] = {
 157                         .speed = I2C_SPEED_FAST,
 158                 },
 159         }"
 160
 161         device domain 0 on
 162                 device ref igpu on end
 163                 device ref dtt on end
 164                 device ref ipu on end
 165                 device ref tbt_pcie_rp0 on end
 166                 device ref tbt_pcie_rp1 on end
 167                 device ref tbt_pcie_rp2 on end
 168                 device ref tbt_pcie_rp3 on end
 169                 device ref crashlog off end
 170                 device ref tcss_xhci on end
 171                 device ref tcss_dma0 on
 172                         chip drivers/intel/usb4/retimer
 173                                 register "dfp" = "{
 174                                         [0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H19),},
 175                                         [1] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H19),}}"
 176                                 device generic 0 on end
 177                         end
 178                 end
 179                 device ref tcss_dma1 on end
 180                 device ref xhci on
 181                         chip drivers/usb/acpi
 182                                 register "desc" = ""Root Hub""
 183                                 register "type" = "UPC_TYPE_HUB"
 184                                 device ref xhci_root_hub on
 185                                         chip drivers/usb/acpi
 186                                                 register "desc" = ""Bluetooth""
 187                                                 register "type" = "UPC_TYPE_INTERNAL"
 188                                                 register "reset_gpio" =
 189                                                         "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
 190                                                 device ref usb2_port10 on end
 191                                         end
 192                                 end
 193                         end
 194                 end
 195                 device ref cnvi_wifi on
 196                         chip drivers/wifi/generic
 197                                 register "wake" = "GPE0_PME_B0"
 198                                 device generic 0 on end
 199                         end
 200                 end
 201                 device ref i2c0 on end
 202                 device ref i2c1 on end
 203                 device ref i2c2 on
 204                         chip drivers/i2c/generic
 205                                 register "hid" = ""10EC5682""
 206                                 register "name" = ""RT58""
 207                                 register "desc" = ""Headset Codec""
 208                                 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F9)"
 209                                 # Set the jd_src to RT5668_JD1 for jack detection
 210                                 register "property_count" = "1"
 211                                 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
 212                                 register "property_list[0].name" = ""realtek,jd-src""
 213                                 register "property_list[0].integer" = "1"
 214                                 device i2c 1a on end
 215                         end
 216                         chip drivers/i2c/max98373
 217                                 register "vmon_slot_no" = "0"
 218                                 register "imon_slot_no" = "1"
 219                                 register "uid" = "0"
 220                                 register "desc" = ""Right Speaker Amp""
 221                                 register "name" = ""MAXR""
 222                                 device i2c 31 on end
 223                         end
 224                         chip drivers/i2c/max98373
 225                                 register "vmon_slot_no" = "2"
 226                                 register "imon_slot_no" = "3"
 227                                 register "uid" = "1"
 228                                 register "desc" = ""Left Speaker Amp""
 229                                 register "name" = ""MAXL""
 230                                 device i2c 32 on end
 231                         end
 232                 end
 233                 device ref i2c3 on end
 234                 device ref heci1 on end
 235                 device ref sata on end
 236                 device ref i2c5 on
 237                         chip drivers/i2c/generic
 238                                 register "hid" = ""ELAN0000""
 239                                 register "desc" = ""ELAN Touchpad""
 240                                 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
 241                                 register "wake" = "GPE0_DW2_15"
 242                                 register "detect" = "1"
 243                                 device i2c 15 on end
 244                         end
 245                 end
 246                 device ref pcie_rp5 on end
 247                 device ref pcie_rp8 on
 248                         chip soc/intel/common/block/pcie/rtd3
 249                                 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)"
 250                                 register "srcclk_pin" = "3"
 251                                 device generic 0 on end
 252                         end
 253                 end
 254                 device ref pcie_rp9 on end
 255                 device ref uart0 on end
 256                 device ref gspi0 on
 257                         chip drivers/spi/acpi
 258                                 register "hid" = "ACPI_DT_NAMESPACE_HID"
 259                                 register "compat_string" = ""google,cr50""
 260                                 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C3_IRQ)"
 261                                 device spi 0 on end
 262                         end
 263                 end
 264                 device ref pch_espi on
 265                         chip ec/google/chromeec
 266                                 use conn0 as mux_conn[0]
 267                                 use conn1 as mux_conn[1]
 268                                 device pnp 0c09.0 on end
 269                         end
 270                 end
 271                 device ref p2sb on end
 272                 device ref pmc hidden
 273                         # The pmc_mux chip driver is a placeholder for the
 274                         # PMC.MUX device in the ACPI hierarchy.
 275                         chip drivers/intel/pmc_mux
 276                                 device generic 0 on
 277                                         chip drivers/intel/pmc_mux/conn
 278                                                 use usb2_port6 as usb2_port
 279                                                 use tcss_usb3_port1 as usb3_port
 280                                                 # SBU is fixed, HSL follows CC
 281                                                 register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
 282                                                 device generic 0 alias conn0 on end
 283                                         end
 284                                         chip drivers/intel/pmc_mux/conn
 285                                                 use usb2_port4 as usb2_port
 286                                                 use tcss_usb3_port2 as usb3_port
 287                                                 # SBU is fixed, HSL follows CC
 288                                                 register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
 289                                                 device generic 1 alias conn1 on end
 290                                         end
 291                                 end
 292                         end
 293                 end
 294                 device ref hda on end
 295                 device ref smbus on end
 296         end
 297 end