src/mainboard/msi/ms7d25/gpio.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <soc/gpio.h>
   4
   5 /*
   6  * Do not program the CLKREQ signals in coreboot to let FSP detect and
   7  * configure CLKREQ pads for PCIe ports. Otherwise the CLKREQ pads are
   8  * reprogrammed by FSP despite having GpioOverride=1 in the following manner:
   9  *
  10  * GPIO (reset) -> (CLKREQ (coreboot, configure pads) ->
  11  * GPIO input (FSP, detect) -> CLKREQ (FSP).
  12  *
  13  * Also if GpioOverride=1 the NAF_VME bit is not set for virtual wire GPIOs
  14  * that require it, e.g. the CPU PCIe CLKREQ bus. The pads that should not be
  15  * touched by coreboot are left commented in this file for reference. CLKREQ
  16  * reprogramming caused undefined behavior when ASPM and Clock PM was being
  17  * enabled by coreboot on PCIe endpoints of CPU PCIe x4 slot (coreboot printed
  18  * a lot of exceptions and simply halted).
  19  */
  20
  21 /* Pad configuration was generated automatically using intelp2m utility */
  22 static const struct pad_config gpio_table[] = {
  23
  24         /* ------- GPIO Community 0 ------- */
  25
  26         /* ------- GPIO Group GPP_I ------- */
  27
  28         /* GPP_I0 - GPIO */
  29         PAD_CFG_GPI_TRIG_OWN(GPP_I0, NONE, PLTRST, OFF, ACPI),
  30         /* GPP_I1 - DDSP_HPD1 */
  31         PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),
  32         /* GPP_I2 - DDSP_HPD2 */
  33         PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1),
  34         /* GPP_I3 - DDSP_HPD3 */
  35         PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1),
  36         /* GPP_I4 - DDSP_HPD4 */
  37         PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1),
  38         /* GPP_I5 - DDPB_CTRLCLK */
  39         PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1),
  40         /* GPP_I6 - DDPB_CTRLDATA */
  41         PAD_CFG_NF(GPP_I6, NONE, PLTRST, NF1),
  42         /* GPP_I7 - DDPC_CTRLCLK */
  43         PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1),
  44         /* GPP_I8 - DDPC_CTRLDATA */
  45         PAD_CFG_NF(GPP_I8, NONE, PLTRST, NF1),
  46         /* GPP_I9 - GPIO */
  47         PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, PLTRST, OFF, ACPI),
  48         /* GPP_I10 - GPIO */
  49         PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, PLTRST, OFF, ACPI),
  50         /* GPP_I11 - USB_OC4# */
  51         PAD_CFG_NF(GPP_I11, NONE, PLTRST, NF1),
  52         /* GPP_I12 - USB_OC5# */
  53         PAD_CFG_NF(GPP_I12, NONE, PLTRST, NF1),
  54         /* GPP_I13 - USB_OC6# */
  55         PAD_CFG_NF(GPP_I13, NONE, PLTRST, NF1),
  56         /* GPP_I14 - USB_OC7# */
  57         PAD_CFG_NF(GPP_I14, NONE, PLTRST, NF1),
  58         /* GPP_I15 - GPIO */
  59         PAD_CFG_GPI_TRIG_OWN(GPP_I15, NONE, PLTRST, OFF, ACPI),
  60         /* GPP_I16 - GPIO */
  61         PAD_CFG_GPI_TRIG_OWN(GPP_I16, NONE, PLTRST, OFF, ACPI),
  62         /* GPP_I17 - GPIO */
  63         PAD_CFG_GPI_TRIG_OWN(GPP_I17, NONE, PLTRST, OFF, ACPI),
  64         /* GPP_I18 - GPIO */
  65         PAD_CFG_GPI_TRIG_OWN(GPP_I18, NONE, PLTRST, OFF, ACPI),
  66         /* GPP_I19 - GPIO */
  67         PAD_CFG_GPI_TRIG_OWN(GPP_I19, NONE, PLTRST, OFF, ACPI),
  68         /* GPP_I20 - GPIO */
  69         PAD_CFG_GPI_TRIG_OWN(GPP_I20, NONE, PLTRST, OFF, ACPI),
  70         /* GPP_I21 - GPIO */
  71         PAD_CFG_GPI_TRIG_OWN(GPP_I21, NONE, PLTRST, OFF, ACPI),
  72         /* GPP_I22 - GPIO */
  73         PAD_CFG_GPI_TRIG_OWN(GPP_I22, NONE, PLTRST, OFF, ACPI),
  74
  75         /* ------- GPIO Group GPP_R ------- */
  76
  77         /* GPP_R0 - HDA_BCLK */
  78         PAD_CFG_NF(GPP_R0, NONE, PLTRST, NF1),
  79         /* GPP_R1 - HDA_SYNC */
  80         PAD_CFG_NF(GPP_R1, NONE, PLTRST, NF1),
  81         /* GPP_R2 - HDA_SDO */
  82         PAD_CFG_NF(GPP_R2, NONE, PLTRST, NF1),
  83         /* GPP_R3 - HDA_SDI0 */
  84         PAD_CFG_NF(GPP_R3, NONE, PLTRST, NF1),
  85         /* GPP_R4 - HDA_RST# */
  86         PAD_CFG_NF(GPP_R4, NONE, PLTRST, NF1),
  87         /* GPP_R5 - GPIO */
  88         PAD_CFG_GPI_TRIG_OWN(GPP_R5, NONE, PLTRST, OFF, ACPI),
  89         /* GPP_R6 - GPIO */
  90         PAD_CFG_GPI_TRIG_OWN(GPP_R6, NONE, PLTRST, OFF, ACPI),
  91         /* GPP_R7 - GPIO */
  92         PAD_CFG_GPI_TRIG_OWN(GPP_R7, NONE, PLTRST, OFF, ACPI),
  93         /* GPP_R8 - GPIO */
  94         PAD_CFG_GPI_TRIG_OWN(GPP_R8, NONE, PLTRST, OFF, ACPI),
  95         /* GPP_R9 - GPIO */
  96         PAD_CFG_GPI_TRIG_OWN(GPP_R9, NONE, PLTRST, OFF, ACPI),
  97         /* GPP_R10 - GPIO */
  98         PAD_CFG_GPI_TRIG_OWN(GPP_R10, NONE, PLTRST, OFF, ACPI),
  99         /* GPP_R11 - GPIO */
 100         PAD_CFG_GPI_TRIG_OWN(GPP_R11, NONE, PLTRST, OFF, ACPI),
 101         /* GPP_R12 - DDP3_CTRLCLK */
 102         PAD_CFG_NF(GPP_R12, NONE, PLTRST, NF2),
 103         /* GPP_R13 - DDP3_CTRLDATA */
 104         PAD_CFG_NF(GPP_R13, NONE, PLTRST, NF2),
 105         /* GPP_R14 - GPIO */
 106         PAD_CFG_GPI_TRIG_OWN(GPP_R14, NONE, PLTRST, OFF, ACPI),
 107         /* GPP_R15 - GPIO */
 108         PAD_CFG_GPI_TRIG_OWN(GPP_R15, NONE, PLTRST, OFF, ACPI),
 109         /* GPP_R16 - DDP1_CTRLCLK */
 110         PAD_CFG_NF(GPP_R16, NONE, PLTRST, NF1),
 111         /* GPP_R17 - DDP1_CTRLDATA */
 112         PAD_CFG_NF(GPP_R17, NONE, PLTRST, NF1),
 113         /* GPP_R18 - GPIO */
 114         PAD_CFG_GPI_TRIG_OWN(GPP_R18, NONE, PLTRST, OFF, ACPI),
 115         /* GPP_R19 - GPIO */
 116         PAD_CFG_GPI_TRIG_OWN(GPP_R19, NONE, PLTRST, OFF, ACPI),
 117         /* GPP_R20 - GPIO */
 118         PAD_CFG_GPI_TRIG_OWN(GPP_R20, NONE, PLTRST, OFF, ACPI),
 119         /* GPP_R21 - GPIO */
 120         PAD_CFG_GPI_TRIG_OWN(GPP_R21, NONE, PLTRST, OFF, ACPI),
 121
 122         /* ------- GPIO Group GPP_J ------- */
 123
 124         /* GPP_J0 - GPIO */
 125         PAD_CFG_GPI_TRIG_OWN(GPP_J0, NONE, PLTRST, OFF, ACPI),
 126         /* GPP_J1 - GPIO */
 127         PAD_CFG_GPI_TRIG_OWN(GPP_J1, NONE, PLTRST, OFF, ACPI),
 128         /* GPP_J2 - CNV_BRI_DT */
 129         PAD_CFG_NF(GPP_J2, NONE, PLTRST, NF1),
 130         /* GPP_J3 - CNV_BRI_RSP */
 131         PAD_CFG_NF(GPP_J3, NONE, PLTRST, NF1),
 132         /* GPP_J4 - CNV_RGI_DT */
 133         PAD_CFG_NF(GPP_J4, NONE, PLTRST, NF1),
 134         /* GPP_J5 - CNV_RGI_RSP */
 135         PAD_CFG_NF(GPP_J5, NONE, PLTRST, NF1),
 136         /* GPP_J6 - GPIO */
 137         PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, PLTRST, OFF, ACPI),
 138         /* GPP_J7 - GPIO */
 139         PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, PLTRST, OFF, ACPI),
 140         /* Let FSP enable the respective CLKREQ pins, see comment at the top of file */
 141         /* GPP_J8 - SRCCLKREQ16# */
 142         // PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
 143         /* GPP_J9 - SRCCLKREQ17# */
 144         // PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
 145         /* GPP_J10 - GPIO */
 146         PAD_CFG_GPI_TRIG_OWN(GPP_J10, NONE, PLTRST, OFF, ACPI),
 147         /* GPP_J11 - GPIO */
 148         PAD_CFG_GPI_TRIG_OWN(GPP_J11, NONE, PLTRST, OFF, ACPI),
 149
 150         /* vGPIO controls certain features like CNVi, include the definitions as well */
 151
 152         /* ------- GPIO Group vGPIO ------- */
 153         /* CNVi BT Enable, TX = 1 */
 154         _PAD_CFG_STRUCT(VGPIO_0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1, 0),
 155         /* CNVi BT host wake */
 156         _PAD_CFG_STRUCT(VGPIO_4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
 157         /* CNVi BT on USB, TX = 1 */
 158         _PAD_CFG_STRUCT(VGPIO_5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1, 0),
 159         _PAD_CFG_STRUCT(VGPIO_6, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),  /* GPIO */
 160         _PAD_CFG_STRUCT(VGPIO_7, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),  /* GPIO */
 161         _PAD_CFG_STRUCT(VGPIO_8, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),  /* GPIO */
 162         _PAD_CFG_STRUCT(VGPIO_9, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),  /* GPIO */
 163         _PAD_CFG_STRUCT(VGPIO_10, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),  /* vCNV_MFUART1_TXD */
 164         _PAD_CFG_STRUCT(VGPIO_11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),  /* vCNV_MFUART1_RXD */
 165         _PAD_CFG_STRUCT(VGPIO_12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),  /* vCNV_MFUART1_CTS# */
 166         _PAD_CFG_STRUCT(VGPIO_13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),  /* vCNV_MFUART1_RTS# */
 167         _PAD_CFG_STRUCT(VGPIO_18, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
 168         _PAD_CFG_STRUCT(VGPIO_19, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
 169         _PAD_CFG_STRUCT(VGPIO_20, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
 170         _PAD_CFG_STRUCT(VGPIO_21, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
 171         _PAD_CFG_STRUCT(VGPIO_22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),  /* vISH_UART0_TXD */
 172         _PAD_CFG_STRUCT(VGPIO_23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),  /* vISH_UART0_RXD */
 173         _PAD_CFG_STRUCT(VGPIO_24, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),  /* vISH_UART0_CTS# */
 174         _PAD_CFG_STRUCT(VGPIO_25, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),  /* vISH_UART0_RTS# */
 175         _PAD_CFG_STRUCT(VGPIO_30, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
 176         _PAD_CFG_STRUCT(VGPIO_31, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
 177         _PAD_CFG_STRUCT(VGPIO_32, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
 178         _PAD_CFG_STRUCT(VGPIO_33, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
 179         _PAD_CFG_STRUCT(VGPIO_34, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
 180         _PAD_CFG_STRUCT(VGPIO_35, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
 181         _PAD_CFG_STRUCT(VGPIO_36, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
 182         _PAD_CFG_STRUCT(VGPIO_37, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0), /* GPIO */
 183
 184         /* ------- GPIO Group vGPIO_0 ------- */
 185         /* These are Virtual USB OC pins */
 186         _PAD_CFG_STRUCT(VGPIO_USB_0,  PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_0 */
 187         _PAD_CFG_STRUCT(VGPIO_USB_1,  PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_1 */
 188         _PAD_CFG_STRUCT(VGPIO_USB_2,  PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_2 */
 189         _PAD_CFG_STRUCT(VGPIO_USB_3,  PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_3 */
 190         _PAD_CFG_STRUCT(VGPIO_USB_8,  PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_8 */
 191         _PAD_CFG_STRUCT(VGPIO_USB_9,  PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_9 */
 192         _PAD_CFG_STRUCT(VGPIO_USB_10, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_10 */
 193         _PAD_CFG_STRUCT(VGPIO_USB_11, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_11 */
 194
 195         /* ------- GPIO Community 1 ------- */
 196
 197         /* ------- GPIO Group GPP_B ------- */
 198
 199         /* GPP_B0 - GPIO */
 200         PAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI),
 201         /* GPP_B1 - GPIO */
 202         PAD_CFG_GPI_TRIG_OWN(GPP_B1, NONE, PLTRST, OFF, ACPI),
 203         /* GPP_B2 - GPIO */
 204         PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, PLTRST, OFF, ACPI),
 205         /* GPP_B3 - GPIO */
 206         PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI),
 207         /* GPP_B4 - GPIO */
 208         PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, PLTRST, OFF, ACPI),
 209         /* GPP_B5 - GPIO */
 210         PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, PLTRST, OFF, ACPI),
 211         /* GPP_B6 - GPIO */
 212         PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, ACPI),
 213         /* GPP_B7 - GPIO */
 214         PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, ACPI),
 215         /* GPP_B8 - GPIO */
 216         PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI),
 217         /* GPP_B9 - GPIO */
 218         PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, PLTRST, OFF, ACPI),
 219         /* GPP_B10 - GPIO */
 220         PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, PLTRST, OFF, ACPI),
 221         /* GPP_B11 - GPIO */
 222         PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI),
 223         /* GPP_B12 - SLP_S0# */
 224         PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1),
 225         /* GPP_B13 - PLTRST# */
 226         PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1),
 227         /* GPP_B14 - SPKR */
 228         PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1),
 229         /* GPP_B15 - GPIO */
 230         PAD_CFG_GPO(GPP_B15, 0, PLTRST),
 231         /* GPP_B16 - GPIO */
 232         PAD_CFG_GPO(GPP_B16, 0, PLTRST),
 233         /* GPP_B17 - GPIO */
 234         PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, PLTRST, OFF, ACPI),
 235         /* GPP_B18 - PMCALERT# */
 236         PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1),
 237         /* GPP_B19 - GPIO */
 238         PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, PLTRST, OFF, ACPI),
 239         /* GPP_B20 - GPIO */
 240         PAD_CFG_GPI_TRIG_OWN(GPP_B20, NONE, PLTRST, OFF, ACPI),
 241         /* GPP_B21 - GPIO */
 242         PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, PLTRST, OFF, ACPI),
 243         /* GPP_B22 - GPIO */
 244         PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, PLTRST, OFF, ACPI),
 245         /* GPP_B23 - GPIO */
 246         PAD_CFG_GPI_TRIG_OWN(GPP_B23, NONE, PLTRST, OFF, ACPI),
 247
 248         /* ------- GPIO Group GPP_G ------- */
 249
 250         /* GPP_G0 - GPIO */
 251         PAD_CFG_GPO(GPP_G0, 0, PLTRST),
 252         /* GPP_G1 - GPIO */
 253         PAD_CFG_GPO(GPP_G1, 1, RSMRST),
 254         /* GPP_G2 - DNX_FORCE_RELOAD */
 255         PAD_CFG_NF(GPP_G2, NONE, PLTRST, NF1),
 256         /* GPP_G3 - GPIO */
 257         PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI),
 258         /* GPP_G4 - GPIO */
 259         PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI),
 260         /* GPP_G5 - SLP_DRAM# */
 261         PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1),
 262         /* GPP_G6 - GPIO */
 263         PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI),
 264         /* GPP_G7 - GPIO */
 265         PAD_NC(GPP_G7, NONE),
 266
 267         /* ------- GPIO Group GPP_H ------- */
 268
 269         /* GPP_H0 - GPIO */
 270         PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, PLTRST, OFF, ACPI),
 271         /* GPP_H1 - GPIO */
 272         PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI),
 273         /* Let FSP enable the respective CLKREQ pins, see comment at the top of file */
 274         /* GPP_H2 - SRCCLKREQ8# */
 275         // PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
 276         /* GPP_H3 - SRCCLKREQ9# */
 277         // PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
 278         /* GPP_H4 - SRCCLKREQ10# */
 279         // PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 280         /* GPP_H5 - SRCCLKREQ11# */
 281         // PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 282         /* GPP_H6 - SRCCLKREQ12# */
 283         // PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 284         /* GPP_H7 - SRCCLKREQ13# */
 285         // PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 286         /* GPP_H8 - SRCCLKREQ14# */
 287         // PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
 288         /* GPP_H9 - SRCCLKREQ15# */
 289         // PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
 290
 291         /* GPP_H10 - GPIO */
 292         PAD_CFG_GPI_TRIG_OWN(GPP_H10, NONE, PLTRST, OFF, ACPI),
 293         /* GPP_H11 - GPIO */
 294         PAD_CFG_GPI_TRIG_OWN(GPP_H11, NONE, PLTRST, OFF, ACPI),
 295         /* GPP_H12 - GPIO */
 296         PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, PLTRST, OFF, ACPI),
 297         /* GPP_H13 - GPIO */
 298         PAD_CFG_GPI_TRIG_OWN(GPP_H13, NONE, PLTRST, OFF, ACPI),
 299         /* GPP_H14 - GPIO */
 300         PAD_CFG_GPI_TRIG_OWN(GPP_H14, NONE, PLTRST, OFF, ACPI),
 301         /* GPP_H15 - GPIO */
 302         PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, ACPI),
 303         /* GPP_H16 - GPIO */
 304         PAD_CFG_GPI_TRIG_OWN(GPP_H16, NONE, PLTRST, OFF, ACPI),
 305         /* GPP_H17 - GPIO */
 306         PAD_CFG_GPI_TRIG_OWN(GPP_H17, NONE, PLTRST, OFF, ACPI),
 307         /* GPP_H18 - GPIO */
 308         PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, PLTRST, OFF, ACPI),
 309         /* GPP_H19 - GPIO */
 310         PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, ACPI),
 311         /* GPP_H20 - GPIO */
 312         PAD_CFG_GPO(GPP_H20, 1, PLTRST),
 313         /* GPP_H21 - GPIO */
 314         PAD_CFG_GPO(GPP_H21, 0, PLTRST),
 315         /* GPP_H22 - GPIO */
 316         PAD_CFG_GPO(GPP_H22, 1, PLTRST),
 317         /* GPP_H23 - GPIO */
 318         PAD_CFG_GPO(GPP_H23, 1, PLTRST),
 319
 320         /* ------- GPIO Community 2 ------- */
 321
 322         /* ------- GPIO Group GPD ------- */
 323
 324         /* GPD0 - GPIO */
 325         PAD_CFG_GPI_TRIG_OWN(GPD0, NONE, PLTRST, OFF, ACPI),
 326         /* GPD1 - GPIO */
 327         PAD_CFG_GPI_TRIG_OWN(GPD1, NONE, PLTRST, OFF, ACPI),
 328         /* GPD2 - LAN_WAKE# */
 329         PAD_CFG_NF(GPD2, NONE, PLTRST, NF1),
 330         /* GPD3 - PWRBTN# */
 331         PAD_CFG_NF(GPD3, NONE, PLTRST, NF1),
 332         /* GPD4 - SLP_S3# */
 333         PAD_CFG_NF(GPD4, NONE, PLTRST, NF1),
 334         /* GPD5 - SLP_S4# */
 335         PAD_CFG_NF(GPD5, NONE, PLTRST, NF1),
 336         /* GPD6 - SLP_A# */
 337         PAD_CFG_NF(GPD6, NONE, PLTRST, NF1),
 338         /* GPD7 - GPIO */
 339         PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, PLTRST, OFF, ACPI),
 340         /* GPD8 - SUSCLK */
 341         PAD_CFG_NF(GPD8, NONE, PLTRST, NF1),
 342         /* GPD9 - SLP_WLAN# */
 343         PAD_CFG_NF(GPD9, NONE, PLTRST, NF1),
 344         /* GPD10 - SLP_S5# */
 345         PAD_CFG_NF(GPD10, NONE, PLTRST, NF1),
 346         /* GPD11 - GPIO */
 347         PAD_CFG_GPI_TRIG_OWN(GPD11, NONE, PLTRST, OFF, ACPI),
 348         /* GPD12 - GPIO */
 349         PAD_CFG_TERM_GPO(GPD12, 1, DN_5K, RSMRST),
 350
 351         /* ------- GPIO Community 3 ------- */
 352
 353         /* ------- GPIO Group GPP_A ------- */
 354
 355         /* GPP_A0 - ESPI_IO0 */
 356         PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1),
 357         /* GPP_A1 - ESPI_IO1 */
 358         PAD_CFG_NF(GPP_A1, NONE, PLTRST, NF1),
 359         /* GPP_A2 - ESPI_IO2 */
 360         PAD_CFG_NF(GPP_A2, NONE, PLTRST, NF1),
 361         /* GPP_A3 - ESPI_IO3 */
 362         PAD_CFG_NF(GPP_A3, NONE, PLTRST, NF1),
 363         /* GPP_A4 - ESPI_CS0# */
 364         PAD_CFG_NF(GPP_A4, NONE, PLTRST, NF1),
 365         /* GPP_A5 - ESPI_CLK */
 366         PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1),
 367         /* GPP_A6 - ESPI_RESET# */
 368         PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1),
 369         /* GPP_A7 - GPIO */
 370         PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI),
 371         /* GPP_A8 - GPIO */
 372         PAD_CFG_GPI_TRIG_OWN(GPP_A8, NONE, PLTRST, OFF, ACPI),
 373         /* GPP_A9 - GPIO */
 374         PAD_CFG_GPI_TRIG_OWN(GPP_A9, NONE, PLTRST, OFF, ACPI),
 375         /* GPP_A10 - GPIO */
 376         PAD_CFG_GPI_TRIG_OWN(GPP_A10, NONE, PLTRST, OFF, ACPI),
 377         /* GPP_A11 - GPIO */
 378         PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, PLTRST, OFF, ACPI),
 379         /* GPP_A12 - GPIO */
 380         PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, PLTRST, OFF, ACPI),
 381         /* GPP_A13 - GPIO */
 382         PAD_CFG_GPI_TRIG_OWN(GPP_A13, NONE, PLTRST, OFF, ACPI),
 383         /* GPP_A14 - GPIO */
 384         PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI),
 385
 386         /* ------- GPIO Group GPP_C ------- */
 387
 388         /* GPP_C0 - SMBCLK */
 389         PAD_CFG_NF(GPP_C0, NONE, PLTRST, NF1),
 390         /* GPP_C1 - SMBDATA */
 391         PAD_CFG_NF(GPP_C1, NONE, PLTRST, NF1),
 392         /* GPP_C2 - SMBALERT# */
 393         PAD_CFG_NF(GPP_C2, NONE, PLTRST, NF1),
 394         /* GPP_C3 - GPIO */
 395         PAD_CFG_GPO(GPP_C3, 1, PLTRST),
 396         /* GPP_C4 - GPIO */
 397         PAD_CFG_GPO(GPP_C4, 1, PLTRST),
 398         /* GPP_C5 - GPIO */
 399         PAD_CFG_GPI_TRIG_OWN(GPP_C5, NONE, PLTRST, OFF, ACPI),
 400         /* GPP_C6 - GPIO */
 401         PAD_CFG_GPO(GPP_C6, 0, PLTRST),
 402         /* GPP_C7 - GPIO */
 403         PAD_CFG_GPO(GPP_C7, 0, PLTRST),
 404         /* GPP_C8 - GPIO */
 405         PAD_CFG_GPO(GPP_C8, 1, RSMRST),
 406         /* GPP_C9 - GPIO */
 407         PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI),
 408         /* GPP_C10 - GPIO */
 409         PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, ACPI),
 410         /* GPP_C11 - GPIO */
 411         PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, PLTRST, OFF, ACPI),
 412         /* GPP_C12 - GPIO */
 413         PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, PLTRST, OFF, ACPI),
 414         /* GPP_C13 - GPIO */
 415         PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, PLTRST, OFF, ACPI),
 416         /* GPP_C14 - GPIO */
 417         PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, PLTRST, OFF, ACPI),
 418         /* GPP_C15 - GPIO */
 419         PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, PLTRST, OFF, ACPI),
 420         /* GPP_C16 - I2C0_SDA */
 421         PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
 422         /* GPP_C17 - I2C0_SCL */
 423         PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
 424         /* GPP_C18 - GPIO */
 425         PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, PLTRST, OFF, ACPI),
 426         /* GPP_C19 - GPIO */
 427         PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, PLTRST, OFF, ACPI),
 428         /* GPP_C20 - GPIO */
 429         PAD_CFG_GPO(GPP_C20, 0, PLTRST),
 430         /* GPP_C21 - GPIO */
 431         PAD_CFG_GPO(GPP_C21, 0, PLTRST),
 432         /* GPP_C22 - GPIO */
 433         PAD_CFG_GPI_TRIG_OWN(GPP_C22, NONE, PLTRST, OFF, ACPI),
 434         /* GPP_C23 - GPIO */
 435         PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, PLTRST, OFF, ACPI),
 436
 437         /* TODO: move VW programming to soc directory and make it dependent on FSP settings? */
 438         /* Let FSP enable the respective CLKREQ pins, see comment at the top of file */
 439         /* CPU PCIe 6.0 CLKREQ virtual wire message bus */
 440         // _PAD_CFG_STRUCT(VGPIO_PCIE_0,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 441         // _PAD_CFG_STRUCT(VGPIO_PCIE_1,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 442         // _PAD_CFG_STRUCT(VGPIO_PCIE_2,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 443         // _PAD_CFG_STRUCT(VGPIO_PCIE_3,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 444         // _PAD_CFG_STRUCT(VGPIO_PCIE_4,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 445         // _PAD_CFG_STRUCT(VGPIO_PCIE_5,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 446         // _PAD_CFG_STRUCT(VGPIO_PCIE_6,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 447         // _PAD_CFG_STRUCT(VGPIO_PCIE_7,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 448         // _PAD_CFG_STRUCT(VGPIO_PCIE_8,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 449         // _PAD_CFG_STRUCT(VGPIO_PCIE_9,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 450         // _PAD_CFG_STRUCT(VGPIO_PCIE_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 451         // _PAD_CFG_STRUCT(VGPIO_PCIE_11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 452         // _PAD_CFG_STRUCT(VGPIO_PCIE_12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 453         // _PAD_CFG_STRUCT(VGPIO_PCIE_13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 454         // _PAD_CFG_STRUCT(VGPIO_PCIE_14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 455         // _PAD_CFG_STRUCT(VGPIO_PCIE_15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 456         // _PAD_CFG_STRUCT(VGPIO_PCIE_64, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 457         // _PAD_CFG_STRUCT(VGPIO_PCIE_65, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 458         // _PAD_CFG_STRUCT(VGPIO_PCIE_66, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 459         // _PAD_CFG_STRUCT(VGPIO_PCIE_67, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 460
 461         /* CPU PCIe 1.0 CLKREQ virtual wire message bus */
 462         // _PAD_CFG_STRUCT(VGPIO_PCIE_16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 463         // _PAD_CFG_STRUCT(VGPIO_PCIE_17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 464         // _PAD_CFG_STRUCT(VGPIO_PCIE_18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 465         // _PAD_CFG_STRUCT(VGPIO_PCIE_19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 466         // _PAD_CFG_STRUCT(VGPIO_PCIE_20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 467         // _PAD_CFG_STRUCT(VGPIO_PCIE_21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 468         // _PAD_CFG_STRUCT(VGPIO_PCIE_22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 469         // _PAD_CFG_STRUCT(VGPIO_PCIE_23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 470         // _PAD_CFG_STRUCT(VGPIO_PCIE_24, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 471         // _PAD_CFG_STRUCT(VGPIO_PCIE_25, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 472         // _PAD_CFG_STRUCT(VGPIO_PCIE_26, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 473         // _PAD_CFG_STRUCT(VGPIO_PCIE_27, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 474         // _PAD_CFG_STRUCT(VGPIO_PCIE_28, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 475         // _PAD_CFG_STRUCT(VGPIO_PCIE_29, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 476         // _PAD_CFG_STRUCT(VGPIO_PCIE_30, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 477         // _PAD_CFG_STRUCT(VGPIO_PCIE_31, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 478         // _PAD_CFG_STRUCT(VGPIO_PCIE_68, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 479         // _PAD_CFG_STRUCT(VGPIO_PCIE_69, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 480         // _PAD_CFG_STRUCT(VGPIO_PCIE_70, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 481         // _PAD_CFG_STRUCT(VGPIO_PCIE_71, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
 482
 483         /* ------- GPIO Community 4 ------- */
 484
 485         /* ------- GPIO Group GPP_S ------- */
 486
 487         /* GPP_S0 - GPIO */
 488         PAD_CFG_GPI_TRIG_OWN(GPP_S0, NONE, PLTRST, OFF, ACPI),
 489         /* GPP_S1 - GPIO */
 490         PAD_CFG_GPI_TRIG_OWN(GPP_S1, NONE, PLTRST, OFF, ACPI),
 491         /* GPP_S2 - GPIO */
 492         PAD_CFG_GPI_TRIG_OWN(GPP_S2, NONE, PLTRST, OFF, ACPI),
 493         /* GPP_S3 - GPIO */
 494         PAD_CFG_GPI_TRIG_OWN(GPP_S3, NONE, PLTRST, OFF, ACPI),
 495         /* GPP_S4 - GPIO */
 496         PAD_CFG_GPI_TRIG_OWN(GPP_S4, NONE, PLTRST, OFF, ACPI),
 497         /* GPP_S5 - GPIO */
 498         PAD_CFG_GPI_TRIG_OWN(GPP_S5, NONE, PLTRST, OFF, ACPI),
 499         /* GPP_S6 - GPIO */
 500         PAD_CFG_GPI_TRIG_OWN(GPP_S6, NONE, PLTRST, OFF, ACPI),
 501         /* GPP_S7 - GPIO */
 502         PAD_CFG_GPI_TRIG_OWN(GPP_S7, NONE, PLTRST, OFF, ACPI),
 503
 504         /* ------- GPIO Group GPP_E ------- */
 505
 506         /* GPP_E0 - SATAXPCIE0 */
 507         PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF1),
 508         /* GPP_E1 - SATAXPCIE1 */
 509         PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1),
 510         /* GPP_E2 - GPIO */
 511         PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, PLTRST, OFF, ACPI),
 512         /* GPP_E3 - GPIO */
 513         PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, PLTRST, OFF, ACPI),
 514         /* GPP_E4 - GPIO */
 515         PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, PLTRST, OFF, ACPI),
 516         /* GPP_E5 - GPIO */
 517         PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, PLTRST, OFF, ACPI),
 518         /* GPP_E6 - GPIO */
 519         PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, PLTRST, OFF, ACPI),
 520         /* GPP_E7 - GPIO */
 521         PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI),
 522         /* GPP_E8 - SATALED# */
 523         PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1),
 524         /* GPP_E9 - USB_OC0# */
 525         PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF1),
 526         /* GPP_E10 - USB_OC1# */
 527         PAD_CFG_NF(GPP_E10, NONE, PLTRST, NF1),
 528         /* GPP_E11 - USB_OC2# */
 529         PAD_CFG_NF(GPP_E11, NONE, PLTRST, NF1),
 530         /* GPP_E12 - USB_OC3# */
 531         PAD_CFG_NF(GPP_E12, NONE, PLTRST, NF1),
 532         /* GPP_E13 - GPIO */
 533         PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, PLTRST, OFF, ACPI),
 534         /* GPP_E14 - GPIO */
 535         PAD_CFG_GPI_TRIG_OWN(GPP_E14, NONE, PLTRST, OFF, ACPI),
 536         /* GPP_E15 - GPIO */
 537         PAD_CFG_GPI_TRIG_OWN(GPP_E15, NONE, PLTRST, OFF, ACPI),
 538         /* GPP_E16 - GPIO */
 539         PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI),
 540         /* GPP_E17 - GPIO */
 541         PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, PLTRST, OFF, ACPI),
 542         /* GPP_E18 - GPIO */
 543         PAD_CFG_GPI_TRIG_OWN(GPP_E18, NONE, PLTRST, OFF, ACPI),
 544         /* GPP_E19 - GPIO */
 545         PAD_CFG_GPI_TRIG_OWN(GPP_E19, NONE, PLTRST, OFF, ACPI),
 546         /* GPP_E20 - GPIO */
 547         PAD_CFG_GPI_TRIG_OWN(GPP_E20, NONE, PLTRST, OFF, ACPI),
 548         /* GPP_E21 - GPIO */
 549         PAD_CFG_GPI_TRIG_OWN(GPP_E21, NONE, PLTRST, OFF, ACPI),
 550
 551         /* ------- GPIO Group GPP_K ------- */
 552
 553         /* GPP_K0 - GPIO */
 554         PAD_CFG_GPI_TRIG_OWN(GPP_K0, NONE, PLTRST, OFF, ACPI),
 555         /* GPP_K1 - GPIO */
 556         PAD_CFG_GPI_TRIG_OWN(GPP_K1, NONE, PLTRST, OFF, ACPI),
 557         /* GPP_K2 - GPIO */
 558         PAD_CFG_GPI_TRIG_OWN(GPP_K2, NONE, PLTRST, OFF, ACPI),
 559         /* GPP_K3 - GPIO */
 560         PAD_CFG_GPI_TRIG_OWN(GPP_K3, NONE, PLTRST, OFF, ACPI),
 561         /* GPP_K4 - GPIO */
 562         PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, PLTRST, OFF, ACPI),
 563         /* GPP_K5 - GPIO */
 564         PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, PLTRST, OFF, ACPI),
 565         /* GPP_K6 - n/a */
 566         PAD_CFG_NF(GPP_K6, UP_20K, DEEP, NF2),
 567         /* GPP_K7 - n/a */
 568         PAD_CFG_NF(GPP_K7, DN_20K, DEEP, NF2),
 569         /* GPP_K8 - CORE_VID0 */
 570         PAD_CFG_NF(GPP_K8, NONE, PLTRST, NF1),
 571         /* GPP_K9 - CORE_VID1 */
 572         PAD_CFG_NF(GPP_K9, NONE, PLTRST, NF1),
 573         /* GPP_K10 - n/a */
 574         PAD_CFG_NF(GPP_K10, UP_20K, DEEP, NF2),
 575         /* GPP_K11 - GPIO */
 576         PAD_CFG_GPI_TRIG_OWN(GPP_K11, NONE, PLTRST, OFF, ACPI),
 577
 578         /* ------- GPIO Group GPP_F ------- */
 579
 580         /* GPP_F0 - GPIO */
 581         PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, PLTRST, OFF, ACPI),
 582         /* GPP_F1 - GPIO */
 583         PAD_CFG_GPI_SCI(GPP_F1, NONE, PLTRST, EDGE_SINGLE, INVERT),
 584         /* GPP_F2 - GPIO */
 585         PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, PLTRST, OFF, ACPI),
 586         /* GPP_F3 - GPIO */
 587         PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI),
 588         /* GPP_F4 - GPIO */
 589         PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, PLTRST, OFF, ACPI),
 590         /* GPP_F5 - GPIO */
 591         PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI),
 592         /* GPP_F6 - GPIO */
 593         PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, PLTRST, OFF, ACPI),
 594         /* GPP_F7 - GPIO */
 595         PAD_CFG_GPI_TRIG_OWN(GPP_F7, NONE, PLTRST, OFF, ACPI),
 596         /* GPP_F8 - SATA_DEVSLP6 */
 597         PAD_CFG_NF(GPP_F8, NONE, PLTRST, NF1),
 598         /* GPP_F9 - SATA_DEVSLP7 */
 599         PAD_CFG_NF(GPP_F9, NONE, PLTRST, NF1),
 600         /* GPP_F10 - GPIO */
 601         PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, PLTRST, OFF, ACPI),
 602         /* GPP_F11 - GPIO */
 603         PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI),
 604         /* GPP_F12 - GPIO */
 605         PAD_CFG_GPO(GPP_F12, 1, RSMRST),
 606         /* GPP_F13 - GPIO */
 607         PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, PLTRST, OFF, ACPI),
 608         /* GPP_F14 - PS_ON# */
 609         PAD_CFG_NF(GPP_F14, NONE, PLTRST, NF1),
 610         /* GPP_F15 - GPIO */
 611         PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, PLTRST, OFF, ACPI),
 612         /* GPP_F16 - GPIO */
 613         PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, PLTRST, OFF, ACPI),
 614         /* GPP_F17 - GPIO */
 615         PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI),
 616         /* GPP_F18 - GPIO */
 617         PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, PLTRST, OFF, ACPI),
 618         /* GPP_F19 - GPIO */
 619         PAD_CFG_GPI_TRIG_OWN(GPP_F19, NONE, PLTRST, OFF, ACPI),
 620         /* GPP_F20 - GPIO */
 621         PAD_CFG_GPI_TRIG_OWN(GPP_F20, NONE, PLTRST, OFF, ACPI),
 622         /* GPP_F21 - GPIO */
 623         PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, PLTRST, OFF, ACPI),
 624         /* GPP_F22 - GPIO */
 625         PAD_CFG_GPI_TRIG_OWN(GPP_F22, NONE, PLTRST, OFF, ACPI),
 626         /* GPP_F23 - GPIO */
 627         PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, PLTRST, OFF, ACPI),
 628
 629         /* ------- GPIO Community 5 ------- */
 630
 631         /* ------- GPIO Group GPP_D ------- */
 632
 633         /* Let FSP enable the respective CLKREQ pins, see comment at the top of file */
 634         /* GPP_D0 - CLKREQ0# */
 635         // PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
 636         /* GPP_D1 - GPIO */
 637         PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI),
 638         /* GPP_D2 - GPIO */
 639         PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI),
 640         /* GPP_D3 - GPIO */
 641         PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI),
 642         /* GPP_D4 - SML1CLK */
 643         PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1),
 644         /* GPP_D5 - CNV_RF_RESET# */
 645         PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF2),
 646         /* GPP_D6 - MODEM_CLKREQ */
 647         PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF3),
 648         /* GPP_D7 - GPIO */
 649         PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, PLTRST, OFF, ACPI),
 650         /* GPP_D8 - GPIO */
 651         PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, PLTRST, OFF, ACPI),
 652         /* GPP_D9 - SML0CLK */
 653         PAD_CFG_NF(GPP_D9, NONE, PLTRST, NF1),
 654         /* GPP_D10 - SML0DATA */
 655         PAD_CFG_NF(GPP_D10, NONE, PLTRST, NF1),
 656         /* GPP_D11 - GPIO */
 657         PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, PLTRST, OFF, ACPI),
 658         /* GPP_D12 - GPIO */
 659         PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, PLTRST, OFF, ACPI),
 660         /* GPP_D13 - GPIO */
 661         PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI),
 662         /* GPP_D14 - GPIO */
 663         PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, OFF, ACPI),
 664         /* GPP_D15 - SML1DATA */
 665         PAD_CFG_NF(GPP_D15, NONE, PLTRST, NF1),
 666         /* GPP_D16 - GPIO */
 667         PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, PLTRST, OFF, ACPI),
 668         /* GPP_D17 - GPIO */
 669         PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, PLTRST, OFF, ACPI),
 670         /* GPP_D18 - GPIO */
 671         PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, PLTRST, OFF, ACPI),
 672         /* GPP_D19 - GPIO */
 673         PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, PLTRST, OFF, ACPI),
 674         /* GPP_D20 - GPIO */
 675         PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, PLTRST, OFF, ACPI),
 676         /* GPP_D21 - GPIO */
 677         PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, PLTRST, OFF, ACPI),
 678         /* GPP_D22 - GPIO */
 679         PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PLTRST, OFF, ACPI),
 680         /* GPP_D23 - GPIO */
 681         PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI),
 682 };