src/mainboard/system76/bonw14/devicetree.cb

   1 chip soc/intel/cannonlake
   2         register "common_soc_config" = "{
   3                 // Touchpad I2C bus
   4                 .i2c[0] = {
   5                         .speed = I2C_SPEED_FAST,
   6                         .rise_time_ns = 80,
   7                         .fall_time_ns = 110,
   8                 },
   9         }"
  10
  11 # CPU (soc/intel/cannonlake/cpu.c)
  12         # Power limit
  13         register "power_limits_config" = "{
  14                 .tdp_pl1_override = 125,
  15                 .tdp_pl2_override = 160,
  16         }"
  17
  18         # Enable Enhanced Intel SpeedStep
  19         register "eist_enable" = "1"
  20
  21 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
  22         register "enable_c6dram" = "1"
  23
  24 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
  25         # Serial I/O
  26         register "SerialIoDevMode" = "{
  27                 [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
  28                 [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console
  29         }"
  30
  31         # Misc
  32         register "AcousticNoiseMitigation" = "1"
  33
  34         # Power
  35         register "PchPmSlpS3MinAssert" = "3" # 50ms
  36         register "PchPmSlpS4MinAssert" = "1" # 1s
  37         register "PchPmSlpSusMinAssert" = "4" # 4s
  38         register "PchPmSlpAMinAssert" = "4" # 2s
  39
  40         # Thermal
  41         register "tcc_offset" = "13"
  42
  43 # PM Util (soc/intel/cannonlake/pmutil.c)
  44         # GPE configuration
  45         # Note that GPE events called out in ASL code rely on this
  46         # route. i.e. If this route changes then the affected GPE
  47         # offset bits also need to be changed.
  48         register "gpe0_dw0" = "PMC_GPP_K"
  49         register "gpe0_dw1" = "PMC_GPP_G"
  50         register "gpe0_dw2" = "PMC_GPP_E"
  51
  52 # Actual device tree
  53         device cpu_cluster 0 on
  54                 device lapic 0 on end
  55         end
  56
  57         device domain 0 on
  58                 subsystemid 0x1558 0x7714 inherit
  59                 device pci 00.0 on  end # Host Bridge
  60                 device pci 01.0 on      # GPU Port
  61                         # PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU)
  62                         register "PcieClkSrcUsage[7]" = "0x40"
  63                         register "PcieClkSrcClkReq[7]" = "7"
  64
  65                         device pci 00.0 on end # VGA controller
  66                         device pci 00.1 on end # Audio device
  67                         device pci 00.2 on end # USB xHCI Host controller
  68                         device pci 00.3 on end # USB Type-C UCSI controller
  69                 end
  70                 # TODO: is this enough to disable iGPU?
  71                 device pci 02.0 off end # Integrated Graphics Device
  72                 device pci 04.0 on  end # SA Thermal device
  73                 device pci 12.0 on  end # Thermal Subsystem
  74                 device pci 12.5 off end # UFS SCS
  75                 device pci 12.6 off end # GSPI #2
  76                 device pci 13.0 off end # Integrated Sensor Hub
  77                 device pci 14.0 on      # USB xHCI
  78                         # USB2
  79                         register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_2
  80                         register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_1
  81                         register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_4
  82                         register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_3
  83                         register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB
  84                         register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C
  85                         register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # XFI
  86                         register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
  87                         register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Light guide
  88                         register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
  89                         register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
  90                         # USB3
  91                         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_2
  92                         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # ANX7440
  93                         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_4
  94                         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_3
  95                 end
  96                 device pci 14.2 on  end # Shared SRAM
  97                 device pci 14.3 on      # CNVi wifi
  98                         chip drivers/wifi/generic
  99                                 register "wake" = "PME_B0_EN_BIT"
 100                                 device generic 0 on end
 101                         end
 102                 end
 103                 device pci 14.5 off end # SDCard
 104                 device pci 15.0 on      # I2C #0
 105                         chip drivers/i2c/hid
 106                                 register "generic.hid" = ""SYNA1202""
 107                                 register "generic.desc" = ""Synaptics Touchpad""
 108                                 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
 109                                 register "generic.detect" = "1"
 110                                 register "hid_desc_reg_offset" = "0x20"
 111                                 device i2c 2c on end
 112                         end
 113                 end
 114                 device pci 15.1 off end # I2C #1
 115                 device pci 15.2 off end # I2C #2
 116                 device pci 15.3 off end # I2C #3
 117                 device pci 16.0 on  end # Management Engine Interface 1
 118                 device pci 16.1 off end # Management Engine Interface 2
 119                 device pci 16.2 off end # Management Engine IDE-R
 120                 device pci 16.3 off end # Management Engine KT Redirection
 121                 device pci 16.4 off end # Management Engine Interface 3
 122                 device pci 16.5 off end # Management Engine Interface 4
 123                 device pci 17.0 on      # SATA
 124                         register "SataPortsEnable[1]" = "1" # SATA1A (SSD)
 125                         register "SataPortsEnable[3]" = "1" # SATA3 (M.2_SATA3)
 126                         register "SataPortsEnable[4]" = "1" # SATA4 (SSD2)
 127                 end
 128                 device pci 19.2 off end # UART #2
 129                 device pci 1a.0 off end # eMMC
 130                 device pci 1b.0 on      # PCI Express Port 17
 131                         # PCI Express root port #17 x4, Clock 14 (SSD2)
 132                         register "PcieRpEnable[16]" = "1"
 133                         register "PcieRpLtrEnable[16]" = "1"
 134                         register "PcieClkSrcUsage[14]" = "16"
 135                         register "PcieClkSrcClkReq[14]" = "14"
 136                 end
 137                 device pci 1b.1 off end # PCI Express Port 18
 138                 device pci 1b.2 off end # PCI Express Port 19
 139                 device pci 1b.3 off end # PCI Express Port 20
 140                 device pci 1b.4 on      # PCI Express Port 21
 141                         # PCI Express root port #21 x4, Clock 15 (SSD3)
 142                         register "PcieRpEnable[20]" = "1"
 143                         register "PcieRpLtrEnable[20]" = "1"
 144                         register "PcieClkSrcUsage[15]" = "20"
 145                         register "PcieClkSrcClkReq[15]" = "15"
 146                 end
 147                 device pci 1b.5 off end # PCI Express Port 22
 148                 device pci 1b.6 off end # PCI Express Port 23
 149                 device pci 1b.7 off end # PCI Express Port 24
 150                 device pci 1c.0 on      # PCI Express Port 1
 151                         # PCI Express root port #1 x4, Clock 6 (Thunderbolt)
 152                         register "PcieRpEnable[0]" = "1"
 153                         register "PcieRpLtrEnable[0]" = "1"
 154                         register "PcieRpHotPlug[0]" = "1"
 155                         register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED
 156                         register "PcieClkSrcClkReq[6]" = "6"
 157                 end
 158                 device pci 1c.1 off end # PCI Express Port 2
 159                 device pci 1c.2 off end # PCI Express Port 3
 160                 device pci 1c.3 off end # PCI Express Port 4
 161                 device pci 1c.4 on      # PCI Express Port 5
 162                         # PCI Express root port #5 x4, Clock 10 (USB 3.2)
 163                         register "PcieRpEnable[4]" = "1"
 164                         register "PcieRpLtrEnable[4]" = "1"
 165                         register "PcieClkSrcUsage[10]" = "4"
 166                         register "PcieClkSrcClkReq[10]" = "10"
 167                 end
 168                 device pci 1c.5 off end # PCI Express Port 6
 169                 device pci 1c.6 off end # PCI Express Port 7
 170                 device pci 1c.7 off end # PCI Express Port 8
 171                 device pci 1d.0 on      # PCI Express Port 9
 172                         # PCI Express root port #9 x4, Clock 8 (SSD)
 173                         register "PcieRpEnable[8]" = "1"
 174                         register "PcieRpLtrEnable[8]" = "1"
 175                         register "PcieClkSrcUsage[8]" = "8"
 176                         register "PcieClkSrcClkReq[8]" = "8"
 177                 end
 178                 device pci 1d.1 off end # PCI Express Port 10
 179                 device pci 1d.2 off end # PCI Express Port 11
 180                 device pci 1d.3 off end # PCI Express Port 12
 181                 device pci 1d.4 on      # PCI Express Port 13
 182                         # PCI Express root port #13 x1, Clock 0 (WLAN)
 183                         register "PcieRpEnable[12]" = "1"
 184                         register "PcieRpLtrEnable[12]" = "1"
 185                         register "PcieClkSrcUsage[0]" = "12"
 186                         register "PcieClkSrcClkReq[0]" = "0"
 187                 end
 188                 device pci 1d.5 on      # PCI Express Port 14
 189                         # PCI Express root port #14 x1, Clock 1 (GLAN)
 190                         register "PcieRpEnable[13]" = "1"
 191                         register "PcieRpLtrEnable[13]" = "1"
 192                         register "PcieClkSrcUsage[1]" = "13"
 193                         register "PcieClkSrcClkReq[1]" = "1"
 194                 end
 195                 device pci 1d.6 on      # PCI Express Port 15
 196                         # PCI Express root port #15 x1, Clock 4 (Card Reader)
 197                         register "PcieRpEnable[14]" = "1"
 198                         register "PcieRpLtrEnable[14]" = "1"
 199                         register "PcieClkSrcUsage[4]" = "14"
 200                         register "PcieClkSrcClkReq[4]" = "4"
 201                 end
 202                 device pci 1d.7 off end # PCI Express Port 16
 203                 device pci 1e.0 off end # UART #0
 204                 device pci 1e.1 off end # UART #1
 205                 device pci 1e.2 off end # GSPI #0
 206                 device pci 1e.3 off end # GSPI #1
 207                 device pci 1f.0 on      # LPC Interface
 208                         register "gen1_dec" = "0x00040069"
 209                         register "gen2_dec" = "0x00fc0e01"
 210                         register "gen3_dec" = "0x00fc0f01"
 211                         chip drivers/pc80/tpm
 212                                 device pnp 0c31.0 on end
 213                         end
 214                 end
 215                 device pci 1f.1 off end # P2SB
 216                 device pci 1f.2 hidden end # Power Management Controller
 217                 device pci 1f.3 on      # Intel HDA
 218                         register "PchHdaAudioLinkHda" = "1"
 219                 end
 220                 device pci 1f.4 on  end # SMBus
 221                 device pci 1f.5 on  end # PCH SPI
 222                 device pci 1f.6 off end # GbE
 223         end
 224 end