src/mainboard/system76/oryp8/devicetree.cb

   1 chip soc/intel/tigerlake
   2         register "common_soc_config" = "{
   3                 // Touchpad I2C bus
   4                 .i2c[0] = {
   5                         .speed = I2C_SPEED_FAST,
   6                         .rise_time_ns = 80,
   7                         .fall_time_ns = 110,
   8                 },
   9         }"
  10
  11 # ACPI (soc/intel/tigerlake/acpi.c)
  12         # Enable Enhanced Intel SpeedStep
  13         register "eist_enable" = "1"
  14
  15 # CPU (soc/intel/tigerlake/cpu.c)
  16         # Power limits
  17         register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{
  18                 .tdp_pl1_override = 45,
  19                 .tdp_pl2_override = 90,
  20         }"
  21         register "power_limits_config[POWER_LIMITS_H_6_CORE]" = "{
  22                 .tdp_pl1_override = 45,
  23                 .tdp_pl2_override = 90,
  24         }"
  25
  26 # FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
  27         # Enable C6 DRAM
  28         register "enable_c6dram" = "1"
  29
  30 # FSP Silicon (soc/intel/tigerlake/fsp_params.c)
  31         # Acoustic settings
  32         register "AcousticNoiseMitigation" = "1"
  33         register "SlowSlewRate" = "SLEW_FAST_8"
  34         register "FastPkgCRampDisable" = "1"
  35
  36         # FIVR configuration
  37         #   Read EXT_RAIL_CONFIG to determine bitmaps
  38         #     sudo devmem2 0xfe0011b8
  39         #     0x0
  40         #   Read EXT_V1P05_VR_CONFIG
  41         #     sudo devmem2 0xfe0011c0
  42         #     0x1a42000
  43         #   Read EXT_VNN_VR_CONFIG0
  44         #     sudo devmem2 0xfe0011c4
  45         #     0x1a42000
  46         # TODO: v1p05 voltage and vnn icc max?
  47         register "ext_fivr_settings" = "{
  48                 .configure_ext_fivr = 1,
  49                 .v1p05_enable_bitmap = 0,
  50                 .vnn_enable_bitmap = 0,
  51                 .v1p05_supported_voltage_bitmap = 0,
  52                 .vnn_supported_voltage_bitmap = 0,
  53                 .v1p05_icc_max_ma = 500,
  54                 .vnn_sx_voltage_mv = 1050,
  55         }"
  56
  57         # Read LPM_EN, make sure to invert the bits
  58         # sudo devmem2 0xfe001c78
  59         # 0x9
  60         register "LpmStateDisableMask" = "
  61                 LPM_S0i2_1 |
  62                 LPM_S0i2_2 |
  63                 LPM_S0i3_1 |
  64                 LPM_S0i3_2 |
  65                 LPM_S0i3_3 |
  66                 LPM_S0i3_4
  67         "
  68
  69         # Thermal
  70         register "tcc_offset" = "10"
  71
  72         # Enable CNVi BT
  73         register "CnviBtCore" = "true"
  74
  75 # PM Util (soc/intel/tigerlake/pmutil.c)
  76         # GPE configuration
  77         register "pmc_gpe0_dw0" = "PMC_GPP_R"
  78         register "pmc_gpe0_dw1" = "PMC_GPP_B"
  79         register "pmc_gpe0_dw2" = "PMC_GPP_D"
  80
  81 # Actual device tree
  82         device cpu_cluster 0 on
  83                 device lapic 0 on end
  84         end
  85
  86         device domain 0 on
  87                 subsystemid 0x1558 0x65f1 inherit
  88
  89                 #From CPU EDS(575683)
  90                 device ref system_agent on end
  91                 device ref peg1 on
  92                         # PCIe PEG1 x16, Clock 9 (DGPU)
  93                         register "PcieClkSrcUsage[9]" = "0x41"
  94                         register "PcieClkSrcClkReq[9]" = "9"
  95                         chip soc/intel/common/block/pcie/rtd3
  96                                 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
  97                                 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
  98                                 register "enable_delay_ms" = "16"
  99                                 register "enable_off_delay_ms" = "4"
 100                                 register "reset_delay_ms" = "10"
 101                                 register "reset_off_delay_ms" = "4"
 102                                 register "srcclk_pin" = "9" # PEG_CLKREQ#
 103                                 device generic 0 on end
 104                         end
 105                 end
 106                 device ref igpu on
 107                         # DDIA is eDP
 108                         register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
 109                         register "DdiPortAHpd" = "1"
 110                         register "DdiPortADdc" = "0"
 111
 112                         register "gfx" = "GMA_DEFAULT_PANEL(0)"
 113                 end
 114                 device ref dptf on end
 115                 device ref peg0 on
 116                         # PCIe PEG0 x4, Clock 7 (SSD1)
 117                         register "PcieClkSrcUsage[7]" = "0x40"
 118                         register "PcieClkSrcClkReq[7]" = "7"
 119                 end
 120                 device ref tbt_pcie_rp0 on end # TYPEC1
 121                 device ref gna on end
 122                 device ref north_xhci on # TYPEC1
 123                         register "TcssXhciEn" = "1"
 124                 end
 125                 device ref tbt_dma0 on end # TYPEC1
 126
 127                 # From PCH EDS(615985)
 128                 device ref south_xhci on
 129                         # USB2
 130                         register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left)
 131                         register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 1)
 132                         register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 2)
 133                         register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key
 134                         register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
 135                         register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1
 136                         register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
 137                         register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
 138                         # USB3
 139                         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left)
 140                         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 1)
 141                         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 2)
 142                 end
 143                 device ref shared_ram on end
 144                 device ref cnvi_wifi on
 145                         chip drivers/wifi/generic
 146                                 register "wake" = "GPE0_PME_B0"
 147                                 device generic 0 on end
 148                         end
 149                 end
 150                 device ref i2c0 on
 151                         # Touchpad I2C bus
 152                         register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
 153                         chip drivers/i2c/hid
 154                                 register "generic.hid" = ""SYNA1202""
 155                                 register "generic.desc" = ""Synaptics Touchpad""
 156                                 register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_R12)"
 157                                 register "generic.detect" = "1"
 158                                 register "hid_desc_reg_offset" = "0x20"
 159                                 device i2c 2c on end
 160                         end
 161                 end
 162                 device ref heci1 on end
 163                 device ref uart2 on
 164                         # Debug console
 165                         register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
 166                 end
 167                 device ref sata on
 168                         register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A)
 169                 end
 170                 device ref pcie_rp5 on
 171                         # PCIe root port #5 x1, Clock 8 (GLAN)
 172                         register "PcieRpEnable[4]" = "1"
 173                         register "PcieRpLtrEnable[4]" = "1"
 174                         register "PcieClkSrcUsage[8]" = "4"
 175                         register "PcieClkSrcClkReq[8]" = "8"
 176                 end
 177                 device ref pcie_rp6 on
 178                         # PCIe root port #6 x1, Clock 10 (CARD)
 179                         register "PcieRpEnable[5]" = "1"
 180                         register "PcieRpLtrEnable[5]" = "1"
 181                         register "PcieClkSrcUsage[10]" = "5"
 182                         register "PcieClkSrcClkReq[10]" = "10"
 183                 end
 184                 device ref pcie_rp8 on
 185                         # PCIe root port #8 x1, Clock 2 (WLAN)
 186                         register "PcieRpEnable[7]" = "1"
 187                         register "PcieRpLtrEnable[7]" = "1"
 188                         register "PcieClkSrcUsage[2]" = "7"
 189                         register "PcieClkSrcClkReq[2]" = "2"
 190                         register "PcieRpSlotImplemented[7]" = "1"
 191                 end
 192                 device ref pcie_rp9 on
 193                         # PCIe root port #9 x4, Clock 6 (SSD2)
 194                         register "PcieRpEnable[8]" = "1"
 195                         register "PcieRpLtrEnable[8]" = "1"
 196                         register "PcieClkSrcUsage[6]" = "8"
 197                         register "PcieClkSrcClkReq[6]" = "6"
 198                         register "PcieRpSlotImplemented[8]" = "1"
 199                 end
 200                 device ref pch_espi on
 201                         register "gen1_dec" = "0x00040069" # EC PM channel
 202                         register "gen2_dec" = "0x00fc0E01" # AP/EC command
 203                         register "gen3_dec" = "0x00fc0F01" # AP/EC debug
 204                         chip drivers/pc80/tpm
 205                                 device pnp 0c31.0 on end
 206                         end
 207                 end
 208                 device ref p2sb on end
 209                 device ref pmc hidden end
 210                 device ref hda on
 211                         register "PchHdaAudioLinkHdaEnable" = "1"
 212                 end
 213                 device ref smbus on
 214                         chip drivers/i2c/tas5825m
 215                                 register "id" = "0"
 216                                 device i2c 4e on end # (8bit address: 0x9c)
 217                         end
 218                 end
 219                 device ref fast_spi on end
 220         end
 221 end