src/mainboard/system76/whl-u/devicetree.cb

   1 chip soc/intel/cannonlake
   2         # Lock Down
   3         register "common_soc_config" = "{
   4                 .i2c[0] = {
   5                         .speed = I2C_SPEED_FAST,
   6                         .rise_time_ns = 80,
   7                         .fall_time_ns = 110,
   8                 },
   9         }"
  10
  11 # CPU (soc/intel/cannonlake/cpu.c)
  12         # Power limit
  13         register "power_limits_config" = "{
  14                 .tdp_pl1_override = 20,
  15                 .tdp_pl2_override = 30,
  16         }"
  17
  18         # Enable Enhanced Intel SpeedStep
  19         register "eist_enable" = "1"
  20
  21 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
  22         register "SaGv" = "SaGv_Enabled"
  23         register "enable_c6dram" = "1"
  24
  25 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
  26         # Serial I/O
  27         register "SerialIoDevMode" = "{
  28                 [PchSerialIoIndexI2C0] = PchSerialIoPci,
  29                 [PchSerialIoIndexUART2] = PchSerialIoPci,
  30         }"
  31
  32         # Misc
  33         register "AcousticNoiseMitigation" = "1"
  34
  35         # Power
  36         register "PchPmSlpS3MinAssert" = "3"    # 50ms
  37         register "PchPmSlpS4MinAssert" = "1"    # 1s
  38         register "PchPmSlpSusMinAssert" = "2"   # 500ms
  39         register "PchPmSlpAMinAssert" = "4"     # 2s
  40
  41         # Thermal
  42         register "tcc_offset" = "12"
  43
  44         # Serial IRQ Continuous
  45         register "serirq_mode" = "SERIRQ_CONTINUOUS"
  46
  47 # PM Util (soc/intel/cannonlake/pmutil.c)
  48         # GPE configuration
  49         # Note that GPE events called out in ASL code rely on this
  50         # route. i.e. If this route changes then the affected GPE
  51         # offset bits also need to be changed.
  52         register "gpe0_dw0" = "PMC_GPP_C"
  53         register "gpe0_dw1" = "PMC_GPP_D"
  54         register "gpe0_dw2" = "PMC_GPP_E"
  55
  56 # Actual device tree
  57         device cpu_cluster 0 on
  58                 device lapic 0 on end
  59         end
  60
  61         device domain 0 on
  62                 device pci 00.0 on  end # Host Bridge
  63                 device pci 02.0 on      # Integrated Graphics Device
  64                         register "gfx" = "GMA_STATIC_DISPLAYS(0)"
  65                 end
  66                 device pci 04.0 on      # SA Thermal device
  67                         register "Device4Enable" = "1"
  68                 end
  69                 device pci 12.0 on  end # Thermal Subsystem
  70                 device pci 12.5 off end # UFS SCS
  71                 device pci 12.6 off end # GSPI #2
  72                 device pci 13.0 off end # Integrated Sensor Hub
  73                 device pci 14.0 on      # USB xHCI
  74                         # USB2
  75                         register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"             # USB-A
  76                         register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"             # 3G / LTE
  77                         register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"          # USB-C
  78                         register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"             # USB-A
  79                         register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)"             # Camera
  80                         register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"             # Bluetooth
  81                         # USB3
  82                         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"         # USB-A
  83                         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"         # 4G on galp3-c, NC on darp5
  84                         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"         # USB-C
  85                         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"         # USB-A
  86                         register "usb3_ports[4]" = "USB3_PORT_EMPTY"                    # Used by TBT
  87                         register "usb3_ports[5]" = "USB3_PORT_EMPTY"                    # Used by TBT
  88                 end
  89                 device pci 14.1 off end # USB xDCI (OTG)
  90                 device pci 14.3 on      # CNVi wifi
  91                         chip drivers/wifi/generic
  92                                 register "wake" = "PME_B0_EN_BIT"
  93                                 device generic 0 on end
  94                         end
  95                 end
  96                 device pci 14.5 off end # SDCard
  97                 device pci 15.0 on  end # I2C #0
  98                 device pci 15.1 off end # I2C #1
  99                 device pci 15.2 off end # I2C #2
 100                 device pci 15.3 off end # I2C #3
 101                 device pci 16.0 on  end # Management Engine Interface 1
 102                 device pci 16.1 off end # Management Engine Interface 2
 103                 device pci 16.2 off end # Management Engine IDE-R
 104                 device pci 16.3 off end # Management Engine KT Redirection
 105                 device pci 16.4 off end # Management Engine Interface 3
 106                 device pci 16.5 off end # Management Engine Interface 4
 107                 device pci 17.0 on      # SATA
 108                         register "SataPortsEnable[0]" = "1"
 109                         register "SataPortsEnable[2]" = "1"
 110                 end
 111                 device pci 19.0 off end # I2C #4
 112                 device pci 19.1 off end # I2C #5
 113                 device pci 19.2 on  end # UART #2
 114                 device pci 1a.0 off end # eMMC
 115                 device pci 1c.0 on  end # PCI Express Port 1
 116                 device pci 1c.1 off end # PCI Express Port 2
 117                 device pci 1c.2 off end # PCI Express Port 3
 118                 device pci 1c.3 off end # PCI Express Port 4
 119                 device pci 1c.4 on      # PCI Express Port 5
 120                         # PCI Express Root port #5 x4, Clock 4 (TBT)
 121                         register "PcieRpEnable[4]" = "1"
 122                         register "PcieRpLtrEnable[4]" = "1"
 123                         register "PcieRpHotPlug[4]" = "1"
 124                         register "PcieClkSrcUsage[4]" = "4"
 125                         register "PcieClkSrcClkReq[4]" = "4"
 126                 end
 127                 device pci 1c.5 off end # PCI Express Port 6
 128                 device pci 1c.6 off end # PCI Express Port 7
 129                 device pci 1c.7 off end # PCI Express Port 8
 130                 device pci 1d.0 on      # PCI Express Port 9
 131                         # PCI Express Root port #9 x1, Clock 3 (LAN)
 132                         register "PcieRpEnable[8]" = "1"
 133                         register "PcieRpLtrEnable[8]" = "1"
 134                         register "PcieClkSrcUsage[3]" = "8"
 135                         register "PcieClkSrcClkReq[3]" = "3"
 136                 end
 137                 device pci 1d.1 on      # PCI Express Port 10
 138                         # PCI Express Root port #10 x1, Clock 2 (WLAN)
 139                         register "PcieRpEnable[9]" = "1"
 140                         register "PcieRpLtrEnable[9]" = "0"
 141                         register "PcieClkSrcUsage[2]" = "9"
 142                         register "PcieClkSrcClkReq[2]" = "2"
 143                 end
 144                 device pci 1d.2 off end # PCI Express Port 11
 145                 device pci 1d.3 off end # PCI Express Port 12
 146                 device pci 1d.4 on      # PCI Express Port 13
 147                         # PCI Express Root port #13 x4, Clock 5 (NVMe)
 148                         register "PcieRpEnable[12]" = "1"
 149                         register "PcieRpLtrEnable[12]" = "1"
 150                         register "PcieClkSrcUsage[5]" = "12"
 151                         register "PcieClkSrcClkReq[5]" = "5"
 152                 end
 153                 device pci 1d.5 off end # PCI Express Port 14
 154                 device pci 1d.6 off end # PCI Express Port 15
 155                 device pci 1d.7 off end # PCI Express Port 16
 156                 device pci 1e.0 off end # UART #0
 157                 device pci 1e.1 off end # UART #1
 158                 device pci 1e.2 off end # GSPI #0
 159                 device pci 1e.3 off end # GSPI #1
 160                 device pci 1f.0 on      # LPC Interface
 161                         register "gen1_dec" = "0x000c0081"
 162                         register "gen2_dec" = "0x00040069"
 163                         register "gen3_dec" = "0x00fc0e01"
 164                         register "gen4_dec" = "0x00fc0f01"
 165                         chip drivers/pc80/tpm
 166                                 device pnp 0c31.0 on end
 167                         end
 168                 end
 169                 device pci 1f.1 off end # P2SB
 170                 device pci 1f.2 hidden end # Power Management Controller
 171                 device pci 1f.3 on      # Intel HDA
 172                         register "PchHdaAudioLinkHda" = "1"
 173                         register "PchHdaAudioLinkDmic0" = "1"
 174                         register "PchHdaAudioLinkDmic1" = "1"
 175                 end
 176                 device pci 1f.4 on  end # SMBus
 177                 device pci 1f.5 on  end # PCH SPI
 178                 device pci 1f.6 off end # GbE
 179         end
 180 end