payloads/edk2: Disable the CPU Timer Lib unless supported
[coreboot.git] / src / superio / fintek / f71869ad / f71869ad_multifunc.c
blob29e609094d8686c9cd51ba3228911f49493fd83f
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <device/device.h>
4 #include <device/pnp.h>
5 #include "chip.h"
6 #include "fintek_internal.h"
8 #define MULTI_FUNC_SEL_REG1 0x28
9 #define MULTI_FUNC_SEL_REG2 0x29
10 #define MULTI_FUNC_SEL_REG3 0x2A
11 #define MULTI_FUNC_SEL_REG4 0x2B
12 #define MULTI_FUNC_SEL_REG5 0x2C
14 void f71869ad_multifunc_init(struct device *dev)
16 const struct superio_fintek_f71869ad_config *conf = dev->chip_info;
18 pnp_enter_conf_mode(dev);
20 /* multi-func select reg1 */
21 pnp_write_config(dev, MULTI_FUNC_SEL_REG1,
22 conf->multi_function_register_1);
24 /* multi-func select reg2 (CLK_TUNE_EN = 0) */
25 pnp_write_config(dev, MULTI_FUNC_SEL_REG2,
26 conf->multi_function_register_2);
28 /* multi-func select reg3 (CLK_TUNE_EN = 0) */
29 pnp_write_config(dev, MULTI_FUNC_SEL_REG3,
30 conf->multi_function_register_3);
32 /* multi-func select reg4 (CLK_TUNE_EN = 0) */
33 pnp_write_config(dev, MULTI_FUNC_SEL_REG4,
34 conf->multi_function_register_4);
36 /* multi-func select reg5 (CLK_TUNE_EN = 0) */
37 pnp_write_config(dev, MULTI_FUNC_SEL_REG5,
38 conf->multi_function_register_5);
40 pnp_exit_conf_mode(dev);