src/soc/intel/common/block/include/intelblocks/cpulib.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef SOC_INTEL_COMMON_BLOCK_CPULIB_H
   4 #define SOC_INTEL_COMMON_BLOCK_CPULIB_H
   5
   6 #include <types.h>
   7
   8 /*
   9  * Set PERF_CTL MSR (0x199) P_Req with
  10  * Turbo Ratio which is the Maximum Ratio.
  11  */
  12 void cpu_set_max_ratio(void);
  13
  14 /* Get CPU bus frequency in MHz */
  15 u32 cpu_get_bus_frequency(void);
  16
  17 /* Get CPU's max non-turbo ratio */
  18 u8 cpu_get_max_non_turbo_ratio(void);
  19
  20 /* Check if CPU is hybrid CPU or not */
  21 bool cpu_is_hybrid_supported(void);
  22
  23 /*
  24  * Returns type of CPU that executing the function. It returns 0x20
  25  * if CPU is atom, otherwise 0x40 if CPU is CORE. The API must be called
  26  * if CPU is hybrid.
  27  */
  28 uint8_t cpu_get_cpu_type(void);
  29 /*
  30  * Get the TDP Nominal Ratio from MSR 0x648 Bits 7:0.
  31  */
  32 u8 cpu_get_tdp_nominal_ratio(void);
  33
  34 /*
  35  * Read PLATFORM_INFO MSR (0xCE).
  36  * Return Value of Bit 34:33 (CONFIG_TDP_LEVELS).
  37  *
  38  * Possible values of Bit 34:33 are -
  39  * 00 : Config TDP not supported
  40  * 01 : One Additional TDP level supported
  41  * 10 : Two Additional TDP level supported
  42  * 11 : Reserved
  43  */
  44 int cpu_config_tdp_levels(void);
  45
  46 /*
  47  * TURBO_RATIO_LIMIT MSR (0x1AD) Bits 31:0 indicates the
  48  * factory configured values for of 1-core, 2-core, 3-core
  49  * and 4-core turbo ratio limits for all processors.
  50  *
  51  * 7:0 -        MAX_TURBO_1_CORE
  52  * 15:8 -       MAX_TURBO_2_CORES
  53  * 23:16 -      MAX_TURBO_3_CORES
  54  * 31:24 -      MAX_TURBO_4_CORES
  55  *
  56  * Set PERF_CTL MSR (0x199) P_Req with that value.
  57  */
  58 void cpu_set_p_state_to_turbo_ratio(void);
  59
  60 /*
  61  * CONFIG_TDP_NOMINAL MSR (0x648) Bits 7:0 tells Nominal
  62  * TDP level ratio to be used for specific processor (in units
  63  * of 100MHz).
  64  *
  65  * Set PERF_CTL MSR (0x199) P_Req with that value.
  66  */
  67 void cpu_set_p_state_to_nominal_tdp_ratio(void);
  68
  69 /*
  70  * PLATFORM_INFO MSR (0xCE) Bits 15:8 tells
  71  * MAX_NON_TURBO_LIM_RATIO.
  72  *
  73  * Set PERF_CTL MSR (0x199) P_Req with that value.
  74  */
  75 void cpu_set_p_state_to_max_non_turbo_ratio(void);
  76
  77 /*
  78  * Set PERF_CTL MSR (0x199) P_Req with the value
  79  * for maximum efficiency. This value is reported in PLATFORM_INFO MSR (0xCE)
  80  * in Bits 47:40 and is extracted with cpu_get_min_ratio().
  81  */
  82 void cpu_set_p_state_to_min_clock_ratio(void);
  83
  84 /*
  85  * Get the Burst/Turbo Mode State from MSR IA32_MISC_ENABLE 0x1A0
  86  * Bit 38 - TURBO_MODE_DISABLE Bit to get state ENABLED / DISABLED.
  87  * Also check for the cpuid 0x6 to check whether Burst mode unsupported.
  88  * Below are the possible cpu_get_burst_mode_state() return values-
  89  * These states are exposed to the User since user
  90  * need to know which is the current Burst Mode State.
  91  */
  92 enum {
  93         BURST_MODE_UNKNOWN,
  94         BURST_MODE_UNAVAILABLE,
  95         BURST_MODE_DISABLED,
  96         BURST_MODE_ENABLED
  97 };
  98 int cpu_get_burst_mode_state(void);
  99
 100 /*
 101  * Program CPU Burst mode
 102  * true = Enable Burst mode.
 103  * false = Disable Burst mode.
 104  */
 105 void cpu_burst_mode(bool burst_mode_status);
 106
 107 /*
 108  * Program Enhanced Intel Speed Step Technology
 109  * true = Enable EIST.
 110  * false = Disable EIST.
 111  */
 112 void cpu_set_eist(bool eist_status);
 113
 114 /*
 115  * SoC specific implementation:
 116  *
 117  * Check CPU security level using ENABLE_IA_UNTRUSTED_MODE of CPU MSR.
 118  * If bit is set, meaning CPU has dropped its security level by entering
 119  * into `untrusted mode`. Otherwise, it's in `trusted mode`.
 120  */
 121 bool cpu_soc_is_in_untrusted_mode(void);
 122
 123 /* SoC function to set the BIOS DONE MSR. */
 124 void cpu_soc_bios_done(void);
 125
 126 /*
 127  * This function fills in the number of Cores(physical) and Threads(virtual)
 128  * of the CPU in the function arguments. It also returns if the number of cores
 129  * and number of threads are equal.
 130  */
 131 int cpu_read_topology(unsigned int *num_phys, unsigned int *num_virt);
 132
 133 /*
 134  * cpu_get_bus_clock returns the bus clock frequency in KHz.
 135  * This is the value the clock ratio is multiplied with.
 136  */
 137 uint32_t cpu_get_bus_clock(void);
 138
 139 /*
 140  * cpu_get_coord_type returns coordination type (SW_ANY or SW_ALL or HW_ALL)
 141  * which is used to populate _PSD object.
 142  */
 143 int cpu_get_coord_type(void);
 144
 145 /*
 146  * cpu_get_min_ratio returns the minimum frequency ratio that is supported
 147  * by this processor
 148  */
 149 uint32_t cpu_get_min_ratio(void);
 150
 151 /*
 152  * cpu_get_max_ratio returns the nominal TDP ratio if available or the
 153  * maximum non turbo frequency ratio for this processor
 154  */
 155 uint32_t cpu_get_max_ratio(void);
 156
 157 /* Thermal throttle activation offset */
 158 void configure_tcc_thermal_target(void);
 159
 160 /*
 161  * cpu_get_power_max calculates CPU TDP in mW
 162  */
 163 uint32_t cpu_get_power_max(void);
 164
 165 /*
 166  * cpu_get_max_turbo_ratio returns the maximum turbo ratio limit for the
 167  * processor
 168  */
 169 uint32_t cpu_get_max_turbo_ratio(void);
 170
 171 /* Configure Machine Check Architecture support */
 172 void mca_configure(void);
 173
 174 /* Lock chipset memory registers to protect SMM */
 175 void cpu_lt_lock_memory(void);
 176
 177 /* Get a supported PRMRR size in bytes with respect to users choice */
 178 int get_valid_prmrr_size(void);
 179
 180 /*
 181  * Enable the emulated ACPI timer in case it's not available or to allow
 182  * disabling the PM ACPI timer (PM1_TMR) for power saving.
 183  */
 184 void enable_pm_timer_emulation(void);
 185
 186 /*
 187  * Initialize core PRMRR
 188  *
 189  * Read the BSP PRMRR snapshot and apply on the rest of the core threads
 190  */
 191 void init_core_prmrr(void);
 192
 193 /*
 194  * Check if TME is supported by the CPU
 195  *
 196  * coreboot shall detect the existence of TME feature by running CPUID instruction:
 197  * CPUID leaf 7/sub-leaf 0: Return Value in ECX [bit 13] = 1
 198  */
 199 bool is_tme_supported(void);
 200
 201 /*
 202  * Set TME core activate MSR
 203  *
 204  * Write zero to TME core activate MSR will translate the TME_ACTIVATE[MK_TME_KEYID_BITS]
 205  * value into PMH mask register.
 206  * TME_ACTIVATE[MK_TME_KEYID_BITS] = MSR 0x982 Bits[32-35]
 207  */
 208 void set_tme_core_activate(void);
 209
 210 /*
 211  * This function checks if the CPU supports SGX feature.
 212  * Returns true if SGX feature is supported otherwise false.
 213  */
 214 bool is_sgx_supported(void);
 215
 216 /*
 217  * This function checks if the CPU supports Key Locker feature.
 218  * Returns true if Key Locker feature is supported otherwise false.
 219  */
 220 bool is_keylocker_supported(void);
 221
 222 /*
 223  * This function prevents the Three Strike Counter from incrementing.
 224  * It helps to collect more useful CPU traces for debugging.
 225  */
 226 void disable_three_strike_error(void);
 227
 228 #endif  /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */