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cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
[coreboot.git]
/
.gitignore
blob
126cae665d8d0089d43876b3807dd98cea0e7531
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junit.xml
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abuild*.xml
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.config
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.config.old
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defconfig
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.coreboot-version
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.xcompile
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.ccwrap
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build/
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coreboot-builds/
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coreboot-builds*/
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site-local
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*.\#
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*.a
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*.bin
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*.debug
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!Kconfig.debug
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*.elf
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*.fd
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*.o
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*.o.d
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*.out
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*.pyc
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*.sw[po]
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/*.rom
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.test
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.dependencies
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# Development friendly files
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tags
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.clang_complete
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.cache
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compile_commands.json
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.vscode/
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# Cross-compile toolkits
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xgcc/
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tarballs/
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# editor backup files, temporary files, IDE project files
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*~
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*.kate-swp
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*.kdev4