src/soc/intel/alderlake/pcie_rp.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <intelblocks/pcie_rp.h>
   5 #include <soc/cpu.h>
   6 #include <soc/pci_devs.h>
   7 #include <soc/pcie.h>
   8
   9 #define CPU_CPIE_VW_IDX_BASE    24
  10
  11 static const struct pcie_rp_group pch_lp_rp_groups[] = {
  12         { .slot = PCH_DEV_SLOT_PCIE,    .count = 8, .lcap_port_base = 1 },
  13         { .slot = PCH_DEV_SLOT_PCIE_1,  .count = 4, .lcap_port_base = 1 },
  14         { 0 }
  15 };
  16
  17 static const struct pcie_rp_group pch_s_rp_groups[] = {
  18         { .slot = PCH_DEV_SLOT_PCIE,    .count = 8, .lcap_port_base = 1 },
  19         { .slot = PCH_DEV_SLOT_PCIE_1,  .count = 8, .lcap_port_base = 1 },
  20         { .slot = PCH_DEV_SLOT_PCIE_2,  .count = 8, .lcap_port_base = 1 },
  21         { .slot = PCH_DEV_SLOT_PCIE_3,  .count = 4, .lcap_port_base = 1 },
  22         { 0 }
  23 };
  24
  25 const struct pcie_rp_group *get_pch_pcie_rp_table(void)
  26 {
  27         if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S))
  28                 return pch_s_rp_groups;
  29
  30         return pch_lp_rp_groups; /* Valid for PCH-P and PCH-N */
  31 }
  32
  33 /*
  34  * ADL-P FSP define CPU RP as below:
  35  * RP1: PEG60 : 0:6:0 : x4 CPU Slot
  36  * RP2: PEG10 : 0:1:0 : x8 CPU Slot
  37  * RP3: PEG62 : 0:6:2 : x4 CPU Slot
  38  */
  39 static const struct pcie_rp_group cpu_rp_groups[] = {
  40         { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1, .lcap_port_base = 1 },
  41         { .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 1, .lcap_port_base = 1 },
  42         { .slot = SA_DEV_SLOT_CPU_6, .start = 2, .count = 1, .lcap_port_base = 1 },
  43         { 0 }
  44 };
  45
  46 static const struct pcie_rp_group cpu_n_rp_groups[] = {
  47         { 0 }
  48 };
  49
  50 static const struct pcie_rp_group cpu_s_rp_groups[] = {
  51         { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1, .lcap_port_base = 1 },
  52         { .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 2, .lcap_port_base = 1 },
  53         { 0 }
  54 };
  55
  56 const struct pcie_rp_group *get_cpu_pcie_rp_table(void)
  57 {
  58         if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_N))
  59                 return cpu_n_rp_groups;
  60
  61         if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S))
  62                 return cpu_s_rp_groups;
  63
  64         return cpu_rp_groups;
  65 }
  66
  67 /*
  68  * TBT's LCAP registers are returning port index which starts from 2 (Usually for other PCIe
  69  * root ports index starts from 1). Thus keeping lcap_port_base 2 for TBT, so that coreboot's
  70  * PCIe remapping logic can return correct index (0-based)
  71  */
  72
  73 static const struct pcie_rp_group tbt_rp_groups[] = {
  74         { .slot = SA_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 2 },
  75         { 0 }
  76 };
  77
  78 const struct pcie_rp_group *get_tbt_pcie_rp_table(void)
  79 {
  80         return tbt_rp_groups;
  81 }
  82
  83 static bool is_part_of_group(const struct device *dev,
  84                              const struct pcie_rp_group *groups)
  85 {
  86         if (dev->path.type != DEVICE_PATH_PCI)
  87                 return false;
  88
  89         const unsigned int slot_to_find = PCI_SLOT(dev->path.pci.devfn);
  90         const unsigned int fn_to_find = PCI_FUNC(dev->path.pci.devfn);
  91         const struct pcie_rp_group *group;
  92         unsigned int i;
  93         unsigned int fn;
  94
  95         for (group = groups; group->count; ++group) {
  96                 for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) {
  97                         if (slot_to_find == group->slot && fn_to_find == fn)
  98                                 return true;
  99                 }
 100         }
 101
 102         return false;
 103 }
 104
 105 enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev)
 106 {
 107         if (is_part_of_group(dev, pch_lp_rp_groups))
 108                 return PCIE_RP_PCH;
 109
 110         if (CONFIG_MAX_CPU_ROOT_PORTS && is_part_of_group(dev, cpu_rp_groups))
 111                 return PCIE_RP_CPU;
 112
 113         return PCIE_RP_UNKNOWN;
 114 }
 115
 116 int soc_get_cpu_rp_vw_idx(const struct device *dev)
 117 {
 118         if (dev->path.type != DEVICE_PATH_PCI)
 119                 return -1;
 120
 121         switch (dev->path.pci.devfn) {
 122         case SA_DEVFN_CPU_PCIE1_0:
 123                 return CPU_CPIE_VW_IDX_BASE;
 124         case SA_DEVFN_CPU_PCIE6_0:
 125                 return CPU_CPIE_VW_IDX_BASE + 3;
 126         case SA_DEVFN_CPU_PCIE6_2:
 127                 return CPU_CPIE_VW_IDX_BASE + 2;
 128         default:
 129                 return -1;
 130         }
 131 }