src/soc/intel/apollolake/pmutil.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #define __SIMPLE_DEVICE__
   4
   5 #include <acpi/acpi.h>
   6 #include <acpi/acpi_pm.h>
   7 #include <arch/io.h>
   8 #include <device/mmio.h>
   9 #include <console/console.h>
  10 #include <device/device.h>
  11 #include <device/pci.h>
  12 #include <intelblocks/msr.h>
  13 #include <intelblocks/pmclib.h>
  14 #include <intelblocks/rtc.h>
  15 #include <intelblocks/tco.h>
  16 #include <soc/iomap.h>
  17 #include <soc/cpu.h>
  18 #include <soc/pci_devs.h>
  19 #include <soc/pm.h>
  20 #include <soc/smbus.h>
  21 #include <security/vboot/vbnv.h>
  22 #include <static.h>
  23
  24 #include "chip.h"
  25
  26 uint8_t *pmc_mmio_regs(void)
  27 {
  28         return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
  29 }
  30
  31 uintptr_t soc_read_pmc_base(void)
  32 {
  33         return (uintptr_t)pmc_mmio_regs();
  34 }
  35
  36 uint32_t *soc_pmc_etr_addr(void)
  37 {
  38         return (uint32_t *)(soc_read_pmc_base() + ETR);
  39 }
  40
  41 const char *const *soc_smi_sts_array(size_t *a)
  42 {
  43         static const char *const smi_sts_bits[] = {
  44                 [BIOS_STS_BIT] = "BIOS",
  45                 [LEGACY_USB_STS_BIT] = "LEGACY USB",
  46                 [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
  47                 [APM_STS_BIT] = "APM",
  48                 [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
  49                 [PM1_STS_BIT] = "PM1",
  50                 [GPE0_STS_BIT] = "GPE0 (reserved)",
  51                 [GPIO_STS_BIT] = "GPIO_SMI",
  52                 [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK_SSMI",
  53                 [MC_SMI_STS_BIT] = "MCSMI",
  54                 [TCO_STS_BIT] = "TCO",
  55                 [PERIODIC_STS_BIT] = "PERIODIC",
  56                 [SERIRQ_SMI_STS_BIT] = "SERIRQ",
  57                 [SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
  58                 [XHCI_SMI_STS_BIT] = "XHCI",
  59                 [HSMBUS_SMI_STS_BIT] = "HOST_SMBUS",
  60                 [SCS_SMI_STS_BIT] = "SCS",
  61                 [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
  62                 [SCC2_SMI_STS_BIT] = "SCC2",
  63                 [SPI_SSMI_STS_BIT] = "SPI_SSMI",
  64                 [SPI_SMI_STS_BIT] = "SPI",
  65                 [PMC_OCP_SMI_STS_BIT] = "OCP_CSE",
  66         };
  67
  68         *a = ARRAY_SIZE(smi_sts_bits);
  69         return smi_sts_bits;
  70 }
  71
  72 /*
  73  * For APL/GLK this check for power button status if nothing else
  74  * is indicating an SMI and SMIs aren't turned into SCIs.
  75  * Apparently, there is no PM1 status bit in the SMI status
  76  * register.  That makes things difficult for
  77  * determining if the power button caused an SMI.
  78  */
  79 uint32_t soc_get_smi_status(uint32_t generic_sts)
  80 {
  81         if (generic_sts == 0 && !(pmc_read_pm1_control() & SCI_EN)) {
  82                 uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
  83
  84                 /* Fake PM1 status bit if power button pressed. */
  85                 if (pm1_sts & PWRBTN_STS)
  86                         generic_sts |= (1 << PM1_STS_BIT);
  87         }
  88
  89         /*
  90          * GPE0_STS is reserved in APL/GLK datasheets. For compatibility
  91          * with common code, mask it out so that it is always zero.
  92          */
  93         return generic_sts & ~(1 << GPE0_STS_BIT);
  94 }
  95
  96 const char *const *soc_tco_sts_array(size_t *a)
  97 {
  98         static const char *const tco_sts_bits[] = {
  99                 [3] = "TIMEOUT",
 100                 [17] = "SECOND_TO",
 101         };
 102
 103         *a = ARRAY_SIZE(tco_sts_bits);
 104         return tco_sts_bits;
 105 }
 106
 107 const char *const *soc_std_gpe_sts_array(size_t *a)
 108 {
 109         static const char *const gpe_sts_bits[] = {
 110                 [0] = "PCIE_SCI",
 111                 [2] = "SWGPE",
 112                 [3] = "PCIE_WAKE0",
 113                 [4] = "PUNIT",
 114                 [6] = "PCIE_WAKE1",
 115                 [7] = "PCIE_WAKE2",
 116                 [8] = "PCIE_WAKE3",
 117                 [9] = "PCI_EXP",
 118                 [10] = "BATLOW",
 119                 [11] = "CSE_PME",
 120                 [12] = "XDCI_PME",
 121                 [13] = "XHCI_PME",
 122                 [14] = "AVS_PME",
 123                 [15] = "GPIO_TIER1_SCI",
 124                 [16] = "SMB_WAK",
 125                 [17] = "SATA_PME",
 126         };
 127
 128         *a = ARRAY_SIZE(gpe_sts_bits);
 129         return gpe_sts_bits;
 130 }
 131
 132 void soc_clear_pm_registers(uintptr_t pmc_bar)
 133 {
 134         uint32_t gen_pmcon1;
 135
 136         gen_pmcon1 = read32p(pmc_bar + GEN_PMCON1);
 137         /* Clear the status bits. The RPS field is cleared on a 0 write. */
 138         write32p(pmc_bar + GEN_PMCON1, gen_pmcon1 & ~RPS);
 139 }
 140
 141 static void gpe0_different_values(const struct soc_intel_apollolake_config *config)
 142 {
 143         bool result = (config->gpe0_dw1 != config->gpe0_dw2) &&
 144                          (config->gpe0_dw1 != config->gpe0_dw3) &&
 145                          (config->gpe0_dw2 != config->gpe0_dw3);
 146
 147         assert(result);
 148 }
 149
 150 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 151 {
 152         DEVTREE_CONST struct soc_intel_apollolake_config *config;
 153
 154         config = config_of_soc();
 155
 156         gpe0_different_values(config);
 157
 158         /* Assign to out variable */
 159         *dw0 = config->gpe0_dw1;
 160         *dw1 = config->gpe0_dw2;
 161         *dw2 = config->gpe0_dw3;
 162 }
 163
 164 void soc_fill_power_state(struct chipset_power_state *ps)
 165 {
 166         uintptr_t pmc_bar0 = soc_read_pmc_base();
 167
 168         ps->tco1_sts = tco_read_reg(TCO1_STS);
 169         ps->tco2_sts = tco_read_reg(TCO2_STS);
 170
 171         ps->prsts = read32p(pmc_bar0 + PRSTS);
 172         ps->gen_pmcon1 = read32p(pmc_bar0 + GEN_PMCON1);
 173         ps->gen_pmcon2 = read32p(pmc_bar0 + GEN_PMCON2);
 174         ps->gen_pmcon3 = read32p(pmc_bar0 + GEN_PMCON3);
 175
 176         printk(BIOS_DEBUG, "prsts: %08x\n",
 177                ps->prsts);
 178         printk(BIOS_DEBUG, "tco_sts:   %04x %04x\n",
 179                ps->tco1_sts, ps->tco2_sts);
 180         printk(BIOS_DEBUG,
 181                "gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",
 182                ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
 183 }
 184
 185 /* Return 0, 3, or 5 to indicate the previous sleep state. */
 186 int soc_prev_sleep_state(const struct chipset_power_state *ps,
 187         int prev_sleep_state)
 188 {
 189         /* WAK_STS bit will not be set when waking from G3 state */
 190
 191         if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon1 & COLD_BOOT_STS))
 192                 prev_sleep_state = ACPI_S5;
 193         return prev_sleep_state;
 194 }
 195
 196 static int rtc_failed(uint32_t gen_pmcon1)
 197 {
 198         return !!(gen_pmcon1 & RPS);
 199 }
 200
 201 int soc_get_rtc_failed(void)
 202 {
 203         const struct chipset_power_state *ps;
 204
 205         if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0)
 206                 return 1;
 207
 208         return rtc_failed(ps->gen_pmcon1);
 209 }
 210
 211 int vbnv_cmos_failed(void)
 212 {
 213         uintptr_t pmc_bar = soc_read_pmc_base();
 214         uint32_t gen_pmcon1 = read32p(pmc_bar + GEN_PMCON1);
 215         int rtc_failure = rtc_failed(gen_pmcon1);
 216
 217         if (rtc_failure) {
 218                 printk(BIOS_INFO, "RTC failed!\n");
 219
 220                 /* We do not want to write 1 to clear-1 bits. Set them to 0. */
 221                 gen_pmcon1 &= ~GEN_PMCON1_CLR1_BITS;
 222
 223                 /* RPS is write 0 to clear. */
 224                 gen_pmcon1 &= ~RPS;
 225
 226                 write32p(pmc_bar + GEN_PMCON1, gen_pmcon1);
 227         }
 228
 229         return rtc_failure;
 230 }
 231
 232 /* STM Support */
 233 uint16_t get_pmbase(void)
 234 {
 235         return (uint16_t)ACPI_BASE_ADDRESS;
 236 }
 237
 238 /* Set which power state system will be after reapplying the power (from G3 State) */
 239 void pmc_soc_set_afterg3_en(const bool on)
 240 {
 241         uint8_t reg8;
 242         uint8_t *const pmcbase = pmc_mmio_regs();
 243
 244         reg8 = read8(pmcbase + GEN_PMCON_A);
 245         if (on)
 246                 reg8 &= ~SLEEP_AFTER_POWER_FAIL;
 247         else
 248                 reg8 |= SLEEP_AFTER_POWER_FAIL;
 249         write8(pmcbase + GEN_PMCON_A, reg8);
 250 }