src/soc/intel/baytrail/chip.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/pci.h>
   5 #include <arch/pci_ops.h>
   6
   7 #include <soc/pci_devs.h>
   8 #include <soc/ramstage.h>
   9 #include "chip.h"
  10
  11 static struct device_operations pci_domain_ops = {
  12         .read_resources   = pci_domain_read_resources,
  13         .set_resources    = pci_domain_set_resources,
  14         .scan_bus         = pci_host_bridge_scan_bus,
  15 };
  16
  17 static struct device_operations cpu_bus_ops = {
  18         .read_resources   = noop_read_resources,
  19         .set_resources    = noop_set_resources,
  20         .init             = mp_cpu_bus_init,
  21 };
  22
  23 static void enable_dev(struct device *dev)
  24 {
  25         /* Set the operations if it is a special bus type */
  26         if (dev->path.type == DEVICE_PATH_DOMAIN) {
  27                 dev->ops = &pci_domain_ops;
  28         } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
  29                 dev->ops = &cpu_bus_ops;
  30         } else if (dev->path.type == DEVICE_PATH_PCI) {
  31                 /* Handle south cluster enablement. */
  32                 if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV &&
  33                     (dev->ops == NULL || dev->ops->enable == NULL)) {
  34                         southcluster_enable_dev(dev);
  35                 }
  36         }
  37 }
  38
  39 /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */
  40 static void soc_init(void *chip_info)
  41 {
  42         baytrail_init_pre_device(chip_info);
  43 }
  44
  45 struct chip_operations soc_intel_baytrail_ops = {
  46         .name = "Intel BayTrail SoC",
  47         .enable_dev = enable_dev,
  48         .init = soc_init,
  49 };
  50
  51 struct pci_operations soc_pci_ops = {
  52         .set_subsystem = &pci_dev_set_subsystem,
  53 };